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drm/amd/display: Fix potential access beyond end of array in CM
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b 37#include "virtual/virtual_stream_encoder.h"
3b94a400 38#include "dpcd_defs.h"
4562236b
HW		 39
40#include "dce80/dce80_resource.h"
41#include "dce100/dce100_resource.h"
42#include "dce110/dce110_resource.h"
43#include "dce112/dce112_resource.h"
ff5ef992
AD		 44#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
45#include "dcn10/dcn10_resource.h"
46#endif
2c8ad2d5 47#include "dce120/dce120_resource.h"
1296423b
BL		 48#define DC_LOGGER \
49 ctx->logger
4562236b
HW		 50enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
51{
52 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
53 switch (asic_id.chip_family) {
54
55 case FAMILY_CI:
4562236b
HW		 56 dc_version = DCE_VERSION_8_0;
57 break;
ebfdf0d0
AD		 58 case FAMILY_KV:
59 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
60 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
61 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
62 dc_version = DCE_VERSION_8_3;
63 else
64 dc_version = DCE_VERSION_8_1;
65 break;
4562236b
HW		 66 case FAMILY_CZ:
67 dc_version = DCE_VERSION_11_0;
68 break;
69
70 case FAMILY_VI:
71 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
72 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
73 dc_version = DCE_VERSION_10_0;
74 break;
75 }
76 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 77 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
78 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 79 dc_version = DCE_VERSION_11_2;
80 }
81 break;
2c8ad2d5
AD		 82 case FAMILY_AI:
83 dc_version = DCE_VERSION_12_0;
84 break;
ff5ef992
AD		 85#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
86 case FAMILY_RV:
87 dc_version = DCN_VERSION_1_0;
88 break;
89#endif
4562236b
HW		 90 default:
91 dc_version = DCE_VERSION_UNKNOWN;
92 break;
93 }
94 return dc_version;
95}
96
97struct resource_pool *dc_create_resource_pool(
fb3466a4 98 struct dc *dc,
4562236b
HW		 99 int num_virtual_links,
100 enum dce_version dc_version,
101 struct hw_asic_id asic_id)
102{
5ac3d3c9 103 struct resource_pool *res_pool = NULL;
4562236b
HW		 104
105 switch (dc_version) {
106 case DCE_VERSION_8_0:
7992a629
AD		 107 res_pool = dce80_create_resource_pool(
108 num_virtual_links, dc);
109 break;
ebfdf0d0 110 case DCE_VERSION_8_1:
7992a629
AD		 111 res_pool = dce81_create_resource_pool(
112 num_virtual_links, dc);
113 break;
ebfdf0d0 114 case DCE_VERSION_8_3:
7992a629 115 res_pool = dce83_create_resource_pool(
4562236b 116 num_virtual_links, dc);
5ac3d3c9 117 break;
4562236b 118 case DCE_VERSION_10_0:
5ac3d3c9 119 res_pool = dce100_create_resource_pool(
4562236b 120 num_virtual_links, dc);
5ac3d3c9 121 break;
4562236b 122 case DCE_VERSION_11_0:
5ac3d3c9 123 res_pool = dce110_create_resource_pool(
4562236b 124 num_virtual_links, dc, asic_id);
5ac3d3c9 125 break;
4562236b 126 case DCE_VERSION_11_2:
5ac3d3c9 127 res_pool = dce112_create_resource_pool(
4562236b 128 num_virtual_links, dc);
5ac3d3c9 129 break;
2c8ad2d5
AD		 130 case DCE_VERSION_12_0:
131 res_pool = dce120_create_resource_pool(
132 num_virtual_links, dc);
133 break;
ff5ef992
AD		 134
135#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
136 case DCN_VERSION_1_0:
137 res_pool = dcn10_create_resource_pool(
503a7c6f 138 num_virtual_links, dc);
ff5ef992
AD		 139 break;
140#endif
3639fa68
ZF		 141
142
4562236b
HW		 143 default:
144 break;
145 }
5ac3d3c9 146 if (res_pool != NULL) {
1515a47b 147 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 148
149 if (dc->ctx->dc_bios->funcs->get_firmware_info(
150 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
151 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
152 } else
153 ASSERT_CRITICAL(false);
154 }
4562236b 155
5ac3d3c9 156 return res_pool;
4562236b
HW		 157}
158
fb3466a4 159void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 160{
161 if (dc) {
162 if (dc->res_pool)
163 dc->res_pool->funcs->destroy(&dc->res_pool);
164
d029810c 165 kfree(dc->hwseq);
4562236b
HW		 166 }
167}
168
169static void update_num_audio(
170 const struct resource_straps *straps,
171 unsigned int *num_audio,
172 struct audio_support *aud_support)
173{
b8e9eb72
CL		 174 aud_support->dp_audio = true;
175 aud_support->hdmi_audio_native = false;
176 aud_support->hdmi_audio_on_dongle = false;
177
4562236b 178 if (straps->hdmi_disable == 0) {
4562236b
HW		 179 if (straps->dc_pinstraps_audio & 0x2) {
180 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 181 aud_support->hdmi_audio_native = true;
4562236b
HW		 182 }
183 }
184
185 switch (straps->audio_stream_number) {
186 case 0: /* multi streams supported */
187 break;
188 case 1: /* multi streams not supported */
189 *num_audio = 1;
190 break;
191 default:
192 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 193 }
4562236b
HW		 194}
195
196bool resource_construct(
197 unsigned int num_virtual_links,
fb3466a4 198 struct dc *dc,
4562236b
HW		 199 struct resource_pool *pool,
200 const struct resource_create_funcs *create_funcs)
201{
202 struct dc_context *ctx = dc->ctx;
203 const struct resource_caps *caps = pool->res_cap;
204 int i;
205 unsigned int num_audio = caps->num_audio;
206 struct resource_straps straps = {0};
207
208 if (create_funcs->read_dce_straps)
209 create_funcs->read_dce_straps(dc->ctx, &straps);
210
211 pool->audio_count = 0;
212 if (create_funcs->create_audio) {
213 /* find the total number of streams available via the
214 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
215 * registers (one for each pin) starting from pin 1
216 * up to the max number of audio pins.
217 * We stop on the first pin where
218 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
219 */
220 update_num_audio(&straps, &num_audio, &pool->audio_support);
221 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
222 struct audio *aud = create_funcs->create_audio(ctx, i);
223
224 if (aud == NULL) {
225 DC_ERR("DC: failed to create audio!\n");
226 return false;
227 }
228
229 if (!aud->funcs->endpoint_valid(aud)) {
230 aud->funcs->destroy(&aud);
231 break;
232 }
233
234 pool->audios[i] = aud;
235 pool->audio_count++;
236 }
237 }
238
239 pool->stream_enc_count = 0;
240 if (create_funcs->create_stream_encoder) {
241 for (i = 0; i < caps->num_stream_encoder; i++) {
242 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
243 if (pool->stream_enc[i] == NULL)
244 DC_ERR("DC: failed to create stream_encoder!\n");
245 pool->stream_enc_count++;
246 }
247 }
4176664b
CL		 248 dc->caps.dynamic_audio = false;
249 if (pool->audio_count < pool->stream_enc_count) {
250 dc->caps.dynamic_audio = true;
251 }
4562236b
HW		 252 for (i = 0; i < num_virtual_links; i++) {
253 pool->stream_enc[pool->stream_enc_count] =
254 virtual_stream_encoder_create(
255 ctx, ctx->dc_bios);
256 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
257 DC_ERR("DC: failed to create stream_encoder!\n");
258 return false;
259 }
260 pool->stream_enc_count++;
261 }
262
263 dc->hwseq = create_funcs->create_hwseq(ctx);
264
265 return true;
266}
267
268
21e67d4d 269void resource_unreference_clock_source(
4562236b 270 struct resource_context *res_ctx,
a2b8659d 271 const struct resource_pool *pool,
4a629536 272 struct clock_source *clock_source)
4562236b
HW		 273{
274 int i;
4a629536 275
a2b8659d 276 for (i = 0; i < pool->clk_src_count; i++) {
4a629536 277 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 278 continue;
279
280 res_ctx->clock_source_ref_count[i]--;
281
4562236b
HW		 282 break;
283 }
284
21e67d4d 285 if (pool->dp_clock_source == clock_source)
4562236b 286 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 287}
288
289void resource_reference_clock_source(
290 struct resource_context *res_ctx,
a2b8659d 291 const struct resource_pool *pool,
4562236b
HW		 292 struct clock_source *clock_source)
293{
294 int i;
a2b8659d
TC		 295 for (i = 0; i < pool->clk_src_count; i++) {
296 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 297 continue;
298
299 res_ctx->clock_source_ref_count[i]++;
300 break;
301 }
302
a2b8659d 303 if (pool->dp_clock_source == clock_source)
4562236b
HW		 304 res_ctx->dp_clock_source_ref_count++;
305}
306
307bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 308 struct dc_stream_state *stream1,
309 struct dc_stream_state *stream2)
4562236b 310{
4fa086b9 311 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 312 return false;
313
4fa086b9 314 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 315 return false;
316
4fa086b9
LSL		 317 if (stream1->timing.h_addressable
318 != stream2->timing.h_addressable)
4562236b
HW		 319 return false;
320
4fa086b9
LSL		 321 if (stream1->timing.v_addressable
322 != stream2->timing.v_addressable)
4562236b
HW		 323 return false;
324
4fa086b9
LSL		 325 if (stream1->timing.pix_clk_khz
326 != stream2->timing.pix_clk_khz)
4562236b
HW		 327 return false;
328
329 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 330 && (!dc_is_dp_signal(stream1->signal)
331 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 332 return false;
333
334 return true;
335}
336
337static bool is_sharable_clk_src(
338 const struct pipe_ctx *pipe_with_clk_src,
339 const struct pipe_ctx *pipe)
340{
341 if (pipe_with_clk_src->clock_source == NULL)
342 return false;
343
344 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
345 return false;
346
347 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
348 return false;
349
350 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
351 && dc_is_dvi_signal(pipe->stream->signal))
352 return false;
353
354 if (dc_is_hdmi_signal(pipe->stream->signal)
355 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
356 return false;
357
358 if (!resource_are_streams_timing_synchronizable(
359 pipe_with_clk_src->stream, pipe->stream))
360 return false;
361
362 return true;
363}
364
365struct clock_source *resource_find_used_clk_src_for_sharing(
366 struct resource_context *res_ctx,
367 struct pipe_ctx *pipe_ctx)
368{
369 int i;
370
371 for (i = 0; i < MAX_PIPES; i++) {
372 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
373 return res_ctx->pipe_ctx[i].clock_source;
374 }
375
376 return NULL;
377}
378
379static enum pixel_format convert_pixel_format_to_dalsurface(
380 enum surface_pixel_format surface_pixel_format)
381{
382 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
383
384 switch (surface_pixel_format) {
385 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
386 dal_pixel_format = PIXEL_FORMAT_INDEX8;
387 break;
388 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
389 dal_pixel_format = PIXEL_FORMAT_RGB565;
390 break;
391 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
392 dal_pixel_format = PIXEL_FORMAT_RGB565;
393 break;
394 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
395 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
396 break;
8693049a 397 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 398 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
399 break;
400 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
401 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
402 break;
403 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
404 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
405 break;
406 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
407 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
408 break;
409 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
410 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
411 dal_pixel_format = PIXEL_FORMAT_FP16;
412 break;
413 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 414 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 415 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 416 break;
ffbcd19a
VP		 417 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
418 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 419 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 420 break;
4562236b
HW		 421 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
422 default:
423 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
424 break;
425 }
426 return dal_pixel_format;
427}
428
429static void rect_swap_helper(struct rect *rect)
430{
99676f20
GS		 431 swap(rect->height, rect->width);
432 swap(rect->x, rect->y);
4562236b
HW		 433}
434
b2d0a103 435static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 436{
3be5262e 437 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 438 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 439 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 440 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 441 struct rect clip = { 0 };
87449a90
AK		 442 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
443 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 444 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 445 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 446 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 447 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 448
7f5c22d1
VP		 449 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
450 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 451 pri_split = false;
452 sec_split = false;
453 }
86006a7f 454
3be5262e
HW		 455 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
456 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 457 rect_swap_helper(&surf_src);
458
4562236b
HW		 459 /* The actual clip is an intersection between stream
460 * source and surface clip
461 */
3be5262e
HW		 462 clip.x = stream->src.x > plane_state->clip_rect.x ?
463 stream->src.x : plane_state->clip_rect.x;
4562236b 464
1fbd2cfc 465 clip.width = stream->src.x + stream->src.width <
3be5262e 466 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 467 stream->src.x + stream->src.width - clip.x :
3be5262e 468 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 469
3be5262e
HW		 470 clip.y = stream->src.y > plane_state->clip_rect.y ?
471 stream->src.y : plane_state->clip_rect.y;
4562236b 472
1fbd2cfc 473 clip.height = stream->src.y + stream->src.height <
3be5262e 474 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 475 stream->src.y + stream->src.height - clip.y :
3be5262e 476 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 477
86006a7f 478 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 479 * num_pixels = clip.num_pix * scl_ratio
480 */
3be5262e
HW		 481 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
482 surf_src.width / plane_state->dst_rect.width;
b2d0a103 483 data->viewport.width = clip.width *
3be5262e 484 surf_src.width / plane_state->dst_rect.width;
4562236b 485
3be5262e
HW		 486 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
487 surf_src.height / plane_state->dst_rect.height;
b2d0a103 488 data->viewport.height = clip.height *
3be5262e 489 surf_src.height / plane_state->dst_rect.height;
4562236b 490
b2d0a103
DL		 491 /* Round down, compensate in init */
492 data->viewport_c.x = data->viewport.x / vpc_div;
493 data->viewport_c.y = data->viewport.y / vpc_div;
494 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
495 dal_fixed31_32_half : dal_fixed31_32_zero;
496 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
497 dal_fixed31_32_half : dal_fixed31_32_zero;
498 /* Round up, assume original video size always even dimensions */
499 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
500 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
501
502 /* Handle hsplit */
0c31a821
YS		 503 if (sec_split) {
504 data->viewport.x += data->viewport.width / 2;
505 data->viewport_c.x += data->viewport_c.width / 2;
506 /* Ceil offset pipe */
507 data->viewport.width = (data->viewport.width + 1) / 2;
508 data->viewport_c.width = (data->viewport_c.width + 1) / 2;
509 } else if (pri_split) {
510 data->viewport.width /= 2;
511 data->viewport_c.width /= 2;
b2d0a103 512 }
1fbd2cfc 513
3be5262e
HW		 514 if (plane_state->rotation == ROTATION_ANGLE_90 ||
515 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 516 rect_swap_helper(&data->viewport_c);
517 rect_swap_helper(&data->viewport);
518 }
4562236b
HW		 519}
520
b2d0a103 521static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 522{
3be5262e 523 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 524 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW		 525 struct rect surf_src = plane_state->src_rect;
526 struct rect surf_clip = plane_state->clip_rect;
c802570e 527 int recout_full_x, recout_full_y;
0c31a821
YS		 528 bool pri_split = pipe_ctx->bottom_pipe &&
529 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
530 bool sec_split = pipe_ctx->top_pipe &&
531 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 532 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 533
3be5262e
HW		 534 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
535 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 536 rect_swap_helper(&surf_src);
537
6702a9ac 538 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 539 if (stream->src.x < surf_clip.x)
6702a9ac 540 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 541 - stream->src.x) * stream->dst.width
542 / stream->src.width;
4562236b 543
6702a9ac 544 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 545 stream->dst.width / stream->src.width;
6702a9ac 546 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 547 stream->dst.x + stream->dst.width)
6702a9ac 548 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 549 stream->dst.x + stream->dst.width
6702a9ac 550 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 551
6702a9ac 552 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 553 if (stream->src.y < surf_clip.y)
6702a9ac 554 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 555 - stream->src.y) * stream->dst.height
556 / stream->src.height;
4562236b 557
6702a9ac 558 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 559 stream->dst.height / stream->src.height;
6702a9ac 560 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 561 stream->dst.y + stream->dst.height)
6702a9ac 562 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 563 stream->dst.y + stream->dst.height
6702a9ac 564 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 565
7b779c99 566 /* Handle h & vsplit */
b0131391
DL		 567 if (sec_split && top_bottom_split) {
568 pipe_ctx->plane_res.scl_data.recout.y +=
569 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 570 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 571 pipe_ctx->plane_res.scl_data.recout.height =
572 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
573 } else if (pri_split && top_bottom_split)
0c31a821 574 pipe_ctx->plane_res.scl_data.recout.height /= 2;
b0131391 575 else if (pri_split || sec_split) {
0c31a821
YS		 576 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
577 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
578 (plane_state->rotation == ROTATION_ANGLE_180);
579
580 if (plane_state->rotation == ROTATION_ANGLE_90
581 || plane_state->rotation == ROTATION_ANGLE_270)
582 /* Secondary_pipe XOR Rotation_270 */
583 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
584
585 if (right_view) {
586 pipe_ctx->plane_res.scl_data.recout.x +=
587 pipe_ctx->plane_res.scl_data.recout.width / 2;
588 /* Ceil offset pipe */
589 pipe_ctx->plane_res.scl_data.recout.width =
590 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
591 } else {
6702a9ac 592 pipe_ctx->plane_res.scl_data.recout.width /= 2;
0c31a821 593 }
b2d0a103 594 }
86006a7f
DL		 595 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
596 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 597 * ratio)
598 */
b0131391 599 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 600 * stream->dst.width / stream->src.width -
3be5262e 601 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 602 * stream->dst.width / stream->src.width;
b0131391 603 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 604 * stream->dst.height / stream->src.height -
3be5262e 605 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 606 * stream->dst.height / stream->src.height;
c802570e 607
6702a9ac
HW		 608 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
609 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
4562236b
HW		 610}
611
b2d0a103 612static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 613{
3be5262e 614 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 615 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 616 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 617 const int in_w = stream->src.width;
618 const int in_h = stream->src.height;
619 const int out_w = stream->dst.width;
620 const int out_h = stream->dst.height;
4562236b 621
3be5262e
HW		 622 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
623 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 624 rect_swap_helper(&surf_src);
625
6702a9ac 626 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 627 surf_src.width,
3be5262e 628 plane_state->dst_rect.width);
6702a9ac 629 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 630 surf_src.height,
3be5262e 631 plane_state->dst_rect.height);
4562236b 632
4fa086b9 633 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 634 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 635 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 636 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 637
6702a9ac
HW		 638 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
639 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
640 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
641 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 642
6702a9ac
HW		 643 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
644 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 645
6702a9ac
HW		 646 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
647 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
648 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
649 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b
HW		 650 }
651}
652
b2d0a103
DL		 653static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
654{
6702a9ac 655 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 656 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK		 657 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
658 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b0131391 659 bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
b2d0a103 660
b0131391
DL		 661 /*
662 * Need to calculate the scan direction for viewport to make adjustments
663 */
664 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
665 flip_vert_scan_dir = true;
666 flip_horz_scan_dir = true;
667 } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
668 flip_vert_scan_dir = true;
669 else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
670 flip_horz_scan_dir = true;
671 if (pipe_ctx->plane_state->horizontal_mirror)
672 flip_horz_scan_dir = !flip_horz_scan_dir;
673
3be5262e
HW		 674 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
675 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 676 rect_swap_helper(&src);
1fbd2cfc
DL		 677 rect_swap_helper(&data->viewport_c);
678 rect_swap_helper(&data->viewport);
679 }
680
b2d0a103
DL		 681 /*
682 * Init calculated according to formula:
683 * init = (scaling_ratio + number_of_taps + 1) / 2
684 * init_bot = init + scaling_ratio
685 * init_c = init + truncated_vp_c_offset(from calculate viewport)
686 */
687 data->inits.h = dal_fixed31_32_div_int(
688 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
689
690 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
691 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
692
693 data->inits.v = dal_fixed31_32_div_int(
694 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
695
696 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
697 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
698
699
700 /* Adjust for viewport end clip-off */
4ee778dc 701 if ((data->viewport.x + data->viewport.width) < (src.x + src.width) && !flip_horz_scan_dir) {
b2d0a103 702 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 703 int int_part = dal_fixed31_32_floor(
704 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 705
1fbd2cfc 706 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 707 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
708 }
4ee778dc 709 if ((data->viewport.y + data->viewport.height) < (src.y + src.height) && !flip_vert_scan_dir) {
b2d0a103 710 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 711 int int_part = dal_fixed31_32_floor(
712 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 713
1fbd2cfc 714 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 715 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
716 }
4ee778dc 717 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div && !flip_horz_scan_dir) {
b2d0a103
DL		 718 int vp_clip = (src.x + src.width) / vpc_div -
719 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 720 int int_part = dal_fixed31_32_floor(
721 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 722
1fbd2cfc 723 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 724 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
725 }
4ee778dc 726 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div && !flip_vert_scan_dir) {
b2d0a103
DL		 727 int vp_clip = (src.y + src.height) / vpc_div -
728 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 729 int int_part = dal_fixed31_32_floor(
730 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 731
1fbd2cfc 732 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 733 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
734 }
735
736 /* Adjust for non-0 viewport offset */
737ae4ea 737 if (data->viewport.x && !flip_horz_scan_dir) {
b2d0a103
DL		 738 int int_part;
739
740 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
741 data->ratios.horz, recout_skip->width));
742 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
743 if (int_part < data->taps.h_taps) {
744 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
745 (data->taps.h_taps - int_part) : data->viewport.x;
746 data->viewport.x -= int_adj;
747 data->viewport.width += int_adj;
748 int_part += int_adj;
749 } else if (int_part > data->taps.h_taps) {
750 data->viewport.x += int_part - data->taps.h_taps;
751 data->viewport.width -= int_part - data->taps.h_taps;
752 int_part = data->taps.h_taps;
753 }
754 data->inits.h.value &= 0xffffffff;
755 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
756 }
757
737ae4ea 758 if (data->viewport_c.x && !flip_horz_scan_dir) {
b2d0a103
DL		 759 int int_part;
760
761 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
762 data->ratios.horz_c, recout_skip->width));
763 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
764 if (int_part < data->taps.h_taps_c) {
765 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
766 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
767 data->viewport_c.x -= int_adj;
768 data->viewport_c.width += int_adj;
769 int_part += int_adj;
770 } else if (int_part > data->taps.h_taps_c) {
771 data->viewport_c.x += int_part - data->taps.h_taps_c;
772 data->viewport_c.width -= int_part - data->taps.h_taps_c;
773 int_part = data->taps.h_taps_c;
774 }
775 data->inits.h_c.value &= 0xffffffff;
776 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
777 }
778
737ae4ea 779 if (data->viewport.y && !flip_vert_scan_dir) {
b2d0a103
DL		 780 int int_part;
781
782 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
783 data->ratios.vert, recout_skip->height));
784 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
785 if (int_part < data->taps.v_taps) {
786 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
787 (data->taps.v_taps - int_part) : data->viewport.y;
788 data->viewport.y -= int_adj;
789 data->viewport.height += int_adj;
790 int_part += int_adj;
791 } else if (int_part > data->taps.v_taps) {
792 data->viewport.y += int_part - data->taps.v_taps;
793 data->viewport.height -= int_part - data->taps.v_taps;
794 int_part = data->taps.v_taps;
795 }
796 data->inits.v.value &= 0xffffffff;
797 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
798 }
799
737ae4ea 800 if (data->viewport_c.y && !flip_vert_scan_dir) {
b2d0a103
DL		 801 int int_part;
802
803 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
804 data->ratios.vert_c, recout_skip->height));
805 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
806 if (int_part < data->taps.v_taps_c) {
807 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
808 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
809 data->viewport_c.y -= int_adj;
810 data->viewport_c.height += int_adj;
811 int_part += int_adj;
812 } else if (int_part > data->taps.v_taps_c) {
813 data->viewport_c.y += int_part - data->taps.v_taps_c;
814 data->viewport_c.height -= int_part - data->taps.v_taps_c;
815 int_part = data->taps.v_taps_c;
816 }
817 data->inits.v_c.value &= 0xffffffff;
818 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
819 }
820
821 /* Interlaced inits based on final vert inits */
822 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
823 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 824
3be5262e
HW		 825 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
826 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 827 rect_swap_helper(&data->viewport_c);
828 rect_swap_helper(&data->viewport);
829 }
b2d0a103
DL		 830}
831
832bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 833{
3be5262e 834 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 835 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103
DL		 836 struct view recout_skip = { 0 };
837 bool res = false;
1296423b 838 struct dc_context *ctx = pipe_ctx->stream->ctx;
4562236b
HW		 839 /* Important: scaling ratio calculation requires pixel format,
840 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 841 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 842 */
6702a9ac 843 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 844 pipe_ctx->plane_state->format);
b2d0a103
DL		 845
846 calculate_scaling_ratios(pipe_ctx);
4562236b 847
b2d0a103 848 calculate_viewport(pipe_ctx);
4562236b 849
6702a9ac 850 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 851 return false;
852
b2d0a103 853 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 854
855 /**
856 * Setting line buffer pixel depth to 24bpp yields banding
857 * on certain displays, such as the Sharp 4k
858 */
6702a9ac 859 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 860
199e458a 861 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 862 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 863
58bb0e63
AJ		 864 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
865 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
4562236b 866
1b6c8067 867
4562236b 868 /* Taps calculations */
d94585a0
YHL		 869 if (pipe_ctx->plane_res.xfm != NULL)
870 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
871 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
872
873 if (pipe_ctx->plane_res.dpp != NULL)
874 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
875 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 876 if (!res) {
877 /* Try 24 bpp linebuffer */
6702a9ac 878 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 879
1b6c8067
BL		 880 if (pipe_ctx->plane_res.xfm != NULL)
881 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
882 pipe_ctx->plane_res.xfm,
883 &pipe_ctx->plane_res.scl_data,
884 &plane_state->scaling_quality);
885
886 if (pipe_ctx->plane_res.dpp != NULL)
887 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
888 pipe_ctx->plane_res.dpp,
889 &pipe_ctx->plane_res.scl_data,
890 &plane_state->scaling_quality);
4562236b
HW		 891 }
892
b2d0a103 893 if (res)
1fbd2cfc 894 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 895 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
896
1296423b 897 DC_LOG_SCALER(
4562236b
HW		 898 "%s: Viewport:\nheight:%d width:%d x:%d "
899 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
900 "y:%d\n",
901 __func__,
6702a9ac
HW		 902 pipe_ctx->plane_res.scl_data.viewport.height,
903 pipe_ctx->plane_res.scl_data.viewport.width,
904 pipe_ctx->plane_res.scl_data.viewport.x,
905 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 906 plane_state->dst_rect.height,
907 plane_state->dst_rect.width,
908 plane_state->dst_rect.x,
909 plane_state->dst_rect.y);
4562236b
HW		 910
911 return res;
912}
913
914
915enum dc_status resource_build_scaling_params_for_context(
fb3466a4 916 const struct dc *dc,
608ac7bb 917 struct dc_state *context)
4562236b
HW		 918{
919 int i;
920
921 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 922 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 923 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 924 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 925 return DC_FAIL_SCALING;
4562236b
HW		 926 }
927
928 return DC_OK;
929}
930
a2b8659d
TC		 931struct pipe_ctx *find_idle_secondary_pipe(
932 struct resource_context *res_ctx,
933 const struct resource_pool *pool)
4562236b
HW		 934{
935 int i;
936 struct pipe_ctx *secondary_pipe = NULL;
937
938 /*
939 * search backwards for the second pipe to keep pipe
940 * assignment more consistent
941 */
942
a2b8659d 943 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 944 if (res_ctx->pipe_ctx[i].stream == NULL) {
945 secondary_pipe = &res_ctx->pipe_ctx[i];
946 secondary_pipe->pipe_idx = i;
947 break;
948 }
949 }
950
951
952 return secondary_pipe;
953}
954
955struct pipe_ctx *resource_get_head_pipe_for_stream(
956 struct resource_context *res_ctx,
0971c40e 957 struct dc_stream_state *stream)
4562236b
HW		 958{
959 int i;
a2b8659d 960 for (i = 0; i < MAX_PIPES; i++) {
4562236b 961 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 962 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 963 return &res_ctx->pipe_ctx[i];
964 break;
965 }
966 }
967 return NULL;
968}
969
19f89e23
AG		 970static struct pipe_ctx *resource_get_tail_pipe_for_stream(
971 struct resource_context *res_ctx,
972 struct dc_stream_state *stream)
973{
974 struct pipe_ctx *head_pipe, *tail_pipe;
975 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
976
977 if (!head_pipe)
978 return NULL;
979
980 tail_pipe = head_pipe->bottom_pipe;
981
982 while (tail_pipe) {
983 head_pipe = tail_pipe;
984 tail_pipe = tail_pipe->bottom_pipe;
985 }
986
987 return head_pipe;
988}
989
4562236b 990/*
ab2541b6
AC		 991 * A free_pipe for a stream is defined here as a pipe
992 * that has no surface attached yet
4562236b 993 */
ab2541b6 994static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 995 struct dc_state *context,
a2b8659d 996 const struct resource_pool *pool,
0971c40e 997 struct dc_stream_state *stream)
4562236b
HW		 998{
999 int i;
745cc746 1000 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1001
1002 struct pipe_ctx *head_pipe = NULL;
1003
1004 /* Find head pipe, which has the back end set up*/
1005
1006 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1007
e41ab030 1008 if (!head_pipe) {
4562236b 1009 ASSERT(0);
e41ab030
HW		 1010 return NULL;
1011 }
4562236b 1012
3be5262e 1013 if (!head_pipe->plane_state)
4562236b
HW		 1014 return head_pipe;
1015
1016 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1017 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1018 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1019 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1020 return &res_ctx->pipe_ctx[i];
1021 }
1022 }
1023
1024 /*
1025 * At this point we have no re-useable pipe for this stream and we need
1026 * to acquire an idle one to satisfy the request
1027 */
1028
a2b8659d 1029 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1030 return NULL;
1031
a2b8659d 1032 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1033
1034}
1035
0f9a536f
DL		 1036#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1037static int acquire_first_split_pipe(
1038 struct resource_context *res_ctx,
1039 const struct resource_pool *pool,
0971c40e 1040 struct dc_stream_state *stream)
0f9a536f
DL		 1041{
1042 int i;
1043
1044 for (i = 0; i < pool->pipe_count; i++) {
1045 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1046
1047 if (pipe_ctx->top_pipe &&
3be5262e 1048 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1049 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1050 if (pipe_ctx->bottom_pipe)
1051 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1052
1053 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1054 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1055 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1056 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1057 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1058 pipe_ctx->stream_res.opp = pool->opps[i];
e07f541f 1059 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
0f9a536f 1060 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1061
1062 pipe_ctx->stream = stream;
1063 return i;
1064 }
1065 }
1066 return -1;
1067}
1068#endif
1069
19f89e23
AG		 1070bool dc_add_plane_to_context(
1071 const struct dc *dc,
0971c40e 1072 struct dc_stream_state *stream,
19f89e23 1073 struct dc_plane_state *plane_state,
608ac7bb 1074 struct dc_state *context)
4562236b
HW		 1075{
1076 int i;
19f89e23
AG		 1077 struct resource_pool *pool = dc->res_pool;
1078 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1079 struct dc_stream_status *stream_status = NULL;
4562236b 1080
19f89e23
AG		 1081 for (i = 0; i < context->stream_count; i++)
1082 if (context->streams[i] == stream) {
1083 stream_status = &context->stream_status[i];
1084 break;
1085 }
1086 if (stream_status == NULL) {
1087 dm_error("Existing stream not found; failed to attach surface!\n");
1088 return false;
1089 }
1090
4562236b 1091
19f89e23
AG		 1092 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1093 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1094 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1095 return false;
1096 }
1097
19f89e23
AG		 1098 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1099
1100 if (!head_pipe) {
1101 dm_error("Head pipe not found for stream_state %p !\n", stream);
1102 return false;
1103 }
1104
19f89e23
AG		 1105 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1106
1107#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1108 if (!free_pipe) {
1109 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1110 if (pipe_idx >= 0)
1111 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1112 }
1113#endif
abb4986e 1114 if (!free_pipe)
19f89e23 1115 return false;
19f89e23 1116
abb4986e
AJ		 1117 /* retain new surfaces */
1118 dc_plane_state_retain(plane_state);
19f89e23
AG		 1119 free_pipe->plane_state = plane_state;
1120
1121 if (head_pipe != free_pipe) {
1122
1123 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1124 ASSERT(tail_pipe);
1125
1126 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1127 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1128 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1129 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1130 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1131 free_pipe->clock_source = tail_pipe->clock_source;
1132 free_pipe->top_pipe = tail_pipe;
1133 tail_pipe->bottom_pipe = free_pipe;
1134 }
1135
1136 /* assign new surfaces*/
1137 stream_status->plane_states[stream_status->plane_count] = plane_state;
1138
1139 stream_status->plane_count++;
1140
1141 return true;
1142}
1143
1144bool dc_remove_plane_from_context(
1145 const struct dc *dc,
1146 struct dc_stream_state *stream,
1147 struct dc_plane_state *plane_state,
608ac7bb 1148 struct dc_state *context)
19f89e23
AG		 1149{
1150 int i;
1151 struct dc_stream_status *stream_status = NULL;
1152 struct resource_pool *pool = dc->res_pool;
1153
ab2541b6 1154 for (i = 0; i < context->stream_count; i++)
4fa086b9 1155 if (context->streams[i] == stream) {
ab2541b6 1156 stream_status = &context->stream_status[i];
4562236b
HW		 1157 break;
1158 }
19f89e23 1159
ab2541b6 1160 if (stream_status == NULL) {
19f89e23 1161 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1162 return false;
1163 }
1164
19f89e23
AG		 1165 /* release pipe for plane*/
1166 for (i = pool->pipe_count - 1; i >= 0; i--) {
1167 struct pipe_ctx *pipe_ctx;
4562236b 1168
19f89e23
AG		 1169 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1170 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1171
19f89e23
AG		 1172 if (pipe_ctx->top_pipe)
1173 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1174
19f89e23
AG		 1175 /* Second condition is to avoid setting NULL to top pipe
1176 * of tail pipe making it look like head pipe in subsequent
1177 * deletes
1178 */
1179 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1180 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1181
19f89e23
AG		 1182 /*
1183 * For head pipe detach surfaces from pipe for tail
1184 * pipe just zero it out
1185 */
1186 if (!pipe_ctx->top_pipe) {
1187 pipe_ctx->plane_state = NULL;
1188 pipe_ctx->bottom_pipe = NULL;
1189 } else {
1190 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1191 }
4562236b 1192 }
19f89e23 1193 }
4562236b 1194
4562236b 1195
19f89e23
AG		 1196 for (i = 0; i < stream_status->plane_count; i++) {
1197 if (stream_status->plane_states[i] == plane_state) {
1198
1199 dc_plane_state_release(stream_status->plane_states[i]);
1200 break;
4562236b 1201 }
19f89e23 1202 }
4562236b 1203
19f89e23
AG		 1204 if (i == stream_status->plane_count) {
1205 dm_error("Existing plane_state not found; failed to detach it!\n");
1206 return false;
4562236b
HW		 1207 }
1208
19f89e23 1209 stream_status->plane_count--;
4562236b 1210
abb4986e
AJ		 1211 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1212 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1213 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1214
1215 stream_status->plane_states[stream_status->plane_count] = NULL;
1216
1217 return true;
1218}
1219
1220bool dc_rem_all_planes_for_stream(
1221 const struct dc *dc,
1222 struct dc_stream_state *stream,
608ac7bb 1223 struct dc_state *context)
19f89e23
AG		 1224{
1225 int i, old_plane_count;
1226 struct dc_stream_status *stream_status = NULL;
1227 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1228
1229 for (i = 0; i < context->stream_count; i++)
1230 if (context->streams[i] == stream) {
1231 stream_status = &context->stream_status[i];
1232 break;
1233 }
1234
1235 if (stream_status == NULL) {
1236 dm_error("Existing stream %p not found!\n", stream);
1237 return false;
1238 }
1239
1240 old_plane_count = stream_status->plane_count;
1241
1242 for (i = 0; i < old_plane_count; i++)
1243 del_planes[i] = stream_status->plane_states[i];
1244
1245 for (i = 0; i < old_plane_count; i++)
1246 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1247 return false;
1248
1249 return true;
1250}
1251
1252static bool add_all_planes_for_stream(
1253 const struct dc *dc,
1254 struct dc_stream_state *stream,
1255 const struct dc_validation_set set[],
1256 int set_count,
608ac7bb 1257 struct dc_state *context)
19f89e23
AG		 1258{
1259 int i, j;
1260
1261 for (i = 0; i < set_count; i++)
1262 if (set[i].stream == stream)
1263 break;
1264
1265 if (i == set_count) {
1266 dm_error("Stream %p not found in set!\n", stream);
1267 return false;
1268 }
4562236b 1269
19f89e23
AG		 1270 for (j = 0; j < set[i].plane_count; j++)
1271 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1272 return false;
4562236b
HW		 1273
1274 return true;
1275}
1276
19f89e23
AG		 1277bool dc_add_all_planes_for_stream(
1278 const struct dc *dc,
1279 struct dc_stream_state *stream,
1280 struct dc_plane_state * const *plane_states,
1281 int plane_count,
608ac7bb 1282 struct dc_state *context)
19f89e23
AG		 1283{
1284 struct dc_validation_set set;
1285 int i;
1286
1287 set.stream = stream;
1288 set.plane_count = plane_count;
1289
1290 for (i = 0; i < plane_count; i++)
1291 set.plane_states[i] = plane_states[i];
1292
1293 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1294}
1295
1296
4562236b 1297
0971c40e
HW		 1298static bool is_timing_changed(struct dc_stream_state *cur_stream,
1299 struct dc_stream_state *new_stream)
4562236b
HW		 1300{
1301 if (cur_stream == NULL)
1302 return true;
1303
1304 /* If sink pointer changed, it means this is a hotplug, we should do
1305 * full hw setting.
1306 */
1307 if (cur_stream->sink != new_stream->sink)
1308 return true;
1309
1310 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1311 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1312 return true;
1313
1314 return memcmp(
4fa086b9
LSL		 1315 &cur_stream->timing,
1316 &new_stream->timing,
4562236b
HW		 1317 sizeof(struct dc_crtc_timing)) != 0;
1318}
1319
1320static bool are_stream_backends_same(
0971c40e 1321 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1322{
1323 if (stream_a == stream_b)
1324 return true;
1325
1326 if (stream_a == NULL || stream_b == NULL)
1327 return false;
1328
1329 if (is_timing_changed(stream_a, stream_b))
1330 return false;
1331
1332 return true;
1333}
1334
d54d29db 1335bool dc_is_stream_unchanged(
0971c40e 1336 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1337{
4562236b 1338
ab2541b6
AC		 1339 if (!are_stream_backends_same(old_stream, stream))
1340 return false;
4562236b
HW		 1341
1342 return true;
1343}
1344
9a5d9c48
LSL		 1345bool dc_is_stream_scaling_unchanged(
1346 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1347{
1348 if (old_stream == stream)
1349 return true;
1350
1351 if (old_stream == NULL || stream == NULL)
1352 return false;
1353
1354 if (memcmp(&old_stream->src,
1355 &stream->src,
1356 sizeof(struct rect)) != 0)
1357 return false;
1358
1359 if (memcmp(&old_stream->dst,
1360 &stream->dst,
1361 sizeof(struct rect)) != 0)
1362 return false;
1363
1364 return true;
1365}
1366
1dc90497 1367static void update_stream_engine_usage(
4562236b 1368 struct resource_context *res_ctx,
a2b8659d 1369 const struct resource_pool *pool,
1dc90497
AG		 1370 struct stream_encoder *stream_enc,
1371 bool acquired)
4562236b
HW		 1372{
1373 int i;
1374
a2b8659d
TC		 1375 for (i = 0; i < pool->stream_enc_count; i++) {
1376 if (pool->stream_enc[i] == stream_enc)
1dc90497 1377 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1378 }
1379}
1380
1381/* TODO: release audio object */
4176664b 1382void update_audio_usage(
4562236b 1383 struct resource_context *res_ctx,
a2b8659d 1384 const struct resource_pool *pool,
1dc90497
AG		 1385 struct audio *audio,
1386 bool acquired)
4562236b
HW		 1387{
1388 int i;
a2b8659d
TC		 1389 for (i = 0; i < pool->audio_count; i++) {
1390 if (pool->audios[i] == audio)
1dc90497 1391 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1392 }
1393}
1394
1395static int acquire_first_free_pipe(
1396 struct resource_context *res_ctx,
a2b8659d 1397 const struct resource_pool *pool,
0971c40e 1398 struct dc_stream_state *stream)
4562236b
HW		 1399{
1400 int i;
1401
a2b8659d 1402 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1403 if (!res_ctx->pipe_ctx[i].stream) {
1404 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1405
6b670fa9 1406 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1407 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1408 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1409 pipe_ctx->plane_res.ipp = pool->ipps[i];
1410 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1411 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1412 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1413 if (pool->dpps[i])
1414 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1415 pipe_ctx->pipe_idx = i;
1416
ff5ef992 1417
4562236b
HW		 1418 pipe_ctx->stream = stream;
1419 return i;
1420 }
1421 }
1422 return -1;
1423}
1424
1425static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1426 struct resource_context *res_ctx,
a2b8659d 1427 const struct resource_pool *pool,
0971c40e 1428 struct dc_stream_state *stream)
4562236b
HW		 1429{
1430 int i;
1431 int j = -1;
d0778ebf 1432 struct dc_link *link = stream->sink->link;
4562236b 1433
a2b8659d 1434 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1435 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1436 pool->stream_enc[i]) {
4562236b
HW		 1437 /* Store first available for MST second display
1438 * in daisy chain use case */
1439 j = i;
a2b8659d 1440 if (pool->stream_enc[i]->id ==
4562236b 1441 link->link_enc->preferred_engine)
a2b8659d 1442 return pool->stream_enc[i];
4562236b
HW		 1443 }
1444 }
1445
1446 /*
1447 * below can happen in cases when stream encoder is acquired:
1448 * 1) for second MST display in chain, so preferred engine already
1449 * acquired;
1450 * 2) for another link, which preferred engine already acquired by any
1451 * MST configuration.
1452 *
1453 * If signal is of DP type and preferred engine not found, return last available
1454 *
1455 * TODO - This is just a patch up and a generic solution is
1456 * required for non DP connectors.
1457 */
1458
1459 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1460 return pool->stream_enc[j];
4562236b
HW		 1461
1462 return NULL;
1463}
1464
a2b8659d
TC		 1465static struct audio *find_first_free_audio(
1466 struct resource_context *res_ctx,
cfb071f7
CL		 1467 const struct resource_pool *pool,
1468 enum engine_id id)
4562236b
HW		 1469{
1470 int i;
66bfd4fd
CL		 1471 for (i = 0; i < pool->audio_count; i++) {
1472 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1473 /*we have enough audio endpoint, find the matching inst*/
1474 if (id != i)
1475 continue;
1476
66bfd4fd 1477 return pool->audios[i];
4562236b 1478 }
66bfd4fd
CL		 1479 }
1480 /*not found the matching one, first come first serve*/
1481 for (i = 0; i < pool->audio_count; i++) {
1482 if (res_ctx->is_audio_acquired[i] == false) {
1483 return pool->audios[i];
4176664b
CL		 1484 }
1485 }
4562236b
HW		 1486 return 0;
1487}
1488
4562236b 1489bool resource_is_stream_unchanged(
608ac7bb 1490 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1491{
ab2541b6 1492 int i;
4562236b 1493
ab2541b6 1494 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1495 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1496
ab2541b6 1497 if (are_stream_backends_same(old_stream, stream))
4562236b 1498 return true;
4562236b
HW		 1499 }
1500
1501 return false;
1502}
1503
13ab1b44 1504enum dc_status dc_add_stream_to_ctx(
1dc90497 1505 struct dc *dc,
608ac7bb 1506 struct dc_state *new_ctx,
1dc90497
AG		 1507 struct dc_stream_state *stream)
1508{
1509 struct dc_context *dc_ctx = dc->ctx;
1510 enum dc_status res;
1511
1512 if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
1513 DC_ERROR("Max streams reached, can add stream %p !\n", stream);
1514 return DC_ERROR_UNEXPECTED;
1515 }
1516
1517 new_ctx->streams[new_ctx->stream_count] = stream;
1518 dc_stream_retain(stream);
1519 new_ctx->stream_count++;
1520
1521 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1522 if (res != DC_OK)
1523 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1524
13ab1b44 1525 return res;
1dc90497
AG		 1526}
1527
62c933f9 1528enum dc_status dc_remove_stream_from_ctx(
1dc90497 1529 struct dc *dc,
608ac7bb 1530 struct dc_state *new_ctx,
1dc90497
AG		 1531 struct dc_stream_state *stream)
1532{
19f89e23 1533 int i;
1dc90497
AG		 1534 struct dc_context *dc_ctx = dc->ctx;
1535 struct pipe_ctx *del_pipe = NULL;
1536
19f89e23 1537 /* Release primary pipe */
1dc90497 1538 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1539 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1540 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1541 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1542
19f89e23
AG		 1543 ASSERT(del_pipe->stream_res.stream_enc);
1544 update_stream_engine_usage(
1545 &new_ctx->res_ctx,
1dc90497 1546 dc->res_pool,
19f89e23
AG		 1547 del_pipe->stream_res.stream_enc,
1548 false);
1dc90497
AG		 1549
1550 if (del_pipe->stream_res.audio)
1551 update_audio_usage(
1552 &new_ctx->res_ctx,
1553 dc->res_pool,
1554 del_pipe->stream_res.audio,
1555 false);
1556
9d0dcecd
HW		 1557 resource_unreference_clock_source(&new_ctx->res_ctx,
1558 dc->res_pool,
1559 del_pipe->clock_source);
1560
e56ae556
NC		 1561 if (dc->res_pool->funcs->remove_stream_from_ctx)
1562 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1563
1dc90497 1564 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG		 1565
1566 break;
1dc90497
AG		 1567 }
1568 }
1569
1570 if (!del_pipe) {
1571 DC_ERROR("Pipe not found for stream %p !\n", stream);
1572 return DC_ERROR_UNEXPECTED;
1573 }
1574
1575 for (i = 0; i < new_ctx->stream_count; i++)
1576 if (new_ctx->streams[i] == stream)
1577 break;
1578
1579 if (new_ctx->streams[i] != stream) {
1580 DC_ERROR("Context doesn't have stream %p !\n", stream);
1581 return DC_ERROR_UNEXPECTED;
1582 }
1583
1584 dc_stream_release(new_ctx->streams[i]);
1585 new_ctx->stream_count--;
1586
1dc90497
AG		 1587 /* Trim back arrays */
1588 for (; i < new_ctx->stream_count; i++) {
1589 new_ctx->streams[i] = new_ctx->streams[i + 1];
1590 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1591 }
1592
1593 new_ctx->streams[new_ctx->stream_count] = NULL;
1594 memset(
1595 &new_ctx->stream_status[new_ctx->stream_count],
1596 0,
1597 sizeof(new_ctx->stream_status[0]));
1598
1599 return DC_OK;
1600}
1601
0971c40e
HW		 1602static struct dc_stream_state *find_pll_sharable_stream(
1603 struct dc_stream_state *stream_needs_pll,
608ac7bb 1604 struct dc_state *context)
4562236b 1605{
ab2541b6 1606 int i;
4562236b 1607
ab2541b6 1608 for (i = 0; i < context->stream_count; i++) {
0971c40e 1609 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1610
ab2541b6
AC		 1611 /* We are looking for non dp, non virtual stream */
1612 if (resource_are_streams_timing_synchronizable(
1613 stream_needs_pll, stream_has_pll)
1614 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1615 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1616 != SIGNAL_TYPE_VIRTUAL)
1617 return stream_has_pll;
4562236b 1618
4562236b
HW		 1619 }
1620
1621 return NULL;
1622}
1623
1624static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1625{
1626 uint32_t pix_clk = timing->pix_clk_khz;
1627 uint32_t normalized_pix_clk = pix_clk;
1628
1629 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1630 pix_clk /= 2;
cc4d99b8
CL		 1631 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1632 switch (timing->display_color_depth) {
1633 case COLOR_DEPTH_888:
1634 normalized_pix_clk = pix_clk;
1635 break;
1636 case COLOR_DEPTH_101010:
1637 normalized_pix_clk = (pix_clk * 30) / 24;
1638 break;
1639 case COLOR_DEPTH_121212:
1640 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1641 break;
cc4d99b8
CL		 1642 case COLOR_DEPTH_161616:
1643 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1644 break;
cc4d99b8
CL		 1645 default:
1646 ASSERT(0);
4562236b 1647 break;
cc4d99b8 1648 }
4562236b 1649 }
4562236b
HW		 1650 return normalized_pix_clk;
1651}
1652
0971c40e 1653static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1654{
9345d987
AG		 1655 /* update actual pixel clock on all streams */
1656 if (dc_is_hdmi_signal(stream->signal))
1657 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1658 &stream->timing);
9345d987
AG		 1659 else
1660 stream->phy_pix_clk =
4fa086b9 1661 stream->timing.pix_clk_khz;
4562236b
HW		 1662}
1663
1664enum dc_status resource_map_pool_resources(
fb3466a4 1665 const struct dc *dc,
608ac7bb 1666 struct dc_state *context,
1dc90497 1667 struct dc_stream_state *stream)
4562236b 1668{
a2b8659d 1669 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1670 int i;
1671 struct dc_context *dc_ctx = dc->ctx;
1672 struct pipe_ctx *pipe_ctx = NULL;
1673 int pipe_idx = -1;
4562236b 1674
1dc90497
AG		 1675 /* TODO Check if this is needed */
1676 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1677 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1678 stream->bit_depth_params =
430ef426
DL		 1679 old_context->streams[i]->bit_depth_params;
1680 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1681 continue;
1682 }
4b679bc3 1683 }
1dc90497 1684 */
7e2fe319 1685
1dc90497
AG		 1686 /* acquire new resources */
1687 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1688
94c6d735 1689#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1690 if (pipe_idx < 0)
13ab1b44 1691 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1692#endif
13ab1b44 1693
1dc90497
AG		 1694 if (pipe_idx < 0)
1695 return DC_NO_CONTROLLER_RESOURCE;
1696
1697 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1698
1699 pipe_ctx->stream_res.stream_enc =
1700 find_first_free_match_stream_enc_for_link(
1701 &context->res_ctx, pool, stream);
1702
1703 if (!pipe_ctx->stream_res.stream_enc)
1704 return DC_NO_STREAM_ENG_RESOURCE;
1705
1706 update_stream_engine_usage(
1707 &context->res_ctx, pool,
1708 pipe_ctx->stream_res.stream_enc,
1709 true);
1710
1711 /* TODO: Add check if ASIC support and EDID audio */
1712 if (!stream->sink->converter_disable_audio &&
1713 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1714 stream->audio_info.mode_count) {
1715 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1716 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1717
1718 /*
1719 * Audio assigned in order first come first get.
1720 * There are asics which has number of audio
1721 * resources less then number of pipes
1722 */
1723 if (pipe_ctx->stream_res.audio)
1724 update_audio_usage(&context->res_ctx, pool,
1725 pipe_ctx->stream_res.audio, true);
1726 }
268cadbd 1727
9aef1a31
S		 1728 /* Add ABM to the resource if on EDP */
1729 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1730 pipe_ctx->stream_res.abm = pool->abm;
1731
1dc90497
AG		 1732 for (i = 0; i < context->stream_count; i++)
1733 if (context->streams[i] == stream) {
1734 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1735 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1736 return DC_OK;
1737 }
4562236b 1738
1dc90497
AG		 1739 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1740 return DC_ERROR_UNEXPECTED;
1741}
4562236b 1742
f36cc577 1743void dc_resource_state_copy_construct_current(
1dc90497 1744 const struct dc *dc,
608ac7bb 1745 struct dc_state *dst_ctx)
1dc90497 1746{
f36cc577 1747 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1748}
1749
ab8db3e1
AG		 1750
1751void dc_resource_state_construct(
1752 const struct dc *dc,
1753 struct dc_state *dst_ctx)
1754{
1755 dst_ctx->dis_clk = dc->res_pool->display_clock;
1756}
1757
e750d56d 1758enum dc_status dc_validate_global_state(
1dc90497 1759 struct dc *dc,
608ac7bb 1760 struct dc_state *new_ctx)
4562236b 1761{
1dc90497 1762 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1763 int i, j;
4562236b 1764
e41ab030
HW		 1765 if (!new_ctx)
1766 return DC_ERROR_UNEXPECTED;
1767
d596e5d0
YS		 1768 if (dc->res_pool->funcs->validate_global) {
1769 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1770 if (result != DC_OK)
1771 return result;
1772 }
4562236b 1773
e41ab030 1774 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 1775 struct dc_stream_state *stream = new_ctx->streams[i];
1776
1777 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1778 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1779
1780 if (pipe_ctx->stream != stream)
1781 continue;
1782
1783 /* Switch to dp clock source only if there is
1784 * no non dp stream that shares the same timing
1785 * with the dp stream.
1786 */
1787 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1788 !find_pll_sharable_stream(stream, new_ctx)) {
1789
9d0dcecd 1790 resource_unreference_clock_source(
1dc90497
AG		 1791 &new_ctx->res_ctx,
1792 dc->res_pool,
9d0dcecd 1793 pipe_ctx->clock_source);
4a629536 1794
1dc90497
AG		 1795 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1796 resource_reference_clock_source(
1797 &new_ctx->res_ctx,
1798 dc->res_pool,
1799 pipe_ctx->clock_source);
1800 }
1801 }
1802 }
1803
1dc90497
AG		 1804 result = resource_build_scaling_params_for_context(dc, new_ctx);
1805
1806 if (result == DC_OK)
1807 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1808 result = DC_FAIL_BANDWIDTH_VALIDATE;
1809
1810 return result;
4562236b
HW		 1811}
1812
6e4d6bee 1813static void patch_gamut_packet_checksum(
e09b6473 1814 struct dc_info_packet *gamut_packet)
4562236b 1815{
4562236b 1816 /* For gamut we recalc checksum */
6e4d6bee 1817 if (gamut_packet->valid) {
4562236b
HW		 1818 uint8_t chk_sum = 0;
1819 uint8_t *ptr;
1820 uint8_t i;
1821
4562236b 1822 /*start of the Gamut data. */
6e4d6bee 1823 ptr = &gamut_packet->sb[3];
4562236b 1824
6e4d6bee 1825 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1826 chk_sum += ptr[i];
1827
6e4d6bee 1828 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1829 }
4562236b
HW		 1830}
1831
1832static void set_avi_info_frame(
e09b6473 1833 struct dc_info_packet *info_packet,
4562236b
HW		 1834 struct pipe_ctx *pipe_ctx)
1835{
0971c40e 1836 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 1837 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 1838 uint32_t pixel_encoding = 0;
1839 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1840 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1841 bool itc = false;
50e27654 1842 uint8_t itc_value = 0;
4562236b 1843 uint8_t cn0_cn1 = 0;
50e27654 1844 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1845 uint8_t *check_sum = NULL;
1846 uint8_t byte_index = 0;
e09b6473 1847 union hdmi_info_packet hdmi_info = {0};
50e27654 1848 union display_content_support support = {0};
4fa086b9 1849 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 1850 enum dc_timing_3d_format format;
4562236b 1851
4fa086b9 1852 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 1853 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 1854 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 1855 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1856
1857 /* Initialize header */
e09b6473 1858 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1859 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1860 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 1861 hdmi_info.bits.header.version = 2;
1862 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1863
1864 /*
1865 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1866 * according to HDMI 2.0 spec (Section 10.1)
1867 */
1868
4fa086b9 1869 switch (stream->timing.pixel_encoding) {
4562236b
HW		 1870 case PIXEL_ENCODING_YCBCR422:
1871 pixel_encoding = 1;
1872 break;
1873
1874 case PIXEL_ENCODING_YCBCR444:
1875 pixel_encoding = 2;
1876 break;
1877 case PIXEL_ENCODING_YCBCR420:
1878 pixel_encoding = 3;
1879 break;
1880
1881 case PIXEL_ENCODING_RGB:
1882 default:
1883 pixel_encoding = 0;
1884 }
1885
1886 /* Y0_Y1_Y2 : The pixel encoding */
1887 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 1888 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1889
1890 /* A0 = 1 Active Format Information valid */
e09b6473 1891 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1892
1893 /* B0, B1 = 3; Bar info data is valid */
e09b6473 1894 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1895
e09b6473 1896 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1897
1898 /* S0, S1 : Underscan / Overscan */
1899 /* TODO: un-hardcode scan type */
1900 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 1901 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 1902
1903 /* C0, C1 : Colorimetry */
8fde5884 1904 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1905 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 1906 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1907 else if (color_space == COLOR_SPACE_YCBCR601 ||
1908 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 1909 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 1910 else {
e09b6473 1911 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1912 }
534db198 1913 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1914 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1915 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 1916 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1917 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1918 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 1919 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1920 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1921 }
1922
4562236b 1923 /* TODO: un-hardcode aspect ratio */
4fa086b9 1924 aspect = stream->timing.aspect_ratio;
4562236b
HW		 1925
1926 switch (aspect) {
1927 case ASPECT_RATIO_4_3:
1928 case ASPECT_RATIO_16_9:
e09b6473 1929 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 1930 break;
1931
1932 case ASPECT_RATIO_NO_DATA:
1933 case ASPECT_RATIO_64_27:
1934 case ASPECT_RATIO_256_135:
1935 default:
e09b6473 1936 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 1937 }
1938
1939 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 1940 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1941
1942 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1943
4562236b 1944 cn0_cn1 = 0;
50e27654
ZF		 1945 cn0_cn1_value = 0;
1946
1947 itc = true;
1948 itc_value = 1;
1949
4fa086b9 1950 support = stream->sink->edid_caps.content_support;
4562236b
HW		 1951
1952 if (itc) {
50e27654
ZF		 1953 if (!support.bits.valid_content_type) {
1954 cn0_cn1_value = 0;
1955 } else {
1956 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1957 if (support.bits.graphics_content == 1) {
1958 cn0_cn1_value = 0;
1959 }
1960 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1961 if (support.bits.photo_content == 1) {
1962 cn0_cn1_value = 1;
1963 } else {
1964 cn0_cn1_value = 0;
1965 itc_value = 0;
1966 }
1967 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1968 if (support.bits.cinema_content == 1) {
1969 cn0_cn1_value = 2;
1970 } else {
1971 cn0_cn1_value = 0;
1972 itc_value = 0;
1973 }
1974 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
1975 if (support.bits.game_content == 1) {
1976 cn0_cn1_value = 3;
1977 } else {
1978 cn0_cn1_value = 0;
1979 itc_value = 0;
1980 }
1981 }
1982 }
e09b6473
AK		 1983 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
1984 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 1985 }
1986
1987 /* TODO : We should handle YCC quantization */
1988 /* but we do not have matrix calculation */
4fa086b9
LSL		 1989 if (stream->sink->edid_caps.qs_bit == 1 &&
1990 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 1991 if (color_space == COLOR_SPACE_SRGB ||
1992 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 1993 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1994 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 1995 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
1996 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 1997 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1998 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 1999 } else {
e09b6473
AK		 2000 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2001 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2002 }
4562236b 2003 } else {
e09b6473
AK		 2004 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2005 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2006 }
50e27654 2007
15e17335 2008 ///VIC
4fa086b9 2009 format = stream->timing.timing_3d_format;
15e17335
CL		 2010 /*todo, add 3DStereo support*/
2011 if (format != TIMING_3D_FORMAT_NONE) {
2012 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2013 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2014 case 1:
2015 vic = 95;
2016 break;
2017 case 2:
2018 vic = 94;
2019 break;
2020 case 3:
2021 vic = 93;
2022 break;
2023 case 4:
2024 vic = 98;
2025 break;
2026 default:
2027 break;
2028 }
2029 }
e09b6473 2030 hdmi_info.bits.VIC0_VIC7 = vic;
4562236b
HW		 2031
2032 /* pixel repetition
2033 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2034 * repetition start from 1 */
e09b6473 2035 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2036
2037 /* Bar Info
2038 * barTop: Line Number of End of Top Bar.
2039 * barBottom: Line Number of Start of Bottom Bar.
2040 * barLeft: Pixel Number of End of Left Bar.
2041 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2042 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2043 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2044 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2045 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2046 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2047 - stream->timing.h_border_right + 1);
4562236b
HW		 2048
2049 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2050 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2051
3e183c5f 2052 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2053
3e183c5f 2054 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e09b6473 2055 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2056
2057 /* one byte complement */
2058 *check_sum = (uint8_t) (0x100 - *check_sum);
2059
2060 /* Store in hw_path_mode */
e09b6473
AK		 2061 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2062 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2063 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2064
e09b6473
AK		 2065 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2066 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2067
2068 info_packet->valid = true;
2069}
2070
6e4d6bee 2071static void set_vendor_info_packet(
e09b6473 2072 struct dc_info_packet *info_packet,
0971c40e 2073 struct dc_stream_state *stream)
4562236b
HW		 2074{
2075 uint32_t length = 0;
2076 bool hdmi_vic_mode = false;
2077 uint8_t checksum = 0;
2078 uint32_t i = 0;
2079 enum dc_timing_3d_format format;
15e17335
CL		 2080 // Can be different depending on packet content /*todo*/
2081 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2082
2083 info_packet->valid = false;
4562236b 2084
4fa086b9
LSL		 2085 format = stream->timing.timing_3d_format;
2086 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2087 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2088
2089 /* Can be different depending on packet content */
2090 length = 5;
2091
4fa086b9
LSL		 2092 if (stream->timing.hdmi_vic != 0
2093 && stream->timing.h_total >= 3840
2094 && stream->timing.v_total >= 2160)
4562236b
HW		 2095 hdmi_vic_mode = true;
2096
2097 /* According to HDMI 1.4a CTS, VSIF should be sent
2098 * for both 3D stereo and HDMI VIC modes.
2099 * For all other modes, there is no VSIF sent. */
2100
2101 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2102 return;
2103
2104 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2105 info_packet->sb[1] = 0x03;
2106 info_packet->sb[2] = 0x0C;
2107 info_packet->sb[3] = 0x00;
2108
2109 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2110 * The value for HDMI_Video_Format are:
2111 * 0x0 (0b000) - No additional HDMI video format is presented in this
2112 * packet
2113 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2114 * parameter follows
2115 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2116 * potentially 3D_Ext_Data follows
2117 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2118 if (format != TIMING_3D_FORMAT_NONE)
2119 info_packet->sb[4] = (2 << 5);
2120 else if (hdmi_vic_mode)
2121 info_packet->sb[4] = (1 << 5);
2122
2123 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2124 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2125 * The value for 3D_Structure are:
2126 * 0x0 - Frame Packing
2127 * 0x1 - Field Alternative
2128 * 0x2 - Line Alternative
2129 * 0x3 - Side-by-Side (full)
2130 * 0x4 - L + depth
2131 * 0x5 - L + depth + graphics + graphics-depth
2132 * 0x6 - Top-and-Bottom
2133 * 0x7 - Reserved for future use
2134 * 0x8 - Side-by-Side (Half)
2135 * 0x9..0xE - Reserved for future use
2136 * 0xF - Not used */
2137 switch (format) {
2138 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2139 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2140 info_packet->sb[5] = (0x0 << 4);
2141 break;
2142
2143 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2144 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2145 info_packet->sb[5] = (0x8 << 4);
2146 length = 6;
2147 break;
2148
2149 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2150 case TIMING_3D_FORMAT_TB_SW_PACKED:
2151 info_packet->sb[5] = (0x6 << 4);
2152 break;
2153
2154 default:
2155 break;
2156 }
2157
2158 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2159 * fill PB5 with the correct HDMI VIC code */
2160 if (hdmi_vic_mode)
4fa086b9 2161 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2162
2163 /* Header */
3e183c5f 2164 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2165 info_packet->hb1 = 0x01; /* Version */
2166
2167 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2168 info_packet->hb2 = (uint8_t) (length);
2169
2170 /* Calculate checksum */
2171 checksum = 0;
2172 checksum += info_packet->hb0;
2173 checksum += info_packet->hb1;
2174 checksum += info_packet->hb2;
2175
2176 for (i = 1; i <= length; i++)
2177 checksum += info_packet->sb[i];
2178
2179 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2180
2181 info_packet->valid = true;
2182}
2183
6e4d6bee 2184static void set_spd_info_packet(
e09b6473 2185 struct dc_info_packet *info_packet,
0971c40e 2186 struct dc_stream_state *stream)
4562236b
HW		 2187{
2188 /* SPD info packet for FreeSync */
2189
2190 unsigned char checksum = 0;
2191 unsigned int idx, payload_size = 0;
2192
2193 /* Check if Freesync is supported. Return if false. If true,
2194 * set the corresponding bit in the info packet
2195 */
4fa086b9 2196 if (stream->freesync_ctx.supported == false)
4562236b
HW		 2197 return;
2198
2199 if (dc_is_hdmi_signal(stream->signal)) {
2200
2201 /* HEADER */
2202
2203 /* HB0 = Packet Type = 0x83 (Source Product
2204 * Descriptor InfoFrame)
2205 */
3e183c5f 2206 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2207
2208 /* HB1 = Version = 0x01 */
2209 info_packet->hb1 = 0x01;
2210
2211 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2212 info_packet->hb2 = 0x08;
2213
2214 payload_size = 0x08;
2215
2216 } else if (dc_is_dp_signal(stream->signal)) {
2217
2218 /* HEADER */
2219
2220 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2221 * when used to associate audio related info packets
2222 */
2223 info_packet->hb0 = 0x00;
2224
2225 /* HB1 = Packet Type = 0x83 (Source Product
2226 * Descriptor InfoFrame)
2227 */
3e183c5f 2228 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2229
2230 /* HB2 = [Bits 7:0 = Least significant eight bits -
2231 * For INFOFRAME, the value must be 1Bh]
2232 */
2233 info_packet->hb2 = 0x1B;
2234
2235 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2236 * [Bits 1:0 = Most significant two bits = 0x00]
2237 */
2238 info_packet->hb3 = 0x04;
2239
2240 payload_size = 0x1B;
2241 }
2242
2243 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2244 info_packet->sb[1] = 0x1A;
2245
2246 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2247 info_packet->sb[2] = 0x00;
2248
2249 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2250 info_packet->sb[3] = 0x00;
2251
2252 /* PB4 = Reserved */
2253 info_packet->sb[4] = 0x00;
2254
2255 /* PB5 = Reserved */
2256 info_packet->sb[5] = 0x00;
2257
2258 /* PB6 = [Bits 7:3 = Reserved] */
2259 info_packet->sb[6] = 0x00;
2260
4fa086b9 2261 if (stream->freesync_ctx.supported == true)
4562236b
HW		 2262 /* PB6 = [Bit 0 = FreeSync Supported] */
2263 info_packet->sb[6] |= 0x01;
2264
4fa086b9 2265 if (stream->freesync_ctx.enabled == true)
4562236b
HW		 2266 /* PB6 = [Bit 1 = FreeSync Enabled] */
2267 info_packet->sb[6] |= 0x02;
2268
4fa086b9 2269 if (stream->freesync_ctx.active == true)
4562236b
HW		 2270 /* PB6 = [Bit 2 = FreeSync Active] */
2271 info_packet->sb[6] |= 0x04;
2272
2273 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2274 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2275 min_refresh_in_micro_hz / 1000000);
2276
2277 /* PB8 = FreeSync Maximum refresh rate (Hz)
2278 *
2279 * Note: We do not use the maximum capable refresh rate
2280 * of the panel, because we should never go above the field
2281 * rate of the mode timing set.
2282 */
4fa086b9 2283 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2284 nominal_refresh_in_micro_hz / 1000000);
2285
2286 /* PB9 - PB27 = Reserved */
2287 for (idx = 9; idx <= 27; idx++)
2288 info_packet->sb[idx] = 0x00;
2289
2290 /* Calculate checksum */
2291 checksum += info_packet->hb0;
2292 checksum += info_packet->hb1;
2293 checksum += info_packet->hb2;
2294 checksum += info_packet->hb3;
2295
2296 for (idx = 1; idx <= payload_size; idx++)
2297 checksum += info_packet->sb[idx];
2298
2299 /* PB0 = Checksum (one byte complement) */
2300 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2301
2302 info_packet->valid = true;
2303}
2304
1646a6fe 2305static void set_hdr_static_info_packet(
e09b6473 2306 struct dc_info_packet *info_packet,
0971c40e 2307 struct dc_stream_state *stream)
1646a6fe 2308{
e5cf325b 2309 uint16_t i = 0;
1646a6fe 2310 enum signal_type signal = stream->signal;
e5cf325b 2311 uint32_t data;
1646a6fe 2312
56ef6ed9 2313 if (!stream->hdr_static_metadata.hdr_supported)
10bff005
YS		 2314 return;
2315
1646a6fe
AW		 2316 if (dc_is_hdmi_signal(signal)) {
2317 info_packet->valid = true;
2318
2319 info_packet->hb0 = 0x87;
2320 info_packet->hb1 = 0x01;
2321 info_packet->hb2 = 0x1A;
2322 i = 1;
2323 } else if (dc_is_dp_signal(signal)) {
2324 info_packet->valid = true;
2325
2326 info_packet->hb0 = 0x00;
2327 info_packet->hb1 = 0x87;
2328 info_packet->hb2 = 0x1D;
2329 info_packet->hb3 = (0x13 << 2);
2330 i = 2;
2331 }
2332
56ef6ed9 2333 data = stream->hdr_static_metadata.is_hdr;
1646a6fe
AW		 2334 info_packet->sb[i++] = data ? 0x02 : 0x00;
2335 info_packet->sb[i++] = 0x00;
2336
56ef6ed9 2337 data = stream->hdr_static_metadata.chromaticity_green_x / 2;
1646a6fe
AW		 2338 info_packet->sb[i++] = data & 0xFF;
2339 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2340
56ef6ed9 2341 data = stream->hdr_static_metadata.chromaticity_green_y / 2;
1646a6fe
AW		 2342 info_packet->sb[i++] = data & 0xFF;
2343 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2344
56ef6ed9 2345 data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
1646a6fe
AW		 2346 info_packet->sb[i++] = data & 0xFF;
2347 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2348
56ef6ed9 2349 data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
1646a6fe
AW		 2350 info_packet->sb[i++] = data & 0xFF;
2351 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2352
56ef6ed9 2353 data = stream->hdr_static_metadata.chromaticity_red_x / 2;
1646a6fe
AW		 2354 info_packet->sb[i++] = data & 0xFF;
2355 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2356
56ef6ed9 2357 data = stream->hdr_static_metadata.chromaticity_red_y / 2;
1646a6fe
AW		 2358 info_packet->sb[i++] = data & 0xFF;
2359 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2360
56ef6ed9 2361 data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
1646a6fe
AW		 2362 info_packet->sb[i++] = data & 0xFF;
2363 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2364
56ef6ed9 2365 data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
1646a6fe
AW		 2366 info_packet->sb[i++] = data & 0xFF;
2367 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2368
56ef6ed9 2369 data = stream->hdr_static_metadata.max_luminance;
1646a6fe
AW		 2370 info_packet->sb[i++] = data & 0xFF;
2371 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2372
56ef6ed9 2373 data = stream->hdr_static_metadata.min_luminance;
1646a6fe
AW		 2374 info_packet->sb[i++] = data & 0xFF;
2375 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2376
56ef6ed9 2377 data = stream->hdr_static_metadata.maximum_content_light_level;
1646a6fe
AW		 2378 info_packet->sb[i++] = data & 0xFF;
2379 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2380
56ef6ed9 2381 data = stream->hdr_static_metadata.maximum_frame_average_light_level;
1646a6fe
AW		 2382 info_packet->sb[i++] = data & 0xFF;
2383 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2384
2385 if (dc_is_hdmi_signal(signal)) {
2386 uint32_t checksum = 0;
2387
2388 checksum += info_packet->hb0;
2389 checksum += info_packet->hb1;
2390 checksum += info_packet->hb2;
2391
2392 for (i = 1; i <= info_packet->hb2; i++)
2393 checksum += info_packet->sb[i];
2394
2395 info_packet->sb[0] = 0x100 - checksum;
2396 } else if (dc_is_dp_signal(signal)) {
2397 info_packet->sb[0] = 0x01;
2398 info_packet->sb[1] = 0x1A;
2399 }
2400}
2401
6e4d6bee 2402static void set_vsc_info_packet(
e09b6473 2403 struct dc_info_packet *info_packet,
0971c40e 2404 struct dc_stream_state *stream)
4562236b
HW		 2405{
2406 unsigned int vscPacketRevision = 0;
2407 unsigned int i;
2408
3b94a400 2409 /*VSC packet set to 2 when DP revision >= 1.2*/
85075fa0 2410 if (stream->psr_version != 0) {
4562236b
HW		 2411 vscPacketRevision = 2;
2412 }
2413
2414 /* VSC packet not needed based on the features
2415 * supported by this DP display
2416 */
2417 if (vscPacketRevision == 0)
2418 return;
2419
2420 if (vscPacketRevision == 0x2) {
2421 /* Secondary-data Packet ID = 0*/
2422 info_packet->hb0 = 0x00;
2423 /* 07h - Packet Type Value indicating Video
2424 * Stream Configuration packet
2425 */
2426 info_packet->hb1 = 0x07;
2427 /* 02h = VSC SDP supporting 3D stereo and PSR
2428 * (applies to eDP v1.3 or higher).
2429 */
2430 info_packet->hb2 = 0x02;
2431 /* 08h = VSC packet supporting 3D stereo + PSR
2432 * (HB2 = 02h).
2433 */
2434 info_packet->hb3 = 0x08;
2435
2436 for (i = 0; i < 28; i++)
2437 info_packet->sb[i] = 0;
2438
2439 info_packet->valid = true;
2440 }
2441
2442 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2443}
2444
f36cc577 2445void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2446{
2447 int i, j;
2448
ab2541b6 2449 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2450 for (j = 0; j < context->stream_status[i].plane_count; j++)
2451 dc_plane_state_release(
2452 context->stream_status[i].plane_states[j]);
4562236b 2453
3be5262e 2454 context->stream_status[i].plane_count = 0;
4fa086b9 2455 dc_stream_release(context->streams[i]);
ab2541b6 2456 context->streams[i] = NULL;
4562236b
HW		 2457 }
2458}
2459
2460/*
ab2541b6 2461 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2462 * by the src_ctx
2463 */
f36cc577 2464void dc_resource_state_copy_construct(
608ac7bb
JZ		 2465 const struct dc_state *src_ctx,
2466 struct dc_state *dst_ctx)
4562236b
HW		 2467{
2468 int i, j;
8ee5702a 2469 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2470
2471 *dst_ctx = *src_ctx;
2472
a2b8659d 2473 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2474 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2475
2476 if (cur_pipe->top_pipe)
2477 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2478
2479 if (cur_pipe->bottom_pipe)
2480 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2481
2482 }
2483
ab2541b6 2484 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2485 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2486 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2487 dc_plane_state_retain(
2488 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2489 }
9a3afbb3
AG		 2490
2491 /* context refcount should not be overridden */
8ee5702a 2492 dst_ctx->refcount = refcount;
9a3afbb3 2493
4562236b
HW		 2494}
2495
2496struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2497 struct resource_context *res_ctx,
2498 const struct resource_pool *pool)
4562236b
HW		 2499{
2500 int i;
2501
a2b8659d 2502 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2503 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2504 return pool->clock_sources[i];
4562236b
HW		 2505 }
2506
2507 return NULL;
2508}
2509
2510void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2511{
2512 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2513 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2514
2515 /* default all packets to invalid */
6e4d6bee
TC		 2516 info->avi.valid = false;
2517 info->gamut.valid = false;
2518 info->vendor.valid = false;
630e3573 2519 info->spd.valid = false;
6e4d6bee
TC		 2520 info->hdrsmd.valid = false;
2521 info->vsc.valid = false;
4562236b
HW		 2522
2523 signal = pipe_ctx->stream->signal;
2524
2525 /* HDMi and DP have different info packets*/
2526 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2527 set_avi_info_frame(&info->avi, pipe_ctx);
2528
2529 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2530
2531 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2532
56ef6ed9 2533 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2534
a33fa99d 2535 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2536 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2537
2538 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2539
56ef6ed9 2540 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2541 }
4562236b 2542
6e4d6bee 2543 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2544}
2545
2546enum dc_status resource_map_clock_resources(
fb3466a4 2547 const struct dc *dc,
608ac7bb 2548 struct dc_state *context,
1dc90497 2549 struct dc_stream_state *stream)
4562236b 2550{
4562236b 2551 /* acquire new resources */
1dc90497
AG		 2552 const struct resource_pool *pool = dc->res_pool;
2553 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2554 &context->res_ctx, stream);
ab2541b6 2555
1dc90497
AG		 2556 if (!pipe_ctx)
2557 return DC_ERROR_UNEXPECTED;
4562236b 2558
1dc90497
AG		 2559 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2560 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2561 pipe_ctx->clock_source = pool->dp_clock_source;
2562 else {
2563 pipe_ctx->clock_source = NULL;
4562236b 2564
1dc90497 2565 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2566 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2567 &context->res_ctx,
2568 pipe_ctx);
4562236b 2569
1dc90497
AG		 2570 if (pipe_ctx->clock_source == NULL)
2571 pipe_ctx->clock_source =
2572 dc_resource_find_first_free_pll(
2573 &context->res_ctx,
2574 pool);
2575 }
4562236b 2576
1dc90497
AG		 2577 if (pipe_ctx->clock_source == NULL)
2578 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2579
1dc90497
AG		 2580 resource_reference_clock_source(
2581 &context->res_ctx, pool,
2582 pipe_ctx->clock_source);
4562236b
HW		 2583
2584 return DC_OK;
2585}
2586
2587/*
2588 * Note: We need to disable output if clock sources change,
2589 * since bios does optimization and doesn't apply if changing
2590 * PHY when not already disabled.
2591 */
2592bool pipe_need_reprogram(
2593 struct pipe_ctx *pipe_ctx_old,
2594 struct pipe_ctx *pipe_ctx)
2595{
cfe4645e
DL		 2596 if (!pipe_ctx_old->stream)
2597 return false;
2598
4562236b
HW		 2599 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2600 return true;
2601
2602 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2603 return true;
2604
afaacef4 2605 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2606 return true;
2607
2608 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2609 && pipe_ctx_old->stream != pipe_ctx->stream)
2610 return true;
2611
8e9c4c8c 2612 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2613 return true;
2614
2615 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2616 return true;
2617
2618
2619 return false;
2620}
529cad0f 2621
0971c40e 2622void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2623 struct bit_depth_reduction_params *fmt_bit_depth)
2624{
4fa086b9 2625 enum dc_dither_option option = stream->dither_option;
529cad0f 2626 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2627 stream->timing.pixel_encoding;
529cad0f
DW		 2628
2629 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2630
603767f9
TC		 2631 if (option == DITHER_OPTION_DEFAULT) {
2632 switch (stream->timing.display_color_depth) {
2633 case COLOR_DEPTH_666:
2634 option = DITHER_OPTION_SPATIAL6;
2635 break;
2636 case COLOR_DEPTH_888:
2637 option = DITHER_OPTION_SPATIAL8;
2638 break;
2639 case COLOR_DEPTH_101010:
2640 option = DITHER_OPTION_SPATIAL10;
2641 break;
2642 default:
2643 option = DITHER_OPTION_DISABLE;
2644 }
2645 }
2646
529cad0f
DW		 2647 if (option == DITHER_OPTION_DISABLE)
2648 return;
2649
2650 if (option == DITHER_OPTION_TRUN6) {
2651 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2652 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2653 } else if (option == DITHER_OPTION_TRUN8 ||
2654 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2655 option == DITHER_OPTION_TRUN8_FM6) {
2656 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2657 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2658 } else if (option == DITHER_OPTION_TRUN10 ||
2659 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2660 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2661 option == DITHER_OPTION_TRUN10_FM8 ||
2662 option == DITHER_OPTION_TRUN10_FM6 ||
2663 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2664 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2665 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2666 }
2667
2668 /* special case - Formatter can only reduce by 4 bits at most.
2669 * When reducing from 12 to 6 bits,
2670 * HW recommends we use trunc with round mode
2671 * (if we did nothing, trunc to 10 bits would be used)
2672 * note that any 12->10 bit reduction is ignored prior to DCE8,
2673 * as the input was 10 bits.
2674 */
2675 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2676 option == DITHER_OPTION_SPATIAL6 ||
2677 option == DITHER_OPTION_FM6) {
2678 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2679 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2680 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2681 }
2682
2683 /* spatial dither
2684 * note that spatial modes 1-3 are never used
2685 */
2686 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2687 option == DITHER_OPTION_SPATIAL6 ||
2688 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2689 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2690 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2691 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2692 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2693 fmt_bit_depth->flags.RGB_RANDOM =
2694 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2695 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2696 option == DITHER_OPTION_SPATIAL8 ||
2697 option == DITHER_OPTION_SPATIAL8_FM6 ||
2698 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2699 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2700 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2701 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2702 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2703 fmt_bit_depth->flags.RGB_RANDOM =
2704 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2705 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2706 option == DITHER_OPTION_SPATIAL10 ||
2707 option == DITHER_OPTION_SPATIAL10_FM8 ||
2708 option == DITHER_OPTION_SPATIAL10_FM6) {
2709 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2710 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2711 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2712 fmt_bit_depth->flags.RGB_RANDOM =
2713 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2714 }
2715
2716 if (option == DITHER_OPTION_SPATIAL6 ||
2717 option == DITHER_OPTION_SPATIAL8 ||
2718 option == DITHER_OPTION_SPATIAL10) {
2719 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2720 } else {
2721 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2722 }
2723
2724 //////////////////////
2725 //// temporal dither
2726 //////////////////////
2727 if (option == DITHER_OPTION_FM6 ||
2728 option == DITHER_OPTION_SPATIAL8_FM6 ||
2729 option == DITHER_OPTION_SPATIAL10_FM6 ||
2730 option == DITHER_OPTION_TRUN10_FM6 ||
2731 option == DITHER_OPTION_TRUN8_FM6 ||
2732 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2733 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2734 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2735 } else if (option == DITHER_OPTION_FM8 ||
2736 option == DITHER_OPTION_SPATIAL10_FM8 ||
2737 option == DITHER_OPTION_TRUN10_FM8) {
2738 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2739 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2740 } else if (option == DITHER_OPTION_FM10) {
2741 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2742 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2743 }
2744
2745 fmt_bit_depth->pixel_encoding = pixel_encoding;
2746}
9345d987 2747
62c933f9 2748enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2749{
fb3466a4 2750 struct dc *core_dc = dc;
4fa086b9 2751 struct dc_link *link = stream->sink->link;
9345d987
AG		 2752 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2753 enum dc_status res = DC_OK;
2754
4fa086b9 2755 calculate_phy_pix_clks(stream);
9345d987 2756
4fa086b9 2757 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2758 res = DC_FAIL_CONTROLLER_VALIDATE;
2759
2760 if (res == DC_OK)
2761 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2762 link->link_enc, stream))
9345d987
AG		 2763 res = DC_FAIL_ENC_VALIDATE;
2764
2765 /* TODO: validate audio ASIC caps, encoder */
2766
2767 if (res == DC_OK)
4fa086b9 2768 res = dc_link_validate_mode_timing(stream,
9345d987 2769 link,
4fa086b9 2770 &stream->timing);
9345d987 2771
62c933f9 2772 return res;
9345d987 2773}
792671d7 2774
62c933f9 2775enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2776{
62c933f9
YS		 2777 enum dc_status res = DC_OK;
2778
792671d7 2779 /* TODO For now validates pixel format only */
8e7095b9 2780 if (dc->res_pool->funcs->validate_plane)
62c933f9 2781 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2782
62c933f9 2783 return res;
792671d7 2784}
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