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drm/amd/display: add missing opp programming for odm
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
33d7598d
JL		 34#include "dccg.h"
35#include "dchubbub.h"
d94585a0 36#include "dpp.h"
5ac3d3c9 37#include "core_types.h"
4562236b 38#include "set_mode_types.h"
4562236b 39#include "virtual/virtual_stream_encoder.h"
3b94a400 40#include "dpcd_defs.h"
4562236b
HW		 41
42#include "dce80/dce80_resource.h"
43#include "dce100/dce100_resource.h"
44#include "dce110/dce110_resource.h"
45#include "dce112/dce112_resource.h"
dc37a9a0 46#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 47#include "dcn10/dcn10_resource.h"
48#endif
2c8ad2d5 49#include "dce120/dce120_resource.h"
5d4b05dd
BL		 50
51#define DC_LOGGER_INIT(logger)
52
4562236b
HW		 53enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
54{
55 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
56 switch (asic_id.chip_family) {
57
58 case FAMILY_CI:
4562236b
HW		 59 dc_version = DCE_VERSION_8_0;
60 break;
ebfdf0d0
AD		 61 case FAMILY_KV:
62 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
63 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
64 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
65 dc_version = DCE_VERSION_8_3;
66 else
67 dc_version = DCE_VERSION_8_1;
68 break;
4562236b
HW		 69 case FAMILY_CZ:
70 dc_version = DCE_VERSION_11_0;
71 break;
72
73 case FAMILY_VI:
74 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
75 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
76 dc_version = DCE_VERSION_10_0;
77 break;
78 }
79 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 80 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 82 dc_version = DCE_VERSION_11_2;
83 }
0c75d5ac
JFZ		 84 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
85 dc_version = DCE_VERSION_11_22;
4562236b 86 break;
2c8ad2d5 87 case FAMILY_AI:
b8b6ce89
LL		 88 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
89 dc_version = DCE_VERSION_12_1;
90 else
91 dc_version = DCE_VERSION_12_0;
2c8ad2d5 92 break;
dc37a9a0 93#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 94 case FAMILY_RV:
95 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 96#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
97 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
98 dc_version = DCN_VERSION_1_01;
99#endif
ff5ef992
AD		 100 break;
101#endif
4562236b
HW		 102 default:
103 dc_version = DCE_VERSION_UNKNOWN;
104 break;
105 }
106 return dc_version;
107}
108
109struct resource_pool *dc_create_resource_pool(
fb3466a4 110 struct dc *dc,
4562236b
HW		 111 int num_virtual_links,
112 enum dce_version dc_version,
113 struct hw_asic_id asic_id)
114{
5ac3d3c9 115 struct resource_pool *res_pool = NULL;
4562236b
HW		 116
117 switch (dc_version) {
118 case DCE_VERSION_8_0:
7992a629
AD		 119 res_pool = dce80_create_resource_pool(
120 num_virtual_links, dc);
121 break;
ebfdf0d0 122 case DCE_VERSION_8_1:
7992a629
AD		 123 res_pool = dce81_create_resource_pool(
124 num_virtual_links, dc);
125 break;
ebfdf0d0 126 case DCE_VERSION_8_3:
7992a629 127 res_pool = dce83_create_resource_pool(
4562236b 128 num_virtual_links, dc);
5ac3d3c9 129 break;
4562236b 130 case DCE_VERSION_10_0:
5ac3d3c9 131 res_pool = dce100_create_resource_pool(
4562236b 132 num_virtual_links, dc);
5ac3d3c9 133 break;
4562236b 134 case DCE_VERSION_11_0:
5ac3d3c9 135 res_pool = dce110_create_resource_pool(
4562236b 136 num_virtual_links, dc, asic_id);
5ac3d3c9 137 break;
4562236b 138 case DCE_VERSION_11_2:
0c75d5ac 139 case DCE_VERSION_11_22:
5ac3d3c9 140 res_pool = dce112_create_resource_pool(
4562236b 141 num_virtual_links, dc);
5ac3d3c9 142 break;
2c8ad2d5 143 case DCE_VERSION_12_0:
b8b6ce89 144 case DCE_VERSION_12_1:
2c8ad2d5
AD		 145 res_pool = dce120_create_resource_pool(
146 num_virtual_links, dc);
147 break;
ff5ef992 148
dc37a9a0 149#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 150 case DCN_VERSION_1_0:
0e3d73f1
BL		 151#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
152 case DCN_VERSION_1_01:
153#endif
ff5ef992 154 res_pool = dcn10_create_resource_pool(
503a7c6f 155 num_virtual_links, dc);
ff5ef992
AD		 156 break;
157#endif
3639fa68
ZF		 158
159
4562236b
HW		 160 default:
161 break;
162 }
5ac3d3c9 163 if (res_pool != NULL) {
1515a47b 164 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 165
166 if (dc->ctx->dc_bios->funcs->get_firmware_info(
167 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
33d7598d
JL		 168 res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
169
170 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
171 // On FPGA these dividers are currently not configured by GDB
172 res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
173 res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
174 } else if (res_pool->dccg && res_pool->hubbub) {
175 // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error
176 // as this value must be known for DCHUB programming
177 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
178 fw_info.pll_info.crystal_frequency,
179 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
180
181 // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error
182 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
183 res_pool->ref_clocks.dccg_ref_clock_inKhz,
184 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
185 } else {
186 // Not all ASICs have DCCG sw component
187 res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
188 res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
189 }
5ac3d3c9
CL		 190 } else
191 ASSERT_CRITICAL(false);
192 }
4562236b 193
5ac3d3c9 194 return res_pool;
4562236b
HW		 195}
196
fb3466a4 197void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 198{
199 if (dc) {
200 if (dc->res_pool)
201 dc->res_pool->funcs->destroy(&dc->res_pool);
202
d029810c 203 kfree(dc->hwseq);
4562236b
HW		 204 }
205}
206
207static void update_num_audio(
208 const struct resource_straps *straps,
209 unsigned int *num_audio,
210 struct audio_support *aud_support)
211{
b8e9eb72
CL		 212 aud_support->dp_audio = true;
213 aud_support->hdmi_audio_native = false;
214 aud_support->hdmi_audio_on_dongle = false;
215
4562236b 216 if (straps->hdmi_disable == 0) {
4562236b
HW		 217 if (straps->dc_pinstraps_audio & 0x2) {
218 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 219 aud_support->hdmi_audio_native = true;
4562236b
HW		 220 }
221 }
222
223 switch (straps->audio_stream_number) {
224 case 0: /* multi streams supported */
225 break;
226 case 1: /* multi streams not supported */
227 *num_audio = 1;
228 break;
229 default:
230 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 231 }
4562236b
HW		 232}
233
234bool resource_construct(
235 unsigned int num_virtual_links,
fb3466a4 236 struct dc *dc,
4562236b
HW		 237 struct resource_pool *pool,
238 const struct resource_create_funcs *create_funcs)
239{
240 struct dc_context *ctx = dc->ctx;
241 const struct resource_caps *caps = pool->res_cap;
242 int i;
243 unsigned int num_audio = caps->num_audio;
244 struct resource_straps straps = {0};
245
246 if (create_funcs->read_dce_straps)
247 create_funcs->read_dce_straps(dc->ctx, &straps);
248
249 pool->audio_count = 0;
250 if (create_funcs->create_audio) {
251 /* find the total number of streams available via the
252 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
253 * registers (one for each pin) starting from pin 1
254 * up to the max number of audio pins.
255 * We stop on the first pin where
256 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
257 */
258 update_num_audio(&straps, &num_audio, &pool->audio_support);
259 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
260 struct audio *aud = create_funcs->create_audio(ctx, i);
261
262 if (aud == NULL) {
263 DC_ERR("DC: failed to create audio!\n");
264 return false;
265 }
266
267 if (!aud->funcs->endpoint_valid(aud)) {
268 aud->funcs->destroy(&aud);
269 break;
270 }
271
272 pool->audios[i] = aud;
273 pool->audio_count++;
274 }
275 }
276
277 pool->stream_enc_count = 0;
278 if (create_funcs->create_stream_encoder) {
279 for (i = 0; i < caps->num_stream_encoder; i++) {
280 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
281 if (pool->stream_enc[i] == NULL)
282 DC_ERR("DC: failed to create stream_encoder!\n");
283 pool->stream_enc_count++;
284 }
285 }
929c3aaa 286
4176664b
CL		 287 dc->caps.dynamic_audio = false;
288 if (pool->audio_count < pool->stream_enc_count) {
289 dc->caps.dynamic_audio = true;
290 }
4562236b
HW		 291 for (i = 0; i < num_virtual_links; i++) {
292 pool->stream_enc[pool->stream_enc_count] =
293 virtual_stream_encoder_create(
294 ctx, ctx->dc_bios);
295 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
296 DC_ERR("DC: failed to create stream_encoder!\n");
297 return false;
298 }
299 pool->stream_enc_count++;
300 }
301
302 dc->hwseq = create_funcs->create_hwseq(ctx);
303
304 return true;
305}
ad8960a6
ML		 306static int find_matching_clock_source(
307 const struct resource_pool *pool,
308 struct clock_source *clock_source)
309{
4562236b 310
ad8960a6
ML		 311 int i;
312
313 for (i = 0; i < pool->clk_src_count; i++) {
314 if (pool->clock_sources[i] == clock_source)
315 return i;
316 }
317 return -1;
318}
4562236b 319
21e67d4d 320void resource_unreference_clock_source(
4562236b 321 struct resource_context *res_ctx,
a2b8659d 322 const struct resource_pool *pool,
4a629536 323 struct clock_source *clock_source)
4562236b 324{
ad8960a6 325 int i = find_matching_clock_source(pool, clock_source);
4562236b 326
ad8960a6 327 if (i > -1)
4562236b
HW		 328 res_ctx->clock_source_ref_count[i]--;
329
21e67d4d 330 if (pool->dp_clock_source == clock_source)
4562236b 331 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 332}
333
334void resource_reference_clock_source(
335 struct resource_context *res_ctx,
a2b8659d 336 const struct resource_pool *pool,
4562236b
HW		 337 struct clock_source *clock_source)
338{
ad8960a6 339 int i = find_matching_clock_source(pool, clock_source);
4562236b 340
ad8960a6 341 if (i > -1)
4562236b 342 res_ctx->clock_source_ref_count[i]++;
4562236b 343
a2b8659d 344 if (pool->dp_clock_source == clock_source)
4562236b
HW		 345 res_ctx->dp_clock_source_ref_count++;
346}
347
ad8960a6
ML		 348int resource_get_clock_source_reference(
349 struct resource_context *res_ctx,
350 const struct resource_pool *pool,
351 struct clock_source *clock_source)
352{
353 int i = find_matching_clock_source(pool, clock_source);
354
355 if (i > -1)
356 return res_ctx->clock_source_ref_count[i];
357
358 if (pool->dp_clock_source == clock_source)
359 return res_ctx->dp_clock_source_ref_count;
360
361 return -1;
362}
363
4562236b 364bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 365 struct dc_stream_state *stream1,
366 struct dc_stream_state *stream2)
4562236b 367{
4fa086b9 368 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 369 return false;
370
4fa086b9 371 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 372 return false;
373
4fa086b9
LSL		 374 if (stream1->timing.h_addressable
375 != stream2->timing.h_addressable)
4562236b
HW		 376 return false;
377
4fa086b9
LSL		 378 if (stream1->timing.v_addressable
379 != stream2->timing.v_addressable)
4562236b
HW		 380 return false;
381
380604e2
KC		 382 if (stream1->timing.pix_clk_100hz
383 != stream2->timing.pix_clk_100hz)
4562236b
HW		 384 return false;
385
3e27e10e
ML		 386 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
387 return false;
388
4562236b 389 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 390 && (!dc_is_dp_signal(stream1->signal)
391 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 392 return false;
393
d77f778e
CL		 394 if (stream1->view_format != stream2->view_format)
395 return false;
396
4562236b
HW		 397 return true;
398}
3e27e10e
ML		 399static bool is_dp_and_hdmi_sharable(
400 struct dc_stream_state *stream1,
401 struct dc_stream_state *stream2)
402{
403 if (stream1->ctx->dc->caps.disable_dp_clk_share)
404 return false;
405
406 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 407 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 408 return false;
3e27e10e
ML		 409
410 return true;
411
412}
4562236b
HW		 413
414static bool is_sharable_clk_src(
415 const struct pipe_ctx *pipe_with_clk_src,
416 const struct pipe_ctx *pipe)
417{
418 if (pipe_with_clk_src->clock_source == NULL)
419 return false;
420
421 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
422 return false;
423
3e27e10e
ML		 424 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
425 (dc_is_dp_signal(pipe->stream->signal) &&
426 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
427 pipe->stream)))
4562236b
HW		 428 return false;
429
430 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 431 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 432 return false;
433
434 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 435 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 436 return false;
437
438 if (!resource_are_streams_timing_synchronizable(
439 pipe_with_clk_src->stream, pipe->stream))
440 return false;
441
442 return true;
443}
444
445struct clock_source *resource_find_used_clk_src_for_sharing(
446 struct resource_context *res_ctx,
447 struct pipe_ctx *pipe_ctx)
448{
449 int i;
450
451 for (i = 0; i < MAX_PIPES; i++) {
452 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
453 return res_ctx->pipe_ctx[i].clock_source;
454 }
455
456 return NULL;
457}
458
459static enum pixel_format convert_pixel_format_to_dalsurface(
460 enum surface_pixel_format surface_pixel_format)
461{
462 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
463
464 switch (surface_pixel_format) {
465 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
466 dal_pixel_format = PIXEL_FORMAT_INDEX8;
467 break;
468 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
469 dal_pixel_format = PIXEL_FORMAT_RGB565;
470 break;
471 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
472 dal_pixel_format = PIXEL_FORMAT_RGB565;
473 break;
474 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
475 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
476 break;
8693049a 477 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 478 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
479 break;
480 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
481 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
482 break;
483 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
484 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
485 break;
486 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
487 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
488 break;
489 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
490 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
491 dal_pixel_format = PIXEL_FORMAT_FP16;
492 break;
493 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 494 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 495 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 496 break;
ffbcd19a
VP		 497 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
498 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 499 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 500 break;
4562236b
HW		 501 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
502 default:
503 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
504 break;
505 }
506 return dal_pixel_format;
507}
508
9b6067c0
DL		 509static inline void get_vp_scan_direction(
510 enum dc_rotation_angle rotation,
511 bool horizontal_mirror,
512 bool *orthogonal_rotation,
513 bool *flip_vert_scan_dir,
514 bool *flip_horz_scan_dir)
4562236b 515{
9b6067c0
DL		 516 *orthogonal_rotation = false;
517 *flip_vert_scan_dir = false;
518 *flip_horz_scan_dir = false;
519 if (rotation == ROTATION_ANGLE_180) {
520 *flip_vert_scan_dir = true;
521 *flip_horz_scan_dir = true;
522 } else if (rotation == ROTATION_ANGLE_90) {
523 *orthogonal_rotation = true;
524 *flip_horz_scan_dir = true;
525 } else if (rotation == ROTATION_ANGLE_270) {
526 *orthogonal_rotation = true;
527 *flip_vert_scan_dir = true;
528 }
529
530 if (horizontal_mirror)
531 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 532}
533
b2d0a103 534static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 535{
3be5262e 536 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 537 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 538 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 539 struct rect surf_src = plane_state->src_rect;
9b6067c0 540 struct rect clip, dest;
87449a90
AK		 541 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
542 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 543 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 544 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 545 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 546 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 547 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 548
7f5c22d1
VP		 549 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
550 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 551 pri_split = false;
552 sec_split = false;
553 }
86006a7f 554
4562236b
HW		 555 /* The actual clip is an intersection between stream
556 * source and surface clip
557 */
9b6067c0 558 dest = plane_state->dst_rect;
3be5262e
HW		 559 clip.x = stream->src.x > plane_state->clip_rect.x ?
560 stream->src.x : plane_state->clip_rect.x;
4562236b 561
1fbd2cfc 562 clip.width = stream->src.x + stream->src.width <
3be5262e 563 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 564 stream->src.x + stream->src.width - clip.x :
3be5262e 565 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 566
3be5262e
HW		 567 clip.y = stream->src.y > plane_state->clip_rect.y ?
568 stream->src.y : plane_state->clip_rect.y;
4562236b 569
1fbd2cfc 570 clip.height = stream->src.y + stream->src.height <
3be5262e 571 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 572 stream->src.y + stream->src.height - clip.y :
3be5262e 573 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 574
9b6067c0
DL		 575 /*
576 * Need to calculate how scan origin is shifted in vp space
577 * to correctly rotate clip and dst
578 */
579 get_vp_scan_direction(
580 plane_state->rotation,
581 plane_state->horizontal_mirror,
582 &orthogonal_rotation,
583 &flip_y_start,
584 &flip_x_start);
585
586 if (orthogonal_rotation) {
587 swap(clip.x, clip.y);
588 swap(clip.width, clip.height);
589 swap(dest.x, dest.y);
590 swap(dest.width, dest.height);
591 }
592 if (flip_x_start) {
593 clip.x = dest.x + dest.width - clip.x - clip.width;
594 dest.x = 0;
595 }
596 if (flip_y_start) {
597 clip.y = dest.y + dest.height - clip.y - clip.height;
598 dest.y = 0;
599 }
600
86006a7f 601 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 602 * num_pixels = clip.num_pix * scl_ratio
603 */
9b6067c0
DL		 604 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
605 data->viewport.width = clip.width * surf_src.width / dest.width;
606
607 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
608 data->viewport.height = clip.height * surf_src.height / dest.height;
609
610 /* Handle split */
611 if (pri_split || sec_split) {
612 if (orthogonal_rotation) {
613 if (flip_y_start != pri_split)
614 data->viewport.height /= 2;
615 else {
616 data->viewport.y += data->viewport.height / 2;
617 /* Ceil offset pipe */
618 data->viewport.height = (data->viewport.height + 1) / 2;
619 }
620 } else {
621 if (flip_x_start != pri_split)
622 data->viewport.width /= 2;
623 else {
624 data->viewport.x += data->viewport.width / 2;
625 /* Ceil offset pipe */
626 data->viewport.width = (data->viewport.width + 1) / 2;
627 }
628 }
629 }
9b5349f7 630
b2d0a103
DL		 631 /* Round down, compensate in init */
632 data->viewport_c.x = data->viewport.x / vpc_div;
633 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 634 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
635 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
636
b2d0a103
DL		 637 /* Round up, assume original video size always even dimensions */
638 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
639 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 640}
641
9b6067c0 642static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 643{
3be5262e 644 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 645 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 646 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS		 647 bool pri_split = pipe_ctx->bottom_pipe &&
648 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
649 bool sec_split = pipe_ctx->top_pipe &&
650 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 651 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 652
6702a9ac 653 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 654 if (stream->src.x < surf_clip.x)
6702a9ac 655 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 656 - stream->src.x) * stream->dst.width
657 / stream->src.width;
4562236b 658
6702a9ac 659 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 660 stream->dst.width / stream->src.width;
6702a9ac 661 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 662 stream->dst.x + stream->dst.width)
6702a9ac 663 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 664 stream->dst.x + stream->dst.width
6702a9ac 665 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 666
6702a9ac 667 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 668 if (stream->src.y < surf_clip.y)
6702a9ac 669 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 670 - stream->src.y) * stream->dst.height
671 / stream->src.height;
4562236b 672
6702a9ac 673 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 674 stream->dst.height / stream->src.height;
6702a9ac 675 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 676 stream->dst.y + stream->dst.height)
6702a9ac 677 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 678 stream->dst.y + stream->dst.height
6702a9ac 679 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 680
9b6067c0 681 /* Handle h & v split, handle rotation using viewport */
b0131391
DL		 682 if (sec_split && top_bottom_split) {
683 pipe_ctx->plane_res.scl_data.recout.y +=
684 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 685 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 686 pipe_ctx->plane_res.scl_data.recout.height =
687 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
688 } else if (pri_split && top_bottom_split)
0c31a821 689 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL		 690 else if (sec_split) {
691 pipe_ctx->plane_res.scl_data.recout.x +=
692 pipe_ctx->plane_res.scl_data.recout.width / 2;
693 /* Ceil offset pipe */
694 pipe_ctx->plane_res.scl_data.recout.width =
695 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
696 } else if (pri_split)
697 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW		 698}
699
b2d0a103 700static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 701{
3be5262e 702 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 703 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 704 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 705 const int in_w = stream->src.width;
706 const int in_h = stream->src.height;
707 const int out_w = stream->dst.width;
708 const int out_h = stream->dst.height;
4562236b 709
9b6067c0 710 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 711 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
712 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 713 swap(surf_src.height, surf_src.width);
86006a7f 714
eb0e5154 715 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 716 surf_src.width,
3be5262e 717 plane_state->dst_rect.width);
eb0e5154 718 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 719 surf_src.height,
3be5262e 720 plane_state->dst_rect.height);
4562236b 721
4fa086b9 722 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 723 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 724 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 725 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 726
6702a9ac
HW		 727 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
728 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
729 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
730 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 731
6702a9ac
HW		 732 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
733 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 734
6702a9ac
HW		 735 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
736 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
737 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
738 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 739 }
0002d3ac
DL		 740 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
741 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
742 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
743 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
744 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
745 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
746 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
747 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 748}
749
9b6067c0
DL		 750static inline void adjust_vp_and_init_for_seamless_clip(
751 bool flip_scan_dir,
752 int recout_skip,
753 int src_size,
754 int taps,
755 struct fixed31_32 ratio,
756 struct fixed31_32 *init,
757 int *vp_offset,
758 int *vp_size)
b2d0a103 759{
9b6067c0 760 if (!flip_scan_dir) {
9a08f51f 761 /* Adjust for viewport end clip-off */
9b6067c0
DL		 762 if ((*vp_offset + *vp_size) < src_size) {
763 int vp_clip = src_size - *vp_size - *vp_offset;
764 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 765
766 int_part = int_part > 0 ? int_part : 0;
9b6067c0 767 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 768 }
b2d0a103 769
9a08f51f 770 /* Adjust for non-0 viewport offset */
9b6067c0 771 if (*vp_offset) {
9a08f51f
DL		 772 int int_part;
773
9b6067c0
DL		 774 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
775 int_part = dc_fixpt_floor(*init) - *vp_offset;
776 if (int_part < taps) {
777 int int_adj = *vp_offset >= (taps - int_part) ?
778 (taps - int_part) : *vp_offset;
779 *vp_offset -= int_adj;
780 *vp_size += int_adj;
9a08f51f 781 int_part += int_adj;
9b6067c0
DL		 782 } else if (int_part > taps) {
783 *vp_offset += int_part - taps;
784 *vp_size -= int_part - taps;
785 int_part = taps;
9a08f51f 786 }
9b6067c0
DL		 787 init->value &= 0xffffffff;
788 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 789 }
790 } else {
791 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 792 if (*vp_offset) {
793 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 794
9a08f51f 795 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 796 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
797 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 798 }
b2d0a103 799
9a08f51f 800 /* Adjust for viewport end clip-off */
9b6067c0 801 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 802 int int_part;
9b6067c0 803 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 804
805 /*
806 * this is init if vp had no offset, keep in mind this is from the
807 * right side of vp due to scan direction
808 */
9b6067c0 809 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 810 /*
811 * this is the difference between first pixel of viewport available to read
812 * and init position, takning into account scan direction
813 */
9b6067c0
DL		 814 int_part = dc_fixpt_floor(*init) - end_offset;
815 if (int_part < taps) {
816 int int_adj = end_offset >= (taps - int_part) ?
817 (taps - int_part) : end_offset;
818 *vp_size += int_adj;
9a08f51f 819 int_part += int_adj;
9b6067c0
DL		 820 } else if (int_part > taps) {
821 *vp_size += int_part - taps;
822 int_part = taps;
9a08f51f 823 }
9b6067c0
DL		 824 init->value &= 0xffffffff;
825 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 826 }
b2d0a103 827 }
9b6067c0 828}
9a08f51f 829
9b6067c0
DL		 830static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
831{
832 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
833 const struct dc_stream_state *stream = pipe_ctx->stream;
834 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
835 struct rect src = pipe_ctx->plane_state->src_rect;
836 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
837 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
838 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
839 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 840
9b6067c0
DL		 841 /*
842 * Need to calculate the scan direction for viewport to make adjustments
843 */
844 get_vp_scan_direction(
845 plane_state->rotation,
846 plane_state->horizontal_mirror,
847 &orthogonal_rotation,
848 &flip_vert_scan_dir,
849 &flip_horz_scan_dir);
850
851 /* Calculate src rect rotation adjusted to recout space */
852 surf_size_h = src.x + src.width;
853 surf_size_v = src.y + src.height;
854 if (flip_horz_scan_dir)
855 src.x = 0;
856 if (flip_vert_scan_dir)
857 src.y = 0;
858 if (orthogonal_rotation) {
859 swap(src.x, src.y);
860 swap(src.width, src.height);
861 }
9a08f51f 862
9b6067c0
DL		 863 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
864 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
865 * - (surf surf_src offset * 1/ full scl ratio))
866 */
867 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
868 * stream->dst.width / stream->src.width -
869 src.x * plane_state->dst_rect.width / src.width
870 * stream->dst.width / stream->src.width);
871 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
872 * stream->dst.height / stream->src.height -
873 src.y * plane_state->dst_rect.height / src.height
874 * stream->dst.height / stream->src.height);
875 if (orthogonal_rotation)
876 swap(recout_skip_h, recout_skip_v);
877 /*
878 * Init calculated according to formula:
879 * init = (scaling_ratio + number_of_taps + 1) / 2
880 * init_bot = init + scaling_ratio
881 * init_c = init + truncated_vp_c_offset(from calculate viewport)
882 */
883 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
884 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 885
9b6067c0
DL		 886 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
887 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 888
9b6067c0
DL		 889 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
890 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 891
9b6067c0
DL		 892 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
893 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 894
9b6067c0
DL		 895 /*
896 * Taps, inits and scaling ratios are in recout space need to rotate
897 * to viewport rotation before adjustment
898 */
899 adjust_vp_and_init_for_seamless_clip(
900 flip_horz_scan_dir,
901 recout_skip_h,
902 surf_size_h,
903 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
904 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
905 orthogonal_rotation ? &data->inits.v : &data->inits.h,
906 &data->viewport.x,
907 &data->viewport.width);
908 adjust_vp_and_init_for_seamless_clip(
909 flip_horz_scan_dir,
910 recout_skip_h,
911 surf_size_h / vpc_div,
912 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
913 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
914 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
915 &data->viewport_c.x,
916 &data->viewport_c.width);
917 adjust_vp_and_init_for_seamless_clip(
918 flip_vert_scan_dir,
919 recout_skip_v,
920 surf_size_v,
921 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
922 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
923 orthogonal_rotation ? &data->inits.h : &data->inits.v,
924 &data->viewport.y,
925 &data->viewport.height);
926 adjust_vp_and_init_for_seamless_clip(
927 flip_vert_scan_dir,
928 recout_skip_v,
929 surf_size_v / vpc_div,
930 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
931 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
932 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
933 &data->viewport_c.y,
934 &data->viewport_c.height);
b2d0a103
DL		 935
936 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 937 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
938 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 939
b2d0a103
DL		 940}
941
942bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 943{
3be5262e 944 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 945 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 946 bool res = false;
5d4b05dd 947 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 948 /* Important: scaling ratio calculation requires pixel format,
949 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 950 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 951 */
6702a9ac 952 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 953 pipe_ctx->plane_state->format);
b2d0a103
DL		 954
955 calculate_scaling_ratios(pipe_ctx);
4562236b 956
b2d0a103 957 calculate_viewport(pipe_ctx);
4562236b 958
6702a9ac 959 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 960 return false;
961
9b6067c0 962 calculate_recout(pipe_ctx);
4562236b
HW		 963
964 /**
965 * Setting line buffer pixel depth to 24bpp yields banding
966 * on certain displays, such as the Sharp 4k
967 */
6702a9ac 968 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 969
199e458a 970 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 971 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 972
58bb0e63
AJ		 973 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
974 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 975
4562236b 976 /* Taps calculations */
d94585a0
YHL		 977 if (pipe_ctx->plane_res.xfm != NULL)
978 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
979 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
980
981 if (pipe_ctx->plane_res.dpp != NULL)
982 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
983 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 984 if (!res) {
985 /* Try 24 bpp linebuffer */
6702a9ac 986 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 987
1b6c8067
BL		 988 if (pipe_ctx->plane_res.xfm != NULL)
989 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
990 pipe_ctx->plane_res.xfm,
991 &pipe_ctx->plane_res.scl_data,
992 &plane_state->scaling_quality);
993
994 if (pipe_ctx->plane_res.dpp != NULL)
995 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
996 pipe_ctx->plane_res.dpp,
997 &pipe_ctx->plane_res.scl_data,
998 &plane_state->scaling_quality);
4562236b
HW		 999 }
1000
b2d0a103 1001 if (res)
1fbd2cfc 1002 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1003 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1004
1296423b 1005 DC_LOG_SCALER(
4562236b
HW		 1006 "%s: Viewport:\nheight:%d width:%d x:%d "
1007 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1008 "y:%d\n",
1009 __func__,
6702a9ac
HW		 1010 pipe_ctx->plane_res.scl_data.viewport.height,
1011 pipe_ctx->plane_res.scl_data.viewport.width,
1012 pipe_ctx->plane_res.scl_data.viewport.x,
1013 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 1014 plane_state->dst_rect.height,
1015 plane_state->dst_rect.width,
1016 plane_state->dst_rect.x,
1017 plane_state->dst_rect.y);
4562236b
HW		 1018
1019 return res;
1020}
1021
1022
1023enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1024 const struct dc *dc,
608ac7bb 1025 struct dc_state *context)
4562236b
HW		 1026{
1027 int i;
1028
1029 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1030 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1031 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1032 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1033 return DC_FAIL_SCALING;
4562236b
HW		 1034 }
1035
1036 return DC_OK;
1037}
1038
a2b8659d
TC		 1039struct pipe_ctx *find_idle_secondary_pipe(
1040 struct resource_context *res_ctx,
1041 const struct resource_pool *pool)
4562236b
HW		 1042{
1043 int i;
1044 struct pipe_ctx *secondary_pipe = NULL;
1045
1046 /*
1047 * search backwards for the second pipe to keep pipe
1048 * assignment more consistent
1049 */
1050
a2b8659d 1051 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 1052 if (res_ctx->pipe_ctx[i].stream == NULL) {
1053 secondary_pipe = &res_ctx->pipe_ctx[i];
1054 secondary_pipe->pipe_idx = i;
1055 break;
1056 }
1057 }
1058
1059
1060 return secondary_pipe;
1061}
1062
1063struct pipe_ctx *resource_get_head_pipe_for_stream(
1064 struct resource_context *res_ctx,
0971c40e 1065 struct dc_stream_state *stream)
4562236b
HW		 1066{
1067 int i;
a2b8659d 1068 for (i = 0; i < MAX_PIPES; i++) {
4562236b 1069 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 1070 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 1071 return &res_ctx->pipe_ctx[i];
1072 break;
1073 }
1074 }
1075 return NULL;
1076}
1077
19f89e23
AG		 1078static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1079 struct resource_context *res_ctx,
1080 struct dc_stream_state *stream)
1081{
1082 struct pipe_ctx *head_pipe, *tail_pipe;
1083 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1084
1085 if (!head_pipe)
1086 return NULL;
1087
1088 tail_pipe = head_pipe->bottom_pipe;
1089
1090 while (tail_pipe) {
1091 head_pipe = tail_pipe;
1092 tail_pipe = tail_pipe->bottom_pipe;
1093 }
1094
1095 return head_pipe;
1096}
1097
4562236b 1098/*
ab2541b6
AC		 1099 * A free_pipe for a stream is defined here as a pipe
1100 * that has no surface attached yet
4562236b 1101 */
ab2541b6 1102static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1103 struct dc_state *context,
a2b8659d 1104 const struct resource_pool *pool,
0971c40e 1105 struct dc_stream_state *stream)
4562236b
HW		 1106{
1107 int i;
745cc746 1108 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1109
1110 struct pipe_ctx *head_pipe = NULL;
1111
1112 /* Find head pipe, which has the back end set up*/
1113
1114 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1115
e41ab030 1116 if (!head_pipe) {
4562236b 1117 ASSERT(0);
e41ab030
HW		 1118 return NULL;
1119 }
4562236b 1120
3be5262e 1121 if (!head_pipe->plane_state)
4562236b
HW		 1122 return head_pipe;
1123
1124 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1125 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1126 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1127 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1128 return &res_ctx->pipe_ctx[i];
1129 }
1130 }
1131
1132 /*
1133 * At this point we have no re-useable pipe for this stream and we need
1134 * to acquire an idle one to satisfy the request
1135 */
1136
a2b8659d 1137 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1138 return NULL;
1139
a2b8659d 1140 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1141
1142}
1143
dc37a9a0 1144#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
0f9a536f
DL		 1145static int acquire_first_split_pipe(
1146 struct resource_context *res_ctx,
1147 const struct resource_pool *pool,
0971c40e 1148 struct dc_stream_state *stream)
0f9a536f
DL		 1149{
1150 int i;
1151
1152 for (i = 0; i < pool->pipe_count; i++) {
1153 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1154
1155 if (pipe_ctx->top_pipe &&
3be5262e 1156 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1157 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1158 if (pipe_ctx->bottom_pipe)
1159 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1160
1161 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1162 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1163 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1164 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1165 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1166 pipe_ctx->stream_res.opp = pool->opps[i];
e07f541f 1167 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
0f9a536f 1168 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1169
1170 pipe_ctx->stream = stream;
1171 return i;
1172 }
1173 }
1174 return -1;
1175}
1176#endif
1177
19f89e23
AG		 1178bool dc_add_plane_to_context(
1179 const struct dc *dc,
0971c40e 1180 struct dc_stream_state *stream,
19f89e23 1181 struct dc_plane_state *plane_state,
608ac7bb 1182 struct dc_state *context)
4562236b
HW		 1183{
1184 int i;
19f89e23
AG		 1185 struct resource_pool *pool = dc->res_pool;
1186 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1187 struct dc_stream_status *stream_status = NULL;
4562236b 1188
19f89e23
AG		 1189 for (i = 0; i < context->stream_count; i++)
1190 if (context->streams[i] == stream) {
1191 stream_status = &context->stream_status[i];
1192 break;
1193 }
1194 if (stream_status == NULL) {
1195 dm_error("Existing stream not found; failed to attach surface!\n");
1196 return false;
1197 }
1198
4562236b 1199
19f89e23
AG		 1200 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1201 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1202 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1203 return false;
1204 }
1205
19f89e23
AG		 1206 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1207
1208 if (!head_pipe) {
1209 dm_error("Head pipe not found for stream_state %p !\n", stream);
1210 return false;
1211 }
1212
00737c59
EB		 1213 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1214 ASSERT(tail_pipe);
1215
19f89e23
AG		 1216 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1217
dc37a9a0 1218#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
19f89e23
AG		 1219 if (!free_pipe) {
1220 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1221 if (pipe_idx >= 0)
1222 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1223 }
1224#endif
abb4986e 1225 if (!free_pipe)
19f89e23 1226 return false;
19f89e23 1227
abb4986e
AJ		 1228 /* retain new surfaces */
1229 dc_plane_state_retain(plane_state);
19f89e23
AG		 1230 free_pipe->plane_state = plane_state;
1231
1232 if (head_pipe != free_pipe) {
19f89e23 1233 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1234 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1235 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1236 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1237 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1238 free_pipe->clock_source = tail_pipe->clock_source;
1239 free_pipe->top_pipe = tail_pipe;
1240 tail_pipe->bottom_pipe = free_pipe;
4a797d24
DL		 1241 } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
1242 ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
1243 free_pipe->bottom_pipe->plane_state = plane_state;
19f89e23
AG		 1244 }
1245
1246 /* assign new surfaces*/
1247 stream_status->plane_states[stream_status->plane_count] = plane_state;
1248
1249 stream_status->plane_count++;
1250
1251 return true;
1252}
1253
1254bool dc_remove_plane_from_context(
1255 const struct dc *dc,
1256 struct dc_stream_state *stream,
1257 struct dc_plane_state *plane_state,
608ac7bb 1258 struct dc_state *context)
19f89e23
AG		 1259{
1260 int i;
1261 struct dc_stream_status *stream_status = NULL;
1262 struct resource_pool *pool = dc->res_pool;
1263
ab2541b6 1264 for (i = 0; i < context->stream_count; i++)
4fa086b9 1265 if (context->streams[i] == stream) {
ab2541b6 1266 stream_status = &context->stream_status[i];
4562236b
HW		 1267 break;
1268 }
19f89e23 1269
ab2541b6 1270 if (stream_status == NULL) {
19f89e23 1271 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1272 return false;
1273 }
1274
19f89e23
AG		 1275 /* release pipe for plane*/
1276 for (i = pool->pipe_count - 1; i >= 0; i--) {
1277 struct pipe_ctx *pipe_ctx;
4562236b 1278
19f89e23
AG		 1279 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1280 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1281
19f89e23
AG		 1282 if (pipe_ctx->top_pipe)
1283 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1284
19f89e23
AG		 1285 /* Second condition is to avoid setting NULL to top pipe
1286 * of tail pipe making it look like head pipe in subsequent
1287 * deletes
1288 */
1289 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1290 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1291
19f89e23
AG		 1292 /*
1293 * For head pipe detach surfaces from pipe for tail
1294 * pipe just zero it out
1295 */
f25f06b6 1296 if (!pipe_ctx->top_pipe || (!pipe_ctx->top_pipe->top_pipe &&
bc219399 1297 pipe_ctx->top_pipe->stream_res.opp != pipe_ctx->stream_res.opp)) {
f25f06b6 1298 pipe_ctx->top_pipe = NULL;
19f89e23
AG		 1299 pipe_ctx->plane_state = NULL;
1300 pipe_ctx->bottom_pipe = NULL;
bc219399 1301 } else {
19f89e23
AG		 1302 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1303 }
4562236b 1304 }
19f89e23 1305 }
4562236b 1306
4562236b 1307
19f89e23
AG		 1308 for (i = 0; i < stream_status->plane_count; i++) {
1309 if (stream_status->plane_states[i] == plane_state) {
1310
1311 dc_plane_state_release(stream_status->plane_states[i]);
1312 break;
4562236b 1313 }
19f89e23 1314 }
4562236b 1315
19f89e23
AG		 1316 if (i == stream_status->plane_count) {
1317 dm_error("Existing plane_state not found; failed to detach it!\n");
1318 return false;
4562236b
HW		 1319 }
1320
19f89e23 1321 stream_status->plane_count--;
4562236b 1322
abb4986e
AJ		 1323 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1324 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1325 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1326
1327 stream_status->plane_states[stream_status->plane_count] = NULL;
1328
1329 return true;
1330}
1331
1332bool dc_rem_all_planes_for_stream(
1333 const struct dc *dc,
1334 struct dc_stream_state *stream,
608ac7bb 1335 struct dc_state *context)
19f89e23
AG		 1336{
1337 int i, old_plane_count;
1338 struct dc_stream_status *stream_status = NULL;
1339 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1340
1341 for (i = 0; i < context->stream_count; i++)
1342 if (context->streams[i] == stream) {
1343 stream_status = &context->stream_status[i];
1344 break;
1345 }
1346
1347 if (stream_status == NULL) {
1348 dm_error("Existing stream %p not found!\n", stream);
1349 return false;
1350 }
1351
1352 old_plane_count = stream_status->plane_count;
1353
1354 for (i = 0; i < old_plane_count; i++)
1355 del_planes[i] = stream_status->plane_states[i];
1356
1357 for (i = 0; i < old_plane_count; i++)
1358 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1359 return false;
1360
1361 return true;
1362}
1363
1364static bool add_all_planes_for_stream(
1365 const struct dc *dc,
1366 struct dc_stream_state *stream,
1367 const struct dc_validation_set set[],
1368 int set_count,
608ac7bb 1369 struct dc_state *context)
19f89e23
AG		 1370{
1371 int i, j;
1372
1373 for (i = 0; i < set_count; i++)
1374 if (set[i].stream == stream)
1375 break;
1376
1377 if (i == set_count) {
1378 dm_error("Stream %p not found in set!\n", stream);
1379 return false;
1380 }
4562236b 1381
19f89e23
AG		 1382 for (j = 0; j < set[i].plane_count; j++)
1383 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1384 return false;
4562236b
HW		 1385
1386 return true;
1387}
1388
19f89e23
AG		 1389bool dc_add_all_planes_for_stream(
1390 const struct dc *dc,
1391 struct dc_stream_state *stream,
1392 struct dc_plane_state * const *plane_states,
1393 int plane_count,
608ac7bb 1394 struct dc_state *context)
19f89e23
AG		 1395{
1396 struct dc_validation_set set;
1397 int i;
1398
1399 set.stream = stream;
1400 set.plane_count = plane_count;
1401
1402 for (i = 0; i < plane_count; i++)
1403 set.plane_states[i] = plane_states[i];
1404
1405 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1406}
1407
1408
6b622181
JP		 1409static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1410 struct dc_stream_state *new_stream)
1411{
1412 if (cur_stream == NULL)
1413 return true;
1414
1415 if (memcmp(&cur_stream->hdr_static_metadata,
1416 &new_stream->hdr_static_metadata,
1417 sizeof(struct dc_info_packet)) != 0)
1418 return true;
1419
1420 return false;
1421}
4562236b 1422
1336926f
A		 1423static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1424 struct dc_stream_state *new_stream)
1425{
1426 if (cur_stream == NULL)
1427 return true;
1428
1429 if (memcmp(&cur_stream->vsc_infopacket,
1430 &new_stream->vsc_infopacket,
1431 sizeof(struct dc_info_packet)) != 0)
1432 return true;
1433
1434 return false;
1435}
1436
0971c40e
HW		 1437static bool is_timing_changed(struct dc_stream_state *cur_stream,
1438 struct dc_stream_state *new_stream)
4562236b
HW		 1439{
1440 if (cur_stream == NULL)
1441 return true;
1442
1443 /* If sink pointer changed, it means this is a hotplug, we should do
1444 * full hw setting.
1445 */
1446 if (cur_stream->sink != new_stream->sink)
1447 return true;
1448
1449 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1450 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1451 return true;
1452
1453 return memcmp(
4fa086b9
LSL		 1454 &cur_stream->timing,
1455 &new_stream->timing,
4562236b
HW		 1456 sizeof(struct dc_crtc_timing)) != 0;
1457}
1458
1459static bool are_stream_backends_same(
0971c40e 1460 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1461{
1462 if (stream_a == stream_b)
1463 return true;
1464
1465 if (stream_a == NULL || stream_b == NULL)
1466 return false;
1467
1468 if (is_timing_changed(stream_a, stream_b))
1469 return false;
1470
6b622181
JP		 1471 if (is_hdr_static_meta_changed(stream_a, stream_b))
1472 return false;
1473
1e7e86c4
ST		 1474 if (stream_a->dpms_off != stream_b->dpms_off)
1475 return false;
1476
1336926f
A		 1477 if (is_vsc_info_packet_changed(stream_a, stream_b))
1478 return false;
1479
4562236b
HW		 1480 return true;
1481}
1482
2119aa17
DF		 1483/**
1484 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1485 *
1486 * Checks if there a difference between the two states
1487 * that would require a mode change.
1488 *
1489 * Does not compare cursor position or attributes.
1490 */
d54d29db 1491bool dc_is_stream_unchanged(
0971c40e 1492 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1493{
4562236b 1494
ab2541b6
AC		 1495 if (!are_stream_backends_same(old_stream, stream))
1496 return false;
4562236b
HW		 1497
1498 return true;
1499}
1500
2119aa17
DF		 1501/**
1502 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1503 */
9a5d9c48
LSL		 1504bool dc_is_stream_scaling_unchanged(
1505 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1506{
1507 if (old_stream == stream)
1508 return true;
1509
1510 if (old_stream == NULL || stream == NULL)
1511 return false;
1512
1513 if (memcmp(&old_stream->src,
1514 &stream->src,
1515 sizeof(struct rect)) != 0)
1516 return false;
1517
1518 if (memcmp(&old_stream->dst,
1519 &stream->dst,
1520 sizeof(struct rect)) != 0)
1521 return false;
1522
1523 return true;
1524}
1525
1dc90497 1526static void update_stream_engine_usage(
4562236b 1527 struct resource_context *res_ctx,
a2b8659d 1528 const struct resource_pool *pool,
1dc90497
AG		 1529 struct stream_encoder *stream_enc,
1530 bool acquired)
4562236b
HW		 1531{
1532 int i;
1533
a2b8659d
TC		 1534 for (i = 0; i < pool->stream_enc_count; i++) {
1535 if (pool->stream_enc[i] == stream_enc)
1dc90497 1536 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1537 }
1538}
1539
1540/* TODO: release audio object */
4176664b 1541void update_audio_usage(
4562236b 1542 struct resource_context *res_ctx,
a2b8659d 1543 const struct resource_pool *pool,
1dc90497
AG		 1544 struct audio *audio,
1545 bool acquired)
4562236b
HW		 1546{
1547 int i;
a2b8659d
TC		 1548 for (i = 0; i < pool->audio_count; i++) {
1549 if (pool->audios[i] == audio)
1dc90497 1550 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1551 }
1552}
1553
1554static int acquire_first_free_pipe(
1555 struct resource_context *res_ctx,
a2b8659d 1556 const struct resource_pool *pool,
0971c40e 1557 struct dc_stream_state *stream)
4562236b
HW		 1558{
1559 int i;
1560
a2b8659d 1561 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1562 if (!res_ctx->pipe_ctx[i].stream) {
1563 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1564
6b670fa9 1565 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1566 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1567 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1568 pipe_ctx->plane_res.ipp = pool->ipps[i];
1569 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1570 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1571 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1572 if (pool->dpps[i])
1573 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1574 pipe_ctx->pipe_idx = i;
1575
ff5ef992 1576
4562236b
HW		 1577 pipe_ctx->stream = stream;
1578 return i;
1579 }
1580 }
1581 return -1;
1582}
1583
1584static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1585 struct resource_context *res_ctx,
a2b8659d 1586 const struct resource_pool *pool,
0971c40e 1587 struct dc_stream_state *stream)
4562236b
HW		 1588{
1589 int i;
1590 int j = -1;
ceb3dbb4 1591 struct dc_link *link = stream->link;
4562236b 1592
a2b8659d 1593 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1594 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1595 pool->stream_enc[i]) {
4562236b
HW		 1596 /* Store first available for MST second display
1597 * in daisy chain use case */
1598 j = i;
a2b8659d 1599 if (pool->stream_enc[i]->id ==
4562236b 1600 link->link_enc->preferred_engine)
a2b8659d 1601 return pool->stream_enc[i];
4562236b
HW		 1602 }
1603 }
1604
1605 /*
1606 * below can happen in cases when stream encoder is acquired:
1607 * 1) for second MST display in chain, so preferred engine already
1608 * acquired;
1609 * 2) for another link, which preferred engine already acquired by any
1610 * MST configuration.
1611 *
1612 * If signal is of DP type and preferred engine not found, return last available
1613 *
1614 * TODO - This is just a patch up and a generic solution is
1615 * required for non DP connectors.
1616 */
1617
cae50a43 1618 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
a2b8659d 1619 return pool->stream_enc[j];
4562236b
HW		 1620
1621 return NULL;
1622}
1623
a2b8659d
TC		 1624static struct audio *find_first_free_audio(
1625 struct resource_context *res_ctx,
cfb071f7
CL		 1626 const struct resource_pool *pool,
1627 enum engine_id id)
4562236b
HW		 1628{
1629 int i;
66bfd4fd
CL		 1630 for (i = 0; i < pool->audio_count; i++) {
1631 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1632 /*we have enough audio endpoint, find the matching inst*/
1633 if (id != i)
1634 continue;
1635
66bfd4fd 1636 return pool->audios[i];
4562236b 1637 }
66bfd4fd
CL		 1638 }
1639 /*not found the matching one, first come first serve*/
1640 for (i = 0; i < pool->audio_count; i++) {
1641 if (res_ctx->is_audio_acquired[i] == false) {
1642 return pool->audios[i];
4176664b
CL		 1643 }
1644 }
4562236b
HW		 1645 return 0;
1646}
1647
4562236b 1648bool resource_is_stream_unchanged(
608ac7bb 1649 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1650{
ab2541b6 1651 int i;
4562236b 1652
ab2541b6 1653 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1654 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1655
ab2541b6 1656 if (are_stream_backends_same(old_stream, stream))
4562236b 1657 return true;
4562236b
HW		 1658 }
1659
1660 return false;
1661}
1662
2119aa17
DF		 1663/**
1664 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1665 */
13ab1b44 1666enum dc_status dc_add_stream_to_ctx(
1dc90497 1667 struct dc *dc,
608ac7bb 1668 struct dc_state *new_ctx,
1dc90497
AG		 1669 struct dc_stream_state *stream)
1670{
1dc90497 1671 enum dc_status res;
eb9714a2 1672 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1673
ece4147f 1674 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1675 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1676 return DC_ERROR_UNEXPECTED;
1677 }
1678
1679 new_ctx->streams[new_ctx->stream_count] = stream;
1680 dc_stream_retain(stream);
1681 new_ctx->stream_count++;
1682
1683 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1684 if (res != DC_OK)
eb9714a2 1685 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1686
13ab1b44 1687 return res;
1dc90497
AG		 1688}
1689
2119aa17
DF		 1690/**
1691 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1692 */
62c933f9 1693enum dc_status dc_remove_stream_from_ctx(
1dc90497 1694 struct dc *dc,
608ac7bb 1695 struct dc_state *new_ctx,
1dc90497
AG		 1696 struct dc_stream_state *stream)
1697{
19f89e23 1698 int i;
1dc90497
AG		 1699 struct dc_context *dc_ctx = dc->ctx;
1700 struct pipe_ctx *del_pipe = NULL;
1701
19f89e23 1702 /* Release primary pipe */
1dc90497 1703 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1704 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1705 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1706 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1707
19f89e23
AG		 1708 ASSERT(del_pipe->stream_res.stream_enc);
1709 update_stream_engine_usage(
1710 &new_ctx->res_ctx,
1dc90497 1711 dc->res_pool,
19f89e23
AG		 1712 del_pipe->stream_res.stream_enc,
1713 false);
1dc90497
AG		 1714
1715 if (del_pipe->stream_res.audio)
1716 update_audio_usage(
1717 &new_ctx->res_ctx,
1718 dc->res_pool,
1719 del_pipe->stream_res.audio,
1720 false);
1721
9d0dcecd
HW		 1722 resource_unreference_clock_source(&new_ctx->res_ctx,
1723 dc->res_pool,
1724 del_pipe->clock_source);
1725
e56ae556
NC		 1726 if (dc->res_pool->funcs->remove_stream_from_ctx)
1727 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1728
1dc90497
AG		 1729 memset(del_pipe, 0, sizeof(*del_pipe));
1730 }
1731 }
1732
1733 if (!del_pipe) {
1734 DC_ERROR("Pipe not found for stream %p !\n", stream);
1735 return DC_ERROR_UNEXPECTED;
1736 }
1737
1738 for (i = 0; i < new_ctx->stream_count; i++)
1739 if (new_ctx->streams[i] == stream)
1740 break;
1741
1742 if (new_ctx->streams[i] != stream) {
1743 DC_ERROR("Context doesn't have stream %p !\n", stream);
1744 return DC_ERROR_UNEXPECTED;
1745 }
1746
1747 dc_stream_release(new_ctx->streams[i]);
1748 new_ctx->stream_count--;
1749
1dc90497
AG		 1750 /* Trim back arrays */
1751 for (; i < new_ctx->stream_count; i++) {
1752 new_ctx->streams[i] = new_ctx->streams[i + 1];
1753 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1754 }
1755
1756 new_ctx->streams[new_ctx->stream_count] = NULL;
1757 memset(
1758 &new_ctx->stream_status[new_ctx->stream_count],
1759 0,
1760 sizeof(new_ctx->stream_status[0]));
1761
1762 return DC_OK;
1763}
1764
0971c40e
HW		 1765static struct dc_stream_state *find_pll_sharable_stream(
1766 struct dc_stream_state *stream_needs_pll,
608ac7bb 1767 struct dc_state *context)
4562236b 1768{
ab2541b6 1769 int i;
4562236b 1770
ab2541b6 1771 for (i = 0; i < context->stream_count; i++) {
0971c40e 1772 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1773
ab2541b6
AC		 1774 /* We are looking for non dp, non virtual stream */
1775 if (resource_are_streams_timing_synchronizable(
1776 stream_needs_pll, stream_has_pll)
1777 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1778 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1779 != SIGNAL_TYPE_VIRTUAL)
1780 return stream_has_pll;
4562236b 1781
4562236b
HW		 1782 }
1783
1784 return NULL;
1785}
1786
1787static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1788{
380604e2 1789 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1790 uint32_t normalized_pix_clk = pix_clk;
1791
1792 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1793 pix_clk /= 2;
cc4d99b8
CL		 1794 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1795 switch (timing->display_color_depth) {
1796 case COLOR_DEPTH_888:
1797 normalized_pix_clk = pix_clk;
1798 break;
1799 case COLOR_DEPTH_101010:
1800 normalized_pix_clk = (pix_clk * 30) / 24;
1801 break;
1802 case COLOR_DEPTH_121212:
1803 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1804 break;
cc4d99b8
CL		 1805 case COLOR_DEPTH_161616:
1806 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1807 break;
cc4d99b8
CL		 1808 default:
1809 ASSERT(0);
4562236b 1810 break;
cc4d99b8 1811 }
4562236b 1812 }
4562236b
HW		 1813 return normalized_pix_clk;
1814}
1815
0971c40e 1816static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1817{
9345d987
AG		 1818 /* update actual pixel clock on all streams */
1819 if (dc_is_hdmi_signal(stream->signal))
1820 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1821 &stream->timing) / 10;
9345d987
AG		 1822 else
1823 stream->phy_pix_clk =
380604e2 1824 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1825
1826 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1827 stream->phy_pix_clk *= 2;
4562236b
HW		 1828}
1829
d2d7885f
AK		 1830static int acquire_resource_from_hw_enabled_state(
1831 struct resource_context *res_ctx,
1832 const struct resource_pool *pool,
1833 struct dc_stream_state *stream)
1834{
1835 struct dc_link *link = stream->link;
1836 unsigned int inst;
1837
1838 /* Check for enabled DIG to identify enabled display */
1839 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1840 return -1;
1841
1842 /* Check for which front end is used by this encoder.
1843 * Note the inst is 1 indexed, where 0 is undefined.
1844 * Note that DIG_FE can source from different OTG but our
1845 * current implementation always map 1-to-1, so this code makes
1846 * the same assumption and doesn't check OTG source.
1847 */
1848 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
1849
1850 /* Instance should be within the range of the pool */
1851 if (inst >= pool->pipe_count)
1852 return -1;
1853
1854 if (!res_ctx->pipe_ctx[inst].stream) {
1855 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
1856
1857 pipe_ctx->stream_res.tg = pool->timing_generators[inst];
1858 pipe_ctx->plane_res.mi = pool->mis[inst];
1859 pipe_ctx->plane_res.hubp = pool->hubps[inst];
1860 pipe_ctx->plane_res.ipp = pool->ipps[inst];
1861 pipe_ctx->plane_res.xfm = pool->transforms[inst];
1862 pipe_ctx->plane_res.dpp = pool->dpps[inst];
1863 pipe_ctx->stream_res.opp = pool->opps[inst];
1864 if (pool->dpps[inst])
1865 pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
1866 pipe_ctx->pipe_idx = inst;
1867
1868 pipe_ctx->stream = stream;
1869 return inst;
1870 }
1871
1872 return -1;
1873}
1874
4562236b 1875enum dc_status resource_map_pool_resources(
fb3466a4 1876 const struct dc *dc,
608ac7bb 1877 struct dc_state *context,
1dc90497 1878 struct dc_stream_state *stream)
4562236b 1879{
a2b8659d 1880 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1881 int i;
1882 struct dc_context *dc_ctx = dc->ctx;
1883 struct pipe_ctx *pipe_ctx = NULL;
1884 int pipe_idx = -1;
46570f09 1885 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1886
1dc90497
AG		 1887 /* TODO Check if this is needed */
1888 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1889 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1890 stream->bit_depth_params =
430ef426
DL		 1891 old_context->streams[i]->bit_depth_params;
1892 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1893 continue;
1894 }
4b679bc3 1895 }
1dc90497 1896 */
7e2fe319 1897
08e1c28d
YMM		 1898 calculate_phy_pix_clks(stream);
1899
46570f09
AK		 1900 /* TODO: Check Linux */
1901 if (dc->config.allow_seamless_boot_optimization &&
1902 !dcb->funcs->is_accelerated_mode(dcb)) {
1903 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1904 stream->apply_seamless_boot_optimization = true;
1905 }
1906
d2d7885f
AK		 1907 if (stream->apply_seamless_boot_optimization)
1908 pipe_idx = acquire_resource_from_hw_enabled_state(
1909 &context->res_ctx,
1910 pool,
1911 stream);
1912
1913 if (pipe_idx < 0)
1914 /* acquire new resources */
1915 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1916
dc37a9a0 1917#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1918 if (pipe_idx < 0)
13ab1b44 1919 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1920#endif
13ab1b44 1921
c5b38aec 1922 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1923 return DC_NO_CONTROLLER_RESOURCE;
1924
1925 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1926
1927 pipe_ctx->stream_res.stream_enc =
1928 find_first_free_match_stream_enc_for_link(
1929 &context->res_ctx, pool, stream);
1930
1931 if (!pipe_ctx->stream_res.stream_enc)
38684e46 1932 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 1933
1934 update_stream_engine_usage(
1935 &context->res_ctx, pool,
1936 pipe_ctx->stream_res.stream_enc,
1937 true);
1938
1939 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 1940 if (!stream->converter_disable_audio &&
1dc90497
AG		 1941 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1942 stream->audio_info.mode_count) {
1943 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1944 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1945
1946 /*
1947 * Audio assigned in order first come first get.
1948 * There are asics which has number of audio
1949 * resources less then number of pipes
1950 */
1951 if (pipe_ctx->stream_res.audio)
1952 update_audio_usage(&context->res_ctx, pool,
1953 pipe_ctx->stream_res.audio, true);
1954 }
268cadbd 1955
9aef1a31
S		 1956 /* Add ABM to the resource if on EDP */
1957 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1958 pipe_ctx->stream_res.abm = pool->abm;
1959
1dc90497
AG		 1960 for (i = 0; i < context->stream_count; i++)
1961 if (context->streams[i] == stream) {
1962 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1963 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1964 return DC_OK;
1965 }
4562236b 1966
1dc90497
AG		 1967 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1968 return DC_ERROR_UNEXPECTED;
1969}
4562236b 1970
2119aa17
DF		 1971/**
1972 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
1973 * Is a shallow copy. Increments refcounts on existing streams and planes.
1974 * @dc: copy out of dc->current_state
1975 * @dst_ctx: copy into this
1976 */
f36cc577 1977void dc_resource_state_copy_construct_current(
1dc90497 1978 const struct dc *dc,
608ac7bb 1979 struct dc_state *dst_ctx)
1dc90497 1980{
f36cc577 1981 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1982}
1983
ab8db3e1
AG		 1984
1985void dc_resource_state_construct(
1986 const struct dc *dc,
1987 struct dc_state *dst_ctx)
1988{
84e7fc05 1989 dst_ctx->dccg = dc->res_pool->clk_mgr;
ab8db3e1
AG		 1990}
1991
2119aa17
DF		 1992/**
1993 * dc_validate_global_state() - Determine if HW can support a given state
1994 * Checks HW resource availability and bandwidth requirement.
1995 * @dc: dc struct for this driver
1996 * @new_ctx: state to be validated
1997 *
1998 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
1999 */
e750d56d 2000enum dc_status dc_validate_global_state(
1dc90497 2001 struct dc *dc,
608ac7bb 2002 struct dc_state *new_ctx)
4562236b 2003{
1dc90497 2004 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2005 int i, j;
4562236b 2006
e41ab030
HW		 2007 if (!new_ctx)
2008 return DC_ERROR_UNEXPECTED;
2009
d596e5d0 2010 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2011 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2012 if (result != DC_OK)
2013 return result;
d596e5d0 2014 }
4562236b 2015
e41ab030 2016 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2017 struct dc_stream_state *stream = new_ctx->streams[i];
2018
2019 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2020 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2021
2022 if (pipe_ctx->stream != stream)
2023 continue;
2024
74eac5f3
SSC		 2025 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2026 pipe_ctx->plane_state &&
2027 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2028 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2029 if (result != DC_OK)
2030 return result;
2031 }
2032
1dc90497
AG		 2033 /* Switch to dp clock source only if there is
2034 * no non dp stream that shares the same timing
2035 * with the dp stream.
2036 */
2037 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2038 !find_pll_sharable_stream(stream, new_ctx)) {
2039
9d0dcecd 2040 resource_unreference_clock_source(
1dc90497
AG		 2041 &new_ctx->res_ctx,
2042 dc->res_pool,
9d0dcecd 2043 pipe_ctx->clock_source);
4a629536 2044
1dc90497
AG		 2045 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2046 resource_reference_clock_source(
2047 &new_ctx->res_ctx,
2048 dc->res_pool,
2049 pipe_ctx->clock_source);
2050 }
2051 }
2052 }
2053
1dc90497
AG		 2054 result = resource_build_scaling_params_for_context(dc, new_ctx);
2055
2056 if (result == DC_OK)
2057 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
2058 result = DC_FAIL_BANDWIDTH_VALIDATE;
2059
2060 return result;
4562236b
HW		 2061}
2062
6e4d6bee 2063static void patch_gamut_packet_checksum(
e09b6473 2064 struct dc_info_packet *gamut_packet)
4562236b 2065{
4562236b 2066 /* For gamut we recalc checksum */
6e4d6bee 2067 if (gamut_packet->valid) {
4562236b
HW		 2068 uint8_t chk_sum = 0;
2069 uint8_t *ptr;
2070 uint8_t i;
2071
4562236b 2072 /*start of the Gamut data. */
6e4d6bee 2073 ptr = &gamut_packet->sb[3];
4562236b 2074
6e4d6bee 2075 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2076 chk_sum += ptr[i];
2077
6e4d6bee 2078 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2079 }
4562236b
HW		 2080}
2081
2082static void set_avi_info_frame(
e09b6473 2083 struct dc_info_packet *info_packet,
4562236b
HW		 2084 struct pipe_ctx *pipe_ctx)
2085{
0971c40e 2086 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2087 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2088 uint32_t pixel_encoding = 0;
2089 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2090 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2091 bool itc = false;
50e27654 2092 uint8_t itc_value = 0;
4562236b 2093 uint8_t cn0_cn1 = 0;
50e27654 2094 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2095 uint8_t *check_sum = NULL;
2096 uint8_t byte_index = 0;
754e3673 2097 union hdmi_info_packet hdmi_info;
50e27654 2098 union display_content_support support = {0};
4fa086b9 2099 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2100 enum dc_timing_3d_format format;
4562236b 2101
754e3673
AK		 2102 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2103
4fa086b9 2104 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2105 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2106 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2107 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2108
2109 /* Initialize header */
e09b6473 2110 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2111 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2112 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2113 hdmi_info.bits.header.version = 2;
2114 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2115
2116 /*
2117 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2118 * according to HDMI 2.0 spec (Section 10.1)
2119 */
2120
4fa086b9 2121 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2122 case PIXEL_ENCODING_YCBCR422:
2123 pixel_encoding = 1;
2124 break;
2125
2126 case PIXEL_ENCODING_YCBCR444:
2127 pixel_encoding = 2;
2128 break;
2129 case PIXEL_ENCODING_YCBCR420:
2130 pixel_encoding = 3;
2131 break;
2132
2133 case PIXEL_ENCODING_RGB:
2134 default:
2135 pixel_encoding = 0;
2136 }
2137
2138 /* Y0_Y1_Y2 : The pixel encoding */
2139 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2140 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2141
2142 /* A0 = 1 Active Format Information valid */
e09b6473 2143 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2144
2145 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2146 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2147
e09b6473 2148 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2149
2150 /* S0, S1 : Underscan / Overscan */
2151 /* TODO: un-hardcode scan type */
2152 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2153 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2154
2155 /* C0, C1 : Colorimetry */
8fde5884 2156 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2157 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2158 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2159 else if (color_space == COLOR_SPACE_YCBCR601 ||
2160 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2161 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2162 else {
e09b6473 2163 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2164 }
534db198 2165 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2166 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2167 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2168 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2169 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2170 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2171 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2172 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2173 }
2174
4562236b 2175 /* TODO: un-hardcode aspect ratio */
4fa086b9 2176 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2177
2178 switch (aspect) {
2179 case ASPECT_RATIO_4_3:
2180 case ASPECT_RATIO_16_9:
e09b6473 2181 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2182 break;
2183
2184 case ASPECT_RATIO_NO_DATA:
2185 case ASPECT_RATIO_64_27:
2186 case ASPECT_RATIO_256_135:
2187 default:
e09b6473 2188 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2189 }
2190
2191 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2192 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2193
2194 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2195
4562236b 2196 cn0_cn1 = 0;
50e27654
ZF		 2197 cn0_cn1_value = 0;
2198
2199 itc = true;
2200 itc_value = 1;
2201
ceb3dbb4 2202 support = stream->content_support;
4562236b
HW		 2203
2204 if (itc) {
50e27654
ZF		 2205 if (!support.bits.valid_content_type) {
2206 cn0_cn1_value = 0;
2207 } else {
2208 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2209 if (support.bits.graphics_content == 1) {
2210 cn0_cn1_value = 0;
2211 }
2212 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2213 if (support.bits.photo_content == 1) {
2214 cn0_cn1_value = 1;
2215 } else {
2216 cn0_cn1_value = 0;
2217 itc_value = 0;
2218 }
2219 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2220 if (support.bits.cinema_content == 1) {
2221 cn0_cn1_value = 2;
2222 } else {
2223 cn0_cn1_value = 0;
2224 itc_value = 0;
2225 }
2226 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2227 if (support.bits.game_content == 1) {
2228 cn0_cn1_value = 3;
2229 } else {
2230 cn0_cn1_value = 0;
2231 itc_value = 0;
2232 }
2233 }
2234 }
e09b6473
AK		 2235 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2236 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2237 }
2238
2239 /* TODO : We should handle YCC quantization */
2240 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2241 if (stream->qs_bit == 1 &&
2242 stream->qy_bit == 1) {
50e27654
ZF		 2243 if (color_space == COLOR_SPACE_SRGB ||
2244 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2245 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2246 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2247 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2248 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2249 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2250 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2251 } else {
e09b6473
AK		 2252 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2253 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2254 }
4562236b 2255 } else {
e09b6473
AK		 2256 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2257 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2258 }
50e27654 2259
15e17335 2260 ///VIC
4fa086b9 2261 format = stream->timing.timing_3d_format;
15e17335
CL		 2262 /*todo, add 3DStereo support*/
2263 if (format != TIMING_3D_FORMAT_NONE) {
2264 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2265 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2266 case 1:
2267 vic = 95;
2268 break;
2269 case 2:
2270 vic = 94;
2271 break;
2272 case 3:
2273 vic = 93;
2274 break;
2275 case 4:
2276 vic = 98;
2277 break;
2278 default:
2279 break;
2280 }
2281 }
e09b6473 2282 hdmi_info.bits.VIC0_VIC7 = vic;
4562236b
HW		 2283
2284 /* pixel repetition
2285 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2286 * repetition start from 1 */
e09b6473 2287 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2288
2289 /* Bar Info
2290 * barTop: Line Number of End of Top Bar.
2291 * barBottom: Line Number of Start of Bottom Bar.
2292 * barLeft: Pixel Number of End of Left Bar.
2293 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2294 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2295 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2296 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2297 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2298 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2299 - stream->timing.h_border_right + 1);
4562236b
HW		 2300
2301 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2302 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2303
3e183c5f 2304 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2305
3e183c5f 2306 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e09b6473 2307 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2308
2309 /* one byte complement */
2310 *check_sum = (uint8_t) (0x100 - *check_sum);
2311
2312 /* Store in hw_path_mode */
e09b6473
AK		 2313 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2314 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2315 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2316
e09b6473
AK		 2317 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2318 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2319
2320 info_packet->valid = true;
2321}
2322
6e4d6bee 2323static void set_vendor_info_packet(
e09b6473 2324 struct dc_info_packet *info_packet,
0971c40e 2325 struct dc_stream_state *stream)
4562236b 2326{
ecd0136b 2327 /* SPD info packet for FreeSync */
4562236b 2328
ecd0136b
HT		 2329 /* Check if Freesync is supported. Return if false. If true,
2330 * set the corresponding bit in the info packet
2331 */
2332 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2333 return;
2334
ecd0136b 2335 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2336}
2337
6e4d6bee 2338static void set_spd_info_packet(
e09b6473 2339 struct dc_info_packet *info_packet,
0971c40e 2340 struct dc_stream_state *stream)
4562236b
HW		 2341{
2342 /* SPD info packet for FreeSync */
2343
4562236b
HW		 2344 /* Check if Freesync is supported. Return if false. If true,
2345 * set the corresponding bit in the info packet
2346 */
98e6436d 2347 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2348 return;
2349
98e6436d 2350 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2351}
2352
1646a6fe 2353static void set_hdr_static_info_packet(
e09b6473 2354 struct dc_info_packet *info_packet,
0971c40e 2355 struct dc_stream_state *stream)
1646a6fe 2356{
0eeef690 2357 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2358
a10dc97a
KK		 2359 if (!stream->hdr_static_metadata.valid ||
2360 stream->use_dynamic_meta)
10bff005
YS		 2361 return;
2362
0eeef690 2363 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2364}
2365
6e4d6bee 2366static void set_vsc_info_packet(
e09b6473 2367 struct dc_info_packet *info_packet,
0971c40e 2368 struct dc_stream_state *stream)
4562236b 2369{
1336926f 2370 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2371 return;
2372
1336926f 2373 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2374}
2375
f36cc577 2376void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2377{
2378 int i, j;
2379
ab2541b6 2380 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2381 for (j = 0; j < context->stream_status[i].plane_count; j++)
2382 dc_plane_state_release(
2383 context->stream_status[i].plane_states[j]);
4562236b 2384
3be5262e 2385 context->stream_status[i].plane_count = 0;
4fa086b9 2386 dc_stream_release(context->streams[i]);
ab2541b6 2387 context->streams[i] = NULL;
4562236b
HW		 2388 }
2389}
2390
f36cc577 2391void dc_resource_state_copy_construct(
608ac7bb
JZ		 2392 const struct dc_state *src_ctx,
2393 struct dc_state *dst_ctx)
4562236b
HW		 2394{
2395 int i, j;
8ee5702a 2396 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2397
2398 *dst_ctx = *src_ctx;
2399
a2b8659d 2400 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2401 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2402
2403 if (cur_pipe->top_pipe)
2404 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2405
2406 if (cur_pipe->bottom_pipe)
2407 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2408
2409 }
2410
ab2541b6 2411 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2412 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2413 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2414 dc_plane_state_retain(
2415 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2416 }
9a3afbb3
AG		 2417
2418 /* context refcount should not be overridden */
8ee5702a 2419 dst_ctx->refcount = refcount;
9a3afbb3 2420
4562236b
HW		 2421}
2422
2423struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2424 struct resource_context *res_ctx,
2425 const struct resource_pool *pool)
4562236b
HW		 2426{
2427 int i;
2428
a2b8659d 2429 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2430 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2431 return pool->clock_sources[i];
4562236b
HW		 2432 }
2433
2434 return NULL;
2435}
2436
2437void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2438{
2439 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2440 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2441
2442 /* default all packets to invalid */
6e4d6bee
TC		 2443 info->avi.valid = false;
2444 info->gamut.valid = false;
2445 info->vendor.valid = false;
630e3573 2446 info->spd.valid = false;
6e4d6bee
TC		 2447 info->hdrsmd.valid = false;
2448 info->vsc.valid = false;
4562236b
HW		 2449
2450 signal = pipe_ctx->stream->signal;
2451
2452 /* HDMi and DP have different info packets*/
2453 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2454 set_avi_info_frame(&info->avi, pipe_ctx);
2455
2456 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2457
2458 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2459
56ef6ed9 2460 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2461
a33fa99d 2462 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2463 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2464
2465 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2466
56ef6ed9 2467 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2468 }
4562236b 2469
6e4d6bee 2470 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2471}
2472
2473enum dc_status resource_map_clock_resources(
fb3466a4 2474 const struct dc *dc,
608ac7bb 2475 struct dc_state *context,
1dc90497 2476 struct dc_stream_state *stream)
4562236b 2477{
4562236b 2478 /* acquire new resources */
1dc90497
AG		 2479 const struct resource_pool *pool = dc->res_pool;
2480 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2481 &context->res_ctx, stream);
ab2541b6 2482
1dc90497
AG		 2483 if (!pipe_ctx)
2484 return DC_ERROR_UNEXPECTED;
4562236b 2485
1dc90497
AG		 2486 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2487 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2488 pipe_ctx->clock_source = pool->dp_clock_source;
2489 else {
2490 pipe_ctx->clock_source = NULL;
4562236b 2491
1dc90497 2492 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2493 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2494 &context->res_ctx,
2495 pipe_ctx);
4562236b 2496
1dc90497
AG		 2497 if (pipe_ctx->clock_source == NULL)
2498 pipe_ctx->clock_source =
2499 dc_resource_find_first_free_pll(
2500 &context->res_ctx,
2501 pool);
2502 }
4562236b 2503
1dc90497
AG		 2504 if (pipe_ctx->clock_source == NULL)
2505 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2506
1dc90497
AG		 2507 resource_reference_clock_source(
2508 &context->res_ctx, pool,
2509 pipe_ctx->clock_source);
4562236b
HW		 2510
2511 return DC_OK;
2512}
2513
2514/*
2515 * Note: We need to disable output if clock sources change,
2516 * since bios does optimization and doesn't apply if changing
2517 * PHY when not already disabled.
2518 */
2519bool pipe_need_reprogram(
2520 struct pipe_ctx *pipe_ctx_old,
2521 struct pipe_ctx *pipe_ctx)
2522{
cfe4645e
DL		 2523 if (!pipe_ctx_old->stream)
2524 return false;
2525
4562236b
HW		 2526 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2527 return true;
2528
2529 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2530 return true;
2531
afaacef4 2532 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2533 return true;
2534
2535 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2536 && pipe_ctx_old->stream != pipe_ctx->stream)
2537 return true;
2538
8e9c4c8c 2539 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2540 return true;
2541
2542 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2543 return true;
2544
6b622181
JP		 2545 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2546 return true;
4562236b 2547
1e7e86c4
ST		 2548 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2549 return true;
2550
1336926f
A		 2551 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2552 return true;
2553
4562236b
HW		 2554 return false;
2555}
529cad0f 2556
0971c40e 2557void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2558 struct bit_depth_reduction_params *fmt_bit_depth)
2559{
4fa086b9 2560 enum dc_dither_option option = stream->dither_option;
529cad0f 2561 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2562 stream->timing.pixel_encoding;
529cad0f
DW		 2563
2564 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2565
603767f9
TC		 2566 if (option == DITHER_OPTION_DEFAULT) {
2567 switch (stream->timing.display_color_depth) {
2568 case COLOR_DEPTH_666:
2569 option = DITHER_OPTION_SPATIAL6;
2570 break;
2571 case COLOR_DEPTH_888:
2572 option = DITHER_OPTION_SPATIAL8;
2573 break;
2574 case COLOR_DEPTH_101010:
2575 option = DITHER_OPTION_SPATIAL10;
2576 break;
2577 default:
2578 option = DITHER_OPTION_DISABLE;
2579 }
2580 }
2581
529cad0f
DW		 2582 if (option == DITHER_OPTION_DISABLE)
2583 return;
2584
2585 if (option == DITHER_OPTION_TRUN6) {
2586 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2587 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2588 } else if (option == DITHER_OPTION_TRUN8 ||
2589 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2590 option == DITHER_OPTION_TRUN8_FM6) {
2591 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2592 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2593 } else if (option == DITHER_OPTION_TRUN10 ||
2594 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2595 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2596 option == DITHER_OPTION_TRUN10_FM8 ||
2597 option == DITHER_OPTION_TRUN10_FM6 ||
2598 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2599 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2600 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2601 }
2602
2603 /* special case - Formatter can only reduce by 4 bits at most.
2604 * When reducing from 12 to 6 bits,
2605 * HW recommends we use trunc with round mode
2606 * (if we did nothing, trunc to 10 bits would be used)
2607 * note that any 12->10 bit reduction is ignored prior to DCE8,
2608 * as the input was 10 bits.
2609 */
2610 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2611 option == DITHER_OPTION_SPATIAL6 ||
2612 option == DITHER_OPTION_FM6) {
2613 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2614 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2615 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2616 }
2617
2618 /* spatial dither
2619 * note that spatial modes 1-3 are never used
2620 */
2621 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2622 option == DITHER_OPTION_SPATIAL6 ||
2623 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2624 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2625 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2626 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2627 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2628 fmt_bit_depth->flags.RGB_RANDOM =
2629 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2630 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2631 option == DITHER_OPTION_SPATIAL8 ||
2632 option == DITHER_OPTION_SPATIAL8_FM6 ||
2633 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2634 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2635 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2636 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2637 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2638 fmt_bit_depth->flags.RGB_RANDOM =
2639 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2640 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2641 option == DITHER_OPTION_SPATIAL10 ||
2642 option == DITHER_OPTION_SPATIAL10_FM8 ||
2643 option == DITHER_OPTION_SPATIAL10_FM6) {
2644 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2645 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2646 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2647 fmt_bit_depth->flags.RGB_RANDOM =
2648 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2649 }
2650
2651 if (option == DITHER_OPTION_SPATIAL6 ||
2652 option == DITHER_OPTION_SPATIAL8 ||
2653 option == DITHER_OPTION_SPATIAL10) {
2654 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2655 } else {
2656 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2657 }
2658
2659 //////////////////////
2660 //// temporal dither
2661 //////////////////////
2662 if (option == DITHER_OPTION_FM6 ||
2663 option == DITHER_OPTION_SPATIAL8_FM6 ||
2664 option == DITHER_OPTION_SPATIAL10_FM6 ||
2665 option == DITHER_OPTION_TRUN10_FM6 ||
2666 option == DITHER_OPTION_TRUN8_FM6 ||
2667 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2668 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2669 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2670 } else if (option == DITHER_OPTION_FM8 ||
2671 option == DITHER_OPTION_SPATIAL10_FM8 ||
2672 option == DITHER_OPTION_TRUN10_FM8) {
2673 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2674 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2675 } else if (option == DITHER_OPTION_FM10) {
2676 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2677 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2678 }
2679
2680 fmt_bit_depth->pixel_encoding = pixel_encoding;
2681}
9345d987 2682
62c933f9 2683enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2684{
fb3466a4 2685 struct dc *core_dc = dc;
ceb3dbb4 2686 struct dc_link *link = stream->link;
9345d987
AG		 2687 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2688 enum dc_status res = DC_OK;
2689
4fa086b9 2690 calculate_phy_pix_clks(stream);
9345d987 2691
4fa086b9 2692 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2693 res = DC_FAIL_CONTROLLER_VALIDATE;
2694
2695 if (res == DC_OK)
2696 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2697 link->link_enc, stream))
9345d987
AG		 2698 res = DC_FAIL_ENC_VALIDATE;
2699
2700 /* TODO: validate audio ASIC caps, encoder */
2701
2702 if (res == DC_OK)
4fa086b9 2703 res = dc_link_validate_mode_timing(stream,
9345d987 2704 link,
4fa086b9 2705 &stream->timing);
9345d987 2706
62c933f9 2707 return res;
9345d987 2708}
792671d7 2709
62c933f9 2710enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2711{
62c933f9
YS		 2712 enum dc_status res = DC_OK;
2713
792671d7 2714 /* TODO For now validates pixel format only */
8e7095b9 2715 if (dc->res_pool->funcs->validate_plane)
62c933f9 2716 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2717
62c933f9 2718 return res;
792671d7 2719}
74eac5f3
SSC		 2720
2721unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2722{
2723 switch (format) {
2724 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2725 return 8;
2726 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2727 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2728 return 12;
2729 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2730 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2731 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2732 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2733 return 16;
2734 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2735 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2736 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2737 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2738 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2739 return 32;
2740 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2741 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2742 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2743 return 64;
2744 default:
2745 ASSERT_CRITICAL(false);
2746 return -1;
2747 }
2748}
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