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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
5ac3d3c9 34#include "core_types.h"
4562236b 35#include "set_mode_types.h"
4562236b
HW		 36#include "virtual/virtual_stream_encoder.h"
37
38#include "dce80/dce80_resource.h"
39#include "dce100/dce100_resource.h"
40#include "dce110/dce110_resource.h"
41#include "dce112/dce112_resource.h"
2c8ad2d5 42#include "dce120/dce120_resource.h"
4562236b
HW		 43
44enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
45{
46 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
47 switch (asic_id.chip_family) {
48
49 case FAMILY_CI:
50 case FAMILY_KV:
51 dc_version = DCE_VERSION_8_0;
52 break;
53 case FAMILY_CZ:
54 dc_version = DCE_VERSION_11_0;
55 break;
56
57 case FAMILY_VI:
58 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
59 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
60 dc_version = DCE_VERSION_10_0;
61 break;
62 }
63 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 64 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
65 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 66 dc_version = DCE_VERSION_11_2;
67 }
68 break;
2c8ad2d5
AD		 69 case FAMILY_AI:
70 dc_version = DCE_VERSION_12_0;
71 break;
4562236b
HW		 72 default:
73 dc_version = DCE_VERSION_UNKNOWN;
74 break;
75 }
76 return dc_version;
77}
78
79struct resource_pool *dc_create_resource_pool(
80 struct core_dc *dc,
81 int num_virtual_links,
82 enum dce_version dc_version,
83 struct hw_asic_id asic_id)
84{
5ac3d3c9 85 struct resource_pool *res_pool = NULL;
4562236b
HW		 86
87 switch (dc_version) {
88 case DCE_VERSION_8_0:
5ac3d3c9 89 res_pool = dce80_create_resource_pool(
4562236b 90 num_virtual_links, dc);
5ac3d3c9 91 break;
4562236b 92 case DCE_VERSION_10_0:
5ac3d3c9 93 res_pool = dce100_create_resource_pool(
4562236b 94 num_virtual_links, dc);
5ac3d3c9 95 break;
4562236b 96 case DCE_VERSION_11_0:
5ac3d3c9 97 res_pool = dce110_create_resource_pool(
4562236b 98 num_virtual_links, dc, asic_id);
5ac3d3c9 99 break;
4562236b 100 case DCE_VERSION_11_2:
5ac3d3c9 101 res_pool = dce112_create_resource_pool(
4562236b 102 num_virtual_links, dc);
5ac3d3c9 103 break;
2c8ad2d5
AD		 104 case DCE_VERSION_12_0:
105 res_pool = dce120_create_resource_pool(
106 num_virtual_links, dc);
107 break;
4562236b
HW		 108 default:
109 break;
110 }
5ac3d3c9
CL		 111 if (res_pool != NULL) {
112 struct firmware_info fw_info = { { 0 } };
113
114 if (dc->ctx->dc_bios->funcs->get_firmware_info(
115 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
116 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
117 } else
118 ASSERT_CRITICAL(false);
119 }
4562236b 120
5ac3d3c9 121 return res_pool;
4562236b
HW		 122}
123
124void dc_destroy_resource_pool(struct core_dc *dc)
125{
126 if (dc) {
127 if (dc->res_pool)
128 dc->res_pool->funcs->destroy(&dc->res_pool);
129
130 if (dc->hwseq)
131 dm_free(dc->hwseq);
132 }
133}
134
135static void update_num_audio(
136 const struct resource_straps *straps,
137 unsigned int *num_audio,
138 struct audio_support *aud_support)
139{
140 if (straps->hdmi_disable == 0) {
141 aud_support->hdmi_audio_native = true;
142 aud_support->hdmi_audio_on_dongle = true;
143 aud_support->dp_audio = true;
144 } else {
145 if (straps->dc_pinstraps_audio & 0x2) {
146 aud_support->hdmi_audio_on_dongle = true;
147 aud_support->dp_audio = true;
148 } else {
149 aud_support->dp_audio = true;
150 }
151 }
152
153 switch (straps->audio_stream_number) {
154 case 0: /* multi streams supported */
155 break;
156 case 1: /* multi streams not supported */
157 *num_audio = 1;
158 break;
159 default:
160 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 161 }
4562236b
HW		 162}
163
164bool resource_construct(
165 unsigned int num_virtual_links,
166 struct core_dc *dc,
167 struct resource_pool *pool,
168 const struct resource_create_funcs *create_funcs)
169{
170 struct dc_context *ctx = dc->ctx;
171 const struct resource_caps *caps = pool->res_cap;
172 int i;
173 unsigned int num_audio = caps->num_audio;
174 struct resource_straps straps = {0};
175
176 if (create_funcs->read_dce_straps)
177 create_funcs->read_dce_straps(dc->ctx, &straps);
178
179 pool->audio_count = 0;
180 if (create_funcs->create_audio) {
181 /* find the total number of streams available via the
182 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
183 * registers (one for each pin) starting from pin 1
184 * up to the max number of audio pins.
185 * We stop on the first pin where
186 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
187 */
188 update_num_audio(&straps, &num_audio, &pool->audio_support);
189 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
190 struct audio *aud = create_funcs->create_audio(ctx, i);
191
192 if (aud == NULL) {
193 DC_ERR("DC: failed to create audio!\n");
194 return false;
195 }
196
197 if (!aud->funcs->endpoint_valid(aud)) {
198 aud->funcs->destroy(&aud);
199 break;
200 }
201
202 pool->audios[i] = aud;
203 pool->audio_count++;
204 }
205 }
206
207 pool->stream_enc_count = 0;
208 if (create_funcs->create_stream_encoder) {
209 for (i = 0; i < caps->num_stream_encoder; i++) {
210 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
211 if (pool->stream_enc[i] == NULL)
212 DC_ERR("DC: failed to create stream_encoder!\n");
213 pool->stream_enc_count++;
214 }
215 }
216
217 for (i = 0; i < num_virtual_links; i++) {
218 pool->stream_enc[pool->stream_enc_count] =
219 virtual_stream_encoder_create(
220 ctx, ctx->dc_bios);
221 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
222 DC_ERR("DC: failed to create stream_encoder!\n");
223 return false;
224 }
225 pool->stream_enc_count++;
226 }
227
228 dc->hwseq = create_funcs->create_hwseq(ctx);
229
230 return true;
231}
232
233
234void resource_unreference_clock_source(
235 struct resource_context *res_ctx,
8c737fcc 236 struct clock_source **clock_source)
4562236b
HW		 237{
238 int i;
239 for (i = 0; i < res_ctx->pool->clk_src_count; i++) {
8c737fcc 240 if (res_ctx->pool->clock_sources[i] != *clock_source)
4562236b
HW		 241 continue;
242
243 res_ctx->clock_source_ref_count[i]--;
244
245 if (res_ctx->clock_source_ref_count[i] == 0)
8c737fcc 246 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b
HW		 247
248 break;
249 }
250
8c737fcc 251 if (res_ctx->pool->dp_clock_source == *clock_source) {
4562236b
HW		 252 res_ctx->dp_clock_source_ref_count--;
253
254 if (res_ctx->dp_clock_source_ref_count == 0)
8c737fcc 255 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b 256 }
8c737fcc 257 *clock_source = NULL;
4562236b
HW		 258}
259
260void resource_reference_clock_source(
261 struct resource_context *res_ctx,
262 struct clock_source *clock_source)
263{
264 int i;
265 for (i = 0; i < res_ctx->pool->clk_src_count; i++) {
266 if (res_ctx->pool->clock_sources[i] != clock_source)
267 continue;
268
269 res_ctx->clock_source_ref_count[i]++;
270 break;
271 }
272
273 if (res_ctx->pool->dp_clock_source == clock_source)
274 res_ctx->dp_clock_source_ref_count++;
275}
276
277bool resource_are_streams_timing_synchronizable(
278 const struct core_stream *stream1,
279 const struct core_stream *stream2)
280{
281 if (stream1->public.timing.h_total != stream2->public.timing.h_total)
282 return false;
283
284 if (stream1->public.timing.v_total != stream2->public.timing.v_total)
285 return false;
286
287 if (stream1->public.timing.h_addressable
288 != stream2->public.timing.h_addressable)
289 return false;
290
291 if (stream1->public.timing.v_addressable
292 != stream2->public.timing.v_addressable)
293 return false;
294
295 if (stream1->public.timing.pix_clk_khz
296 != stream2->public.timing.pix_clk_khz)
297 return false;
298
299 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 300 && (!dc_is_dp_signal(stream1->signal)
301 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 302 return false;
303
304 return true;
305}
306
307static bool is_sharable_clk_src(
308 const struct pipe_ctx *pipe_with_clk_src,
309 const struct pipe_ctx *pipe)
310{
311 if (pipe_with_clk_src->clock_source == NULL)
312 return false;
313
314 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
315 return false;
316
317 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
318 return false;
319
320 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
321 && dc_is_dvi_signal(pipe->stream->signal))
322 return false;
323
324 if (dc_is_hdmi_signal(pipe->stream->signal)
325 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
326 return false;
327
328 if (!resource_are_streams_timing_synchronizable(
329 pipe_with_clk_src->stream, pipe->stream))
330 return false;
331
332 return true;
333}
334
335struct clock_source *resource_find_used_clk_src_for_sharing(
336 struct resource_context *res_ctx,
337 struct pipe_ctx *pipe_ctx)
338{
339 int i;
340
341 for (i = 0; i < MAX_PIPES; i++) {
342 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
343 return res_ctx->pipe_ctx[i].clock_source;
344 }
345
346 return NULL;
347}
348
349static enum pixel_format convert_pixel_format_to_dalsurface(
350 enum surface_pixel_format surface_pixel_format)
351{
352 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
353
354 switch (surface_pixel_format) {
355 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
356 dal_pixel_format = PIXEL_FORMAT_INDEX8;
357 break;
358 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
359 dal_pixel_format = PIXEL_FORMAT_RGB565;
360 break;
361 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
362 dal_pixel_format = PIXEL_FORMAT_RGB565;
363 break;
364 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
365 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
366 break;
8693049a 367 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 368 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
369 break;
370 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
371 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
372 break;
373 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
374 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
375 break;
376 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
377 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
378 break;
379 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
380 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
381 dal_pixel_format = PIXEL_FORMAT_FP16;
382 break;
383 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b
HW		 384 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
385 dal_pixel_format = PIXEL_FORMAT_420BPP12;
386 break;
ffbcd19a
VP		 387 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
388 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
389 dal_pixel_format = PIXEL_FORMAT_420BPP15;
390 break;
4562236b
HW		 391 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
392 default:
393 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
394 break;
395 }
396 return dal_pixel_format;
397}
398
399static void rect_swap_helper(struct rect *rect)
400{
401 uint32_t temp = 0;
402
403 temp = rect->height;
404 rect->height = rect->width;
405 rect->width = temp;
406
407 temp = rect->x;
408 rect->x = rect->y;
409 rect->y = temp;
410}
411
b2d0a103 412static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 413{
b2d0a103 414 const struct dc_surface *surface = &pipe_ctx->surface->public;
1fbd2cfc 415 const struct dc_stream *stream = &pipe_ctx->stream->public;
b2d0a103 416 struct scaler_data *data = &pipe_ctx->scl_data;
1fbd2cfc 417 struct rect clip = { 0 };
b2d0a103
DL		 418 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
419 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
1fbd2cfc
DL		 420 bool pri_split = pipe_ctx->bottom_pipe &&
421 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
422 bool sec_split = pipe_ctx->top_pipe &&
423 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
4562236b 424
7b779c99
VP		 425 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
426 stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
427 pri_split = false;
428 sec_split = false;
429 }
4562236b
HW		 430 /* The actual clip is an intersection between stream
431 * source and surface clip
432 */
1fbd2cfc
DL		 433 clip.x = stream->src.x > surface->clip_rect.x ?
434 stream->src.x : surface->clip_rect.x;
4562236b 435
1fbd2cfc
DL		 436 clip.width = stream->src.x + stream->src.width <
437 surface->clip_rect.x + surface->clip_rect.width ?
438 stream->src.x + stream->src.width - clip.x :
439 surface->clip_rect.x + surface->clip_rect.width - clip.x ;
4562236b 440
1fbd2cfc
DL		 441 clip.y = stream->src.y > surface->clip_rect.y ?
442 stream->src.y : surface->clip_rect.y;
4562236b 443
1fbd2cfc
DL		 444 clip.height = stream->src.y + stream->src.height <
445 surface->clip_rect.y + surface->clip_rect.height ?
446 stream->src.y + stream->src.height - clip.y :
447 surface->clip_rect.y + surface->clip_rect.height - clip.y ;
4562236b 448
1fbd2cfc 449 /* offset = src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 450 * num_pixels = clip.num_pix * scl_ratio
451 */
1fbd2cfc
DL		 452 data->viewport.x = surface->src_rect.x + (clip.x - surface->dst_rect.x) *
453 surface->src_rect.width / surface->dst_rect.width;
b2d0a103 454 data->viewport.width = clip.width *
1fbd2cfc 455 surface->src_rect.width / surface->dst_rect.width;
4562236b 456
1fbd2cfc
DL		 457 data->viewport.y = surface->src_rect.y + (clip.y - surface->dst_rect.y) *
458 surface->src_rect.height / surface->dst_rect.height;
b2d0a103 459 data->viewport.height = clip.height *
1fbd2cfc 460 surface->src_rect.height / surface->dst_rect.height;
4562236b 461
b2d0a103
DL		 462 /* Round down, compensate in init */
463 data->viewport_c.x = data->viewport.x / vpc_div;
464 data->viewport_c.y = data->viewport.y / vpc_div;
465 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
466 dal_fixed31_32_half : dal_fixed31_32_zero;
467 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
468 dal_fixed31_32_half : dal_fixed31_32_zero;
469 /* Round up, assume original video size always even dimensions */
470 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
471 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
472
473 /* Handle hsplit */
1fbd2cfc
DL		 474 if (pri_split || sec_split) {
475 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
476 bool right_view = (sec_split != surface->horizontal_mirror) !=
477 (surface->rotation == ROTATION_ANGLE_180);
478
479 if (surface->rotation == ROTATION_ANGLE_90
480 || surface->rotation == ROTATION_ANGLE_270)
481 /* Secondary_pipe XOR Rotation_270 */
482 right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 483
484 if (right_view) {
485 data->viewport.width /= 2;
486 data->viewport_c.width /= 2;
487 data->viewport.x += data->viewport.width;
488 data->viewport_c.x += data->viewport_c.width;
489 /* Ceil offset pipe */
490 data->viewport.width += data->viewport.width % 2;
491 data->viewport_c.width += data->viewport_c.width % 2;
492 } else {
493 data->viewport.width /= 2;
494 data->viewport_c.width /= 2;
495 }
b2d0a103 496 }
1fbd2cfc
DL		 497
498 if (surface->rotation == ROTATION_ANGLE_90 ||
499 surface->rotation == ROTATION_ANGLE_270) {
500 rect_swap_helper(&data->viewport_c);
501 rect_swap_helper(&data->viewport);
502 }
4562236b
HW		 503}
504
b2d0a103 505static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 506{
b2d0a103 507 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b
HW		 508 struct core_stream *stream = pipe_ctx->stream;
509 struct rect clip = surface->clip_rect;
c802570e 510 int recout_full_x, recout_full_y;
4562236b
HW		 511
512 pipe_ctx->scl_data.recout.x = stream->public.dst.x;
513 if (stream->public.src.x < clip.x)
514 pipe_ctx->scl_data.recout.x += (clip.x
515 - stream->public.src.x) * stream->public.dst.width
516 / stream->public.src.width;
517
518 pipe_ctx->scl_data.recout.width = clip.width *
519 stream->public.dst.width / stream->public.src.width;
520 if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x >
521 stream->public.dst.x + stream->public.dst.width)
522 pipe_ctx->scl_data.recout.width =
523 stream->public.dst.x + stream->public.dst.width
524 - pipe_ctx->scl_data.recout.x;
525
526 pipe_ctx->scl_data.recout.y = stream->public.dst.y;
527 if (stream->public.src.y < clip.y)
528 pipe_ctx->scl_data.recout.y += (clip.y
529 - stream->public.src.y) * stream->public.dst.height
530 / stream->public.src.height;
531
532 pipe_ctx->scl_data.recout.height = clip.height *
533 stream->public.dst.height / stream->public.src.height;
534 if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y >
535 stream->public.dst.y + stream->public.dst.height)
536 pipe_ctx->scl_data.recout.height =
537 stream->public.dst.y + stream->public.dst.height
538 - pipe_ctx->scl_data.recout.y;
b2d0a103 539
7b779c99
VP		 540 /* Handle h & vsplit */
541 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface ==
542 pipe_ctx->surface) {
543 if (stream->public.timing.timing_3d_format ==
544 TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
545 pipe_ctx->scl_data.recout.height /= 2;
546 pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height;
547 /* Floor primary pipe, ceil 2ndary pipe */
548 pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2;
549 } else {
550 pipe_ctx->scl_data.recout.width /= 2;
551 pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
552 pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
553 }
554 } else if (pipe_ctx->bottom_pipe &&
555 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
556 if (stream->public.timing.timing_3d_format ==
557 TIMING_3D_FORMAT_TOP_AND_BOTTOM)
558 pipe_ctx->scl_data.recout.height /= 2;
559 else
560 pipe_ctx->scl_data.recout.width /= 2;
b2d0a103
DL		 561 }
562
c802570e
DL		 563 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream src offset)
564 * * 1/ stream scaling ratio) - (surf src offset * 1/ full scl
565 * ratio)
566 */
567 recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x)
568 * stream->public.dst.width / stream->public.src.width -
569 surface->src_rect.x * surface->dst_rect.width / surface->src_rect.width
570 * stream->public.dst.width / stream->public.src.width;
571 recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y)
572 * stream->public.dst.height / stream->public.src.height -
573 surface->src_rect.y * surface->dst_rect.height / surface->src_rect.height
574 * stream->public.dst.height / stream->public.src.height;
575
576 recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
577 recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
4562236b
HW		 578}
579
b2d0a103 580static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 581{
b2d0a103 582 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 583 struct core_stream *stream = pipe_ctx->stream;
1fbd2cfc
DL		 584 const int in_w = stream->public.src.width;
585 const int in_h = stream->public.src.height;
586 const int out_w = stream->public.dst.width;
587 const int out_h = stream->public.dst.height;
4562236b
HW		 588
589 pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
590 surface->src_rect.width,
591 surface->dst_rect.width);
592 pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
593 surface->src_rect.height,
594 surface->dst_rect.height);
595
596 if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
597 pipe_ctx->scl_data.ratios.horz.value *= 2;
598 else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
599 pipe_ctx->scl_data.ratios.vert.value *= 2;
600
601 pipe_ctx->scl_data.ratios.vert.value = div64_s64(
602 pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
603 pipe_ctx->scl_data.ratios.horz.value = div64_s64(
604 pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
605
606 pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
607 pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
608
b2d0a103
DL		 609 if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
610 || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
4562236b
HW		 611 pipe_ctx->scl_data.ratios.horz_c.value /= 2;
612 pipe_ctx->scl_data.ratios.vert_c.value /= 2;
613 }
614}
615
b2d0a103
DL		 616static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
617{
618 struct scaler_data *data = &pipe_ctx->scl_data;
619 struct rect src = pipe_ctx->surface->public.src_rect;
620 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
621 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
622
1fbd2cfc
DL		 623 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
624 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
625 rect_swap_helper(&data->viewport_c);
626 rect_swap_helper(&data->viewport);
627 }
628
b2d0a103
DL		 629 /*
630 * Init calculated according to formula:
631 * init = (scaling_ratio + number_of_taps + 1) / 2
632 * init_bot = init + scaling_ratio
633 * init_c = init + truncated_vp_c_offset(from calculate viewport)
634 */
635 data->inits.h = dal_fixed31_32_div_int(
636 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
637
638 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
639 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
640
641 data->inits.v = dal_fixed31_32_div_int(
642 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
643
644 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
645 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
646
647
648 /* Adjust for viewport end clip-off */
649 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
650 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 651 int int_part = dal_fixed31_32_floor(
652 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 653
1fbd2cfc 654 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 655 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
656 }
657 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
658 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 659 int int_part = dal_fixed31_32_floor(
660 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 661
1fbd2cfc 662 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 663 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
664 }
665 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
666 int vp_clip = (src.x + src.width) / vpc_div -
667 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 668 int int_part = dal_fixed31_32_floor(
669 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 670
1fbd2cfc 671 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 672 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
673 }
674 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
675 int vp_clip = (src.y + src.height) / vpc_div -
676 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 677 int int_part = dal_fixed31_32_floor(
678 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 679
1fbd2cfc 680 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 681 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
682 }
683
684 /* Adjust for non-0 viewport offset */
685 if (data->viewport.x) {
686 int int_part;
687
688 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
689 data->ratios.horz, recout_skip->width));
690 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
691 if (int_part < data->taps.h_taps) {
692 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
693 (data->taps.h_taps - int_part) : data->viewport.x;
694 data->viewport.x -= int_adj;
695 data->viewport.width += int_adj;
696 int_part += int_adj;
697 } else if (int_part > data->taps.h_taps) {
698 data->viewport.x += int_part - data->taps.h_taps;
699 data->viewport.width -= int_part - data->taps.h_taps;
700 int_part = data->taps.h_taps;
701 }
702 data->inits.h.value &= 0xffffffff;
703 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
704 }
705
706 if (data->viewport_c.x) {
707 int int_part;
708
709 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
710 data->ratios.horz_c, recout_skip->width));
711 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
712 if (int_part < data->taps.h_taps_c) {
713 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
714 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
715 data->viewport_c.x -= int_adj;
716 data->viewport_c.width += int_adj;
717 int_part += int_adj;
718 } else if (int_part > data->taps.h_taps_c) {
719 data->viewport_c.x += int_part - data->taps.h_taps_c;
720 data->viewport_c.width -= int_part - data->taps.h_taps_c;
721 int_part = data->taps.h_taps_c;
722 }
723 data->inits.h_c.value &= 0xffffffff;
724 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
725 }
726
727 if (data->viewport.y) {
728 int int_part;
729
730 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
731 data->ratios.vert, recout_skip->height));
732 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
733 if (int_part < data->taps.v_taps) {
734 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
735 (data->taps.v_taps - int_part) : data->viewport.y;
736 data->viewport.y -= int_adj;
737 data->viewport.height += int_adj;
738 int_part += int_adj;
739 } else if (int_part > data->taps.v_taps) {
740 data->viewport.y += int_part - data->taps.v_taps;
741 data->viewport.height -= int_part - data->taps.v_taps;
742 int_part = data->taps.v_taps;
743 }
744 data->inits.v.value &= 0xffffffff;
745 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
746 }
747
748 if (data->viewport_c.y) {
749 int int_part;
750
751 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
752 data->ratios.vert_c, recout_skip->height));
753 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
754 if (int_part < data->taps.v_taps_c) {
755 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
756 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
757 data->viewport_c.y -= int_adj;
758 data->viewport_c.height += int_adj;
759 int_part += int_adj;
760 } else if (int_part > data->taps.v_taps_c) {
761 data->viewport_c.y += int_part - data->taps.v_taps_c;
762 data->viewport_c.height -= int_part - data->taps.v_taps_c;
763 int_part = data->taps.v_taps_c;
764 }
765 data->inits.v_c.value &= 0xffffffff;
766 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
767 }
768
769 /* Interlaced inits based on final vert inits */
770 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
771 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc
DL		 772
773 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
774 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
775 rect_swap_helper(&data->viewport_c);
776 rect_swap_helper(&data->viewport);
777 }
b2d0a103
DL		 778}
779
780bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 781{
b2d0a103 782 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 783 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
b2d0a103
DL		 784 struct view recout_skip = { 0 };
785 bool res = false;
786
4562236b
HW		 787 /* Important: scaling ratio calculation requires pixel format,
788 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 789 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 790 */
b2d0a103
DL		 791 pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
792 pipe_ctx->surface->public.format);
793
794 calculate_scaling_ratios(pipe_ctx);
4562236b 795
b2d0a103 796 calculate_viewport(pipe_ctx);
4562236b
HW		 797
798 if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
799 return false;
800
b2d0a103 801 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 802
803 /**
804 * Setting line buffer pixel depth to 24bpp yields banding
805 * on certain displays, such as the Sharp 4k
806 */
807 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
808
809 pipe_ctx->scl_data.h_active = timing->h_addressable;
810 pipe_ctx->scl_data.v_active = timing->v_addressable;
811
812 /* Taps calculations */
813 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
814 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
815
816 if (!res) {
817 /* Try 24 bpp linebuffer */
818 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
819
820 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
821 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
822 }
823
b2d0a103 824 if (res)
1fbd2cfc 825 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 826 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
827
4562236b
HW		 828 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
829 "%s: Viewport:\nheight:%d width:%d x:%d "
830 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
831 "y:%d\n",
832 __func__,
833 pipe_ctx->scl_data.viewport.height,
834 pipe_ctx->scl_data.viewport.width,
835 pipe_ctx->scl_data.viewport.x,
836 pipe_ctx->scl_data.viewport.y,
837 surface->dst_rect.height,
838 surface->dst_rect.width,
839 surface->dst_rect.x,
840 surface->dst_rect.y);
841
842 return res;
843}
844
845
846enum dc_status resource_build_scaling_params_for_context(
847 const struct core_dc *dc,
848 struct validate_context *context)
849{
850 int i;
851
852 for (i = 0; i < MAX_PIPES; i++) {
853 if (context->res_ctx.pipe_ctx[i].surface != NULL &&
854 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 855 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 856 return DC_FAIL_SCALING;
4562236b
HW		 857 }
858
859 return DC_OK;
860}
861
ab2541b6 862static void detach_surfaces_for_stream(
4562236b 863 struct validate_context *context,
ab2541b6 864 const struct dc_stream *dc_stream)
4562236b
HW		 865{
866 int i;
ab2541b6 867 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 868
869 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
870 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
871 if (cur_pipe->stream == stream) {
872 cur_pipe->surface = NULL;
873 cur_pipe->top_pipe = NULL;
874 cur_pipe->bottom_pipe = NULL;
875 }
876 }
877}
878
879struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx)
880{
881 int i;
882 struct pipe_ctx *secondary_pipe = NULL;
883
884 /*
885 * search backwards for the second pipe to keep pipe
886 * assignment more consistent
887 */
888
889 for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) {
890 if (res_ctx->pipe_ctx[i].stream == NULL) {
891 secondary_pipe = &res_ctx->pipe_ctx[i];
892 secondary_pipe->pipe_idx = i;
893 break;
894 }
895 }
896
897
898 return secondary_pipe;
899}
900
901struct pipe_ctx *resource_get_head_pipe_for_stream(
902 struct resource_context *res_ctx,
903 const struct core_stream *stream)
904{
905 int i;
906 for (i = 0; i < res_ctx->pool->pipe_count; i++) {
907 if (res_ctx->pipe_ctx[i].stream == stream &&
e73c1efc 908 res_ctx->pipe_ctx[i].stream_enc) {
4562236b
HW		 909 return &res_ctx->pipe_ctx[i];
910 break;
911 }
912 }
913 return NULL;
914}
915
916/*
ab2541b6
AC		 917 * A free_pipe for a stream is defined here as a pipe
918 * that has no surface attached yet
4562236b 919 */
ab2541b6 920static struct pipe_ctx *acquire_free_pipe_for_stream(
745cc746 921 struct validate_context *context,
ab2541b6 922 const struct dc_stream *dc_stream)
4562236b
HW		 923{
924 int i;
745cc746 925 struct resource_context *res_ctx = &context->res_ctx;
ab2541b6 926 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 927
928 struct pipe_ctx *head_pipe = NULL;
929
930 /* Find head pipe, which has the back end set up*/
931
932 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
933
934 if (!head_pipe)
935 ASSERT(0);
936
937 if (!head_pipe->surface)
938 return head_pipe;
939
940 /* Re-use pipe already acquired for this stream if available*/
941 for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) {
942 if (res_ctx->pipe_ctx[i].stream == stream &&
943 !res_ctx->pipe_ctx[i].surface) {
944 return &res_ctx->pipe_ctx[i];
945 }
946 }
947
948 /*
949 * At this point we have no re-useable pipe for this stream and we need
950 * to acquire an idle one to satisfy the request
951 */
952
953 if(!res_ctx->pool->funcs->acquire_idle_pipe_for_layer)
954 return NULL;
955
745cc746 956 return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(context, stream);
4562236b
HW		 957
958}
959
ab2541b6 960static void release_free_pipes_for_stream(
4562236b 961 struct resource_context *res_ctx,
ab2541b6 962 const struct dc_stream *dc_stream)
4562236b
HW		 963{
964 int i;
ab2541b6 965 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 966
967 for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) {
968 if (res_ctx->pipe_ctx[i].stream == stream &&
969 !res_ctx->pipe_ctx[i].surface) {
970 res_ctx->pipe_ctx[i].stream = NULL;
971 }
972 }
973}
974
975bool resource_attach_surfaces_to_context(
976 const struct dc_surface * const *surfaces,
977 int surface_count,
ab2541b6 978 const struct dc_stream *dc_stream,
4562236b
HW		 979 struct validate_context *context)
980{
981 int i;
982 struct pipe_ctx *tail_pipe;
ab2541b6 983 struct dc_stream_status *stream_status = NULL;
4562236b
HW		 984
985
986 if (surface_count > MAX_SURFACE_NUM) {
987 dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
988 surface_count, MAX_SURFACE_NUM);
989 return false;
990 }
991
ab2541b6
AC		 992 for (i = 0; i < context->stream_count; i++)
993 if (&context->streams[i]->public == dc_stream) {
994 stream_status = &context->stream_status[i];
4562236b
HW		 995 break;
996 }
ab2541b6
AC		 997 if (stream_status == NULL) {
998 dm_error("Existing stream not found; failed to attach surfaces\n");
4562236b
HW		 999 return false;
1000 }
1001
1002 /* retain new surfaces */
1003 for (i = 0; i < surface_count; i++)
1004 dc_surface_retain(surfaces[i]);
1005
ab2541b6 1006 detach_surfaces_for_stream(context, dc_stream);
4562236b
HW		 1007
1008 /* release existing surfaces*/
ab2541b6
AC		 1009 for (i = 0; i < stream_status->surface_count; i++)
1010 dc_surface_release(stream_status->surfaces[i]);
4562236b 1011
ab2541b6
AC		 1012 for (i = surface_count; i < stream_status->surface_count; i++)
1013 stream_status->surfaces[i] = NULL;
4562236b 1014
ab2541b6 1015 stream_status->surface_count = 0;
4562236b
HW		 1016
1017 if (surface_count == 0)
1018 return true;
1019
1020 tail_pipe = NULL;
1021 for (i = 0; i < surface_count; i++) {
1022 struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
745cc746 1023 struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(context, dc_stream);
4562236b
HW		 1024
1025 if (!free_pipe) {
ab2541b6 1026 stream_status->surfaces[i] = NULL;
4562236b
HW		 1027 return false;
1028 }
1029
1030 free_pipe->surface = surface;
1031
1032 if (tail_pipe) {
1033 free_pipe->top_pipe = tail_pipe;
1034 tail_pipe->bottom_pipe = free_pipe;
1035 }
1036
1037 tail_pipe = free_pipe;
1038 }
1039
ab2541b6 1040 release_free_pipes_for_stream(&context->res_ctx, dc_stream);
4562236b
HW		 1041
1042 /* assign new surfaces*/
1043 for (i = 0; i < surface_count; i++)
ab2541b6 1044 stream_status->surfaces[i] = surfaces[i];
4562236b 1045
ab2541b6 1046 stream_status->surface_count = surface_count;
4562236b
HW		 1047
1048 return true;
1049}
1050
1051
1052static bool is_timing_changed(const struct core_stream *cur_stream,
1053 const struct core_stream *new_stream)
1054{
1055 if (cur_stream == NULL)
1056 return true;
1057
1058 /* If sink pointer changed, it means this is a hotplug, we should do
1059 * full hw setting.
1060 */
1061 if (cur_stream->sink != new_stream->sink)
1062 return true;
1063
1064 /* If output color space is changed, need to reprogram info frames */
1065 if (cur_stream->public.output_color_space !=
1066 new_stream->public.output_color_space)
1067 return true;
1068
1069 return memcmp(
1070 &cur_stream->public.timing,
1071 &new_stream->public.timing,
1072 sizeof(struct dc_crtc_timing)) != 0;
1073}
1074
1075static bool are_stream_backends_same(
1076 const struct core_stream *stream_a, const struct core_stream *stream_b)
1077{
1078 if (stream_a == stream_b)
1079 return true;
1080
1081 if (stream_a == NULL || stream_b == NULL)
1082 return false;
1083
1084 if (is_timing_changed(stream_a, stream_b))
1085 return false;
1086
1087 return true;
1088}
1089
ab2541b6
AC		 1090bool is_stream_unchanged(
1091 const struct core_stream *old_stream, const struct core_stream *stream)
4562236b 1092{
4562236b 1093
ab2541b6
AC		 1094 if (!are_stream_backends_same(old_stream, stream))
1095 return false;
4562236b
HW		 1096
1097 return true;
1098}
1099
1100bool resource_validate_attach_surfaces(
1101 const struct dc_validation_set set[],
1102 int set_count,
1103 const struct validate_context *old_context,
1104 struct validate_context *context)
1105{
1106 int i, j;
1107
1108 for (i = 0; i < set_count; i++) {
ab2541b6
AC		 1109 for (j = 0; j < old_context->stream_count; j++)
1110 if (is_stream_unchanged(
1111 old_context->streams[j],
1112 context->streams[i])) {
4562236b 1113 if (!resource_attach_surfaces_to_context(
ab2541b6
AC		 1114 old_context->stream_status[j].surfaces,
1115 old_context->stream_status[j].surface_count,
1116 &context->streams[i]->public,
4562236b
HW		 1117 context))
1118 return false;
ab2541b6 1119 context->stream_status[i] = old_context->stream_status[j];
4562236b
HW		 1120 }
1121 if (set[i].surface_count != 0)
1122 if (!resource_attach_surfaces_to_context(
1123 set[i].surfaces,
1124 set[i].surface_count,
ab2541b6 1125 &context->streams[i]->public,
4562236b
HW		 1126 context))
1127 return false;
1128
1129 }
1130
1131 return true;
1132}
1133
1134/* Maximum TMDS single link pixel clock 165MHz */
1135#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1136
1137static void set_stream_engine_in_use(
1138 struct resource_context *res_ctx,
1139 struct stream_encoder *stream_enc)
1140{
1141 int i;
1142
1143 for (i = 0; i < res_ctx->pool->stream_enc_count; i++) {
1144 if (res_ctx->pool->stream_enc[i] == stream_enc)
1145 res_ctx->is_stream_enc_acquired[i] = true;
1146 }
1147}
1148
1149/* TODO: release audio object */
1150static void set_audio_in_use(
1151 struct resource_context *res_ctx,
1152 struct audio *audio)
1153{
1154 int i;
1155 for (i = 0; i < res_ctx->pool->audio_count; i++) {
1156 if (res_ctx->pool->audios[i] == audio) {
1157 res_ctx->is_audio_acquired[i] = true;
1158 }
1159 }
1160}
1161
1162static int acquire_first_free_pipe(
1163 struct resource_context *res_ctx,
1164 struct core_stream *stream)
1165{
1166 int i;
1167
1168 for (i = 0; i < res_ctx->pool->pipe_count; i++) {
1169 if (!res_ctx->pipe_ctx[i].stream) {
1170 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1171
1172 pipe_ctx->tg = res_ctx->pool->timing_generators[i];
1173 pipe_ctx->mi = res_ctx->pool->mis[i];
1174 pipe_ctx->ipp = res_ctx->pool->ipps[i];
1175 pipe_ctx->xfm = res_ctx->pool->transforms[i];
1176 pipe_ctx->opp = res_ctx->pool->opps[i];
1177 pipe_ctx->dis_clk = res_ctx->pool->display_clock;
1178 pipe_ctx->pipe_idx = i;
1179
1180 pipe_ctx->stream = stream;
1181 return i;
1182 }
1183 }
1184 return -1;
1185}
1186
1187static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1188 struct resource_context *res_ctx,
1189 struct core_stream *stream)
1190{
1191 int i;
1192 int j = -1;
1193 struct core_link *link = stream->sink->link;
1194
1195 for (i = 0; i < res_ctx->pool->stream_enc_count; i++) {
1196 if (!res_ctx->is_stream_enc_acquired[i] &&
1197 res_ctx->pool->stream_enc[i]) {
1198 /* Store first available for MST second display
1199 * in daisy chain use case */
1200 j = i;
1201 if (res_ctx->pool->stream_enc[i]->id ==
1202 link->link_enc->preferred_engine)
1203 return res_ctx->pool->stream_enc[i];
1204 }
1205 }
1206
1207 /*
1208 * below can happen in cases when stream encoder is acquired:
1209 * 1) for second MST display in chain, so preferred engine already
1210 * acquired;
1211 * 2) for another link, which preferred engine already acquired by any
1212 * MST configuration.
1213 *
1214 * If signal is of DP type and preferred engine not found, return last available
1215 *
1216 * TODO - This is just a patch up and a generic solution is
1217 * required for non DP connectors.
1218 */
1219
1220 if (j >= 0 && dc_is_dp_signal(stream->signal))
1221 return res_ctx->pool->stream_enc[j];
1222
1223 return NULL;
1224}
1225
1226static struct audio *find_first_free_audio(struct resource_context *res_ctx)
1227{
1228 int i;
1229 for (i = 0; i < res_ctx->pool->audio_count; i++) {
1230 if (res_ctx->is_audio_acquired[i] == false) {
1231 return res_ctx->pool->audios[i];
1232 }
1233 }
1234
1235 return 0;
1236}
1237
1238static void update_stream_signal(struct core_stream *stream)
1239{
8b32076c
ST		 1240 if (stream->public.output_signal == SIGNAL_TYPE_NONE) {
1241 const struct dc_sink *dc_sink = stream->public.sink;
1242
1243 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
1244 stream->signal =
1245 stream->sink->link->
1246 public.connector_signal;
4562236b 1247 else
8b32076c
ST		 1248 stream->signal = dc_sink->sink_signal;
1249 } else {
1250 stream->signal = stream->public.output_signal;
1251 }
1252
1253 if (stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK &&
1254 stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
1255 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
4562236b
HW		 1256}
1257
1258bool resource_is_stream_unchanged(
ab2541b6 1259 const struct validate_context *old_context, const struct core_stream *stream)
4562236b 1260{
ab2541b6 1261 int i;
4562236b 1262
ab2541b6
AC		 1263 for (i = 0; i < old_context->stream_count; i++) {
1264 const struct core_stream *old_stream = old_context->streams[i];
4562236b 1265
ab2541b6 1266 if (are_stream_backends_same(old_stream, stream))
4562236b 1267 return true;
4562236b
HW		 1268 }
1269
1270 return false;
1271}
1272
1273static void copy_pipe_ctx(
1274 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1275{
1276 struct core_surface *surface = to_pipe_ctx->surface;
1277 struct core_stream *stream = to_pipe_ctx->stream;
1278
1279 *to_pipe_ctx = *from_pipe_ctx;
1280 to_pipe_ctx->stream = stream;
1281 if (surface != NULL)
1282 to_pipe_ctx->surface = surface;
1283}
1284
1285static struct core_stream *find_pll_sharable_stream(
1286 const struct core_stream *stream_needs_pll,
1287 struct validate_context *context)
1288{
ab2541b6 1289 int i;
4562236b 1290
ab2541b6
AC		 1291 for (i = 0; i < context->stream_count; i++) {
1292 struct core_stream *stream_has_pll = context->streams[i];
4562236b 1293
ab2541b6
AC		 1294 /* We are looking for non dp, non virtual stream */
1295 if (resource_are_streams_timing_synchronizable(
1296 stream_needs_pll, stream_has_pll)
1297 && !dc_is_dp_signal(stream_has_pll->signal)
1298 && stream_has_pll->sink->link->public.connector_signal
1299 != SIGNAL_TYPE_VIRTUAL)
1300 return stream_has_pll;
4562236b 1301
4562236b
HW		 1302 }
1303
1304 return NULL;
1305}
1306
1307static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1308{
1309 uint32_t pix_clk = timing->pix_clk_khz;
1310 uint32_t normalized_pix_clk = pix_clk;
1311
1312 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1313 pix_clk /= 2;
cc4d99b8
CL		 1314 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1315 switch (timing->display_color_depth) {
1316 case COLOR_DEPTH_888:
1317 normalized_pix_clk = pix_clk;
1318 break;
1319 case COLOR_DEPTH_101010:
1320 normalized_pix_clk = (pix_clk * 30) / 24;
1321 break;
1322 case COLOR_DEPTH_121212:
1323 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1324 break;
cc4d99b8
CL		 1325 case COLOR_DEPTH_161616:
1326 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1327 break;
cc4d99b8
CL		 1328 default:
1329 ASSERT(0);
4562236b 1330 break;
cc4d99b8 1331 }
4562236b 1332 }
4562236b
HW		 1333 return normalized_pix_clk;
1334}
1335
1336static void calculate_phy_pix_clks(
1337 const struct core_dc *dc,
1338 struct validate_context *context)
1339{
ab2541b6 1340 int i;
4562236b 1341
ab2541b6
AC		 1342 for (i = 0; i < context->stream_count; i++) {
1343 struct core_stream *stream = context->streams[i];
4562236b 1344
ab2541b6 1345 update_stream_signal(stream);
4562236b 1346
ab2541b6
AC		 1347 /* update actual pixel clock on all streams */
1348 if (dc_is_hdmi_signal(stream->signal))
1349 stream->phy_pix_clk = get_norm_pix_clk(
1350 &stream->public.timing);
1351 else
1352 stream->phy_pix_clk =
1353 stream->public.timing.pix_clk_khz;
4562236b
HW		 1354 }
1355}
1356
1357enum dc_status resource_map_pool_resources(
1358 const struct core_dc *dc,
1359 struct validate_context *context)
1360{
ab2541b6 1361 int i, j;
4562236b
HW		 1362
1363 calculate_phy_pix_clks(dc, context);
1364
ab2541b6
AC		 1365 for (i = 0; i < context->stream_count; i++) {
1366 struct core_stream *stream = context->streams[i];
4562236b 1367
4b679bc3
CL		 1368 if (!resource_is_stream_unchanged(dc->current_context, stream)) {
1369 if (stream != NULL && dc->current_context->streams[i] != NULL) {
1370 stream->bit_depth_params =
1371 dc->current_context->streams[i]->bit_depth_params;
1372 stream->clamping = dc->current_context->streams[i]->clamping;
ab2541b6 1373 continue;
4b679bc3
CL		 1374 }
1375 }
7e2fe319 1376
ab2541b6
AC		 1377 /* mark resources used for stream that is already active */
1378 for (j = 0; j < MAX_PIPES; j++) {
1379 struct pipe_ctx *pipe_ctx =
1380 &context->res_ctx.pipe_ctx[j];
1381 const struct pipe_ctx *old_pipe_ctx =
1382 &dc->current_context->res_ctx.pipe_ctx[j];
4562236b 1383
ab2541b6
AC		 1384 if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
1385 continue;
8c737fcc 1386
268cadbd
YS		 1387 if (old_pipe_ctx->top_pipe)
1388 continue;
1389
ab2541b6
AC		 1390 pipe_ctx->stream = stream;
1391 copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
4562236b 1392
ab2541b6
AC		 1393 /* Split pipe resource, do not acquire back end */
1394 if (!pipe_ctx->stream_enc)
1395 continue;
4562236b 1396
ab2541b6
AC		 1397 set_stream_engine_in_use(
1398 &context->res_ctx,
1399 pipe_ctx->stream_enc);
1400
1401 /* Switch to dp clock source only if there is
1402 * no non dp stream that shares the same timing
1403 * with the dp stream.
1404 */
1405 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1406 !find_pll_sharable_stream(stream, context))
1407 pipe_ctx->clock_source =
1408 context->res_ctx.pool->dp_clock_source;
1409
1410 resource_reference_clock_source(
1411 &context->res_ctx,
1412 pipe_ctx->clock_source);
1413
1414 set_audio_in_use(&context->res_ctx,
1415 pipe_ctx->audio);
4562236b
HW		 1416 }
1417 }
1418
ab2541b6
AC		 1419 for (i = 0; i < context->stream_count; i++) {
1420 struct core_stream *stream = context->streams[i];
1421 struct pipe_ctx *pipe_ctx = NULL;
1422 int pipe_idx = -1;
4562236b 1423
ab2541b6
AC		 1424 if (resource_is_stream_unchanged(dc->current_context, stream))
1425 continue;
1426 /* acquire new resources */
1427 pipe_idx = acquire_first_free_pipe(&context->res_ctx, stream);
1428 if (pipe_idx < 0)
1429 return DC_NO_CONTROLLER_RESOURCE;
1430
1431
1432 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1433
1434 pipe_ctx->stream_enc =
1435 find_first_free_match_stream_enc_for_link(
1436 &context->res_ctx, stream);
1437
1438 if (!pipe_ctx->stream_enc)
1439 return DC_NO_STREAM_ENG_RESOURCE;
1440
1441 set_stream_engine_in_use(
1442 &context->res_ctx,
1443 pipe_ctx->stream_enc);
1444
1445 /* TODO: Add check if ASIC support and EDID audio */
4a9a5d62 1446 if (!stream->sink->public.converter_disable_audio &&
ab2541b6
AC		 1447 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1448 stream->public.audio_info.mode_count) {
1449 pipe_ctx->audio = find_first_free_audio(
1450 &context->res_ctx);
1451
1452 /*
1453 * Audio assigned in order first come first get.
1454 * There are asics which has number of audio
1455 * resources less then number of pipes
1456 */
1457 if (pipe_ctx->audio)
1458 set_audio_in_use(
4562236b 1459 &context->res_ctx,
ab2541b6 1460 pipe_ctx->audio);
4562236b 1461 }
ab2541b6
AC		 1462
1463 context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
4562236b
HW		 1464 }
1465
1466 return DC_OK;
1467}
1468
ab2541b6
AC		 1469/* first stream in the context is used to populate the rest */
1470void validate_guaranteed_copy_streams(
4562236b 1471 struct validate_context *context,
ab2541b6 1472 int max_streams)
4562236b
HW		 1473{
1474 int i;
1475
ab2541b6
AC		 1476 for (i = 1; i < max_streams; i++) {
1477 context->streams[i] = context->streams[0];
4562236b
HW		 1478
1479 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1480 &context->res_ctx.pipe_ctx[i]);
1481 context->res_ctx.pipe_ctx[i].stream =
1482 context->res_ctx.pipe_ctx[0].stream;
1483
ab2541b6
AC		 1484 dc_stream_retain(&context->streams[i]->public);
1485 context->stream_count++;
4562236b
HW		 1486 }
1487}
1488
6e4d6bee
TC		 1489static void patch_gamut_packet_checksum(
1490 struct encoder_info_packet *gamut_packet)
4562236b 1491{
4562236b 1492 /* For gamut we recalc checksum */
6e4d6bee 1493 if (gamut_packet->valid) {
4562236b
HW		 1494 uint8_t chk_sum = 0;
1495 uint8_t *ptr;
1496 uint8_t i;
1497
4562236b 1498 /*start of the Gamut data. */
6e4d6bee 1499 ptr = &gamut_packet->sb[3];
4562236b 1500
6e4d6bee 1501 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1502 chk_sum += ptr[i];
1503
6e4d6bee 1504 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1505 }
4562236b
HW		 1506}
1507
1508static void set_avi_info_frame(
6e4d6bee 1509 struct encoder_info_packet *info_packet,
4562236b
HW		 1510 struct pipe_ctx *pipe_ctx)
1511{
1512 struct core_stream *stream = pipe_ctx->stream;
1513 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1514 struct info_frame info_frame = { {0} };
1515 uint32_t pixel_encoding = 0;
1516 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1517 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1518 bool itc = false;
1519 uint8_t cn0_cn1 = 0;
1520 uint8_t *check_sum = NULL;
1521 uint8_t byte_index = 0;
e8d726b7 1522 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
4562236b 1523
4562236b
HW		 1524 color_space = pipe_ctx->stream->public.output_color_space;
1525
1526 /* Initialize header */
e8d726b7 1527 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1528 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1529 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1530 hdmi_info->bits.header.version = 2;
1531 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1532
1533 /*
1534 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1535 * according to HDMI 2.0 spec (Section 10.1)
1536 */
1537
1538 switch (stream->public.timing.pixel_encoding) {
1539 case PIXEL_ENCODING_YCBCR422:
1540 pixel_encoding = 1;
1541 break;
1542
1543 case PIXEL_ENCODING_YCBCR444:
1544 pixel_encoding = 2;
1545 break;
1546 case PIXEL_ENCODING_YCBCR420:
1547 pixel_encoding = 3;
1548 break;
1549
1550 case PIXEL_ENCODING_RGB:
1551 default:
1552 pixel_encoding = 0;
1553 }
1554
1555 /* Y0_Y1_Y2 : The pixel encoding */
1556 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1557 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1558
1559 /* A0 = 1 Active Format Information valid */
e8d726b7 1560 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1561
1562 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1563 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1564
e8d726b7 1565 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1566
1567 /* S0, S1 : Underscan / Overscan */
1568 /* TODO: un-hardcode scan type */
1569 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1570 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1571
1572 /* C0, C1 : Colorimetry */
8fde5884
CL		 1573 if (color_space == COLOR_SPACE_YCBCR709 ||
1574 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1575 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1576 else if (color_space == COLOR_SPACE_YCBCR601 ||
1577 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1578 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884
CL		 1579 else {
1580 if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
1581 BREAK_TO_DEBUGGER();
e8d726b7 1582 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1583 }
534db198 1584 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1585 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1586 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1587 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1588 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1589 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1590 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1591 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1592 }
1593
4562236b
HW		 1594 /* TODO: un-hardcode aspect ratio */
1595 aspect = stream->public.timing.aspect_ratio;
1596
1597 switch (aspect) {
1598 case ASPECT_RATIO_4_3:
1599 case ASPECT_RATIO_16_9:
e8d726b7 1600 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1601 break;
1602
1603 case ASPECT_RATIO_NO_DATA:
1604 case ASPECT_RATIO_64_27:
1605 case ASPECT_RATIO_256_135:
1606 default:
e8d726b7 1607 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1608 }
1609
1610 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1611 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1612
1613 /* TODO: un-hardcode cn0_cn1 and itc */
1614 cn0_cn1 = 0;
1615 itc = false;
1616
1617 if (itc) {
e8d726b7
RA		 1618 hdmi_info->bits.ITC = 1;
1619 hdmi_info->bits.CN0_CN1 = cn0_cn1;
4562236b
HW		 1620 }
1621
1622 /* TODO : We should handle YCC quantization */
1623 /* but we do not have matrix calculation */
1624 if (color_space == COLOR_SPACE_SRGB) {
e8d726b7
RA		 1625 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1626 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
4562236b 1627 } else if (color_space == COLOR_SPACE_SRGB_LIMITED) {
e8d726b7
RA		 1628 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1629 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 1630 } else {
e8d726b7
RA		 1631 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
1632 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b
HW		 1633 }
1634
e8d726b7 1635 hdmi_info->bits.VIC0_VIC7 =
4562236b
HW		 1636 stream->public.timing.vic;
1637
1638 /* pixel repetition
1639 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
1640 * repetition start from 1 */
e8d726b7 1641 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 1642
1643 /* Bar Info
1644 * barTop: Line Number of End of Top Bar.
1645 * barBottom: Line Number of Start of Bottom Bar.
1646 * barLeft: Pixel Number of End of Left Bar.
1647 * barRight: Pixel Number of Start of Right Bar. */
e8d726b7
RA		 1648 hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
1649 hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top
4562236b 1650 - stream->public.timing.v_border_bottom + 1);
e8d726b7
RA		 1651 hdmi_info->bits.bar_left = stream->public.timing.h_border_left;
1652 hdmi_info->bits.bar_right = (stream->public.timing.h_total
4562236b
HW		 1653 - stream->public.timing.h_border_right + 1);
1654
1655 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 1656 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
1657
3e183c5f 1658 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 1659
3e183c5f 1660 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 1661 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 1662
1663 /* one byte complement */
1664 *check_sum = (uint8_t) (0x100 - *check_sum);
1665
1666 /* Store in hw_path_mode */
e8d726b7
RA		 1667 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
1668 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
1669 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 1670
e66e4d64
HW		 1671 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
1672 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 1673 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 1674 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 1675
1676 info_packet->valid = true;
1677}
1678
6e4d6bee
TC		 1679static void set_vendor_info_packet(
1680 struct encoder_info_packet *info_packet,
1681 struct core_stream *stream)
4562236b
HW		 1682{
1683 uint32_t length = 0;
1684 bool hdmi_vic_mode = false;
1685 uint8_t checksum = 0;
1686 uint32_t i = 0;
1687 enum dc_timing_3d_format format;
1688
4562236b
HW		 1689 format = stream->public.timing.timing_3d_format;
1690
1691 /* Can be different depending on packet content */
1692 length = 5;
1693
1694 if (stream->public.timing.hdmi_vic != 0
1695 && stream->public.timing.h_total >= 3840
1696 && stream->public.timing.v_total >= 2160)
1697 hdmi_vic_mode = true;
1698
1699 /* According to HDMI 1.4a CTS, VSIF should be sent
1700 * for both 3D stereo and HDMI VIC modes.
1701 * For all other modes, there is no VSIF sent. */
1702
1703 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
1704 return;
1705
1706 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
1707 info_packet->sb[1] = 0x03;
1708 info_packet->sb[2] = 0x0C;
1709 info_packet->sb[3] = 0x00;
1710
1711 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
1712 * The value for HDMI_Video_Format are:
1713 * 0x0 (0b000) - No additional HDMI video format is presented in this
1714 * packet
1715 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
1716 * parameter follows
1717 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
1718 * potentially 3D_Ext_Data follows
1719 * 0x3..0x7 (0b011..0b111) - reserved for future use */
1720 if (format != TIMING_3D_FORMAT_NONE)
1721 info_packet->sb[4] = (2 << 5);
1722 else if (hdmi_vic_mode)
1723 info_packet->sb[4] = (1 << 5);
1724
1725 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
1726 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
1727 * The value for 3D_Structure are:
1728 * 0x0 - Frame Packing
1729 * 0x1 - Field Alternative
1730 * 0x2 - Line Alternative
1731 * 0x3 - Side-by-Side (full)
1732 * 0x4 - L + depth
1733 * 0x5 - L + depth + graphics + graphics-depth
1734 * 0x6 - Top-and-Bottom
1735 * 0x7 - Reserved for future use
1736 * 0x8 - Side-by-Side (Half)
1737 * 0x9..0xE - Reserved for future use
1738 * 0xF - Not used */
1739 switch (format) {
1740 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
1741 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
1742 info_packet->sb[5] = (0x0 << 4);
1743 break;
1744
1745 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
1746 case TIMING_3D_FORMAT_SBS_SW_PACKED:
1747 info_packet->sb[5] = (0x8 << 4);
1748 length = 6;
1749 break;
1750
1751 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
1752 case TIMING_3D_FORMAT_TB_SW_PACKED:
1753 info_packet->sb[5] = (0x6 << 4);
1754 break;
1755
1756 default:
1757 break;
1758 }
1759
1760 /*PB5: If PB4 is set to 0x1 (extended resolution format)
1761 * fill PB5 with the correct HDMI VIC code */
1762 if (hdmi_vic_mode)
1763 info_packet->sb[5] = stream->public.timing.hdmi_vic;
1764
1765 /* Header */
3e183c5f 1766 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 1767 info_packet->hb1 = 0x01; /* Version */
1768
1769 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
1770 info_packet->hb2 = (uint8_t) (length);
1771
1772 /* Calculate checksum */
1773 checksum = 0;
1774 checksum += info_packet->hb0;
1775 checksum += info_packet->hb1;
1776 checksum += info_packet->hb2;
1777
1778 for (i = 1; i <= length; i++)
1779 checksum += info_packet->sb[i];
1780
1781 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
1782
1783 info_packet->valid = true;
1784}
1785
6e4d6bee
TC		 1786static void set_spd_info_packet(
1787 struct encoder_info_packet *info_packet,
1788 struct core_stream *stream)
4562236b
HW		 1789{
1790 /* SPD info packet for FreeSync */
1791
1792 unsigned char checksum = 0;
1793 unsigned int idx, payload_size = 0;
1794
1795 /* Check if Freesync is supported. Return if false. If true,
1796 * set the corresponding bit in the info packet
1797 */
1798 if (stream->public.freesync_ctx.supported == false)
1799 return;
1800
1801 if (dc_is_hdmi_signal(stream->signal)) {
1802
1803 /* HEADER */
1804
1805 /* HB0 = Packet Type = 0x83 (Source Product
1806 * Descriptor InfoFrame)
1807 */
3e183c5f 1808 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1809
1810 /* HB1 = Version = 0x01 */
1811 info_packet->hb1 = 0x01;
1812
1813 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1814 info_packet->hb2 = 0x08;
1815
1816 payload_size = 0x08;
1817
1818 } else if (dc_is_dp_signal(stream->signal)) {
1819
1820 /* HEADER */
1821
1822 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1823 * when used to associate audio related info packets
1824 */
1825 info_packet->hb0 = 0x00;
1826
1827 /* HB1 = Packet Type = 0x83 (Source Product
1828 * Descriptor InfoFrame)
1829 */
3e183c5f 1830 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1831
1832 /* HB2 = [Bits 7:0 = Least significant eight bits -
1833 * For INFOFRAME, the value must be 1Bh]
1834 */
1835 info_packet->hb2 = 0x1B;
1836
1837 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
1838 * [Bits 1:0 = Most significant two bits = 0x00]
1839 */
1840 info_packet->hb3 = 0x04;
1841
1842 payload_size = 0x1B;
1843 }
1844
1845 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
1846 info_packet->sb[1] = 0x1A;
1847
1848 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
1849 info_packet->sb[2] = 0x00;
1850
1851 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
1852 info_packet->sb[3] = 0x00;
1853
1854 /* PB4 = Reserved */
1855 info_packet->sb[4] = 0x00;
1856
1857 /* PB5 = Reserved */
1858 info_packet->sb[5] = 0x00;
1859
1860 /* PB6 = [Bits 7:3 = Reserved] */
1861 info_packet->sb[6] = 0x00;
1862
1863 if (stream->public.freesync_ctx.supported == true)
1864 /* PB6 = [Bit 0 = FreeSync Supported] */
1865 info_packet->sb[6] |= 0x01;
1866
1867 if (stream->public.freesync_ctx.enabled == true)
1868 /* PB6 = [Bit 1 = FreeSync Enabled] */
1869 info_packet->sb[6] |= 0x02;
1870
1871 if (stream->public.freesync_ctx.active == true)
1872 /* PB6 = [Bit 2 = FreeSync Active] */
1873 info_packet->sb[6] |= 0x04;
1874
1875 /* PB7 = FreeSync Minimum refresh rate (Hz) */
1876 info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx.
1877 min_refresh_in_micro_hz / 1000000);
1878
1879 /* PB8 = FreeSync Maximum refresh rate (Hz)
1880 *
1881 * Note: We do not use the maximum capable refresh rate
1882 * of the panel, because we should never go above the field
1883 * rate of the mode timing set.
1884 */
1885 info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx.
1886 nominal_refresh_in_micro_hz / 1000000);
1887
1888 /* PB9 - PB27 = Reserved */
1889 for (idx = 9; idx <= 27; idx++)
1890 info_packet->sb[idx] = 0x00;
1891
1892 /* Calculate checksum */
1893 checksum += info_packet->hb0;
1894 checksum += info_packet->hb1;
1895 checksum += info_packet->hb2;
1896 checksum += info_packet->hb3;
1897
1898 for (idx = 1; idx <= payload_size; idx++)
1899 checksum += info_packet->sb[idx];
1900
1901 /* PB0 = Checksum (one byte complement) */
1902 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
1903
1904 info_packet->valid = true;
1905}
1906
1646a6fe 1907static void set_hdr_static_info_packet(
6e4d6bee 1908 struct encoder_info_packet *info_packet,
1646a6fe 1909 struct core_surface *surface,
6e4d6bee 1910 struct core_stream *stream)
1646a6fe 1911{
e5cf325b 1912 uint16_t i = 0;
1646a6fe 1913 enum signal_type signal = stream->signal;
e5cf325b
HW		 1914 struct dc_hdr_static_metadata hdr_metadata;
1915 uint32_t data;
1646a6fe
AW		 1916
1917 if (!surface)
1918 return;
1919
e5cf325b 1920 hdr_metadata = surface->public.hdr_static_ctx;
1646a6fe 1921
70063a59 1922 if (!hdr_metadata.hdr_supported)
10bff005
YS		 1923 return;
1924
1646a6fe
AW		 1925 if (dc_is_hdmi_signal(signal)) {
1926 info_packet->valid = true;
1927
1928 info_packet->hb0 = 0x87;
1929 info_packet->hb1 = 0x01;
1930 info_packet->hb2 = 0x1A;
1931 i = 1;
1932 } else if (dc_is_dp_signal(signal)) {
1933 info_packet->valid = true;
1934
1935 info_packet->hb0 = 0x00;
1936 info_packet->hb1 = 0x87;
1937 info_packet->hb2 = 0x1D;
1938 info_packet->hb3 = (0x13 << 2);
1939 i = 2;
1940 }
1941
1646a6fe
AW		 1942 data = hdr_metadata.is_hdr;
1943 info_packet->sb[i++] = data ? 0x02 : 0x00;
1944 info_packet->sb[i++] = 0x00;
1945
1946 data = hdr_metadata.chromaticity_green_x / 2;
1947 info_packet->sb[i++] = data & 0xFF;
1948 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1949
1950 data = hdr_metadata.chromaticity_green_y / 2;
1951 info_packet->sb[i++] = data & 0xFF;
1952 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1953
1954 data = hdr_metadata.chromaticity_blue_x / 2;
1955 info_packet->sb[i++] = data & 0xFF;
1956 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1957
1958 data = hdr_metadata.chromaticity_blue_y / 2;
1959 info_packet->sb[i++] = data & 0xFF;
1960 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1961
1962 data = hdr_metadata.chromaticity_red_x / 2;
1963 info_packet->sb[i++] = data & 0xFF;
1964 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1965
1966 data = hdr_metadata.chromaticity_red_y / 2;
1967 info_packet->sb[i++] = data & 0xFF;
1968 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1969
1970 data = hdr_metadata.chromaticity_white_point_x / 2;
1971 info_packet->sb[i++] = data & 0xFF;
1972 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1973
1974 data = hdr_metadata.chromaticity_white_point_y / 2;
1975 info_packet->sb[i++] = data & 0xFF;
1976 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1977
1978 data = hdr_metadata.max_luminance;
1979 info_packet->sb[i++] = data & 0xFF;
1980 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1981
1982 data = hdr_metadata.min_luminance;
1983 info_packet->sb[i++] = data & 0xFF;
1984 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1985
1986 data = hdr_metadata.maximum_content_light_level;
1987 info_packet->sb[i++] = data & 0xFF;
1988 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1989
1990 data = hdr_metadata.maximum_frame_average_light_level;
1991 info_packet->sb[i++] = data & 0xFF;
1992 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1993
1994 if (dc_is_hdmi_signal(signal)) {
1995 uint32_t checksum = 0;
1996
1997 checksum += info_packet->hb0;
1998 checksum += info_packet->hb1;
1999 checksum += info_packet->hb2;
2000
2001 for (i = 1; i <= info_packet->hb2; i++)
2002 checksum += info_packet->sb[i];
2003
2004 info_packet->sb[0] = 0x100 - checksum;
2005 } else if (dc_is_dp_signal(signal)) {
2006 info_packet->sb[0] = 0x01;
2007 info_packet->sb[1] = 0x1A;
2008 }
2009}
2010
6e4d6bee
TC		 2011static void set_vsc_info_packet(
2012 struct encoder_info_packet *info_packet,
2013 struct core_stream *stream)
4562236b
HW		 2014{
2015 unsigned int vscPacketRevision = 0;
2016 unsigned int i;
2017
94267b3d 2018 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2019 vscPacketRevision = 2;
2020 }
2021
2022 /* VSC packet not needed based on the features
2023 * supported by this DP display
2024 */
2025 if (vscPacketRevision == 0)
2026 return;
2027
2028 if (vscPacketRevision == 0x2) {
2029 /* Secondary-data Packet ID = 0*/
2030 info_packet->hb0 = 0x00;
2031 /* 07h - Packet Type Value indicating Video
2032 * Stream Configuration packet
2033 */
2034 info_packet->hb1 = 0x07;
2035 /* 02h = VSC SDP supporting 3D stereo and PSR
2036 * (applies to eDP v1.3 or higher).
2037 */
2038 info_packet->hb2 = 0x02;
2039 /* 08h = VSC packet supporting 3D stereo + PSR
2040 * (HB2 = 02h).
2041 */
2042 info_packet->hb3 = 0x08;
2043
2044 for (i = 0; i < 28; i++)
2045 info_packet->sb[i] = 0;
2046
2047 info_packet->valid = true;
2048 }
2049
2050 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2051}
2052
8122a253 2053void dc_resource_validate_ctx_destruct(struct validate_context *context)
4562236b
HW		 2054{
2055 int i, j;
2056
ab2541b6
AC		 2057 for (i = 0; i < context->stream_count; i++) {
2058 for (j = 0; j < context->stream_status[i].surface_count; j++)
4562236b 2059 dc_surface_release(
ab2541b6 2060 context->stream_status[i].surfaces[j]);
4562236b 2061
ab2541b6
AC		 2062 context->stream_status[i].surface_count = 0;
2063 dc_stream_release(&context->streams[i]->public);
2064 context->streams[i] = NULL;
4562236b
HW		 2065 }
2066}
2067
2068/*
ab2541b6 2069 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2070 * by the src_ctx
2071 */
8122a253 2072void dc_resource_validate_ctx_copy_construct(
4562236b
HW		 2073 const struct validate_context *src_ctx,
2074 struct validate_context *dst_ctx)
2075{
2076 int i, j;
2077
2078 *dst_ctx = *src_ctx;
2079
2080 for (i = 0; i < dst_ctx->res_ctx.pool->pipe_count; i++) {
2081 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2082
2083 if (cur_pipe->top_pipe)
2084 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2085
2086 if (cur_pipe->bottom_pipe)
2087 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2088
2089 }
2090
ab2541b6
AC		 2091 for (i = 0; i < dst_ctx->stream_count; i++) {
2092 dc_stream_retain(&dst_ctx->streams[i]->public);
2093 for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++)
4562236b 2094 dc_surface_retain(
ab2541b6 2095 dst_ctx->stream_status[i].surfaces[j]);
4562236b
HW		 2096 }
2097}
2098
2099struct clock_source *dc_resource_find_first_free_pll(
2100 struct resource_context *res_ctx)
2101{
2102 int i;
2103
2104 for (i = 0; i < res_ctx->pool->clk_src_count; ++i) {
2105 if (res_ctx->clock_source_ref_count[i] == 0)
2106 return res_ctx->pool->clock_sources[i];
2107 }
2108
2109 return NULL;
2110}
2111
2112void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2113{
2114 enum signal_type signal = SIGNAL_TYPE_NONE;
6e4d6bee 2115 struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
4562236b
HW		 2116
2117 /* default all packets to invalid */
6e4d6bee
TC		 2118 info->avi.valid = false;
2119 info->gamut.valid = false;
2120 info->vendor.valid = false;
2121 info->hdrsmd.valid = false;
2122 info->vsc.valid = false;
4562236b
HW		 2123
2124 signal = pipe_ctx->stream->signal;
2125
2126 /* HDMi and DP have different info packets*/
2127 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2128 set_avi_info_frame(&info->avi, pipe_ctx);
2129
2130 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2131
2132 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2133
2134 set_hdr_static_info_packet(&info->hdrsmd,
2135 pipe_ctx->surface, pipe_ctx->stream);
2136
a33fa99d 2137 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2138 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2139
2140 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2141
2142 set_hdr_static_info_packet(&info->hdrsmd,
2143 pipe_ctx->surface, pipe_ctx->stream);
a33fa99d 2144 }
4562236b 2145
6e4d6bee 2146 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2147}
2148
2149enum dc_status resource_map_clock_resources(
2150 const struct core_dc *dc,
2151 struct validate_context *context)
2152{
ab2541b6 2153 int i, j;
4562236b
HW		 2154
2155 /* acquire new resources */
ab2541b6
AC		 2156 for (i = 0; i < context->stream_count; i++) {
2157 const struct core_stream *stream = context->streams[i];
4562236b 2158
ab2541b6
AC		 2159 if (resource_is_stream_unchanged(dc->current_context, stream))
2160 continue;
2161
2162 for (j = 0; j < MAX_PIPES; j++) {
2163 struct pipe_ctx *pipe_ctx =
2164 &context->res_ctx.pipe_ctx[j];
4562236b 2165
ab2541b6 2166 if (context->res_ctx.pipe_ctx[j].stream != stream)
4562236b
HW		 2167 continue;
2168
ab2541b6
AC		 2169 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2170 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2171 pipe_ctx->clock_source =
2172 context->res_ctx.pool->dp_clock_source;
2173 else {
2174 pipe_ctx->clock_source = NULL;
4562236b 2175
ab2541b6
AC		 2176 if (!dc->public.config.disable_disp_pll_sharing)
2177 resource_find_used_clk_src_for_sharing(
2178 &context->res_ctx,
2179 pipe_ctx);
4562236b 2180
ab2541b6 2181 if (pipe_ctx->clock_source == NULL)
4562236b 2182 pipe_ctx->clock_source =
ab2541b6
AC		 2183 dc_resource_find_first_free_pll(&context->res_ctx);
2184 }
4562236b 2185
ab2541b6
AC		 2186 if (pipe_ctx->clock_source == NULL)
2187 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2188
ab2541b6
AC		 2189 resource_reference_clock_source(
2190 &context->res_ctx,
2191 pipe_ctx->clock_source);
4562236b 2192
ab2541b6
AC		 2193 /* only one cs per stream regardless of mpo */
2194 break;
4562236b
HW		 2195 }
2196 }
2197
2198 return DC_OK;
2199}
2200
2201/*
2202 * Note: We need to disable output if clock sources change,
2203 * since bios does optimization and doesn't apply if changing
2204 * PHY when not already disabled.
2205 */
2206bool pipe_need_reprogram(
2207 struct pipe_ctx *pipe_ctx_old,
2208 struct pipe_ctx *pipe_ctx)
2209{
2210 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2211 return true;
2212
2213 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2214 return true;
2215
2216 if (pipe_ctx_old->audio != pipe_ctx->audio)
2217 return true;
2218
2219 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2220 && pipe_ctx_old->stream != pipe_ctx->stream)
2221 return true;
2222
2223 if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
2224 return true;
2225
2226 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2227 return true;
2228
2229
2230 return false;
2231}
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