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4562236b HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | #include "dm_services.h" | |
26 | ||
27 | #include "resource.h" | |
28 | #include "include/irq_service_interface.h" | |
29 | #include "link_encoder.h" | |
30 | #include "stream_encoder.h" | |
31 | #include "opp.h" | |
32 | #include "timing_generator.h" | |
33 | #include "transform.h" | |
5ac3d3c9 | 34 | #include "core_types.h" |
4562236b | 35 | #include "set_mode_types.h" |
4562236b HW |
36 | #include "virtual/virtual_stream_encoder.h" |
37 | ||
38 | #include "dce80/dce80_resource.h" | |
39 | #include "dce100/dce100_resource.h" | |
40 | #include "dce110/dce110_resource.h" | |
41 | #include "dce112/dce112_resource.h" | |
ff5ef992 AD |
42 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
43 | #include "dcn10/dcn10_resource.h" | |
44 | #endif | |
2c8ad2d5 | 45 | #include "dce120/dce120_resource.h" |
4562236b HW |
46 | |
47 | enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) | |
48 | { | |
49 | enum dce_version dc_version = DCE_VERSION_UNKNOWN; | |
50 | switch (asic_id.chip_family) { | |
51 | ||
52 | case FAMILY_CI: | |
53 | case FAMILY_KV: | |
54 | dc_version = DCE_VERSION_8_0; | |
55 | break; | |
56 | case FAMILY_CZ: | |
57 | dc_version = DCE_VERSION_11_0; | |
58 | break; | |
59 | ||
60 | case FAMILY_VI: | |
61 | if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || | |
62 | ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { | |
63 | dc_version = DCE_VERSION_10_0; | |
64 | break; | |
65 | } | |
66 | if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || | |
b264d345 JL |
67 | ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || |
68 | ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { | |
4562236b HW |
69 | dc_version = DCE_VERSION_11_2; |
70 | } | |
71 | break; | |
2c8ad2d5 AD |
72 | case FAMILY_AI: |
73 | dc_version = DCE_VERSION_12_0; | |
74 | break; | |
ff5ef992 AD |
75 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
76 | case FAMILY_RV: | |
77 | dc_version = DCN_VERSION_1_0; | |
78 | break; | |
79 | #endif | |
4562236b HW |
80 | default: |
81 | dc_version = DCE_VERSION_UNKNOWN; | |
82 | break; | |
83 | } | |
84 | return dc_version; | |
85 | } | |
86 | ||
87 | struct resource_pool *dc_create_resource_pool( | |
88 | struct core_dc *dc, | |
89 | int num_virtual_links, | |
90 | enum dce_version dc_version, | |
91 | struct hw_asic_id asic_id) | |
92 | { | |
5ac3d3c9 | 93 | struct resource_pool *res_pool = NULL; |
4562236b HW |
94 | |
95 | switch (dc_version) { | |
96 | case DCE_VERSION_8_0: | |
5ac3d3c9 | 97 | res_pool = dce80_create_resource_pool( |
4562236b | 98 | num_virtual_links, dc); |
5ac3d3c9 | 99 | break; |
4562236b | 100 | case DCE_VERSION_10_0: |
5ac3d3c9 | 101 | res_pool = dce100_create_resource_pool( |
4562236b | 102 | num_virtual_links, dc); |
5ac3d3c9 | 103 | break; |
4562236b | 104 | case DCE_VERSION_11_0: |
5ac3d3c9 | 105 | res_pool = dce110_create_resource_pool( |
4562236b | 106 | num_virtual_links, dc, asic_id); |
5ac3d3c9 | 107 | break; |
4562236b | 108 | case DCE_VERSION_11_2: |
5ac3d3c9 | 109 | res_pool = dce112_create_resource_pool( |
4562236b | 110 | num_virtual_links, dc); |
5ac3d3c9 | 111 | break; |
2c8ad2d5 AD |
112 | case DCE_VERSION_12_0: |
113 | res_pool = dce120_create_resource_pool( | |
114 | num_virtual_links, dc); | |
115 | break; | |
ff5ef992 AD |
116 | |
117 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | |
118 | case DCN_VERSION_1_0: | |
119 | res_pool = dcn10_create_resource_pool( | |
120 | num_virtual_links, dc); | |
121 | break; | |
122 | #endif | |
4562236b HW |
123 | default: |
124 | break; | |
125 | } | |
5ac3d3c9 CL |
126 | if (res_pool != NULL) { |
127 | struct firmware_info fw_info = { { 0 } }; | |
128 | ||
129 | if (dc->ctx->dc_bios->funcs->get_firmware_info( | |
130 | dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { | |
131 | res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency; | |
132 | } else | |
133 | ASSERT_CRITICAL(false); | |
134 | } | |
4562236b | 135 | |
5ac3d3c9 | 136 | return res_pool; |
4562236b HW |
137 | } |
138 | ||
139 | void dc_destroy_resource_pool(struct core_dc *dc) | |
140 | { | |
141 | if (dc) { | |
142 | if (dc->res_pool) | |
143 | dc->res_pool->funcs->destroy(&dc->res_pool); | |
144 | ||
145 | if (dc->hwseq) | |
146 | dm_free(dc->hwseq); | |
147 | } | |
148 | } | |
149 | ||
150 | static void update_num_audio( | |
151 | const struct resource_straps *straps, | |
152 | unsigned int *num_audio, | |
153 | struct audio_support *aud_support) | |
154 | { | |
155 | if (straps->hdmi_disable == 0) { | |
156 | aud_support->hdmi_audio_native = true; | |
157 | aud_support->hdmi_audio_on_dongle = true; | |
158 | aud_support->dp_audio = true; | |
159 | } else { | |
160 | if (straps->dc_pinstraps_audio & 0x2) { | |
161 | aud_support->hdmi_audio_on_dongle = true; | |
162 | aud_support->dp_audio = true; | |
163 | } else { | |
164 | aud_support->dp_audio = true; | |
165 | } | |
166 | } | |
167 | ||
168 | switch (straps->audio_stream_number) { | |
169 | case 0: /* multi streams supported */ | |
170 | break; | |
171 | case 1: /* multi streams not supported */ | |
172 | *num_audio = 1; | |
173 | break; | |
174 | default: | |
175 | DC_ERR("DC: unexpected audio fuse!\n"); | |
17a96033 | 176 | } |
4562236b HW |
177 | } |
178 | ||
179 | bool resource_construct( | |
180 | unsigned int num_virtual_links, | |
181 | struct core_dc *dc, | |
182 | struct resource_pool *pool, | |
183 | const struct resource_create_funcs *create_funcs) | |
184 | { | |
185 | struct dc_context *ctx = dc->ctx; | |
186 | const struct resource_caps *caps = pool->res_cap; | |
187 | int i; | |
188 | unsigned int num_audio = caps->num_audio; | |
189 | struct resource_straps straps = {0}; | |
190 | ||
191 | if (create_funcs->read_dce_straps) | |
192 | create_funcs->read_dce_straps(dc->ctx, &straps); | |
193 | ||
194 | pool->audio_count = 0; | |
195 | if (create_funcs->create_audio) { | |
196 | /* find the total number of streams available via the | |
197 | * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT | |
198 | * registers (one for each pin) starting from pin 1 | |
199 | * up to the max number of audio pins. | |
200 | * We stop on the first pin where | |
201 | * PORT_CONNECTIVITY == 1 (as instructed by HW team). | |
202 | */ | |
203 | update_num_audio(&straps, &num_audio, &pool->audio_support); | |
204 | for (i = 0; i < pool->pipe_count && i < num_audio; i++) { | |
205 | struct audio *aud = create_funcs->create_audio(ctx, i); | |
206 | ||
207 | if (aud == NULL) { | |
208 | DC_ERR("DC: failed to create audio!\n"); | |
209 | return false; | |
210 | } | |
211 | ||
212 | if (!aud->funcs->endpoint_valid(aud)) { | |
213 | aud->funcs->destroy(&aud); | |
214 | break; | |
215 | } | |
216 | ||
217 | pool->audios[i] = aud; | |
218 | pool->audio_count++; | |
219 | } | |
220 | } | |
221 | ||
222 | pool->stream_enc_count = 0; | |
223 | if (create_funcs->create_stream_encoder) { | |
224 | for (i = 0; i < caps->num_stream_encoder; i++) { | |
225 | pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); | |
226 | if (pool->stream_enc[i] == NULL) | |
227 | DC_ERR("DC: failed to create stream_encoder!\n"); | |
228 | pool->stream_enc_count++; | |
229 | } | |
230 | } | |
231 | ||
232 | for (i = 0; i < num_virtual_links; i++) { | |
233 | pool->stream_enc[pool->stream_enc_count] = | |
234 | virtual_stream_encoder_create( | |
235 | ctx, ctx->dc_bios); | |
236 | if (pool->stream_enc[pool->stream_enc_count] == NULL) { | |
237 | DC_ERR("DC: failed to create stream_encoder!\n"); | |
238 | return false; | |
239 | } | |
240 | pool->stream_enc_count++; | |
241 | } | |
242 | ||
243 | dc->hwseq = create_funcs->create_hwseq(ctx); | |
244 | ||
245 | return true; | |
246 | } | |
247 | ||
248 | ||
249 | void resource_unreference_clock_source( | |
250 | struct resource_context *res_ctx, | |
a2b8659d | 251 | const struct resource_pool *pool, |
8c737fcc | 252 | struct clock_source **clock_source) |
4562236b HW |
253 | { |
254 | int i; | |
a2b8659d TC |
255 | for (i = 0; i < pool->clk_src_count; i++) { |
256 | if (pool->clock_sources[i] != *clock_source) | |
4562236b HW |
257 | continue; |
258 | ||
259 | res_ctx->clock_source_ref_count[i]--; | |
260 | ||
261 | if (res_ctx->clock_source_ref_count[i] == 0) | |
8c737fcc | 262 | (*clock_source)->funcs->cs_power_down(*clock_source); |
4562236b HW |
263 | |
264 | break; | |
265 | } | |
266 | ||
a2b8659d | 267 | if (pool->dp_clock_source == *clock_source) { |
4562236b HW |
268 | res_ctx->dp_clock_source_ref_count--; |
269 | ||
270 | if (res_ctx->dp_clock_source_ref_count == 0) | |
8c737fcc | 271 | (*clock_source)->funcs->cs_power_down(*clock_source); |
4562236b | 272 | } |
8c737fcc | 273 | *clock_source = NULL; |
4562236b HW |
274 | } |
275 | ||
276 | void resource_reference_clock_source( | |
277 | struct resource_context *res_ctx, | |
a2b8659d | 278 | const struct resource_pool *pool, |
4562236b HW |
279 | struct clock_source *clock_source) |
280 | { | |
281 | int i; | |
a2b8659d TC |
282 | for (i = 0; i < pool->clk_src_count; i++) { |
283 | if (pool->clock_sources[i] != clock_source) | |
4562236b HW |
284 | continue; |
285 | ||
286 | res_ctx->clock_source_ref_count[i]++; | |
287 | break; | |
288 | } | |
289 | ||
a2b8659d | 290 | if (pool->dp_clock_source == clock_source) |
4562236b HW |
291 | res_ctx->dp_clock_source_ref_count++; |
292 | } | |
293 | ||
294 | bool resource_are_streams_timing_synchronizable( | |
295 | const struct core_stream *stream1, | |
296 | const struct core_stream *stream2) | |
297 | { | |
298 | if (stream1->public.timing.h_total != stream2->public.timing.h_total) | |
299 | return false; | |
300 | ||
301 | if (stream1->public.timing.v_total != stream2->public.timing.v_total) | |
302 | return false; | |
303 | ||
304 | if (stream1->public.timing.h_addressable | |
305 | != stream2->public.timing.h_addressable) | |
306 | return false; | |
307 | ||
308 | if (stream1->public.timing.v_addressable | |
309 | != stream2->public.timing.v_addressable) | |
310 | return false; | |
311 | ||
312 | if (stream1->public.timing.pix_clk_khz | |
313 | != stream2->public.timing.pix_clk_khz) | |
314 | return false; | |
315 | ||
316 | if (stream1->phy_pix_clk != stream2->phy_pix_clk | |
7e2fe319 CL |
317 | && (!dc_is_dp_signal(stream1->signal) |
318 | || !dc_is_dp_signal(stream2->signal))) | |
4562236b HW |
319 | return false; |
320 | ||
321 | return true; | |
322 | } | |
323 | ||
324 | static bool is_sharable_clk_src( | |
325 | const struct pipe_ctx *pipe_with_clk_src, | |
326 | const struct pipe_ctx *pipe) | |
327 | { | |
328 | if (pipe_with_clk_src->clock_source == NULL) | |
329 | return false; | |
330 | ||
331 | if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) | |
332 | return false; | |
333 | ||
334 | if (dc_is_dp_signal(pipe_with_clk_src->stream->signal)) | |
335 | return false; | |
336 | ||
337 | if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) | |
338 | && dc_is_dvi_signal(pipe->stream->signal)) | |
339 | return false; | |
340 | ||
341 | if (dc_is_hdmi_signal(pipe->stream->signal) | |
342 | && dc_is_dvi_signal(pipe_with_clk_src->stream->signal)) | |
343 | return false; | |
344 | ||
345 | if (!resource_are_streams_timing_synchronizable( | |
346 | pipe_with_clk_src->stream, pipe->stream)) | |
347 | return false; | |
348 | ||
349 | return true; | |
350 | } | |
351 | ||
352 | struct clock_source *resource_find_used_clk_src_for_sharing( | |
353 | struct resource_context *res_ctx, | |
354 | struct pipe_ctx *pipe_ctx) | |
355 | { | |
356 | int i; | |
357 | ||
358 | for (i = 0; i < MAX_PIPES; i++) { | |
359 | if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) | |
360 | return res_ctx->pipe_ctx[i].clock_source; | |
361 | } | |
362 | ||
363 | return NULL; | |
364 | } | |
365 | ||
366 | static enum pixel_format convert_pixel_format_to_dalsurface( | |
367 | enum surface_pixel_format surface_pixel_format) | |
368 | { | |
369 | enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; | |
370 | ||
371 | switch (surface_pixel_format) { | |
372 | case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: | |
373 | dal_pixel_format = PIXEL_FORMAT_INDEX8; | |
374 | break; | |
375 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: | |
376 | dal_pixel_format = PIXEL_FORMAT_RGB565; | |
377 | break; | |
378 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |
379 | dal_pixel_format = PIXEL_FORMAT_RGB565; | |
380 | break; | |
381 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: | |
382 | dal_pixel_format = PIXEL_FORMAT_ARGB8888; | |
383 | break; | |
8693049a | 384 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: |
4562236b HW |
385 | dal_pixel_format = PIXEL_FORMAT_ARGB8888; |
386 | break; | |
387 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: | |
388 | dal_pixel_format = PIXEL_FORMAT_ARGB2101010; | |
389 | break; | |
390 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: | |
391 | dal_pixel_format = PIXEL_FORMAT_ARGB2101010; | |
392 | break; | |
393 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: | |
394 | dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; | |
395 | break; | |
396 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |
397 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |
398 | dal_pixel_format = PIXEL_FORMAT_FP16; | |
399 | break; | |
400 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: | |
4562236b HW |
401 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: |
402 | dal_pixel_format = PIXEL_FORMAT_420BPP12; | |
403 | break; | |
ffbcd19a VP |
404 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: |
405 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: | |
406 | dal_pixel_format = PIXEL_FORMAT_420BPP15; | |
407 | break; | |
4562236b HW |
408 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: |
409 | default: | |
410 | dal_pixel_format = PIXEL_FORMAT_UNKNOWN; | |
411 | break; | |
412 | } | |
413 | return dal_pixel_format; | |
414 | } | |
415 | ||
416 | static void rect_swap_helper(struct rect *rect) | |
417 | { | |
418 | uint32_t temp = 0; | |
419 | ||
420 | temp = rect->height; | |
421 | rect->height = rect->width; | |
422 | rect->width = temp; | |
423 | ||
424 | temp = rect->x; | |
425 | rect->x = rect->y; | |
426 | rect->y = temp; | |
427 | } | |
428 | ||
b2d0a103 | 429 | static void calculate_viewport(struct pipe_ctx *pipe_ctx) |
4562236b | 430 | { |
b2d0a103 | 431 | const struct dc_surface *surface = &pipe_ctx->surface->public; |
1fbd2cfc | 432 | const struct dc_stream *stream = &pipe_ctx->stream->public; |
b2d0a103 | 433 | struct scaler_data *data = &pipe_ctx->scl_data; |
86006a7f | 434 | struct rect surf_src = surface->src_rect; |
1fbd2cfc | 435 | struct rect clip = { 0 }; |
b2d0a103 DL |
436 | int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 |
437 | || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; | |
1fbd2cfc DL |
438 | bool pri_split = pipe_ctx->bottom_pipe && |
439 | pipe_ctx->bottom_pipe->surface == pipe_ctx->surface; | |
440 | bool sec_split = pipe_ctx->top_pipe && | |
441 | pipe_ctx->top_pipe->surface == pipe_ctx->surface; | |
4562236b | 442 | |
7f5c22d1 VP |
443 | if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || |
444 | stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { | |
7b779c99 VP |
445 | pri_split = false; |
446 | sec_split = false; | |
447 | } | |
86006a7f DL |
448 | |
449 | if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || | |
450 | pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) | |
451 | rect_swap_helper(&surf_src); | |
452 | ||
4562236b HW |
453 | /* The actual clip is an intersection between stream |
454 | * source and surface clip | |
455 | */ | |
1fbd2cfc DL |
456 | clip.x = stream->src.x > surface->clip_rect.x ? |
457 | stream->src.x : surface->clip_rect.x; | |
4562236b | 458 | |
1fbd2cfc DL |
459 | clip.width = stream->src.x + stream->src.width < |
460 | surface->clip_rect.x + surface->clip_rect.width ? | |
461 | stream->src.x + stream->src.width - clip.x : | |
462 | surface->clip_rect.x + surface->clip_rect.width - clip.x ; | |
4562236b | 463 | |
1fbd2cfc DL |
464 | clip.y = stream->src.y > surface->clip_rect.y ? |
465 | stream->src.y : surface->clip_rect.y; | |
4562236b | 466 | |
1fbd2cfc DL |
467 | clip.height = stream->src.y + stream->src.height < |
468 | surface->clip_rect.y + surface->clip_rect.height ? | |
469 | stream->src.y + stream->src.height - clip.y : | |
470 | surface->clip_rect.y + surface->clip_rect.height - clip.y ; | |
4562236b | 471 | |
86006a7f | 472 | /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio |
4562236b HW |
473 | * num_pixels = clip.num_pix * scl_ratio |
474 | */ | |
86006a7f DL |
475 | data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) * |
476 | surf_src.width / surface->dst_rect.width; | |
b2d0a103 | 477 | data->viewport.width = clip.width * |
86006a7f | 478 | surf_src.width / surface->dst_rect.width; |
4562236b | 479 | |
86006a7f DL |
480 | data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) * |
481 | surf_src.height / surface->dst_rect.height; | |
b2d0a103 | 482 | data->viewport.height = clip.height * |
86006a7f | 483 | surf_src.height / surface->dst_rect.height; |
4562236b | 484 | |
b2d0a103 DL |
485 | /* Round down, compensate in init */ |
486 | data->viewport_c.x = data->viewport.x / vpc_div; | |
487 | data->viewport_c.y = data->viewport.y / vpc_div; | |
488 | data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? | |
489 | dal_fixed31_32_half : dal_fixed31_32_zero; | |
490 | data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? | |
491 | dal_fixed31_32_half : dal_fixed31_32_zero; | |
492 | /* Round up, assume original video size always even dimensions */ | |
493 | data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div; | |
494 | data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; | |
495 | ||
496 | /* Handle hsplit */ | |
1fbd2cfc DL |
497 | if (pri_split || sec_split) { |
498 | /* HMirror XOR Secondary_pipe XOR Rotation_180 */ | |
499 | bool right_view = (sec_split != surface->horizontal_mirror) != | |
500 | (surface->rotation == ROTATION_ANGLE_180); | |
501 | ||
502 | if (surface->rotation == ROTATION_ANGLE_90 | |
503 | || surface->rotation == ROTATION_ANGLE_270) | |
504 | /* Secondary_pipe XOR Rotation_270 */ | |
505 | right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split; | |
9e6c74ce DL |
506 | |
507 | if (right_view) { | |
508 | data->viewport.width /= 2; | |
509 | data->viewport_c.width /= 2; | |
510 | data->viewport.x += data->viewport.width; | |
511 | data->viewport_c.x += data->viewport_c.width; | |
512 | /* Ceil offset pipe */ | |
513 | data->viewport.width += data->viewport.width % 2; | |
514 | data->viewport_c.width += data->viewport_c.width % 2; | |
515 | } else { | |
516 | data->viewport.width /= 2; | |
517 | data->viewport_c.width /= 2; | |
518 | } | |
b2d0a103 | 519 | } |
1fbd2cfc DL |
520 | |
521 | if (surface->rotation == ROTATION_ANGLE_90 || | |
522 | surface->rotation == ROTATION_ANGLE_270) { | |
523 | rect_swap_helper(&data->viewport_c); | |
524 | rect_swap_helper(&data->viewport); | |
525 | } | |
4562236b HW |
526 | } |
527 | ||
b2d0a103 | 528 | static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) |
4562236b | 529 | { |
b2d0a103 | 530 | const struct dc_surface *surface = &pipe_ctx->surface->public; |
4562236b | 531 | struct core_stream *stream = pipe_ctx->stream; |
86006a7f DL |
532 | struct rect surf_src = surface->src_rect; |
533 | struct rect surf_clip = surface->clip_rect; | |
c802570e | 534 | int recout_full_x, recout_full_y; |
4562236b | 535 | |
86006a7f DL |
536 | if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || |
537 | pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) | |
538 | rect_swap_helper(&surf_src); | |
539 | ||
4562236b | 540 | pipe_ctx->scl_data.recout.x = stream->public.dst.x; |
86006a7f DL |
541 | if (stream->public.src.x < surf_clip.x) |
542 | pipe_ctx->scl_data.recout.x += (surf_clip.x | |
4562236b HW |
543 | - stream->public.src.x) * stream->public.dst.width |
544 | / stream->public.src.width; | |
545 | ||
86006a7f | 546 | pipe_ctx->scl_data.recout.width = surf_clip.width * |
4562236b HW |
547 | stream->public.dst.width / stream->public.src.width; |
548 | if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x > | |
549 | stream->public.dst.x + stream->public.dst.width) | |
550 | pipe_ctx->scl_data.recout.width = | |
551 | stream->public.dst.x + stream->public.dst.width | |
552 | - pipe_ctx->scl_data.recout.x; | |
553 | ||
554 | pipe_ctx->scl_data.recout.y = stream->public.dst.y; | |
86006a7f DL |
555 | if (stream->public.src.y < surf_clip.y) |
556 | pipe_ctx->scl_data.recout.y += (surf_clip.y | |
4562236b HW |
557 | - stream->public.src.y) * stream->public.dst.height |
558 | / stream->public.src.height; | |
559 | ||
86006a7f | 560 | pipe_ctx->scl_data.recout.height = surf_clip.height * |
4562236b HW |
561 | stream->public.dst.height / stream->public.src.height; |
562 | if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y > | |
563 | stream->public.dst.y + stream->public.dst.height) | |
564 | pipe_ctx->scl_data.recout.height = | |
565 | stream->public.dst.y + stream->public.dst.height | |
566 | - pipe_ctx->scl_data.recout.y; | |
b2d0a103 | 567 | |
7b779c99 VP |
568 | /* Handle h & vsplit */ |
569 | if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == | |
570 | pipe_ctx->surface) { | |
7f5c22d1 | 571 | if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { |
7b779c99 VP |
572 | pipe_ctx->scl_data.recout.height /= 2; |
573 | pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; | |
574 | /* Floor primary pipe, ceil 2ndary pipe */ | |
575 | pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2; | |
576 | } else { | |
577 | pipe_ctx->scl_data.recout.width /= 2; | |
578 | pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width; | |
579 | pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2; | |
580 | } | |
581 | } else if (pipe_ctx->bottom_pipe && | |
86006a7f | 582 | pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { |
7f5c22d1 | 583 | if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) |
7b779c99 VP |
584 | pipe_ctx->scl_data.recout.height /= 2; |
585 | else | |
586 | pipe_ctx->scl_data.recout.width /= 2; | |
b2d0a103 DL |
587 | } |
588 | ||
86006a7f DL |
589 | /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset) |
590 | * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl | |
c802570e DL |
591 | * ratio) |
592 | */ | |
593 | recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x) | |
594 | * stream->public.dst.width / stream->public.src.width - | |
86006a7f | 595 | surf_src.x * surface->dst_rect.width / surf_src.width |
c802570e DL |
596 | * stream->public.dst.width / stream->public.src.width; |
597 | recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y) | |
598 | * stream->public.dst.height / stream->public.src.height - | |
86006a7f | 599 | surf_src.y * surface->dst_rect.height / surf_src.height |
c802570e DL |
600 | * stream->public.dst.height / stream->public.src.height; |
601 | ||
602 | recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; | |
603 | recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y; | |
4562236b HW |
604 | } |
605 | ||
b2d0a103 | 606 | static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) |
4562236b | 607 | { |
b2d0a103 | 608 | const struct dc_surface *surface = &pipe_ctx->surface->public; |
4562236b | 609 | struct core_stream *stream = pipe_ctx->stream; |
86006a7f | 610 | struct rect surf_src = surface->src_rect; |
1fbd2cfc DL |
611 | const int in_w = stream->public.src.width; |
612 | const int in_h = stream->public.src.height; | |
613 | const int out_w = stream->public.dst.width; | |
614 | const int out_h = stream->public.dst.height; | |
4562236b | 615 | |
86006a7f DL |
616 | if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || |
617 | pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) | |
618 | rect_swap_helper(&surf_src); | |
619 | ||
4562236b | 620 | pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction( |
86006a7f | 621 | surf_src.width, |
4562236b HW |
622 | surface->dst_rect.width); |
623 | pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction( | |
86006a7f | 624 | surf_src.height, |
4562236b HW |
625 | surface->dst_rect.height); |
626 | ||
7f5c22d1 | 627 | if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) |
4562236b HW |
628 | pipe_ctx->scl_data.ratios.horz.value *= 2; |
629 | else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) | |
630 | pipe_ctx->scl_data.ratios.vert.value *= 2; | |
631 | ||
632 | pipe_ctx->scl_data.ratios.vert.value = div64_s64( | |
633 | pipe_ctx->scl_data.ratios.vert.value * in_h, out_h); | |
634 | pipe_ctx->scl_data.ratios.horz.value = div64_s64( | |
635 | pipe_ctx->scl_data.ratios.horz.value * in_w, out_w); | |
636 | ||
637 | pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz; | |
638 | pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert; | |
639 | ||
b2d0a103 DL |
640 | if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12 |
641 | || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) { | |
4562236b HW |
642 | pipe_ctx->scl_data.ratios.horz_c.value /= 2; |
643 | pipe_ctx->scl_data.ratios.vert_c.value /= 2; | |
644 | } | |
645 | } | |
646 | ||
b2d0a103 DL |
647 | static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) |
648 | { | |
649 | struct scaler_data *data = &pipe_ctx->scl_data; | |
650 | struct rect src = pipe_ctx->surface->public.src_rect; | |
651 | int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 | |
652 | || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; | |
653 | ||
86006a7f | 654 | |
1fbd2cfc DL |
655 | if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || |
656 | pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) { | |
86006a7f | 657 | rect_swap_helper(&src); |
1fbd2cfc DL |
658 | rect_swap_helper(&data->viewport_c); |
659 | rect_swap_helper(&data->viewport); | |
660 | } | |
661 | ||
b2d0a103 DL |
662 | /* |
663 | * Init calculated according to formula: | |
664 | * init = (scaling_ratio + number_of_taps + 1) / 2 | |
665 | * init_bot = init + scaling_ratio | |
666 | * init_c = init + truncated_vp_c_offset(from calculate viewport) | |
667 | */ | |
668 | data->inits.h = dal_fixed31_32_div_int( | |
669 | dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2); | |
670 | ||
671 | data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int( | |
672 | dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)); | |
673 | ||
674 | data->inits.v = dal_fixed31_32_div_int( | |
675 | dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2); | |
676 | ||
677 | data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int( | |
678 | dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)); | |
679 | ||
680 | ||
681 | /* Adjust for viewport end clip-off */ | |
682 | if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) { | |
683 | int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x; | |
1fbd2cfc DL |
684 | int int_part = dal_fixed31_32_floor( |
685 | dal_fixed31_32_sub(data->inits.h, data->ratios.horz)); | |
b2d0a103 | 686 | |
1fbd2cfc | 687 | int_part = int_part > 0 ? int_part : 0; |
b2d0a103 DL |
688 | data->viewport.width += int_part < vp_clip ? int_part : vp_clip; |
689 | } | |
690 | if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) { | |
691 | int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y; | |
1fbd2cfc DL |
692 | int int_part = dal_fixed31_32_floor( |
693 | dal_fixed31_32_sub(data->inits.v, data->ratios.vert)); | |
b2d0a103 | 694 | |
1fbd2cfc | 695 | int_part = int_part > 0 ? int_part : 0; |
b2d0a103 DL |
696 | data->viewport.height += int_part < vp_clip ? int_part : vp_clip; |
697 | } | |
698 | if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) { | |
699 | int vp_clip = (src.x + src.width) / vpc_div - | |
700 | data->viewport_c.width - data->viewport_c.x; | |
1fbd2cfc DL |
701 | int int_part = dal_fixed31_32_floor( |
702 | dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c)); | |
b2d0a103 | 703 | |
1fbd2cfc | 704 | int_part = int_part > 0 ? int_part : 0; |
b2d0a103 DL |
705 | data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip; |
706 | } | |
707 | if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) { | |
708 | int vp_clip = (src.y + src.height) / vpc_div - | |
709 | data->viewport_c.height - data->viewport_c.y; | |
1fbd2cfc DL |
710 | int int_part = dal_fixed31_32_floor( |
711 | dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c)); | |
b2d0a103 | 712 | |
1fbd2cfc | 713 | int_part = int_part > 0 ? int_part : 0; |
b2d0a103 DL |
714 | data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip; |
715 | } | |
716 | ||
717 | /* Adjust for non-0 viewport offset */ | |
718 | if (data->viewport.x) { | |
719 | int int_part; | |
720 | ||
721 | data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int( | |
722 | data->ratios.horz, recout_skip->width)); | |
723 | int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x; | |
724 | if (int_part < data->taps.h_taps) { | |
725 | int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ? | |
726 | (data->taps.h_taps - int_part) : data->viewport.x; | |
727 | data->viewport.x -= int_adj; | |
728 | data->viewport.width += int_adj; | |
729 | int_part += int_adj; | |
730 | } else if (int_part > data->taps.h_taps) { | |
731 | data->viewport.x += int_part - data->taps.h_taps; | |
732 | data->viewport.width -= int_part - data->taps.h_taps; | |
733 | int_part = data->taps.h_taps; | |
734 | } | |
735 | data->inits.h.value &= 0xffffffff; | |
736 | data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part); | |
737 | } | |
738 | ||
739 | if (data->viewport_c.x) { | |
740 | int int_part; | |
741 | ||
742 | data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int( | |
743 | data->ratios.horz_c, recout_skip->width)); | |
744 | int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x; | |
745 | if (int_part < data->taps.h_taps_c) { | |
746 | int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ? | |
747 | (data->taps.h_taps_c - int_part) : data->viewport_c.x; | |
748 | data->viewport_c.x -= int_adj; | |
749 | data->viewport_c.width += int_adj; | |
750 | int_part += int_adj; | |
751 | } else if (int_part > data->taps.h_taps_c) { | |
752 | data->viewport_c.x += int_part - data->taps.h_taps_c; | |
753 | data->viewport_c.width -= int_part - data->taps.h_taps_c; | |
754 | int_part = data->taps.h_taps_c; | |
755 | } | |
756 | data->inits.h_c.value &= 0xffffffff; | |
757 | data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part); | |
758 | } | |
759 | ||
760 | if (data->viewport.y) { | |
761 | int int_part; | |
762 | ||
763 | data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int( | |
764 | data->ratios.vert, recout_skip->height)); | |
765 | int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y; | |
766 | if (int_part < data->taps.v_taps) { | |
767 | int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ? | |
768 | (data->taps.v_taps - int_part) : data->viewport.y; | |
769 | data->viewport.y -= int_adj; | |
770 | data->viewport.height += int_adj; | |
771 | int_part += int_adj; | |
772 | } else if (int_part > data->taps.v_taps) { | |
773 | data->viewport.y += int_part - data->taps.v_taps; | |
774 | data->viewport.height -= int_part - data->taps.v_taps; | |
775 | int_part = data->taps.v_taps; | |
776 | } | |
777 | data->inits.v.value &= 0xffffffff; | |
778 | data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part); | |
779 | } | |
780 | ||
781 | if (data->viewport_c.y) { | |
782 | int int_part; | |
783 | ||
784 | data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int( | |
785 | data->ratios.vert_c, recout_skip->height)); | |
786 | int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y; | |
787 | if (int_part < data->taps.v_taps_c) { | |
788 | int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ? | |
789 | (data->taps.v_taps_c - int_part) : data->viewport_c.y; | |
790 | data->viewport_c.y -= int_adj; | |
791 | data->viewport_c.height += int_adj; | |
792 | int_part += int_adj; | |
793 | } else if (int_part > data->taps.v_taps_c) { | |
794 | data->viewport_c.y += int_part - data->taps.v_taps_c; | |
795 | data->viewport_c.height -= int_part - data->taps.v_taps_c; | |
796 | int_part = data->taps.v_taps_c; | |
797 | } | |
798 | data->inits.v_c.value &= 0xffffffff; | |
799 | data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part); | |
800 | } | |
801 | ||
802 | /* Interlaced inits based on final vert inits */ | |
803 | data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); | |
804 | data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); | |
1fbd2cfc DL |
805 | |
806 | if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || | |
807 | pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) { | |
808 | rect_swap_helper(&data->viewport_c); | |
809 | rect_swap_helper(&data->viewport); | |
810 | } | |
b2d0a103 DL |
811 | } |
812 | ||
813 | bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) | |
4562236b | 814 | { |
b2d0a103 | 815 | const struct dc_surface *surface = &pipe_ctx->surface->public; |
4562236b | 816 | struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; |
b2d0a103 DL |
817 | struct view recout_skip = { 0 }; |
818 | bool res = false; | |
819 | ||
4562236b HW |
820 | /* Important: scaling ratio calculation requires pixel format, |
821 | * lb depth calculation requires recout and taps require scaling ratios. | |
b2d0a103 | 822 | * Inits require viewport, taps, ratios and recout of split pipe |
4562236b | 823 | */ |
b2d0a103 DL |
824 | pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( |
825 | pipe_ctx->surface->public.format); | |
826 | ||
827 | calculate_scaling_ratios(pipe_ctx); | |
4562236b | 828 | |
b2d0a103 | 829 | calculate_viewport(pipe_ctx); |
4562236b HW |
830 | |
831 | if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16) | |
832 | return false; | |
833 | ||
b2d0a103 | 834 | calculate_recout(pipe_ctx, &recout_skip); |
4562236b HW |
835 | |
836 | /** | |
837 | * Setting line buffer pixel depth to 24bpp yields banding | |
838 | * on certain displays, such as the Sharp 4k | |
839 | */ | |
840 | pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; | |
841 | ||
842 | pipe_ctx->scl_data.h_active = timing->h_addressable; | |
843 | pipe_ctx->scl_data.v_active = timing->v_addressable; | |
844 | ||
845 | /* Taps calculations */ | |
846 | res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( | |
847 | pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); | |
848 | ||
849 | if (!res) { | |
850 | /* Try 24 bpp linebuffer */ | |
851 | pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; | |
852 | ||
853 | res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( | |
854 | pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); | |
855 | } | |
856 | ||
b2d0a103 | 857 | if (res) |
1fbd2cfc | 858 | /* May need to re-check lb size after this in some obscure scenario */ |
b2d0a103 DL |
859 | calculate_inits_and_adj_vp(pipe_ctx, &recout_skip); |
860 | ||
4562236b HW |
861 | dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER, |
862 | "%s: Viewport:\nheight:%d width:%d x:%d " | |
863 | "y:%d\n dst_rect:\nheight:%d width:%d x:%d " | |
864 | "y:%d\n", | |
865 | __func__, | |
866 | pipe_ctx->scl_data.viewport.height, | |
867 | pipe_ctx->scl_data.viewport.width, | |
868 | pipe_ctx->scl_data.viewport.x, | |
869 | pipe_ctx->scl_data.viewport.y, | |
870 | surface->dst_rect.height, | |
871 | surface->dst_rect.width, | |
872 | surface->dst_rect.x, | |
873 | surface->dst_rect.y); | |
874 | ||
875 | return res; | |
876 | } | |
877 | ||
878 | ||
879 | enum dc_status resource_build_scaling_params_for_context( | |
880 | const struct core_dc *dc, | |
881 | struct validate_context *context) | |
882 | { | |
883 | int i; | |
884 | ||
885 | for (i = 0; i < MAX_PIPES; i++) { | |
886 | if (context->res_ctx.pipe_ctx[i].surface != NULL && | |
887 | context->res_ctx.pipe_ctx[i].stream != NULL) | |
b2d0a103 | 888 | if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) |
f84a8161 | 889 | return DC_FAIL_SCALING; |
4562236b HW |
890 | } |
891 | ||
892 | return DC_OK; | |
893 | } | |
894 | ||
a2b8659d TC |
895 | struct pipe_ctx *find_idle_secondary_pipe( |
896 | struct resource_context *res_ctx, | |
897 | const struct resource_pool *pool) | |
4562236b HW |
898 | { |
899 | int i; | |
900 | struct pipe_ctx *secondary_pipe = NULL; | |
901 | ||
902 | /* | |
903 | * search backwards for the second pipe to keep pipe | |
904 | * assignment more consistent | |
905 | */ | |
906 | ||
a2b8659d | 907 | for (i = pool->pipe_count - 1; i >= 0; i--) { |
4562236b HW |
908 | if (res_ctx->pipe_ctx[i].stream == NULL) { |
909 | secondary_pipe = &res_ctx->pipe_ctx[i]; | |
910 | secondary_pipe->pipe_idx = i; | |
911 | break; | |
912 | } | |
913 | } | |
914 | ||
915 | ||
916 | return secondary_pipe; | |
917 | } | |
918 | ||
919 | struct pipe_ctx *resource_get_head_pipe_for_stream( | |
920 | struct resource_context *res_ctx, | |
921 | const struct core_stream *stream) | |
922 | { | |
923 | int i; | |
a2b8659d | 924 | for (i = 0; i < MAX_PIPES; i++) { |
4562236b | 925 | if (res_ctx->pipe_ctx[i].stream == stream && |
e73c1efc | 926 | res_ctx->pipe_ctx[i].stream_enc) { |
4562236b HW |
927 | return &res_ctx->pipe_ctx[i]; |
928 | break; | |
929 | } | |
930 | } | |
931 | return NULL; | |
932 | } | |
933 | ||
934 | /* | |
ab2541b6 AC |
935 | * A free_pipe for a stream is defined here as a pipe |
936 | * that has no surface attached yet | |
4562236b | 937 | */ |
ab2541b6 | 938 | static struct pipe_ctx *acquire_free_pipe_for_stream( |
745cc746 | 939 | struct validate_context *context, |
a2b8659d | 940 | const struct resource_pool *pool, |
ab2541b6 | 941 | const struct dc_stream *dc_stream) |
4562236b HW |
942 | { |
943 | int i; | |
745cc746 | 944 | struct resource_context *res_ctx = &context->res_ctx; |
ab2541b6 | 945 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); |
4562236b HW |
946 | |
947 | struct pipe_ctx *head_pipe = NULL; | |
948 | ||
949 | /* Find head pipe, which has the back end set up*/ | |
950 | ||
951 | head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); | |
952 | ||
953 | if (!head_pipe) | |
954 | ASSERT(0); | |
955 | ||
956 | if (!head_pipe->surface) | |
957 | return head_pipe; | |
958 | ||
959 | /* Re-use pipe already acquired for this stream if available*/ | |
a2b8659d | 960 | for (i = pool->pipe_count - 1; i >= 0; i--) { |
4562236b HW |
961 | if (res_ctx->pipe_ctx[i].stream == stream && |
962 | !res_ctx->pipe_ctx[i].surface) { | |
963 | return &res_ctx->pipe_ctx[i]; | |
964 | } | |
965 | } | |
966 | ||
967 | /* | |
968 | * At this point we have no re-useable pipe for this stream and we need | |
969 | * to acquire an idle one to satisfy the request | |
970 | */ | |
971 | ||
a2b8659d | 972 | if (!pool->funcs->acquire_idle_pipe_for_layer) |
4562236b HW |
973 | return NULL; |
974 | ||
a2b8659d | 975 | return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream); |
4562236b HW |
976 | |
977 | } | |
978 | ||
ab2541b6 | 979 | static void release_free_pipes_for_stream( |
4562236b | 980 | struct resource_context *res_ctx, |
ab2541b6 | 981 | const struct dc_stream *dc_stream) |
4562236b HW |
982 | { |
983 | int i; | |
ab2541b6 | 984 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); |
4562236b | 985 | |
a2b8659d | 986 | for (i = MAX_PIPES - 1; i >= 0; i--) { |
05a19c39 | 987 | /* never release the topmost pipe*/ |
4562236b | 988 | if (res_ctx->pipe_ctx[i].stream == stream && |
05a19c39 | 989 | res_ctx->pipe_ctx[i].top_pipe && |
4562236b | 990 | !res_ctx->pipe_ctx[i].surface) { |
05a19c39 | 991 | memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx)); |
4562236b HW |
992 | } |
993 | } | |
994 | } | |
995 | ||
0f9a536f DL |
996 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
997 | static int acquire_first_split_pipe( | |
998 | struct resource_context *res_ctx, | |
999 | const struct resource_pool *pool, | |
1000 | struct core_stream *stream) | |
1001 | { | |
1002 | int i; | |
1003 | ||
1004 | for (i = 0; i < pool->pipe_count; i++) { | |
1005 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; | |
1006 | ||
1007 | if (pipe_ctx->top_pipe && | |
1008 | pipe_ctx->top_pipe->surface == pipe_ctx->surface) { | |
0f9a536f DL |
1009 | pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; |
1010 | if (pipe_ctx->bottom_pipe) | |
1011 | pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; | |
1012 | ||
1013 | memset(pipe_ctx, 0, sizeof(*pipe_ctx)); | |
1014 | pipe_ctx->tg = pool->timing_generators[i]; | |
1015 | pipe_ctx->mi = pool->mis[i]; | |
1016 | pipe_ctx->ipp = pool->ipps[i]; | |
1017 | pipe_ctx->xfm = pool->transforms[i]; | |
1018 | pipe_ctx->opp = pool->opps[i]; | |
1019 | pipe_ctx->dis_clk = pool->display_clock; | |
f0558542 | 1020 | pipe_ctx->mpcc = pool->mpcc[i]; |
0f9a536f | 1021 | pipe_ctx->pipe_idx = i; |
0f9a536f DL |
1022 | |
1023 | pipe_ctx->stream = stream; | |
1024 | return i; | |
1025 | } | |
1026 | } | |
1027 | return -1; | |
1028 | } | |
1029 | #endif | |
1030 | ||
4562236b HW |
1031 | bool resource_attach_surfaces_to_context( |
1032 | const struct dc_surface * const *surfaces, | |
1033 | int surface_count, | |
ab2541b6 | 1034 | const struct dc_stream *dc_stream, |
a2b8659d TC |
1035 | struct validate_context *context, |
1036 | const struct resource_pool *pool) | |
4562236b HW |
1037 | { |
1038 | int i; | |
1039 | struct pipe_ctx *tail_pipe; | |
ab2541b6 | 1040 | struct dc_stream_status *stream_status = NULL; |
05a19c39 | 1041 | struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); |
4562236b HW |
1042 | |
1043 | ||
1044 | if (surface_count > MAX_SURFACE_NUM) { | |
1045 | dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n", | |
1046 | surface_count, MAX_SURFACE_NUM); | |
1047 | return false; | |
1048 | } | |
1049 | ||
ab2541b6 AC |
1050 | for (i = 0; i < context->stream_count; i++) |
1051 | if (&context->streams[i]->public == dc_stream) { | |
1052 | stream_status = &context->stream_status[i]; | |
4562236b HW |
1053 | break; |
1054 | } | |
ab2541b6 AC |
1055 | if (stream_status == NULL) { |
1056 | dm_error("Existing stream not found; failed to attach surfaces\n"); | |
4562236b HW |
1057 | return false; |
1058 | } | |
1059 | ||
1060 | /* retain new surfaces */ | |
1061 | for (i = 0; i < surface_count; i++) | |
1062 | dc_surface_retain(surfaces[i]); | |
1063 | ||
05a19c39 DL |
1064 | /* detach surfaces from pipes */ |
1065 | for (i = 0; i < pool->pipe_count; i++) | |
1066 | if (context->res_ctx.pipe_ctx[i].stream == stream) { | |
1067 | context->res_ctx.pipe_ctx[i].surface = NULL; | |
1068 | context->res_ctx.pipe_ctx[i].bottom_pipe = NULL; | |
1069 | } | |
4562236b HW |
1070 | |
1071 | /* release existing surfaces*/ | |
ab2541b6 AC |
1072 | for (i = 0; i < stream_status->surface_count; i++) |
1073 | dc_surface_release(stream_status->surfaces[i]); | |
4562236b | 1074 | |
ab2541b6 AC |
1075 | for (i = surface_count; i < stream_status->surface_count; i++) |
1076 | stream_status->surfaces[i] = NULL; | |
4562236b | 1077 | |
4562236b HW |
1078 | tail_pipe = NULL; |
1079 | for (i = 0; i < surface_count; i++) { | |
1080 | struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); | |
a2b8659d TC |
1081 | struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( |
1082 | context, pool, dc_stream); | |
4562236b | 1083 | |
0f9a536f DL |
1084 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1085 | if (!free_pipe) { | |
1086 | int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); | |
1087 | if (pipe_idx >= 0) | |
1088 | free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; | |
1089 | } | |
1090 | #endif | |
4562236b | 1091 | if (!free_pipe) { |
ab2541b6 | 1092 | stream_status->surfaces[i] = NULL; |
4562236b HW |
1093 | return false; |
1094 | } | |
1095 | ||
1096 | free_pipe->surface = surface; | |
1097 | ||
1098 | if (tail_pipe) { | |
1099 | free_pipe->top_pipe = tail_pipe; | |
1100 | tail_pipe->bottom_pipe = free_pipe; | |
1101 | } | |
1102 | ||
1103 | tail_pipe = free_pipe; | |
1104 | } | |
1105 | ||
ab2541b6 | 1106 | release_free_pipes_for_stream(&context->res_ctx, dc_stream); |
4562236b HW |
1107 | |
1108 | /* assign new surfaces*/ | |
1109 | for (i = 0; i < surface_count; i++) | |
ab2541b6 | 1110 | stream_status->surfaces[i] = surfaces[i]; |
4562236b | 1111 | |
ab2541b6 | 1112 | stream_status->surface_count = surface_count; |
4562236b HW |
1113 | |
1114 | return true; | |
1115 | } | |
1116 | ||
1117 | ||
1118 | static bool is_timing_changed(const struct core_stream *cur_stream, | |
1119 | const struct core_stream *new_stream) | |
1120 | { | |
1121 | if (cur_stream == NULL) | |
1122 | return true; | |
1123 | ||
1124 | /* If sink pointer changed, it means this is a hotplug, we should do | |
1125 | * full hw setting. | |
1126 | */ | |
1127 | if (cur_stream->sink != new_stream->sink) | |
1128 | return true; | |
1129 | ||
1130 | /* If output color space is changed, need to reprogram info frames */ | |
1131 | if (cur_stream->public.output_color_space != | |
1132 | new_stream->public.output_color_space) | |
1133 | return true; | |
1134 | ||
1135 | return memcmp( | |
1136 | &cur_stream->public.timing, | |
1137 | &new_stream->public.timing, | |
1138 | sizeof(struct dc_crtc_timing)) != 0; | |
1139 | } | |
1140 | ||
1141 | static bool are_stream_backends_same( | |
1142 | const struct core_stream *stream_a, const struct core_stream *stream_b) | |
1143 | { | |
1144 | if (stream_a == stream_b) | |
1145 | return true; | |
1146 | ||
1147 | if (stream_a == NULL || stream_b == NULL) | |
1148 | return false; | |
1149 | ||
1150 | if (is_timing_changed(stream_a, stream_b)) | |
1151 | return false; | |
1152 | ||
1153 | return true; | |
1154 | } | |
1155 | ||
ab2541b6 AC |
1156 | bool is_stream_unchanged( |
1157 | const struct core_stream *old_stream, const struct core_stream *stream) | |
4562236b | 1158 | { |
4562236b | 1159 | |
ab2541b6 AC |
1160 | if (!are_stream_backends_same(old_stream, stream)) |
1161 | return false; | |
4562236b HW |
1162 | |
1163 | return true; | |
1164 | } | |
1165 | ||
1166 | bool resource_validate_attach_surfaces( | |
1167 | const struct dc_validation_set set[], | |
1168 | int set_count, | |
1169 | const struct validate_context *old_context, | |
a2b8659d TC |
1170 | struct validate_context *context, |
1171 | const struct resource_pool *pool) | |
4562236b HW |
1172 | { |
1173 | int i, j; | |
1174 | ||
1175 | for (i = 0; i < set_count; i++) { | |
430ef426 | 1176 | for (j = 0; old_context && j < old_context->stream_count; j++) |
ab2541b6 AC |
1177 | if (is_stream_unchanged( |
1178 | old_context->streams[j], | |
1179 | context->streams[i])) { | |
4562236b | 1180 | if (!resource_attach_surfaces_to_context( |
ab2541b6 AC |
1181 | old_context->stream_status[j].surfaces, |
1182 | old_context->stream_status[j].surface_count, | |
1183 | &context->streams[i]->public, | |
a2b8659d | 1184 | context, pool)) |
4562236b | 1185 | return false; |
ab2541b6 | 1186 | context->stream_status[i] = old_context->stream_status[j]; |
4562236b HW |
1187 | } |
1188 | if (set[i].surface_count != 0) | |
1189 | if (!resource_attach_surfaces_to_context( | |
1190 | set[i].surfaces, | |
1191 | set[i].surface_count, | |
ab2541b6 | 1192 | &context->streams[i]->public, |
a2b8659d | 1193 | context, pool)) |
4562236b HW |
1194 | return false; |
1195 | ||
1196 | } | |
1197 | ||
1198 | return true; | |
1199 | } | |
1200 | ||
1201 | /* Maximum TMDS single link pixel clock 165MHz */ | |
1202 | #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 | |
909e8c9e | 1203 | #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 |
4562236b HW |
1204 | |
1205 | static void set_stream_engine_in_use( | |
1206 | struct resource_context *res_ctx, | |
a2b8659d | 1207 | const struct resource_pool *pool, |
4562236b HW |
1208 | struct stream_encoder *stream_enc) |
1209 | { | |
1210 | int i; | |
1211 | ||
a2b8659d TC |
1212 | for (i = 0; i < pool->stream_enc_count; i++) { |
1213 | if (pool->stream_enc[i] == stream_enc) | |
4562236b HW |
1214 | res_ctx->is_stream_enc_acquired[i] = true; |
1215 | } | |
1216 | } | |
1217 | ||
1218 | /* TODO: release audio object */ | |
1219 | static void set_audio_in_use( | |
1220 | struct resource_context *res_ctx, | |
a2b8659d | 1221 | const struct resource_pool *pool, |
4562236b HW |
1222 | struct audio *audio) |
1223 | { | |
1224 | int i; | |
a2b8659d TC |
1225 | for (i = 0; i < pool->audio_count; i++) { |
1226 | if (pool->audios[i] == audio) | |
4562236b | 1227 | res_ctx->is_audio_acquired[i] = true; |
4562236b HW |
1228 | } |
1229 | } | |
1230 | ||
1231 | static int acquire_first_free_pipe( | |
1232 | struct resource_context *res_ctx, | |
a2b8659d | 1233 | const struct resource_pool *pool, |
4562236b HW |
1234 | struct core_stream *stream) |
1235 | { | |
1236 | int i; | |
1237 | ||
a2b8659d | 1238 | for (i = 0; i < pool->pipe_count; i++) { |
4562236b HW |
1239 | if (!res_ctx->pipe_ctx[i].stream) { |
1240 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; | |
1241 | ||
f0558542 DL |
1242 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1243 | pipe_ctx->mpcc = pool->mpcc[i]; | |
1244 | #endif | |
a2b8659d TC |
1245 | pipe_ctx->tg = pool->timing_generators[i]; |
1246 | pipe_ctx->mi = pool->mis[i]; | |
1247 | pipe_ctx->ipp = pool->ipps[i]; | |
1248 | pipe_ctx->xfm = pool->transforms[i]; | |
1249 | pipe_ctx->opp = pool->opps[i]; | |
1250 | pipe_ctx->dis_clk = pool->display_clock; | |
4562236b HW |
1251 | pipe_ctx->pipe_idx = i; |
1252 | ||
ff5ef992 | 1253 | |
4562236b HW |
1254 | pipe_ctx->stream = stream; |
1255 | return i; | |
1256 | } | |
1257 | } | |
1258 | return -1; | |
1259 | } | |
1260 | ||
1261 | static struct stream_encoder *find_first_free_match_stream_enc_for_link( | |
1262 | struct resource_context *res_ctx, | |
a2b8659d | 1263 | const struct resource_pool *pool, |
4562236b HW |
1264 | struct core_stream *stream) |
1265 | { | |
1266 | int i; | |
1267 | int j = -1; | |
1268 | struct core_link *link = stream->sink->link; | |
1269 | ||
a2b8659d | 1270 | for (i = 0; i < pool->stream_enc_count; i++) { |
4562236b | 1271 | if (!res_ctx->is_stream_enc_acquired[i] && |
a2b8659d | 1272 | pool->stream_enc[i]) { |
4562236b HW |
1273 | /* Store first available for MST second display |
1274 | * in daisy chain use case */ | |
1275 | j = i; | |
a2b8659d | 1276 | if (pool->stream_enc[i]->id == |
4562236b | 1277 | link->link_enc->preferred_engine) |
a2b8659d | 1278 | return pool->stream_enc[i]; |
4562236b HW |
1279 | } |
1280 | } | |
1281 | ||
1282 | /* | |
1283 | * below can happen in cases when stream encoder is acquired: | |
1284 | * 1) for second MST display in chain, so preferred engine already | |
1285 | * acquired; | |
1286 | * 2) for another link, which preferred engine already acquired by any | |
1287 | * MST configuration. | |
1288 | * | |
1289 | * If signal is of DP type and preferred engine not found, return last available | |
1290 | * | |
1291 | * TODO - This is just a patch up and a generic solution is | |
1292 | * required for non DP connectors. | |
1293 | */ | |
1294 | ||
1295 | if (j >= 0 && dc_is_dp_signal(stream->signal)) | |
a2b8659d | 1296 | return pool->stream_enc[j]; |
4562236b HW |
1297 | |
1298 | return NULL; | |
1299 | } | |
1300 | ||
a2b8659d TC |
1301 | static struct audio *find_first_free_audio( |
1302 | struct resource_context *res_ctx, | |
1303 | const struct resource_pool *pool) | |
4562236b HW |
1304 | { |
1305 | int i; | |
a2b8659d | 1306 | for (i = 0; i < pool->audio_count; i++) { |
4562236b | 1307 | if (res_ctx->is_audio_acquired[i] == false) { |
a2b8659d | 1308 | return pool->audios[i]; |
4562236b HW |
1309 | } |
1310 | } | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | static void update_stream_signal(struct core_stream *stream) | |
1316 | { | |
8b32076c ST |
1317 | if (stream->public.output_signal == SIGNAL_TYPE_NONE) { |
1318 | const struct dc_sink *dc_sink = stream->public.sink; | |
1319 | ||
1320 | if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) | |
1321 | stream->signal = | |
1322 | stream->sink->link-> | |
1323 | public.connector_signal; | |
4562236b | 1324 | else |
8b32076c ST |
1325 | stream->signal = dc_sink->sink_signal; |
1326 | } else { | |
1327 | stream->signal = stream->public.output_signal; | |
1328 | } | |
1329 | ||
56dcade3 | 1330 | if (dc_is_dvi_signal(stream->signal)) { |
909e8c9e CL |
1331 | if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && |
1332 | stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) | |
56dcade3 HW |
1333 | stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; |
1334 | else | |
1335 | stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
1336 | } | |
4562236b HW |
1337 | } |
1338 | ||
1339 | bool resource_is_stream_unchanged( | |
ab2541b6 | 1340 | const struct validate_context *old_context, const struct core_stream *stream) |
4562236b | 1341 | { |
ab2541b6 | 1342 | int i; |
4562236b | 1343 | |
ab2541b6 AC |
1344 | for (i = 0; i < old_context->stream_count; i++) { |
1345 | const struct core_stream *old_stream = old_context->streams[i]; | |
4562236b | 1346 | |
ab2541b6 | 1347 | if (are_stream_backends_same(old_stream, stream)) |
4562236b | 1348 | return true; |
4562236b HW |
1349 | } |
1350 | ||
1351 | return false; | |
1352 | } | |
1353 | ||
1354 | static void copy_pipe_ctx( | |
1355 | const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) | |
1356 | { | |
1357 | struct core_surface *surface = to_pipe_ctx->surface; | |
1358 | struct core_stream *stream = to_pipe_ctx->stream; | |
1359 | ||
1360 | *to_pipe_ctx = *from_pipe_ctx; | |
1361 | to_pipe_ctx->stream = stream; | |
1362 | if (surface != NULL) | |
1363 | to_pipe_ctx->surface = surface; | |
1364 | } | |
1365 | ||
1366 | static struct core_stream *find_pll_sharable_stream( | |
1367 | const struct core_stream *stream_needs_pll, | |
1368 | struct validate_context *context) | |
1369 | { | |
ab2541b6 | 1370 | int i; |
4562236b | 1371 | |
ab2541b6 AC |
1372 | for (i = 0; i < context->stream_count; i++) { |
1373 | struct core_stream *stream_has_pll = context->streams[i]; | |
4562236b | 1374 | |
ab2541b6 AC |
1375 | /* We are looking for non dp, non virtual stream */ |
1376 | if (resource_are_streams_timing_synchronizable( | |
1377 | stream_needs_pll, stream_has_pll) | |
1378 | && !dc_is_dp_signal(stream_has_pll->signal) | |
1379 | && stream_has_pll->sink->link->public.connector_signal | |
1380 | != SIGNAL_TYPE_VIRTUAL) | |
1381 | return stream_has_pll; | |
4562236b | 1382 | |
4562236b HW |
1383 | } |
1384 | ||
1385 | return NULL; | |
1386 | } | |
1387 | ||
1388 | static int get_norm_pix_clk(const struct dc_crtc_timing *timing) | |
1389 | { | |
1390 | uint32_t pix_clk = timing->pix_clk_khz; | |
1391 | uint32_t normalized_pix_clk = pix_clk; | |
1392 | ||
1393 | if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
1394 | pix_clk /= 2; | |
cc4d99b8 CL |
1395 | if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { |
1396 | switch (timing->display_color_depth) { | |
1397 | case COLOR_DEPTH_888: | |
1398 | normalized_pix_clk = pix_clk; | |
1399 | break; | |
1400 | case COLOR_DEPTH_101010: | |
1401 | normalized_pix_clk = (pix_clk * 30) / 24; | |
1402 | break; | |
1403 | case COLOR_DEPTH_121212: | |
1404 | normalized_pix_clk = (pix_clk * 36) / 24; | |
4562236b | 1405 | break; |
cc4d99b8 CL |
1406 | case COLOR_DEPTH_161616: |
1407 | normalized_pix_clk = (pix_clk * 48) / 24; | |
4562236b | 1408 | break; |
cc4d99b8 CL |
1409 | default: |
1410 | ASSERT(0); | |
4562236b | 1411 | break; |
cc4d99b8 | 1412 | } |
4562236b | 1413 | } |
4562236b HW |
1414 | return normalized_pix_clk; |
1415 | } | |
1416 | ||
430ef426 | 1417 | static void calculate_phy_pix_clks(struct validate_context *context) |
4562236b | 1418 | { |
ab2541b6 | 1419 | int i; |
4562236b | 1420 | |
ab2541b6 AC |
1421 | for (i = 0; i < context->stream_count; i++) { |
1422 | struct core_stream *stream = context->streams[i]; | |
4562236b | 1423 | |
ab2541b6 | 1424 | update_stream_signal(stream); |
4562236b | 1425 | |
ab2541b6 AC |
1426 | /* update actual pixel clock on all streams */ |
1427 | if (dc_is_hdmi_signal(stream->signal)) | |
1428 | stream->phy_pix_clk = get_norm_pix_clk( | |
1429 | &stream->public.timing); | |
1430 | else | |
1431 | stream->phy_pix_clk = | |
1432 | stream->public.timing.pix_clk_khz; | |
4562236b HW |
1433 | } |
1434 | } | |
1435 | ||
1436 | enum dc_status resource_map_pool_resources( | |
1437 | const struct core_dc *dc, | |
430ef426 DL |
1438 | struct validate_context *context, |
1439 | struct validate_context *old_context) | |
4562236b | 1440 | { |
a2b8659d | 1441 | const struct resource_pool *pool = dc->res_pool; |
ab2541b6 | 1442 | int i, j; |
4562236b | 1443 | |
430ef426 | 1444 | calculate_phy_pix_clks(context); |
4562236b | 1445 | |
430ef426 | 1446 | for (i = 0; old_context && i < context->stream_count; i++) { |
ab2541b6 | 1447 | struct core_stream *stream = context->streams[i]; |
4562236b | 1448 | |
430ef426 DL |
1449 | if (!resource_is_stream_unchanged(old_context, stream)) { |
1450 | if (stream != NULL && old_context->streams[i] != NULL) { | |
4b679bc3 | 1451 | stream->bit_depth_params = |
430ef426 DL |
1452 | old_context->streams[i]->bit_depth_params; |
1453 | stream->clamping = old_context->streams[i]->clamping; | |
a2b8659d TC |
1454 | continue; |
1455 | } | |
4b679bc3 | 1456 | } |
7e2fe319 | 1457 | |
ab2541b6 | 1458 | /* mark resources used for stream that is already active */ |
a2b8659d | 1459 | for (j = 0; j < pool->pipe_count; j++) { |
ab2541b6 AC |
1460 | struct pipe_ctx *pipe_ctx = |
1461 | &context->res_ctx.pipe_ctx[j]; | |
1462 | const struct pipe_ctx *old_pipe_ctx = | |
430ef426 | 1463 | &old_context->res_ctx.pipe_ctx[j]; |
4562236b | 1464 | |
ab2541b6 AC |
1465 | if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) |
1466 | continue; | |
8c737fcc | 1467 | |
268cadbd YS |
1468 | if (old_pipe_ctx->top_pipe) |
1469 | continue; | |
1470 | ||
ab2541b6 AC |
1471 | pipe_ctx->stream = stream; |
1472 | copy_pipe_ctx(old_pipe_ctx, pipe_ctx); | |
4562236b | 1473 | |
ab2541b6 AC |
1474 | /* Split pipe resource, do not acquire back end */ |
1475 | if (!pipe_ctx->stream_enc) | |
1476 | continue; | |
4562236b | 1477 | |
ab2541b6 | 1478 | set_stream_engine_in_use( |
a2b8659d | 1479 | &context->res_ctx, pool, |
ab2541b6 AC |
1480 | pipe_ctx->stream_enc); |
1481 | ||
1482 | /* Switch to dp clock source only if there is | |
1483 | * no non dp stream that shares the same timing | |
1484 | * with the dp stream. | |
1485 | */ | |
1486 | if (dc_is_dp_signal(pipe_ctx->stream->signal) && | |
1487 | !find_pll_sharable_stream(stream, context)) | |
a2b8659d | 1488 | pipe_ctx->clock_source = pool->dp_clock_source; |
ab2541b6 AC |
1489 | |
1490 | resource_reference_clock_source( | |
a2b8659d | 1491 | &context->res_ctx, pool, |
ab2541b6 AC |
1492 | pipe_ctx->clock_source); |
1493 | ||
a2b8659d TC |
1494 | set_audio_in_use(&context->res_ctx, pool, |
1495 | pipe_ctx->audio); | |
4562236b HW |
1496 | } |
1497 | } | |
1498 | ||
ab2541b6 AC |
1499 | for (i = 0; i < context->stream_count; i++) { |
1500 | struct core_stream *stream = context->streams[i]; | |
1501 | struct pipe_ctx *pipe_ctx = NULL; | |
1502 | int pipe_idx = -1; | |
4562236b | 1503 | |
430ef426 | 1504 | if (old_context && resource_is_stream_unchanged(old_context, stream)) |
ab2541b6 AC |
1505 | continue; |
1506 | /* acquire new resources */ | |
5d11e9fc DL |
1507 | pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); |
1508 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | |
1509 | if (pipe_idx < 0) | |
1510 | acquire_first_split_pipe(&context->res_ctx, pool, stream); | |
1511 | #endif | |
ab2541b6 AC |
1512 | if (pipe_idx < 0) |
1513 | return DC_NO_CONTROLLER_RESOURCE; | |
1514 | ||
ab2541b6 AC |
1515 | pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; |
1516 | ||
1517 | pipe_ctx->stream_enc = | |
1518 | find_first_free_match_stream_enc_for_link( | |
a2b8659d | 1519 | &context->res_ctx, pool, stream); |
ab2541b6 AC |
1520 | |
1521 | if (!pipe_ctx->stream_enc) | |
1522 | return DC_NO_STREAM_ENG_RESOURCE; | |
1523 | ||
1524 | set_stream_engine_in_use( | |
a2b8659d | 1525 | &context->res_ctx, pool, |
ab2541b6 AC |
1526 | pipe_ctx->stream_enc); |
1527 | ||
1528 | /* TODO: Add check if ASIC support and EDID audio */ | |
4a9a5d62 | 1529 | if (!stream->sink->public.converter_disable_audio && |
ab2541b6 AC |
1530 | dc_is_audio_capable_signal(pipe_ctx->stream->signal) && |
1531 | stream->public.audio_info.mode_count) { | |
1532 | pipe_ctx->audio = find_first_free_audio( | |
a2b8659d | 1533 | &context->res_ctx, pool); |
ab2541b6 AC |
1534 | |
1535 | /* | |
1536 | * Audio assigned in order first come first get. | |
1537 | * There are asics which has number of audio | |
1538 | * resources less then number of pipes | |
1539 | */ | |
1540 | if (pipe_ctx->audio) | |
1541 | set_audio_in_use( | |
a2b8659d | 1542 | &context->res_ctx, pool, |
ab2541b6 | 1543 | pipe_ctx->audio); |
4562236b | 1544 | } |
ab2541b6 AC |
1545 | |
1546 | context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst; | |
4562236b HW |
1547 | } |
1548 | ||
1549 | return DC_OK; | |
1550 | } | |
1551 | ||
ab2541b6 AC |
1552 | /* first stream in the context is used to populate the rest */ |
1553 | void validate_guaranteed_copy_streams( | |
4562236b | 1554 | struct validate_context *context, |
ab2541b6 | 1555 | int max_streams) |
4562236b HW |
1556 | { |
1557 | int i; | |
1558 | ||
ab2541b6 AC |
1559 | for (i = 1; i < max_streams; i++) { |
1560 | context->streams[i] = context->streams[0]; | |
4562236b HW |
1561 | |
1562 | copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], | |
1563 | &context->res_ctx.pipe_ctx[i]); | |
1564 | context->res_ctx.pipe_ctx[i].stream = | |
1565 | context->res_ctx.pipe_ctx[0].stream; | |
1566 | ||
ab2541b6 AC |
1567 | dc_stream_retain(&context->streams[i]->public); |
1568 | context->stream_count++; | |
4562236b HW |
1569 | } |
1570 | } | |
1571 | ||
6e4d6bee TC |
1572 | static void patch_gamut_packet_checksum( |
1573 | struct encoder_info_packet *gamut_packet) | |
4562236b | 1574 | { |
4562236b | 1575 | /* For gamut we recalc checksum */ |
6e4d6bee | 1576 | if (gamut_packet->valid) { |
4562236b HW |
1577 | uint8_t chk_sum = 0; |
1578 | uint8_t *ptr; | |
1579 | uint8_t i; | |
1580 | ||
4562236b | 1581 | /*start of the Gamut data. */ |
6e4d6bee | 1582 | ptr = &gamut_packet->sb[3]; |
4562236b | 1583 | |
6e4d6bee | 1584 | for (i = 0; i <= gamut_packet->sb[1]; i++) |
4562236b HW |
1585 | chk_sum += ptr[i]; |
1586 | ||
6e4d6bee | 1587 | gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); |
1646a6fe | 1588 | } |
4562236b HW |
1589 | } |
1590 | ||
1591 | static void set_avi_info_frame( | |
6e4d6bee | 1592 | struct encoder_info_packet *info_packet, |
4562236b HW |
1593 | struct pipe_ctx *pipe_ctx) |
1594 | { | |
1595 | struct core_stream *stream = pipe_ctx->stream; | |
1596 | enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; | |
1597 | struct info_frame info_frame = { {0} }; | |
1598 | uint32_t pixel_encoding = 0; | |
1599 | enum scanning_type scan_type = SCANNING_TYPE_NODATA; | |
1600 | enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; | |
1601 | bool itc = false; | |
1602 | uint8_t cn0_cn1 = 0; | |
1603 | uint8_t *check_sum = NULL; | |
1604 | uint8_t byte_index = 0; | |
e8d726b7 | 1605 | union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; |
4562236b | 1606 | |
4562236b | 1607 | color_space = pipe_ctx->stream->public.output_color_space; |
e5f2038e CL |
1608 | if (color_space == COLOR_SPACE_UNKNOWN) |
1609 | color_space = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_RGB)? | |
1610 | COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; | |
4562236b HW |
1611 | |
1612 | /* Initialize header */ | |
e8d726b7 | 1613 | hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; |
4562236b HW |
1614 | /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall |
1615 | * not be used in HDMI 2.0 (Section 10.1) */ | |
e8d726b7 RA |
1616 | hdmi_info->bits.header.version = 2; |
1617 | hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE; | |
4562236b HW |
1618 | |
1619 | /* | |
1620 | * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built | |
1621 | * according to HDMI 2.0 spec (Section 10.1) | |
1622 | */ | |
1623 | ||
1624 | switch (stream->public.timing.pixel_encoding) { | |
1625 | case PIXEL_ENCODING_YCBCR422: | |
1626 | pixel_encoding = 1; | |
1627 | break; | |
1628 | ||
1629 | case PIXEL_ENCODING_YCBCR444: | |
1630 | pixel_encoding = 2; | |
1631 | break; | |
1632 | case PIXEL_ENCODING_YCBCR420: | |
1633 | pixel_encoding = 3; | |
1634 | break; | |
1635 | ||
1636 | case PIXEL_ENCODING_RGB: | |
1637 | default: | |
1638 | pixel_encoding = 0; | |
1639 | } | |
1640 | ||
1641 | /* Y0_Y1_Y2 : The pixel encoding */ | |
1642 | /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ | |
e8d726b7 | 1643 | hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding; |
4562236b HW |
1644 | |
1645 | /* A0 = 1 Active Format Information valid */ | |
e8d726b7 | 1646 | hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID; |
4562236b HW |
1647 | |
1648 | /* B0, B1 = 3; Bar info data is valid */ | |
e8d726b7 | 1649 | hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID; |
4562236b | 1650 | |
e8d726b7 | 1651 | hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; |
4562236b HW |
1652 | |
1653 | /* S0, S1 : Underscan / Overscan */ | |
1654 | /* TODO: un-hardcode scan type */ | |
1655 | scan_type = SCANNING_TYPE_UNDERSCAN; | |
e8d726b7 | 1656 | hdmi_info->bits.S0_S1 = scan_type; |
4562236b HW |
1657 | |
1658 | /* C0, C1 : Colorimetry */ | |
8fde5884 CL |
1659 | if (color_space == COLOR_SPACE_YCBCR709 || |
1660 | color_space == COLOR_SPACE_YCBCR709_LIMITED) | |
e8d726b7 | 1661 | hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709; |
8fde5884 CL |
1662 | else if (color_space == COLOR_SPACE_YCBCR601 || |
1663 | color_space == COLOR_SPACE_YCBCR601_LIMITED) | |
e8d726b7 | 1664 | hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601; |
8fde5884 CL |
1665 | else { |
1666 | if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB) | |
1667 | BREAK_TO_DEBUGGER(); | |
e8d726b7 | 1668 | hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA; |
8fde5884 | 1669 | } |
534db198 | 1670 | if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || |
8fde5884 CL |
1671 | color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || |
1672 | color_space == COLOR_SPACE_2020_YCBCR) { | |
e8d726b7 RA |
1673 | hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; |
1674 | hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED; | |
534db198 | 1675 | } else if (color_space == COLOR_SPACE_ADOBERGB) { |
e8d726b7 RA |
1676 | hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; |
1677 | hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED; | |
534db198 AZ |
1678 | } |
1679 | ||
4562236b HW |
1680 | /* TODO: un-hardcode aspect ratio */ |
1681 | aspect = stream->public.timing.aspect_ratio; | |
1682 | ||
1683 | switch (aspect) { | |
1684 | case ASPECT_RATIO_4_3: | |
1685 | case ASPECT_RATIO_16_9: | |
e8d726b7 | 1686 | hdmi_info->bits.M0_M1 = aspect; |
4562236b HW |
1687 | break; |
1688 | ||
1689 | case ASPECT_RATIO_NO_DATA: | |
1690 | case ASPECT_RATIO_64_27: | |
1691 | case ASPECT_RATIO_256_135: | |
1692 | default: | |
e8d726b7 | 1693 | hdmi_info->bits.M0_M1 = 0; |
4562236b HW |
1694 | } |
1695 | ||
1696 | /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ | |
e8d726b7 | 1697 | hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; |
4562236b HW |
1698 | |
1699 | /* TODO: un-hardcode cn0_cn1 and itc */ | |
1700 | cn0_cn1 = 0; | |
1701 | itc = false; | |
1702 | ||
1703 | if (itc) { | |
e8d726b7 RA |
1704 | hdmi_info->bits.ITC = 1; |
1705 | hdmi_info->bits.CN0_CN1 = cn0_cn1; | |
4562236b HW |
1706 | } |
1707 | ||
1708 | /* TODO : We should handle YCC quantization */ | |
1709 | /* but we do not have matrix calculation */ | |
1710 | if (color_space == COLOR_SPACE_SRGB) { | |
e8d726b7 RA |
1711 | hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; |
1712 | hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE; | |
4562236b | 1713 | } else if (color_space == COLOR_SPACE_SRGB_LIMITED) { |
e8d726b7 RA |
1714 | hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; |
1715 | hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; | |
4562236b | 1716 | } else { |
e8d726b7 RA |
1717 | hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; |
1718 | hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; | |
4562236b HW |
1719 | } |
1720 | ||
e8d726b7 | 1721 | hdmi_info->bits.VIC0_VIC7 = |
4562236b HW |
1722 | stream->public.timing.vic; |
1723 | ||
1724 | /* pixel repetition | |
1725 | * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel | |
1726 | * repetition start from 1 */ | |
e8d726b7 | 1727 | hdmi_info->bits.PR0_PR3 = 0; |
4562236b HW |
1728 | |
1729 | /* Bar Info | |
1730 | * barTop: Line Number of End of Top Bar. | |
1731 | * barBottom: Line Number of Start of Bottom Bar. | |
1732 | * barLeft: Pixel Number of End of Left Bar. | |
1733 | * barRight: Pixel Number of Start of Right Bar. */ | |
e8d726b7 RA |
1734 | hdmi_info->bits.bar_top = stream->public.timing.v_border_top; |
1735 | hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top | |
4562236b | 1736 | - stream->public.timing.v_border_bottom + 1); |
e8d726b7 RA |
1737 | hdmi_info->bits.bar_left = stream->public.timing.h_border_left; |
1738 | hdmi_info->bits.bar_right = (stream->public.timing.h_total | |
4562236b HW |
1739 | - stream->public.timing.h_border_right + 1); |
1740 | ||
1741 | /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ | |
e8d726b7 RA |
1742 | check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0]; |
1743 | ||
3e183c5f | 1744 | *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2; |
4562236b | 1745 | |
3e183c5f | 1746 | for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++) |
e8d726b7 | 1747 | *check_sum += hdmi_info->packet_raw_data.sb[byte_index]; |
4562236b HW |
1748 | |
1749 | /* one byte complement */ | |
1750 | *check_sum = (uint8_t) (0x100 - *check_sum); | |
1751 | ||
1752 | /* Store in hw_path_mode */ | |
e8d726b7 RA |
1753 | info_packet->hb0 = hdmi_info->packet_raw_data.hb0; |
1754 | info_packet->hb1 = hdmi_info->packet_raw_data.hb1; | |
1755 | info_packet->hb2 = hdmi_info->packet_raw_data.hb2; | |
4562236b | 1756 | |
e66e4d64 HW |
1757 | for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet. |
1758 | info_packet_hdmi.packet_raw_data.sb); byte_index++) | |
4562236b | 1759 | info_packet->sb[byte_index] = info_frame.avi_info_packet. |
e66e4d64 | 1760 | info_packet_hdmi.packet_raw_data.sb[byte_index]; |
4562236b HW |
1761 | |
1762 | info_packet->valid = true; | |
1763 | } | |
1764 | ||
6e4d6bee TC |
1765 | static void set_vendor_info_packet( |
1766 | struct encoder_info_packet *info_packet, | |
1767 | struct core_stream *stream) | |
4562236b HW |
1768 | { |
1769 | uint32_t length = 0; | |
1770 | bool hdmi_vic_mode = false; | |
1771 | uint8_t checksum = 0; | |
1772 | uint32_t i = 0; | |
1773 | enum dc_timing_3d_format format; | |
1774 | ||
4562236b | 1775 | format = stream->public.timing.timing_3d_format; |
7f5c22d1 VP |
1776 | if (stream->public.view_format == VIEW_3D_FORMAT_NONE) |
1777 | format = TIMING_3D_FORMAT_NONE; | |
4562236b HW |
1778 | |
1779 | /* Can be different depending on packet content */ | |
1780 | length = 5; | |
1781 | ||
1782 | if (stream->public.timing.hdmi_vic != 0 | |
1783 | && stream->public.timing.h_total >= 3840 | |
1784 | && stream->public.timing.v_total >= 2160) | |
1785 | hdmi_vic_mode = true; | |
1786 | ||
1787 | /* According to HDMI 1.4a CTS, VSIF should be sent | |
1788 | * for both 3D stereo and HDMI VIC modes. | |
1789 | * For all other modes, there is no VSIF sent. */ | |
1790 | ||
1791 | if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode) | |
1792 | return; | |
1793 | ||
1794 | /* 24bit IEEE Registration identifier (0x000c03). LSB first. */ | |
1795 | info_packet->sb[1] = 0x03; | |
1796 | info_packet->sb[2] = 0x0C; | |
1797 | info_packet->sb[3] = 0x00; | |
1798 | ||
1799 | /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format. | |
1800 | * The value for HDMI_Video_Format are: | |
1801 | * 0x0 (0b000) - No additional HDMI video format is presented in this | |
1802 | * packet | |
1803 | * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC | |
1804 | * parameter follows | |
1805 | * 0x2 (0b010) - 3D format indication present. 3D_Structure and | |
1806 | * potentially 3D_Ext_Data follows | |
1807 | * 0x3..0x7 (0b011..0b111) - reserved for future use */ | |
1808 | if (format != TIMING_3D_FORMAT_NONE) | |
1809 | info_packet->sb[4] = (2 << 5); | |
1810 | else if (hdmi_vic_mode) | |
1811 | info_packet->sb[4] = (1 << 5); | |
1812 | ||
1813 | /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2): | |
1814 | * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure. | |
1815 | * The value for 3D_Structure are: | |
1816 | * 0x0 - Frame Packing | |
1817 | * 0x1 - Field Alternative | |
1818 | * 0x2 - Line Alternative | |
1819 | * 0x3 - Side-by-Side (full) | |
1820 | * 0x4 - L + depth | |
1821 | * 0x5 - L + depth + graphics + graphics-depth | |
1822 | * 0x6 - Top-and-Bottom | |
1823 | * 0x7 - Reserved for future use | |
1824 | * 0x8 - Side-by-Side (Half) | |
1825 | * 0x9..0xE - Reserved for future use | |
1826 | * 0xF - Not used */ | |
1827 | switch (format) { | |
1828 | case TIMING_3D_FORMAT_HW_FRAME_PACKING: | |
1829 | case TIMING_3D_FORMAT_SW_FRAME_PACKING: | |
1830 | info_packet->sb[5] = (0x0 << 4); | |
1831 | break; | |
1832 | ||
1833 | case TIMING_3D_FORMAT_SIDE_BY_SIDE: | |
1834 | case TIMING_3D_FORMAT_SBS_SW_PACKED: | |
1835 | info_packet->sb[5] = (0x8 << 4); | |
1836 | length = 6; | |
1837 | break; | |
1838 | ||
1839 | case TIMING_3D_FORMAT_TOP_AND_BOTTOM: | |
1840 | case TIMING_3D_FORMAT_TB_SW_PACKED: | |
1841 | info_packet->sb[5] = (0x6 << 4); | |
1842 | break; | |
1843 | ||
1844 | default: | |
1845 | break; | |
1846 | } | |
1847 | ||
1848 | /*PB5: If PB4 is set to 0x1 (extended resolution format) | |
1849 | * fill PB5 with the correct HDMI VIC code */ | |
1850 | if (hdmi_vic_mode) | |
1851 | info_packet->sb[5] = stream->public.timing.hdmi_vic; | |
1852 | ||
1853 | /* Header */ | |
3e183c5f | 1854 | info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */ |
4562236b HW |
1855 | info_packet->hb1 = 0x01; /* Version */ |
1856 | ||
1857 | /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */ | |
1858 | info_packet->hb2 = (uint8_t) (length); | |
1859 | ||
1860 | /* Calculate checksum */ | |
1861 | checksum = 0; | |
1862 | checksum += info_packet->hb0; | |
1863 | checksum += info_packet->hb1; | |
1864 | checksum += info_packet->hb2; | |
1865 | ||
1866 | for (i = 1; i <= length; i++) | |
1867 | checksum += info_packet->sb[i]; | |
1868 | ||
1869 | info_packet->sb[0] = (uint8_t) (0x100 - checksum); | |
1870 | ||
1871 | info_packet->valid = true; | |
1872 | } | |
1873 | ||
6e4d6bee TC |
1874 | static void set_spd_info_packet( |
1875 | struct encoder_info_packet *info_packet, | |
1876 | struct core_stream *stream) | |
4562236b HW |
1877 | { |
1878 | /* SPD info packet for FreeSync */ | |
1879 | ||
1880 | unsigned char checksum = 0; | |
1881 | unsigned int idx, payload_size = 0; | |
1882 | ||
1883 | /* Check if Freesync is supported. Return if false. If true, | |
1884 | * set the corresponding bit in the info packet | |
1885 | */ | |
1886 | if (stream->public.freesync_ctx.supported == false) | |
1887 | return; | |
1888 | ||
1889 | if (dc_is_hdmi_signal(stream->signal)) { | |
1890 | ||
1891 | /* HEADER */ | |
1892 | ||
1893 | /* HB0 = Packet Type = 0x83 (Source Product | |
1894 | * Descriptor InfoFrame) | |
1895 | */ | |
3e183c5f | 1896 | info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD; |
4562236b HW |
1897 | |
1898 | /* HB1 = Version = 0x01 */ | |
1899 | info_packet->hb1 = 0x01; | |
1900 | ||
1901 | /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */ | |
1902 | info_packet->hb2 = 0x08; | |
1903 | ||
1904 | payload_size = 0x08; | |
1905 | ||
1906 | } else if (dc_is_dp_signal(stream->signal)) { | |
1907 | ||
1908 | /* HEADER */ | |
1909 | ||
1910 | /* HB0 = Secondary-data Packet ID = 0 - Only non-zero | |
1911 | * when used to associate audio related info packets | |
1912 | */ | |
1913 | info_packet->hb0 = 0x00; | |
1914 | ||
1915 | /* HB1 = Packet Type = 0x83 (Source Product | |
1916 | * Descriptor InfoFrame) | |
1917 | */ | |
3e183c5f | 1918 | info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD; |
4562236b HW |
1919 | |
1920 | /* HB2 = [Bits 7:0 = Least significant eight bits - | |
1921 | * For INFOFRAME, the value must be 1Bh] | |
1922 | */ | |
1923 | info_packet->hb2 = 0x1B; | |
1924 | ||
1925 | /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1] | |
1926 | * [Bits 1:0 = Most significant two bits = 0x00] | |
1927 | */ | |
1928 | info_packet->hb3 = 0x04; | |
1929 | ||
1930 | payload_size = 0x1B; | |
1931 | } | |
1932 | ||
1933 | /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ | |
1934 | info_packet->sb[1] = 0x1A; | |
1935 | ||
1936 | /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ | |
1937 | info_packet->sb[2] = 0x00; | |
1938 | ||
1939 | /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ | |
1940 | info_packet->sb[3] = 0x00; | |
1941 | ||
1942 | /* PB4 = Reserved */ | |
1943 | info_packet->sb[4] = 0x00; | |
1944 | ||
1945 | /* PB5 = Reserved */ | |
1946 | info_packet->sb[5] = 0x00; | |
1947 | ||
1948 | /* PB6 = [Bits 7:3 = Reserved] */ | |
1949 | info_packet->sb[6] = 0x00; | |
1950 | ||
1951 | if (stream->public.freesync_ctx.supported == true) | |
1952 | /* PB6 = [Bit 0 = FreeSync Supported] */ | |
1953 | info_packet->sb[6] |= 0x01; | |
1954 | ||
1955 | if (stream->public.freesync_ctx.enabled == true) | |
1956 | /* PB6 = [Bit 1 = FreeSync Enabled] */ | |
1957 | info_packet->sb[6] |= 0x02; | |
1958 | ||
1959 | if (stream->public.freesync_ctx.active == true) | |
1960 | /* PB6 = [Bit 2 = FreeSync Active] */ | |
1961 | info_packet->sb[6] |= 0x04; | |
1962 | ||
1963 | /* PB7 = FreeSync Minimum refresh rate (Hz) */ | |
1964 | info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx. | |
1965 | min_refresh_in_micro_hz / 1000000); | |
1966 | ||
1967 | /* PB8 = FreeSync Maximum refresh rate (Hz) | |
1968 | * | |
1969 | * Note: We do not use the maximum capable refresh rate | |
1970 | * of the panel, because we should never go above the field | |
1971 | * rate of the mode timing set. | |
1972 | */ | |
1973 | info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx. | |
1974 | nominal_refresh_in_micro_hz / 1000000); | |
1975 | ||
1976 | /* PB9 - PB27 = Reserved */ | |
1977 | for (idx = 9; idx <= 27; idx++) | |
1978 | info_packet->sb[idx] = 0x00; | |
1979 | ||
1980 | /* Calculate checksum */ | |
1981 | checksum += info_packet->hb0; | |
1982 | checksum += info_packet->hb1; | |
1983 | checksum += info_packet->hb2; | |
1984 | checksum += info_packet->hb3; | |
1985 | ||
1986 | for (idx = 1; idx <= payload_size; idx++) | |
1987 | checksum += info_packet->sb[idx]; | |
1988 | ||
1989 | /* PB0 = Checksum (one byte complement) */ | |
1990 | info_packet->sb[0] = (unsigned char) (0x100 - checksum); | |
1991 | ||
1992 | info_packet->valid = true; | |
1993 | } | |
1994 | ||
1646a6fe | 1995 | static void set_hdr_static_info_packet( |
6e4d6bee | 1996 | struct encoder_info_packet *info_packet, |
1646a6fe | 1997 | struct core_surface *surface, |
6e4d6bee | 1998 | struct core_stream *stream) |
1646a6fe | 1999 | { |
e5cf325b | 2000 | uint16_t i = 0; |
1646a6fe | 2001 | enum signal_type signal = stream->signal; |
e5cf325b HW |
2002 | struct dc_hdr_static_metadata hdr_metadata; |
2003 | uint32_t data; | |
1646a6fe AW |
2004 | |
2005 | if (!surface) | |
2006 | return; | |
2007 | ||
e5cf325b | 2008 | hdr_metadata = surface->public.hdr_static_ctx; |
1646a6fe | 2009 | |
70063a59 | 2010 | if (!hdr_metadata.hdr_supported) |
10bff005 YS |
2011 | return; |
2012 | ||
1646a6fe AW |
2013 | if (dc_is_hdmi_signal(signal)) { |
2014 | info_packet->valid = true; | |
2015 | ||
2016 | info_packet->hb0 = 0x87; | |
2017 | info_packet->hb1 = 0x01; | |
2018 | info_packet->hb2 = 0x1A; | |
2019 | i = 1; | |
2020 | } else if (dc_is_dp_signal(signal)) { | |
2021 | info_packet->valid = true; | |
2022 | ||
2023 | info_packet->hb0 = 0x00; | |
2024 | info_packet->hb1 = 0x87; | |
2025 | info_packet->hb2 = 0x1D; | |
2026 | info_packet->hb3 = (0x13 << 2); | |
2027 | i = 2; | |
2028 | } | |
2029 | ||
1646a6fe AW |
2030 | data = hdr_metadata.is_hdr; |
2031 | info_packet->sb[i++] = data ? 0x02 : 0x00; | |
2032 | info_packet->sb[i++] = 0x00; | |
2033 | ||
2034 | data = hdr_metadata.chromaticity_green_x / 2; | |
2035 | info_packet->sb[i++] = data & 0xFF; | |
2036 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2037 | ||
2038 | data = hdr_metadata.chromaticity_green_y / 2; | |
2039 | info_packet->sb[i++] = data & 0xFF; | |
2040 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2041 | ||
2042 | data = hdr_metadata.chromaticity_blue_x / 2; | |
2043 | info_packet->sb[i++] = data & 0xFF; | |
2044 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2045 | ||
2046 | data = hdr_metadata.chromaticity_blue_y / 2; | |
2047 | info_packet->sb[i++] = data & 0xFF; | |
2048 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2049 | ||
2050 | data = hdr_metadata.chromaticity_red_x / 2; | |
2051 | info_packet->sb[i++] = data & 0xFF; | |
2052 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2053 | ||
2054 | data = hdr_metadata.chromaticity_red_y / 2; | |
2055 | info_packet->sb[i++] = data & 0xFF; | |
2056 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2057 | ||
2058 | data = hdr_metadata.chromaticity_white_point_x / 2; | |
2059 | info_packet->sb[i++] = data & 0xFF; | |
2060 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2061 | ||
2062 | data = hdr_metadata.chromaticity_white_point_y / 2; | |
2063 | info_packet->sb[i++] = data & 0xFF; | |
2064 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2065 | ||
2066 | data = hdr_metadata.max_luminance; | |
2067 | info_packet->sb[i++] = data & 0xFF; | |
2068 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2069 | ||
2070 | data = hdr_metadata.min_luminance; | |
2071 | info_packet->sb[i++] = data & 0xFF; | |
2072 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2073 | ||
2074 | data = hdr_metadata.maximum_content_light_level; | |
2075 | info_packet->sb[i++] = data & 0xFF; | |
2076 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2077 | ||
2078 | data = hdr_metadata.maximum_frame_average_light_level; | |
2079 | info_packet->sb[i++] = data & 0xFF; | |
2080 | info_packet->sb[i++] = (data & 0xFF00) >> 8; | |
2081 | ||
2082 | if (dc_is_hdmi_signal(signal)) { | |
2083 | uint32_t checksum = 0; | |
2084 | ||
2085 | checksum += info_packet->hb0; | |
2086 | checksum += info_packet->hb1; | |
2087 | checksum += info_packet->hb2; | |
2088 | ||
2089 | for (i = 1; i <= info_packet->hb2; i++) | |
2090 | checksum += info_packet->sb[i]; | |
2091 | ||
2092 | info_packet->sb[0] = 0x100 - checksum; | |
2093 | } else if (dc_is_dp_signal(signal)) { | |
2094 | info_packet->sb[0] = 0x01; | |
2095 | info_packet->sb[1] = 0x1A; | |
2096 | } | |
2097 | } | |
2098 | ||
6e4d6bee TC |
2099 | static void set_vsc_info_packet( |
2100 | struct encoder_info_packet *info_packet, | |
2101 | struct core_stream *stream) | |
4562236b HW |
2102 | { |
2103 | unsigned int vscPacketRevision = 0; | |
2104 | unsigned int i; | |
2105 | ||
94267b3d | 2106 | if (stream->sink->link->psr_enabled) { |
4562236b HW |
2107 | vscPacketRevision = 2; |
2108 | } | |
2109 | ||
2110 | /* VSC packet not needed based on the features | |
2111 | * supported by this DP display | |
2112 | */ | |
2113 | if (vscPacketRevision == 0) | |
2114 | return; | |
2115 | ||
2116 | if (vscPacketRevision == 0x2) { | |
2117 | /* Secondary-data Packet ID = 0*/ | |
2118 | info_packet->hb0 = 0x00; | |
2119 | /* 07h - Packet Type Value indicating Video | |
2120 | * Stream Configuration packet | |
2121 | */ | |
2122 | info_packet->hb1 = 0x07; | |
2123 | /* 02h = VSC SDP supporting 3D stereo and PSR | |
2124 | * (applies to eDP v1.3 or higher). | |
2125 | */ | |
2126 | info_packet->hb2 = 0x02; | |
2127 | /* 08h = VSC packet supporting 3D stereo + PSR | |
2128 | * (HB2 = 02h). | |
2129 | */ | |
2130 | info_packet->hb3 = 0x08; | |
2131 | ||
2132 | for (i = 0; i < 28; i++) | |
2133 | info_packet->sb[i] = 0; | |
2134 | ||
2135 | info_packet->valid = true; | |
2136 | } | |
2137 | ||
2138 | /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ | |
2139 | } | |
2140 | ||
8122a253 | 2141 | void dc_resource_validate_ctx_destruct(struct validate_context *context) |
4562236b HW |
2142 | { |
2143 | int i, j; | |
2144 | ||
ab2541b6 AC |
2145 | for (i = 0; i < context->stream_count; i++) { |
2146 | for (j = 0; j < context->stream_status[i].surface_count; j++) | |
4562236b | 2147 | dc_surface_release( |
ab2541b6 | 2148 | context->stream_status[i].surfaces[j]); |
4562236b | 2149 | |
ab2541b6 AC |
2150 | context->stream_status[i].surface_count = 0; |
2151 | dc_stream_release(&context->streams[i]->public); | |
2152 | context->streams[i] = NULL; | |
4562236b HW |
2153 | } |
2154 | } | |
2155 | ||
2156 | /* | |
ab2541b6 | 2157 | * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced |
4562236b HW |
2158 | * by the src_ctx |
2159 | */ | |
8122a253 | 2160 | void dc_resource_validate_ctx_copy_construct( |
4562236b HW |
2161 | const struct validate_context *src_ctx, |
2162 | struct validate_context *dst_ctx) | |
2163 | { | |
2164 | int i, j; | |
2165 | ||
2166 | *dst_ctx = *src_ctx; | |
2167 | ||
a2b8659d | 2168 | for (i = 0; i < MAX_PIPES; i++) { |
4562236b HW |
2169 | struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; |
2170 | ||
2171 | if (cur_pipe->top_pipe) | |
2172 | cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; | |
2173 | ||
2174 | if (cur_pipe->bottom_pipe) | |
2175 | cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; | |
2176 | ||
2177 | } | |
2178 | ||
ab2541b6 AC |
2179 | for (i = 0; i < dst_ctx->stream_count; i++) { |
2180 | dc_stream_retain(&dst_ctx->streams[i]->public); | |
2181 | for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) | |
4562236b | 2182 | dc_surface_retain( |
ab2541b6 | 2183 | dst_ctx->stream_status[i].surfaces[j]); |
4562236b HW |
2184 | } |
2185 | } | |
2186 | ||
2187 | struct clock_source *dc_resource_find_first_free_pll( | |
a2b8659d TC |
2188 | struct resource_context *res_ctx, |
2189 | const struct resource_pool *pool) | |
4562236b HW |
2190 | { |
2191 | int i; | |
2192 | ||
a2b8659d | 2193 | for (i = 0; i < pool->clk_src_count; ++i) { |
4562236b | 2194 | if (res_ctx->clock_source_ref_count[i] == 0) |
a2b8659d | 2195 | return pool->clock_sources[i]; |
4562236b HW |
2196 | } |
2197 | ||
2198 | return NULL; | |
2199 | } | |
2200 | ||
2201 | void resource_build_info_frame(struct pipe_ctx *pipe_ctx) | |
2202 | { | |
2203 | enum signal_type signal = SIGNAL_TYPE_NONE; | |
6e4d6bee | 2204 | struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame; |
4562236b HW |
2205 | |
2206 | /* default all packets to invalid */ | |
6e4d6bee TC |
2207 | info->avi.valid = false; |
2208 | info->gamut.valid = false; | |
2209 | info->vendor.valid = false; | |
630e3573 | 2210 | info->spd.valid = false; |
6e4d6bee TC |
2211 | info->hdrsmd.valid = false; |
2212 | info->vsc.valid = false; | |
4562236b HW |
2213 | |
2214 | signal = pipe_ctx->stream->signal; | |
2215 | ||
2216 | /* HDMi and DP have different info packets*/ | |
2217 | if (dc_is_hdmi_signal(signal)) { | |
6e4d6bee TC |
2218 | set_avi_info_frame(&info->avi, pipe_ctx); |
2219 | ||
2220 | set_vendor_info_packet(&info->vendor, pipe_ctx->stream); | |
2221 | ||
2222 | set_spd_info_packet(&info->spd, pipe_ctx->stream); | |
2223 | ||
2224 | set_hdr_static_info_packet(&info->hdrsmd, | |
2225 | pipe_ctx->surface, pipe_ctx->stream); | |
2226 | ||
a33fa99d | 2227 | } else if (dc_is_dp_signal(signal)) { |
6e4d6bee TC |
2228 | set_vsc_info_packet(&info->vsc, pipe_ctx->stream); |
2229 | ||
2230 | set_spd_info_packet(&info->spd, pipe_ctx->stream); | |
2231 | ||
2232 | set_hdr_static_info_packet(&info->hdrsmd, | |
2233 | pipe_ctx->surface, pipe_ctx->stream); | |
a33fa99d | 2234 | } |
4562236b | 2235 | |
6e4d6bee | 2236 | patch_gamut_packet_checksum(&info->gamut); |
4562236b HW |
2237 | } |
2238 | ||
2239 | enum dc_status resource_map_clock_resources( | |
2240 | const struct core_dc *dc, | |
430ef426 DL |
2241 | struct validate_context *context, |
2242 | struct validate_context *old_context) | |
4562236b | 2243 | { |
ab2541b6 | 2244 | int i, j; |
a2b8659d | 2245 | const struct resource_pool *pool = dc->res_pool; |
4562236b HW |
2246 | |
2247 | /* acquire new resources */ | |
ab2541b6 AC |
2248 | for (i = 0; i < context->stream_count; i++) { |
2249 | const struct core_stream *stream = context->streams[i]; | |
4562236b | 2250 | |
430ef426 | 2251 | if (old_context && resource_is_stream_unchanged(old_context, stream)) |
ab2541b6 AC |
2252 | continue; |
2253 | ||
2254 | for (j = 0; j < MAX_PIPES; j++) { | |
2255 | struct pipe_ctx *pipe_ctx = | |
2256 | &context->res_ctx.pipe_ctx[j]; | |
4562236b | 2257 | |
ab2541b6 | 2258 | if (context->res_ctx.pipe_ctx[j].stream != stream) |
4562236b HW |
2259 | continue; |
2260 | ||
ab2541b6 AC |
2261 | if (dc_is_dp_signal(pipe_ctx->stream->signal) |
2262 | || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) | |
a2b8659d | 2263 | pipe_ctx->clock_source = pool->dp_clock_source; |
ab2541b6 AC |
2264 | else { |
2265 | pipe_ctx->clock_source = NULL; | |
4562236b | 2266 | |
ab2541b6 AC |
2267 | if (!dc->public.config.disable_disp_pll_sharing) |
2268 | resource_find_used_clk_src_for_sharing( | |
2269 | &context->res_ctx, | |
2270 | pipe_ctx); | |
4562236b | 2271 | |
ab2541b6 | 2272 | if (pipe_ctx->clock_source == NULL) |
4562236b | 2273 | pipe_ctx->clock_source = |
a2b8659d TC |
2274 | dc_resource_find_first_free_pll( |
2275 | &context->res_ctx, | |
2276 | pool); | |
ab2541b6 | 2277 | } |
4562236b | 2278 | |
ab2541b6 AC |
2279 | if (pipe_ctx->clock_source == NULL) |
2280 | return DC_NO_CLOCK_SOURCE_RESOURCE; | |
4562236b | 2281 | |
ab2541b6 | 2282 | resource_reference_clock_source( |
a2b8659d | 2283 | &context->res_ctx, pool, |
ab2541b6 | 2284 | pipe_ctx->clock_source); |
4562236b | 2285 | |
ab2541b6 AC |
2286 | /* only one cs per stream regardless of mpo */ |
2287 | break; | |
4562236b HW |
2288 | } |
2289 | } | |
2290 | ||
2291 | return DC_OK; | |
2292 | } | |
2293 | ||
2294 | /* | |
2295 | * Note: We need to disable output if clock sources change, | |
2296 | * since bios does optimization and doesn't apply if changing | |
2297 | * PHY when not already disabled. | |
2298 | */ | |
2299 | bool pipe_need_reprogram( | |
2300 | struct pipe_ctx *pipe_ctx_old, | |
2301 | struct pipe_ctx *pipe_ctx) | |
2302 | { | |
2303 | if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) | |
2304 | return true; | |
2305 | ||
2306 | if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) | |
2307 | return true; | |
2308 | ||
2309 | if (pipe_ctx_old->audio != pipe_ctx->audio) | |
2310 | return true; | |
2311 | ||
2312 | if (pipe_ctx_old->clock_source != pipe_ctx->clock_source | |
2313 | && pipe_ctx_old->stream != pipe_ctx->stream) | |
2314 | return true; | |
2315 | ||
2316 | if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc) | |
2317 | return true; | |
2318 | ||
2319 | if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) | |
2320 | return true; | |
2321 | ||
2322 | ||
2323 | return false; | |
2324 | } | |
529cad0f DW |
2325 | |
2326 | void resource_build_bit_depth_reduction_params(const struct core_stream *stream, | |
2327 | struct bit_depth_reduction_params *fmt_bit_depth) | |
2328 | { | |
2329 | enum dc_dither_option option = stream->public.dither_option; | |
2330 | enum dc_pixel_encoding pixel_encoding = | |
2331 | stream->public.timing.pixel_encoding; | |
2332 | ||
2333 | memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); | |
2334 | ||
2335 | if (option == DITHER_OPTION_DISABLE) | |
2336 | return; | |
2337 | ||
2338 | if (option == DITHER_OPTION_TRUN6) { | |
2339 | fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; | |
2340 | fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; | |
2341 | } else if (option == DITHER_OPTION_TRUN8 || | |
2342 | option == DITHER_OPTION_TRUN8_SPATIAL6 || | |
2343 | option == DITHER_OPTION_TRUN8_FM6) { | |
2344 | fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; | |
2345 | fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; | |
2346 | } else if (option == DITHER_OPTION_TRUN10 || | |
2347 | option == DITHER_OPTION_TRUN10_SPATIAL6 || | |
2348 | option == DITHER_OPTION_TRUN10_SPATIAL8 || | |
2349 | option == DITHER_OPTION_TRUN10_FM8 || | |
2350 | option == DITHER_OPTION_TRUN10_FM6 || | |
2351 | option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { | |
2352 | fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; | |
2353 | fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; | |
2354 | } | |
2355 | ||
2356 | /* special case - Formatter can only reduce by 4 bits at most. | |
2357 | * When reducing from 12 to 6 bits, | |
2358 | * HW recommends we use trunc with round mode | |
2359 | * (if we did nothing, trunc to 10 bits would be used) | |
2360 | * note that any 12->10 bit reduction is ignored prior to DCE8, | |
2361 | * as the input was 10 bits. | |
2362 | */ | |
2363 | if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || | |
2364 | option == DITHER_OPTION_SPATIAL6 || | |
2365 | option == DITHER_OPTION_FM6) { | |
2366 | fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; | |
2367 | fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; | |
2368 | fmt_bit_depth->flags.TRUNCATE_MODE = 1; | |
2369 | } | |
2370 | ||
2371 | /* spatial dither | |
2372 | * note that spatial modes 1-3 are never used | |
2373 | */ | |
2374 | if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || | |
2375 | option == DITHER_OPTION_SPATIAL6 || | |
2376 | option == DITHER_OPTION_TRUN10_SPATIAL6 || | |
2377 | option == DITHER_OPTION_TRUN8_SPATIAL6) { | |
2378 | fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; | |
2379 | fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; | |
2380 | fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; | |
2381 | fmt_bit_depth->flags.RGB_RANDOM = | |
2382 | (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; | |
2383 | } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || | |
2384 | option == DITHER_OPTION_SPATIAL8 || | |
2385 | option == DITHER_OPTION_SPATIAL8_FM6 || | |
2386 | option == DITHER_OPTION_TRUN10_SPATIAL8 || | |
2387 | option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { | |
2388 | fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; | |
2389 | fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; | |
2390 | fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; | |
2391 | fmt_bit_depth->flags.RGB_RANDOM = | |
2392 | (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; | |
2393 | } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || | |
2394 | option == DITHER_OPTION_SPATIAL10 || | |
2395 | option == DITHER_OPTION_SPATIAL10_FM8 || | |
2396 | option == DITHER_OPTION_SPATIAL10_FM6) { | |
2397 | fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; | |
2398 | fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; | |
2399 | fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; | |
2400 | fmt_bit_depth->flags.RGB_RANDOM = | |
2401 | (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; | |
2402 | } | |
2403 | ||
2404 | if (option == DITHER_OPTION_SPATIAL6 || | |
2405 | option == DITHER_OPTION_SPATIAL8 || | |
2406 | option == DITHER_OPTION_SPATIAL10) { | |
2407 | fmt_bit_depth->flags.FRAME_RANDOM = 0; | |
2408 | } else { | |
2409 | fmt_bit_depth->flags.FRAME_RANDOM = 1; | |
2410 | } | |
2411 | ||
2412 | ////////////////////// | |
2413 | //// temporal dither | |
2414 | ////////////////////// | |
2415 | if (option == DITHER_OPTION_FM6 || | |
2416 | option == DITHER_OPTION_SPATIAL8_FM6 || | |
2417 | option == DITHER_OPTION_SPATIAL10_FM6 || | |
2418 | option == DITHER_OPTION_TRUN10_FM6 || | |
2419 | option == DITHER_OPTION_TRUN8_FM6 || | |
2420 | option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { | |
2421 | fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; | |
2422 | fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; | |
2423 | } else if (option == DITHER_OPTION_FM8 || | |
2424 | option == DITHER_OPTION_SPATIAL10_FM8 || | |
2425 | option == DITHER_OPTION_TRUN10_FM8) { | |
2426 | fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; | |
2427 | fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; | |
2428 | } else if (option == DITHER_OPTION_FM10) { | |
2429 | fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; | |
2430 | fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; | |
2431 | } | |
2432 | ||
2433 | fmt_bit_depth->pixel_encoding = pixel_encoding; | |
2434 | } |