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drm/amd/display: move trace buffer to uncached memory.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b 44
683b5950
MR		 45#if defined(CONFIG_DRM_AMD_DC_SI)
46#include "dce60/dce60_resource.h"
47#endif
4562236b
HW		 48#include "dce80/dce80_resource.h"
49#include "dce100/dce100_resource.h"
50#include "dce110/dce110_resource.h"
51#include "dce112/dce112_resource.h"
cf2156e2 52#include "dce120/dce120_resource.h"
b86a1aa3 53#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 54#include "dcn10/dcn10_resource.h"
7ed4e635 55#include "dcn20/dcn20_resource.h"
e22ece54 56#include "dcn21/dcn21_resource.h"
20f2ffe5
AD		 57#include "dcn30/dcn30_resource.h"
58#include "dcn301/dcn301_resource.h"
59#include "dcn302/dcn302_resource.h"
36d26912 60#endif
5d4b05dd
BL		 61
62#define DC_LOGGER_INIT(logger)
63
4562236b
HW		 64enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
65{
66 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
67 switch (asic_id.chip_family) {
68
683b5950
MR		 69#if defined(CONFIG_DRM_AMD_DC_SI)
70 case FAMILY_SI:
71 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
72 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
34b0c779 74 dc_version = DCE_VERSION_6_0;
683b5950
MR		 75 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
76 dc_version = DCE_VERSION_6_4;
77 else
78 dc_version = DCE_VERSION_6_1;
79 break;
80#endif
4562236b 81 case FAMILY_CI:
4562236b
HW		 82 dc_version = DCE_VERSION_8_0;
83 break;
ebfdf0d0
AD		 84 case FAMILY_KV:
85 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
88 dc_version = DCE_VERSION_8_3;
89 else
90 dc_version = DCE_VERSION_8_1;
91 break;
4562236b
HW		 92 case FAMILY_CZ:
93 dc_version = DCE_VERSION_11_0;
94 break;
95
96 case FAMILY_VI:
97 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
98 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
99 dc_version = DCE_VERSION_10_0;
100 break;
101 }
102 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 103 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
104 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 105 dc_version = DCE_VERSION_11_2;
106 }
0c75d5ac
JFZ		 107 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
108 dc_version = DCE_VERSION_11_22;
4562236b 109 break;
2c8ad2d5 110 case FAMILY_AI:
b8b6ce89
LL		 111 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
112 dc_version = DCE_VERSION_12_1;
113 else
114 dc_version = DCE_VERSION_12_0;
2c8ad2d5 115 break;
b86a1aa3 116#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 117 case FAMILY_RV:
118 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 119 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
120 dc_version = DCN_VERSION_1_01;
e22ece54
BL		 121 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
122 dc_version = DCN_VERSION_2_1;
9ba93114
RL		 123 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
124 dc_version = DCN_VERSION_2_1;
ff5ef992 125 break;
7ed4e635 126
7ed4e635
HW		 127 case FAMILY_NV:
128 dc_version = DCN_VERSION_2_0;
5dba4991
BL		 129 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
130 dc_version = DCN_VERSION_3_0;
36d26912
BL		 131 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
132 dc_version = DCN_VERSION_3_02;
7ed4e635 133 break;
3a83e4e6 134
3a83e4e6
RL		 135 case FAMILY_VGH:
136 dc_version = DCN_VERSION_3_01;
137 break;
138#endif
4562236b
HW		 139 default:
140 dc_version = DCE_VERSION_UNKNOWN;
141 break;
142 }
143 return dc_version;
144}
145
d9673c92
HW		 146struct resource_pool *dc_create_resource_pool(struct dc *dc,
147 const struct dc_init_data *init_data,
148 enum dce_version dc_version)
4562236b 149{
5ac3d3c9 150 struct resource_pool *res_pool = NULL;
4562236b
HW		 151
152 switch (dc_version) {
683b5950
MR		 153#if defined(CONFIG_DRM_AMD_DC_SI)
154 case DCE_VERSION_6_0:
155 res_pool = dce60_create_resource_pool(
156 init_data->num_virtual_links, dc);
157 break;
158 case DCE_VERSION_6_1:
159 res_pool = dce61_create_resource_pool(
160 init_data->num_virtual_links, dc);
161 break;
162 case DCE_VERSION_6_4:
163 res_pool = dce64_create_resource_pool(
164 init_data->num_virtual_links, dc);
165 break;
166#endif
4562236b 167 case DCE_VERSION_8_0:
7992a629 168 res_pool = dce80_create_resource_pool(
d9673c92 169 init_data->num_virtual_links, dc);
7992a629 170 break;
ebfdf0d0 171 case DCE_VERSION_8_1:
7992a629 172 res_pool = dce81_create_resource_pool(
d9673c92 173 init_data->num_virtual_links, dc);
7992a629 174 break;
ebfdf0d0 175 case DCE_VERSION_8_3:
7992a629 176 res_pool = dce83_create_resource_pool(
d9673c92 177 init_data->num_virtual_links, dc);
5ac3d3c9 178 break;
4562236b 179 case DCE_VERSION_10_0:
5ac3d3c9 180 res_pool = dce100_create_resource_pool(
d9673c92 181 init_data->num_virtual_links, dc);
5ac3d3c9 182 break;
4562236b 183 case DCE_VERSION_11_0:
5ac3d3c9 184 res_pool = dce110_create_resource_pool(
d9673c92
HW		 185 init_data->num_virtual_links, dc,
186 init_data->asic_id);
5ac3d3c9 187 break;
4562236b 188 case DCE_VERSION_11_2:
0c75d5ac 189 case DCE_VERSION_11_22:
5ac3d3c9 190 res_pool = dce112_create_resource_pool(
d9673c92 191 init_data->num_virtual_links, dc);
5ac3d3c9 192 break;
2c8ad2d5 193 case DCE_VERSION_12_0:
b8b6ce89 194 case DCE_VERSION_12_1:
2c8ad2d5 195 res_pool = dce120_create_resource_pool(
d9673c92 196 init_data->num_virtual_links, dc);
2c8ad2d5 197 break;
ff5ef992 198
b86a1aa3 199#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 200 case DCN_VERSION_1_0:
0e3d73f1 201 case DCN_VERSION_1_01:
d9673c92 202 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 203 break;
7ed4e635
HW		 204 case DCN_VERSION_2_0:
205 res_pool = dcn20_create_resource_pool(init_data, dc);
206 break;
e22ece54
BL		 207 case DCN_VERSION_2_1:
208 res_pool = dcn21_create_resource_pool(init_data, dc);
209 break;
5dba4991
BL		 210 case DCN_VERSION_3_0:
211 res_pool = dcn30_create_resource_pool(init_data, dc);
212 break;
3a83e4e6
RL		 213 case DCN_VERSION_3_01:
214 res_pool = dcn301_create_resource_pool(init_data, dc);
215 break;
36d26912
BL		 216 case DCN_VERSION_3_02:
217 res_pool = dcn302_create_resource_pool(init_data, dc);
218 break;
3a83e4e6 219#endif
4562236b
HW		 220 default:
221 break;
222 }
f49cfa27 223
5ac3d3c9 224 if (res_pool != NULL) {
9adc8050 225 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 226 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 227 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 228 /* initialize with firmware data first, no all
229 * ASIC have DCCG SW component. FPGA or
230 * simulation need initialization of
231 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
232 * with xtalin_clock_inKhz
233 */
234 res_pool->ref_clocks.dccg_ref_clock_inKhz =
235 res_pool->ref_clocks.xtalin_clock_inKhz;
236 res_pool->ref_clocks.dchub_ref_clock_inKhz =
237 res_pool->ref_clocks.xtalin_clock_inKhz;
238 } else
239 ASSERT_CRITICAL(false);
5ac3d3c9 240 }
4562236b 241
5ac3d3c9 242 return res_pool;
4562236b
HW		 243}
244
fb3466a4 245void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 246{
247 if (dc) {
248 if (dc->res_pool)
249 dc->res_pool->funcs->destroy(&dc->res_pool);
250
d029810c 251 kfree(dc->hwseq);
4562236b
HW		 252 }
253}
254
255static void update_num_audio(
256 const struct resource_straps *straps,
257 unsigned int *num_audio,
258 struct audio_support *aud_support)
259{
b8e9eb72
CL		 260 aud_support->dp_audio = true;
261 aud_support->hdmi_audio_native = false;
262 aud_support->hdmi_audio_on_dongle = false;
263
4562236b 264 if (straps->hdmi_disable == 0) {
4562236b
HW		 265 if (straps->dc_pinstraps_audio & 0x2) {
266 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 267 aud_support->hdmi_audio_native = true;
4562236b
HW		 268 }
269 }
270
271 switch (straps->audio_stream_number) {
272 case 0: /* multi streams supported */
273 break;
274 case 1: /* multi streams not supported */
275 *num_audio = 1;
276 break;
277 default:
278 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 279 }
4562236b
HW		 280}
281
282bool resource_construct(
283 unsigned int num_virtual_links,
fb3466a4 284 struct dc *dc,
4562236b
HW		 285 struct resource_pool *pool,
286 const struct resource_create_funcs *create_funcs)
287{
288 struct dc_context *ctx = dc->ctx;
289 const struct resource_caps *caps = pool->res_cap;
290 int i;
291 unsigned int num_audio = caps->num_audio;
292 struct resource_straps straps = {0};
293
294 if (create_funcs->read_dce_straps)
295 create_funcs->read_dce_straps(dc->ctx, &straps);
296
297 pool->audio_count = 0;
298 if (create_funcs->create_audio) {
299 /* find the total number of streams available via the
300 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
301 * registers (one for each pin) starting from pin 1
302 * up to the max number of audio pins.
303 * We stop on the first pin where
304 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
305 */
306 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 307 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 308 struct audio *aud = create_funcs->create_audio(ctx, i);
309
310 if (aud == NULL) {
311 DC_ERR("DC: failed to create audio!\n");
312 return false;
313 }
4562236b
HW		 314 if (!aud->funcs->endpoint_valid(aud)) {
315 aud->funcs->destroy(&aud);
316 break;
317 }
4562236b
HW		 318 pool->audios[i] = aud;
319 pool->audio_count++;
320 }
321 }
322
323 pool->stream_enc_count = 0;
324 if (create_funcs->create_stream_encoder) {
325 for (i = 0; i < caps->num_stream_encoder; i++) {
326 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
327 if (pool->stream_enc[i] == NULL)
328 DC_ERR("DC: failed to create stream_encoder!\n");
329 pool->stream_enc_count++;
330 }
331 }
929c3aaa 332
20f2ffe5 333#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 334 for (i = 0; i < caps->num_mpc_3dlut; i++) {
335 pool->mpc_lut[i] = dc_create_3dlut_func();
336 if (pool->mpc_lut[i] == NULL)
337 DC_ERR("DC: failed to create MPC 3dlut!\n");
338 pool->mpc_shaper[i] = dc_create_transfer_func();
339 if (pool->mpc_shaper[i] == NULL)
340 DC_ERR("DC: failed to create MPC shaper!\n");
341 }
342#endif
4176664b
CL		 343 dc->caps.dynamic_audio = false;
344 if (pool->audio_count < pool->stream_enc_count) {
345 dc->caps.dynamic_audio = true;
346 }
4562236b
HW		 347 for (i = 0; i < num_virtual_links; i++) {
348 pool->stream_enc[pool->stream_enc_count] =
349 virtual_stream_encoder_create(
350 ctx, ctx->dc_bios);
351 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
352 DC_ERR("DC: failed to create stream_encoder!\n");
353 return false;
354 }
355 pool->stream_enc_count++;
356 }
357
358 dc->hwseq = create_funcs->create_hwseq(ctx);
359
360 return true;
361}
ad8960a6
ML		 362static int find_matching_clock_source(
363 const struct resource_pool *pool,
364 struct clock_source *clock_source)
365{
4562236b 366
ad8960a6
ML		 367 int i;
368
369 for (i = 0; i < pool->clk_src_count; i++) {
370 if (pool->clock_sources[i] == clock_source)
371 return i;
372 }
373 return -1;
374}
4562236b 375
21e67d4d 376void resource_unreference_clock_source(
4562236b 377 struct resource_context *res_ctx,
a2b8659d 378 const struct resource_pool *pool,
4a629536 379 struct clock_source *clock_source)
4562236b 380{
ad8960a6 381 int i = find_matching_clock_source(pool, clock_source);
4562236b 382
ad8960a6 383 if (i > -1)
4562236b
HW		 384 res_ctx->clock_source_ref_count[i]--;
385
21e67d4d 386 if (pool->dp_clock_source == clock_source)
4562236b 387 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 388}
389
390void resource_reference_clock_source(
391 struct resource_context *res_ctx,
a2b8659d 392 const struct resource_pool *pool,
4562236b
HW		 393 struct clock_source *clock_source)
394{
ad8960a6 395 int i = find_matching_clock_source(pool, clock_source);
4562236b 396
ad8960a6 397 if (i > -1)
4562236b 398 res_ctx->clock_source_ref_count[i]++;
4562236b 399
a2b8659d 400 if (pool->dp_clock_source == clock_source)
4562236b
HW		 401 res_ctx->dp_clock_source_ref_count++;
402}
403
ad8960a6
ML		 404int resource_get_clock_source_reference(
405 struct resource_context *res_ctx,
406 const struct resource_pool *pool,
407 struct clock_source *clock_source)
408{
409 int i = find_matching_clock_source(pool, clock_source);
410
411 if (i > -1)
412 return res_ctx->clock_source_ref_count[i];
413
414 if (pool->dp_clock_source == clock_source)
415 return res_ctx->dp_clock_source_ref_count;
416
417 return -1;
418}
419
4562236b 420bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 421 struct dc_stream_state *stream1,
422 struct dc_stream_state *stream2)
4562236b 423{
4fa086b9 424 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 425 return false;
426
4fa086b9 427 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 428 return false;
429
4fa086b9
LSL		 430 if (stream1->timing.h_addressable
431 != stream2->timing.h_addressable)
4562236b
HW		 432 return false;
433
4fa086b9
LSL		 434 if (stream1->timing.v_addressable
435 != stream2->timing.v_addressable)
4562236b
HW		 436 return false;
437
8582aea2
DG		 438 if (stream1->timing.v_front_porch
439 != stream2->timing.v_front_porch)
440 return false;
441
380604e2
KC		 442 if (stream1->timing.pix_clk_100hz
443 != stream2->timing.pix_clk_100hz)
4562236b
HW		 444 return false;
445
3e27e10e
ML		 446 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
447 return false;
448
4562236b 449 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 450 && (!dc_is_dp_signal(stream1->signal)
451 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 452 return false;
453
d77f778e
CL		 454 if (stream1->view_format != stream2->view_format)
455 return false;
456
0460f9ab
JL		 457 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
458 return false;
459
4562236b
HW		 460 return true;
461}
3e27e10e
ML		 462static bool is_dp_and_hdmi_sharable(
463 struct dc_stream_state *stream1,
464 struct dc_stream_state *stream2)
465{
466 if (stream1->ctx->dc->caps.disable_dp_clk_share)
467 return false;
468
469 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 470 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 471 return false;
3e27e10e
ML		 472
473 return true;
474
475}
4562236b
HW		 476
477static bool is_sharable_clk_src(
478 const struct pipe_ctx *pipe_with_clk_src,
479 const struct pipe_ctx *pipe)
480{
481 if (pipe_with_clk_src->clock_source == NULL)
482 return false;
483
484 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
485 return false;
486
3e27e10e
ML		 487 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
488 (dc_is_dp_signal(pipe->stream->signal) &&
489 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
490 pipe->stream)))
4562236b
HW		 491 return false;
492
493 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 494 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 495 return false;
496
497 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 498 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 499 return false;
500
501 if (!resource_are_streams_timing_synchronizable(
502 pipe_with_clk_src->stream, pipe->stream))
503 return false;
504
505 return true;
506}
507
508struct clock_source *resource_find_used_clk_src_for_sharing(
509 struct resource_context *res_ctx,
510 struct pipe_ctx *pipe_ctx)
511{
512 int i;
513
514 for (i = 0; i < MAX_PIPES; i++) {
515 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
516 return res_ctx->pipe_ctx[i].clock_source;
517 }
518
519 return NULL;
520}
521
522static enum pixel_format convert_pixel_format_to_dalsurface(
523 enum surface_pixel_format surface_pixel_format)
524{
525 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
526
527 switch (surface_pixel_format) {
528 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
529 dal_pixel_format = PIXEL_FORMAT_INDEX8;
530 break;
531 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
532 dal_pixel_format = PIXEL_FORMAT_RGB565;
533 break;
534 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
535 dal_pixel_format = PIXEL_FORMAT_RGB565;
536 break;
537 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
538 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
539 break;
8693049a 540 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 541 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
542 break;
543 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
544 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
545 break;
546 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
547 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
548 break;
549 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
550 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
551 break;
552 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
553 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
554 dal_pixel_format = PIXEL_FORMAT_FP16;
555 break;
556 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 557 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 558 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 559 break;
ffbcd19a
VP		 560 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
561 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 562 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 563 break;
4562236b
HW		 564 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
565 default:
566 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
567 break;
568 }
569 return dal_pixel_format;
570}
571
9b6067c0
DL		 572static inline void get_vp_scan_direction(
573 enum dc_rotation_angle rotation,
574 bool horizontal_mirror,
575 bool *orthogonal_rotation,
576 bool *flip_vert_scan_dir,
577 bool *flip_horz_scan_dir)
4562236b 578{
9b6067c0
DL		 579 *orthogonal_rotation = false;
580 *flip_vert_scan_dir = false;
581 *flip_horz_scan_dir = false;
582 if (rotation == ROTATION_ANGLE_180) {
583 *flip_vert_scan_dir = true;
584 *flip_horz_scan_dir = true;
585 } else if (rotation == ROTATION_ANGLE_90) {
586 *orthogonal_rotation = true;
587 *flip_horz_scan_dir = true;
588 } else if (rotation == ROTATION_ANGLE_270) {
589 *orthogonal_rotation = true;
590 *flip_vert_scan_dir = true;
591 }
592
593 if (horizontal_mirror)
594 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 595}
596
570bc18c
DL		 597int get_num_mpc_splits(struct pipe_ctx *pipe)
598{
599 int mpc_split_count = 0;
600 struct pipe_ctx *other_pipe = pipe->bottom_pipe;
601
602 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
603 mpc_split_count++;
604 other_pipe = other_pipe->bottom_pipe;
605 }
606 other_pipe = pipe->top_pipe;
607 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
608 mpc_split_count++;
609 other_pipe = other_pipe->top_pipe;
610 }
611
612 return mpc_split_count;
613}
614
228a10d4
AD		 615int get_num_odm_splits(struct pipe_ctx *pipe)
616{
617 int odm_split_count = 0;
618 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
619 while (next_pipe) {
620 odm_split_count++;
621 next_pipe = next_pipe->next_odm_pipe;
622 }
623 pipe = pipe->prev_odm_pipe;
624 while (pipe) {
625 odm_split_count++;
626 pipe = pipe->prev_odm_pipe;
627 }
628 return odm_split_count;
629}
630
5bf24270
DL		 631static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
632{
633 *split_count = get_num_odm_splits(pipe_ctx);
634 *split_idx = 0;
635 if (*split_count == 0) {
636 /*Check for mpc split*/
637 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
638
570bc18c 639 *split_count = get_num_mpc_splits(pipe_ctx);
5bf24270
DL		 640 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
641 (*split_idx)++;
5bf24270
DL		 642 split_pipe = split_pipe->top_pipe;
643 }
5bf24270
DL		 644 } else {
645 /*Get odm split index*/
646 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
647
648 while (split_pipe) {
649 (*split_idx)++;
650 split_pipe = split_pipe->prev_odm_pipe;
651 }
652 }
653}
654
b2d0a103 655static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 656{
3be5262e 657 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 658 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 659 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 660 struct rect surf_src = plane_state->src_rect;
9b6067c0 661 struct rect clip, dest;
87449a90
AK		 662 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
663 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
5bf24270
DL		 664 int split_count = 0;
665 int split_idx = 0;
9b6067c0 666 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 667
5bf24270
DL		 668 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
669
7f5c22d1
VP		 670 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
671 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
5bf24270
DL		 672 split_count = 0;
673 split_idx = 0;
7b779c99 674 }
86006a7f 675
4562236b
HW		 676 /* The actual clip is an intersection between stream
677 * source and surface clip
678 */
9b6067c0 679 dest = plane_state->dst_rect;
3be5262e
HW		 680 clip.x = stream->src.x > plane_state->clip_rect.x ?
681 stream->src.x : plane_state->clip_rect.x;
4562236b 682
1fbd2cfc 683 clip.width = stream->src.x + stream->src.width <
3be5262e 684 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 685 stream->src.x + stream->src.width - clip.x :
3be5262e 686 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 687
3be5262e
HW		 688 clip.y = stream->src.y > plane_state->clip_rect.y ?
689 stream->src.y : plane_state->clip_rect.y;
4562236b 690
1fbd2cfc 691 clip.height = stream->src.y + stream->src.height <
3be5262e 692 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 693 stream->src.y + stream->src.height - clip.y :
3be5262e 694 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 695
9b6067c0
DL		 696 /*
697 * Need to calculate how scan origin is shifted in vp space
698 * to correctly rotate clip and dst
699 */
700 get_vp_scan_direction(
701 plane_state->rotation,
702 plane_state->horizontal_mirror,
703 &orthogonal_rotation,
704 &flip_y_start,
705 &flip_x_start);
706
707 if (orthogonal_rotation) {
708 swap(clip.x, clip.y);
709 swap(clip.width, clip.height);
710 swap(dest.x, dest.y);
711 swap(dest.width, dest.height);
712 }
713 if (flip_x_start) {
714 clip.x = dest.x + dest.width - clip.x - clip.width;
715 dest.x = 0;
716 }
717 if (flip_y_start) {
718 clip.y = dest.y + dest.height - clip.y - clip.height;
719 dest.y = 0;
720 }
721
86006a7f 722 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 723 * num_pixels = clip.num_pix * scl_ratio
724 */
9b6067c0
DL		 725 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
726 data->viewport.width = clip.width * surf_src.width / dest.width;
727
728 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
729 data->viewport.height = clip.height * surf_src.height / dest.height;
730
731 /* Handle split */
5bf24270
DL		 732 if (split_count) {
733 /* extra pixels in the division remainder need to go to pipes after
734 * the extra pixel index minus one(epimo) defined here as:
735 */
736 int epimo = 0;
737
9b6067c0 738 if (orthogonal_rotation) {
5bf24270
DL		 739 if (flip_y_start)
740 split_idx = split_count - split_idx;
741
742 epimo = split_count - data->viewport.height % (split_count + 1);
743
744 data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
745 if (split_idx > epimo)
746 data->viewport.y += split_idx - epimo - 1;
747 data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0 748 } else {
5bf24270
DL		 749 if (flip_x_start)
750 split_idx = split_count - split_idx;
751
752 epimo = split_count - data->viewport.width % (split_count + 1);
753
754 data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
755 if (split_idx > epimo)
756 data->viewport.x += split_idx - epimo - 1;
757 data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0
DL		 758 }
759 }
9b5349f7 760
b2d0a103
DL		 761 /* Round down, compensate in init */
762 data->viewport_c.x = data->viewport.x / vpc_div;
763 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 764 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
765 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
766
b2d0a103
DL		 767 /* Round up, assume original video size always even dimensions */
768 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
769 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
fa90219a
DL		 770
771 data->viewport_unadjusted = data->viewport;
772 data->viewport_c_unadjusted = data->viewport_c;
4562236b
HW		 773}
774
9b6067c0 775static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 776{
3be5262e 777 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 778 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 779 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 780 struct rect surf_clip = plane_state->clip_rect;
5bf24270
DL		 781 bool pri_split_tb = pipe_ctx->bottom_pipe &&
782 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
783 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
784 bool sec_split_tb = pipe_ctx->top_pipe &&
785 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
786 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
787 int split_count = 0;
788 int split_idx = 0;
789
790 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
791
05e3d830
WC		 792 /*
793 * Only the leftmost ODM pipe should be offset by a nonzero distance
794 */
25b31581 795 if (!pipe_ctx->prev_odm_pipe) {
05e3d830 796 data->recout.x = stream->dst.x;
25b31581
WC		 797 if (stream->src.x < surf_clip.x)
798 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
4fa086b9 799 / stream->src.width;
4562236b 800
25b31581
WC		 801 } else
802 data->recout.x = 0;
803
84aef2ab
DL		 804 if (stream->src.x > surf_clip.x)
805 surf_clip.width -= stream->src.x - surf_clip.x;
5bf24270
DL		 806 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
807 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
808 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
4562236b 809
5bf24270 810 data->recout.y = stream->dst.y;
4fa086b9 811 if (stream->src.y < surf_clip.y)
5bf24270 812 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
4fa086b9 813 / stream->src.height;
84aef2ab
DL		 814 else if (stream->src.y > surf_clip.y)
815 surf_clip.height -= stream->src.y - surf_clip.y;
4562236b 816
5bf24270
DL		 817 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
818 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
819 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
b2d0a103 820
9b6067c0 821 /* Handle h & v split, handle rotation using viewport */
5bf24270
DL		 822 if (sec_split_tb) {
823 data->recout.y += data->recout.height / 2;
0c31a821 824 /* Floor primary pipe, ceil 2ndary pipe */
5bf24270
DL		 825 data->recout.height = (data->recout.height + 1) / 2;
826 } else if (pri_split_tb)
827 data->recout.height /= 2;
828 else if (split_count) {
829 /* extra pixels in the division remainder need to go to pipes after
830 * the extra pixel index minus one(epimo) defined here as:
831 */
832 int epimo = split_count - data->recout.width % (split_count + 1);
833
834 /*no recout offset due to odm */
835 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
836 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
837 if (split_idx > epimo)
838 data->recout.x += split_idx - epimo - 1;
839 }
840 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
841 }
4562236b
HW		 842}
843
b2d0a103 844static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 845{
3be5262e 846 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 847 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 848 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 849 const int in_w = stream->src.width;
850 const int in_h = stream->src.height;
851 const int out_w = stream->dst.width;
852 const int out_h = stream->dst.height;
4562236b 853
9b6067c0 854 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 855 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
856 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 857 swap(surf_src.height, surf_src.width);
86006a7f 858
eb0e5154 859 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 860 surf_src.width,
3be5262e 861 plane_state->dst_rect.width);
eb0e5154 862 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 863 surf_src.height,
3be5262e 864 plane_state->dst_rect.height);
4562236b 865
4fa086b9 866 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 867 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 868 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 869 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 870
6702a9ac
HW		 871 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
872 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
873 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
874 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 875
6702a9ac
HW		 876 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
877 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 878
6702a9ac
HW		 879 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
880 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
881 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
882 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 883 }
0002d3ac
DL		 884 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
885 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
886 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
887 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
888 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
889 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
890 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
891 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 892}
893
9b6067c0
DL		 894static inline void adjust_vp_and_init_for_seamless_clip(
895 bool flip_scan_dir,
896 int recout_skip,
897 int src_size,
898 int taps,
899 struct fixed31_32 ratio,
900 struct fixed31_32 *init,
901 int *vp_offset,
902 int *vp_size)
b2d0a103 903{
9b6067c0 904 if (!flip_scan_dir) {
9a08f51f 905 /* Adjust for viewport end clip-off */
9b6067c0
DL		 906 if ((*vp_offset + *vp_size) < src_size) {
907 int vp_clip = src_size - *vp_size - *vp_offset;
908 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 909
910 int_part = int_part > 0 ? int_part : 0;
9b6067c0 911 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 912 }
b2d0a103 913
9a08f51f 914 /* Adjust for non-0 viewport offset */
9b6067c0 915 if (*vp_offset) {
9a08f51f
DL		 916 int int_part;
917
9b6067c0
DL		 918 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
919 int_part = dc_fixpt_floor(*init) - *vp_offset;
920 if (int_part < taps) {
921 int int_adj = *vp_offset >= (taps - int_part) ?
922 (taps - int_part) : *vp_offset;
923 *vp_offset -= int_adj;
924 *vp_size += int_adj;
9a08f51f 925 int_part += int_adj;
9b6067c0
DL		 926 } else if (int_part > taps) {
927 *vp_offset += int_part - taps;
928 *vp_size -= int_part - taps;
929 int_part = taps;
9a08f51f 930 }
9b6067c0
DL		 931 init->value &= 0xffffffff;
932 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 933 }
934 } else {
935 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 936 if (*vp_offset) {
937 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 938
9a08f51f 939 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 940 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
941 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 942 }
b2d0a103 943
9a08f51f 944 /* Adjust for viewport end clip-off */
9b6067c0 945 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 946 int int_part;
9b6067c0 947 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 948
949 /*
950 * this is init if vp had no offset, keep in mind this is from the
951 * right side of vp due to scan direction
952 */
9b6067c0 953 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 954 /*
955 * this is the difference between first pixel of viewport available to read
956 * and init position, takning into account scan direction
957 */
9b6067c0
DL		 958 int_part = dc_fixpt_floor(*init) - end_offset;
959 if (int_part < taps) {
960 int int_adj = end_offset >= (taps - int_part) ?
961 (taps - int_part) : end_offset;
962 *vp_size += int_adj;
9a08f51f 963 int_part += int_adj;
9b6067c0
DL		 964 } else if (int_part > taps) {
965 *vp_size += int_part - taps;
966 int_part = taps;
9a08f51f 967 }
9b6067c0
DL		 968 init->value &= 0xffffffff;
969 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 970 }
b2d0a103 971 }
9b6067c0 972}
9a08f51f 973
9b6067c0
DL		 974static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
975{
976 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
977 const struct dc_stream_state *stream = pipe_ctx->stream;
05e3d830 978 struct pipe_ctx *odm_pipe = pipe_ctx;
9b6067c0
DL		 979 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
980 struct rect src = pipe_ctx->plane_state->src_rect;
981 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
982 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
983 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
984 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
7287a675 985 int odm_idx = 0;
9a08f51f 986
9b6067c0
DL		 987 /*
988 * Need to calculate the scan direction for viewport to make adjustments
989 */
990 get_vp_scan_direction(
991 plane_state->rotation,
992 plane_state->horizontal_mirror,
993 &orthogonal_rotation,
994 &flip_vert_scan_dir,
995 &flip_horz_scan_dir);
996
997 /* Calculate src rect rotation adjusted to recout space */
998 surf_size_h = src.x + src.width;
999 surf_size_v = src.y + src.height;
1000 if (flip_horz_scan_dir)
1001 src.x = 0;
1002 if (flip_vert_scan_dir)
1003 src.y = 0;
1004 if (orthogonal_rotation) {
1005 swap(src.x, src.y);
1006 swap(src.width, src.height);
1007 }
9a08f51f 1008
05e3d830
WC		 1009 /*modified recout_skip_h calculation due to odm having no recout offset*/
1010 while (odm_pipe->prev_odm_pipe) {
1011 odm_idx++;
1012 odm_pipe = odm_pipe->prev_odm_pipe;
1013 }
1014 /*odm_pipe is the leftmost pipe in the ODM group*/
1015 recout_skip_h = odm_idx * data->recout.width;
1016
9b6067c0
DL		 1017 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
1018 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
1019 * - (surf surf_src offset * 1/ full scl ratio))
1020 */
05e3d830
WC		 1021 recout_skip_h += odm_pipe->plane_res.scl_data.recout.x
1022 - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
9b6067c0
DL		 1023 * stream->dst.width / stream->src.width -
1024 src.x * plane_state->dst_rect.width / src.width
1025 * stream->dst.width / stream->src.width);
05e3d830 1026
5bf24270 1027
9b6067c0
DL		 1028 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
1029 * stream->dst.height / stream->src.height -
1030 src.y * plane_state->dst_rect.height / src.height
1031 * stream->dst.height / stream->src.height);
1032 if (orthogonal_rotation)
1033 swap(recout_skip_h, recout_skip_v);
1034 /*
1035 * Init calculated according to formula:
1036 * init = (scaling_ratio + number_of_taps + 1) / 2
1037 * init_bot = init + scaling_ratio
1038 * init_c = init + truncated_vp_c_offset(from calculate viewport)
1039 */
1040 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
1041 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 1042
9b6067c0
DL		 1043 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
1044 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 1045
9b6067c0
DL		 1046 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
1047 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 1048
9b6067c0
DL		 1049 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
1050 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 1051
9b6067c0
DL		 1052 /*
1053 * Taps, inits and scaling ratios are in recout space need to rotate
1054 * to viewport rotation before adjustment
1055 */
1056 adjust_vp_and_init_for_seamless_clip(
1057 flip_horz_scan_dir,
1058 recout_skip_h,
1059 surf_size_h,
1060 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
1061 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
1062 orthogonal_rotation ? &data->inits.v : &data->inits.h,
1063 &data->viewport.x,
1064 &data->viewport.width);
1065 adjust_vp_and_init_for_seamless_clip(
1066 flip_horz_scan_dir,
1067 recout_skip_h,
1068 surf_size_h / vpc_div,
1069 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
1070 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
1071 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
1072 &data->viewport_c.x,
1073 &data->viewport_c.width);
1074 adjust_vp_and_init_for_seamless_clip(
1075 flip_vert_scan_dir,
1076 recout_skip_v,
1077 surf_size_v,
1078 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
1079 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
1080 orthogonal_rotation ? &data->inits.h : &data->inits.v,
1081 &data->viewport.y,
1082 &data->viewport.height);
1083 adjust_vp_and_init_for_seamless_clip(
1084 flip_vert_scan_dir,
1085 recout_skip_v,
1086 surf_size_v / vpc_div,
1087 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
1088 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
1089 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
1090 &data->viewport_c.y,
1091 &data->viewport_c.height);
b2d0a103
DL		 1092
1093 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 1094 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
1095 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 1096
b2d0a103 1097}
3b733278 1098
89d07b66
ST		 1099/*
1100 * When handling 270 rotation in mixed SLS mode, we have
1101 * stream->timing.h_border_left that is non zero. If we are doing
1102 * pipe-splitting, this h_border_left value gets added to recout.x and when it
1103 * calls calculate_inits_and_adj_vp() and
1104 * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
1105 * pipe to be incorrect.
1106 *
1107 * To fix this, instead of using stream->timing.h_border_left, we can use
1108 * stream->dst.x to represent the border instead. So we will set h_border_left
1109 * to 0 and shift the appropriate amount in stream->dst.x. We will then
1110 * perform all calculations in resource_build_scaling_params() based on this
1111 * and then restore the h_border_left and stream->dst.x to their original
1112 * values.
1113 *
1114 * shift_border_left_to_dst() will shift the amount of h_border_left to
1115 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst()
1116 * will restore h_border_left and stream->dst.x back to their original values
1117 * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
1118 * original h_border_left value in its calculation.
1119 */
c88855f3 1120static int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
89d07b66
ST		 1121{
1122 int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
1123
1124 if (store_h_border_left) {
1125 pipe_ctx->stream->timing.h_border_left = 0;
1126 pipe_ctx->stream->dst.x += store_h_border_left;
1127 }
1128 return store_h_border_left;
1129}
1130
c88855f3
LJ		 1131static void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
1132 int store_h_border_left)
89d07b66
ST		 1133{
1134 pipe_ctx->stream->dst.x -= store_h_border_left;
1135 pipe_ctx->stream->timing.h_border_left = store_h_border_left;
1136}
1137
b2d0a103 1138bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 1139{
3be5262e 1140 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 1141 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 1142 bool res = false;
89d07b66 1143 int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
5d4b05dd 1144 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 1145 /* Important: scaling ratio calculation requires pixel format,
1146 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 1147 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 1148 */
6702a9ac 1149 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 1150 pipe_ctx->plane_state->format);
b2d0a103
DL		 1151
1152 calculate_scaling_ratios(pipe_ctx);
4562236b 1153
b2d0a103 1154 calculate_viewport(pipe_ctx);
4562236b 1155
40d916a2
NC		 1156 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
1157 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) {
89d07b66
ST		 1158 if (store_h_border_left) {
1159 restore_border_left_from_dst(pipe_ctx,
1160 store_h_border_left);
1161 }
4562236b 1162 return false;
89d07b66 1163 }
4562236b 1164
9b6067c0 1165 calculate_recout(pipe_ctx);
4562236b
HW		 1166
1167 /**
1168 * Setting line buffer pixel depth to 24bpp yields banding
1169 * on certain displays, such as the Sharp 4k
1170 */
6702a9ac 1171 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
33eef72f 1172 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
4562236b 1173
199e458a 1174 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1175 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1176
89d07b66
ST		 1177 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1178 store_h_border_left + timing->h_border_right;
1179 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1180 timing->v_border_top + timing->v_border_bottom;
5bf24270
DL		 1181 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1182 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1b6c8067 1183
4562236b 1184 /* Taps calculations */
d94585a0
YHL		 1185 if (pipe_ctx->plane_res.xfm != NULL)
1186 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1187 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1188
1189 if (pipe_ctx->plane_res.dpp != NULL)
1190 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1191 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1192
f7938bc0 1193
4562236b
HW		 1194 if (!res) {
1195 /* Try 24 bpp linebuffer */
6702a9ac 1196 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1197
1b6c8067
BL		 1198 if (pipe_ctx->plane_res.xfm != NULL)
1199 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1200 pipe_ctx->plane_res.xfm,
1201 &pipe_ctx->plane_res.scl_data,
1202 &plane_state->scaling_quality);
1203
1204 if (pipe_ctx->plane_res.dpp != NULL)
1205 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1206 pipe_ctx->plane_res.dpp,
1207 &pipe_ctx->plane_res.scl_data,
1208 &plane_state->scaling_quality);
4562236b
HW		 1209 }
1210
b2d0a103 1211 if (res)
1fbd2cfc 1212 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1213 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1214
3c0dcf9f
DL		 1215 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1216 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1217 __func__,
1218 pipe_ctx->pipe_idx,
1219 pipe_ctx->plane_res.scl_data.viewport.height,
1220 pipe_ctx->plane_res.scl_data.viewport.width,
1221 pipe_ctx->plane_res.scl_data.viewport.x,
1222 pipe_ctx->plane_res.scl_data.viewport.y,
1223 pipe_ctx->plane_res.scl_data.recout.height,
1224 pipe_ctx->plane_res.scl_data.recout.width,
1225 pipe_ctx->plane_res.scl_data.recout.x,
1226 pipe_ctx->plane_res.scl_data.recout.y,
1227 pipe_ctx->plane_res.scl_data.h_active,
1228 pipe_ctx->plane_res.scl_data.v_active,
1229 plane_state->src_rect.height,
1230 plane_state->src_rect.width,
1231 plane_state->src_rect.x,
1232 plane_state->src_rect.y,
1233 plane_state->dst_rect.height,
1234 plane_state->dst_rect.width,
1235 plane_state->dst_rect.x,
1236 plane_state->dst_rect.y,
1237 plane_state->clip_rect.height,
1238 plane_state->clip_rect.width,
1239 plane_state->clip_rect.x,
1240 plane_state->clip_rect.y);
4562236b 1241
89d07b66
ST		 1242 if (store_h_border_left)
1243 restore_border_left_from_dst(pipe_ctx, store_h_border_left);
1244
4562236b
HW		 1245 return res;
1246}
1247
1248
1249enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1250 const struct dc *dc,
608ac7bb 1251 struct dc_state *context)
4562236b
HW		 1252{
1253 int i;
1254
1255 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1256 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1257 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1258 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1259 return DC_FAIL_SCALING;
4562236b
HW		 1260 }
1261
1262 return DC_OK;
1263}
1264
a2b8659d
TC		 1265struct pipe_ctx *find_idle_secondary_pipe(
1266 struct resource_context *res_ctx,
5581192d
JL		 1267 const struct resource_pool *pool,
1268 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1269{
1270 int i;
1271 struct pipe_ctx *secondary_pipe = NULL;
1272
1273 /*
5581192d
JL		 1274 * We add a preferred pipe mapping to avoid the chance that
1275 * MPCCs already in use will need to be reassigned to other trees.
1276 * For example, if we went with the strict, assign backwards logic:
1277 *
1278 * (State 1)
1279 * Display A on, no surface, top pipe = 0
1280 * Display B on, no surface, top pipe = 1
1281 *
1282 * (State 2)
1283 * Display A on, no surface, top pipe = 0
1284 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1285 *
1286 * (State 3)
1287 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1288 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1289 *
1290 * The state 2->3 transition requires remapping MPCC 5 from display B
1291 * to display A.
1292 *
1293 * However, with the preferred pipe logic, state 2 would look like:
1294 *
1295 * (State 2)
1296 * Display A on, no surface, top pipe = 0
1297 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1298 *
1299 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1300 */
5581192d
JL		 1301 if (primary_pipe) {
1302 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1303 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1304 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1305 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1306 }
1307 }
1308
5581192d
JL		 1309 /*
1310 * search backwards for the second pipe to keep pipe
1311 * assignment more consistent
1312 */
1313 if (!secondary_pipe)
1314 for (i = pool->pipe_count - 1; i >= 0; i--) {
1315 if (res_ctx->pipe_ctx[i].stream == NULL) {
1316 secondary_pipe = &res_ctx->pipe_ctx[i];
1317 secondary_pipe->pipe_idx = i;
1318 break;
1319 }
1320 }
4562236b
HW		 1321
1322 return secondary_pipe;
1323}
1324
1325struct pipe_ctx *resource_get_head_pipe_for_stream(
1326 struct resource_context *res_ctx,
0971c40e 1327 struct dc_stream_state *stream)
4562236b
HW		 1328{
1329 int i;
22498036 1330
a2b8659d 1331 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL		 1332 if (res_ctx->pipe_ctx[i].stream == stream
1333 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1334 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1335 return &res_ctx->pipe_ctx[i];
4562236b
HW		 1336 }
1337 return NULL;
1338}
1339
b1f6d01c 1340static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1341 struct resource_context *res_ctx,
b1f6d01c 1342 struct pipe_ctx *head_pipe)
19f89e23 1343{
b1f6d01c 1344 struct pipe_ctx *tail_pipe;
19f89e23
AG		 1345
1346 tail_pipe = head_pipe->bottom_pipe;
1347
1348 while (tail_pipe) {
1349 head_pipe = tail_pipe;
1350 tail_pipe = tail_pipe->bottom_pipe;
1351 }
1352
1353 return head_pipe;
1354}
1355
4562236b 1356/*
ab2541b6
AC		 1357 * A free_pipe for a stream is defined here as a pipe
1358 * that has no surface attached yet
4562236b 1359 */
b1f6d01c 1360static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1361 struct dc_state *context,
a2b8659d 1362 const struct resource_pool *pool,
b1f6d01c 1363 struct pipe_ctx *head_pipe)
4562236b
HW		 1364{
1365 int i;
745cc746 1366 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1367
3be5262e 1368 if (!head_pipe->plane_state)
4562236b
HW		 1369 return head_pipe;
1370
1371 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1372 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1373 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1374 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1375 return &res_ctx->pipe_ctx[i];
1376 }
1377 }
1378
1379 /*
1380 * At this point we have no re-useable pipe for this stream and we need
1381 * to acquire an idle one to satisfy the request
1382 */
1383
a2b8659d 1384 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1385 return NULL;
1386
b1f6d01c 1387 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW		 1388}
1389
b86a1aa3 1390#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL		 1391static int acquire_first_split_pipe(
1392 struct resource_context *res_ctx,
1393 const struct resource_pool *pool,
0971c40e 1394 struct dc_stream_state *stream)
0f9a536f
DL		 1395{
1396 int i;
1397
1398 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1399 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1400
b1f6d01c 1401 if (split_pipe->top_pipe &&
79592db3
DL		 1402 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1403 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1404 if (split_pipe->bottom_pipe)
1405 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1406
1407 if (split_pipe->top_pipe->plane_state)
1408 resource_build_scaling_params(split_pipe->top_pipe);
1409
1410 memset(split_pipe, 0, sizeof(*split_pipe));
1411 split_pipe->stream_res.tg = pool->timing_generators[i];
1412 split_pipe->plane_res.hubp = pool->hubps[i];
1413 split_pipe->plane_res.ipp = pool->ipps[i];
1414 split_pipe->plane_res.dpp = pool->dpps[i];
1415 split_pipe->stream_res.opp = pool->opps[i];
1416 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1417 split_pipe->pipe_idx = i;
1418
1419 split_pipe->stream = stream;
0f9a536f
DL		 1420 return i;
1421 }
1422 }
1423 return -1;
1424}
1425#endif
1426
19f89e23
AG		 1427bool dc_add_plane_to_context(
1428 const struct dc *dc,
0971c40e 1429 struct dc_stream_state *stream,
19f89e23 1430 struct dc_plane_state *plane_state,
608ac7bb 1431 struct dc_state *context)
4562236b
HW		 1432{
1433 int i;
19f89e23
AG		 1434 struct resource_pool *pool = dc->res_pool;
1435 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1436 struct dc_stream_status *stream_status = NULL;
4562236b 1437
19f89e23
AG		 1438 for (i = 0; i < context->stream_count; i++)
1439 if (context->streams[i] == stream) {
1440 stream_status = &context->stream_status[i];
1441 break;
1442 }
1443 if (stream_status == NULL) {
1444 dm_error("Existing stream not found; failed to attach surface!\n");
1445 return false;
1446 }
1447
4562236b 1448
19f89e23
AG		 1449 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1450 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1451 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1452 return false;
1453 }
1454
19f89e23
AG		 1455 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1456
1457 if (!head_pipe) {
1458 dm_error("Head pipe not found for stream_state %p !\n", stream);
1459 return false;
1460 }
1461
b1f6d01c
DL		 1462 /* retain new surface, but only once per stream */
1463 dc_plane_state_retain(plane_state);
00737c59 1464
b1f6d01c 1465 while (head_pipe) {
b1f6d01c 1466 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1467
b86a1aa3 1468 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL		 1469 if (!free_pipe) {
1470 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1471 if (pipe_idx >= 0)
1472 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1473 }
1474 #endif
1475 if (!free_pipe) {
1476 dc_plane_state_release(plane_state);
1477 return false;
1478 }
19f89e23 1479
b1f6d01c
DL		 1480 free_pipe->plane_state = plane_state;
1481
1482 if (head_pipe != free_pipe) {
5b5c1777
JP		 1483 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1484 ASSERT(tail_pipe);
b1f6d01c
DL		 1485 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1486 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1487 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1488 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1489 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1490 free_pipe->clock_source = tail_pipe->clock_source;
1491 free_pipe->top_pipe = tail_pipe;
1492 tail_pipe->bottom_pipe = free_pipe;
2e7b43e6
DL		 1493 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1494 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1495 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1496 }
1497 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1498 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1499 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1500 }
b1f6d01c
DL		 1501 }
1502 head_pipe = head_pipe->next_odm_pipe;
1503 }
19f89e23
AG		 1504 /* assign new surfaces*/
1505 stream_status->plane_states[stream_status->plane_count] = plane_state;
1506
1507 stream_status->plane_count++;
1508
1509 return true;
1510}
1511
1512bool dc_remove_plane_from_context(
1513 const struct dc *dc,
1514 struct dc_stream_state *stream,
1515 struct dc_plane_state *plane_state,
608ac7bb 1516 struct dc_state *context)
19f89e23
AG		 1517{
1518 int i;
1519 struct dc_stream_status *stream_status = NULL;
1520 struct resource_pool *pool = dc->res_pool;
1521
ab2541b6 1522 for (i = 0; i < context->stream_count; i++)
4fa086b9 1523 if (context->streams[i] == stream) {
ab2541b6 1524 stream_status = &context->stream_status[i];
4562236b
HW		 1525 break;
1526 }
19f89e23 1527
ab2541b6 1528 if (stream_status == NULL) {
19f89e23 1529 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1530 return false;
1531 }
1532
19f89e23
AG		 1533 /* release pipe for plane*/
1534 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1535 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1536
6ffaa6fc 1537 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG		 1538 if (pipe_ctx->top_pipe)
1539 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1540
19f89e23
AG		 1541 /* Second condition is to avoid setting NULL to top pipe
1542 * of tail pipe making it look like head pipe in subsequent
1543 * deletes
1544 */
1545 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1546 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1547
19f89e23
AG		 1548 /*
1549 * For head pipe detach surfaces from pipe for tail
1550 * pipe just zero it out
1551 */
b1f6d01c 1552 if (!pipe_ctx->top_pipe)
19f89e23 1553 pipe_ctx->plane_state = NULL;
b1f6d01c 1554 else
19f89e23 1555 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1556 }
19f89e23 1557 }
4562236b 1558
4562236b 1559
19f89e23
AG		 1560 for (i = 0; i < stream_status->plane_count; i++) {
1561 if (stream_status->plane_states[i] == plane_state) {
1562
1563 dc_plane_state_release(stream_status->plane_states[i]);
1564 break;
4562236b 1565 }
19f89e23 1566 }
4562236b 1567
19f89e23
AG		 1568 if (i == stream_status->plane_count) {
1569 dm_error("Existing plane_state not found; failed to detach it!\n");
1570 return false;
4562236b
HW		 1571 }
1572
19f89e23 1573 stream_status->plane_count--;
4562236b 1574
abb4986e
AJ		 1575 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1576 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1577 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1578
1579 stream_status->plane_states[stream_status->plane_count] = NULL;
1580
1581 return true;
1582}
1583
1584bool dc_rem_all_planes_for_stream(
1585 const struct dc *dc,
1586 struct dc_stream_state *stream,
608ac7bb 1587 struct dc_state *context)
19f89e23
AG		 1588{
1589 int i, old_plane_count;
1590 struct dc_stream_status *stream_status = NULL;
1591 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1592
1593 for (i = 0; i < context->stream_count; i++)
1594 if (context->streams[i] == stream) {
1595 stream_status = &context->stream_status[i];
1596 break;
1597 }
1598
1599 if (stream_status == NULL) {
1600 dm_error("Existing stream %p not found!\n", stream);
1601 return false;
1602 }
1603
1604 old_plane_count = stream_status->plane_count;
1605
1606 for (i = 0; i < old_plane_count; i++)
1607 del_planes[i] = stream_status->plane_states[i];
1608
1609 for (i = 0; i < old_plane_count; i++)
1610 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1611 return false;
1612
1613 return true;
1614}
1615
1616static bool add_all_planes_for_stream(
1617 const struct dc *dc,
1618 struct dc_stream_state *stream,
1619 const struct dc_validation_set set[],
1620 int set_count,
608ac7bb 1621 struct dc_state *context)
19f89e23
AG		 1622{
1623 int i, j;
1624
1625 for (i = 0; i < set_count; i++)
1626 if (set[i].stream == stream)
1627 break;
1628
1629 if (i == set_count) {
1630 dm_error("Stream %p not found in set!\n", stream);
1631 return false;
1632 }
4562236b 1633
19f89e23
AG		 1634 for (j = 0; j < set[i].plane_count; j++)
1635 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1636 return false;
4562236b
HW		 1637
1638 return true;
1639}
1640
19f89e23
AG		 1641bool dc_add_all_planes_for_stream(
1642 const struct dc *dc,
1643 struct dc_stream_state *stream,
1644 struct dc_plane_state * const *plane_states,
1645 int plane_count,
608ac7bb 1646 struct dc_state *context)
19f89e23
AG		 1647{
1648 struct dc_validation_set set;
1649 int i;
1650
1651 set.stream = stream;
1652 set.plane_count = plane_count;
1653
1654 for (i = 0; i < plane_count; i++)
1655 set.plane_states[i] = plane_states[i];
1656
1657 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1658}
1659
0971c40e
HW		 1660static bool is_timing_changed(struct dc_stream_state *cur_stream,
1661 struct dc_stream_state *new_stream)
4562236b
HW		 1662{
1663 if (cur_stream == NULL)
1664 return true;
1665
1666 /* If sink pointer changed, it means this is a hotplug, we should do
1667 * full hw setting.
1668 */
1669 if (cur_stream->sink != new_stream->sink)
1670 return true;
1671
1672 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1673 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1674 return true;
1675
1676 return memcmp(
4fa086b9
LSL		 1677 &cur_stream->timing,
1678 &new_stream->timing,
4562236b
HW		 1679 sizeof(struct dc_crtc_timing)) != 0;
1680}
1681
1682static bool are_stream_backends_same(
0971c40e 1683 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1684{
1685 if (stream_a == stream_b)
1686 return true;
1687
1688 if (stream_a == NULL || stream_b == NULL)
1689 return false;
1690
1691 if (is_timing_changed(stream_a, stream_b))
1692 return false;
1693
1e7e86c4
ST		 1694 if (stream_a->dpms_off != stream_b->dpms_off)
1695 return false;
1696
4562236b
HW		 1697 return true;
1698}
1699
625a15bf 1700/*
2119aa17
DF		 1701 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1702 *
1703 * Checks if there a difference between the two states
1704 * that would require a mode change.
1705 *
1706 * Does not compare cursor position or attributes.
1707 */
d54d29db 1708bool dc_is_stream_unchanged(
0971c40e 1709 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1710{
4562236b 1711
ab2541b6
AC		 1712 if (!are_stream_backends_same(old_stream, stream))
1713 return false;
4562236b 1714
0460f9ab
JL		 1715 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1716 return false;
1717
4562236b
HW		 1718 return true;
1719}
1720
625a15bf 1721/*
2119aa17
DF		 1722 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1723 */
9a5d9c48
LSL		 1724bool dc_is_stream_scaling_unchanged(
1725 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1726{
1727 if (old_stream == stream)
1728 return true;
1729
1730 if (old_stream == NULL || stream == NULL)
1731 return false;
1732
1733 if (memcmp(&old_stream->src,
1734 &stream->src,
1735 sizeof(struct rect)) != 0)
1736 return false;
1737
1738 if (memcmp(&old_stream->dst,
1739 &stream->dst,
1740 sizeof(struct rect)) != 0)
1741 return false;
1742
1743 return true;
1744}
1745
1dc90497 1746static void update_stream_engine_usage(
4562236b 1747 struct resource_context *res_ctx,
a2b8659d 1748 const struct resource_pool *pool,
1dc90497
AG		 1749 struct stream_encoder *stream_enc,
1750 bool acquired)
4562236b
HW		 1751{
1752 int i;
1753
a2b8659d
TC		 1754 for (i = 0; i < pool->stream_enc_count; i++) {
1755 if (pool->stream_enc[i] == stream_enc)
1dc90497 1756 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1757 }
1758}
1759
1760/* TODO: release audio object */
4176664b 1761void update_audio_usage(
4562236b 1762 struct resource_context *res_ctx,
a2b8659d 1763 const struct resource_pool *pool,
1dc90497
AG		 1764 struct audio *audio,
1765 bool acquired)
4562236b
HW		 1766{
1767 int i;
a2b8659d
TC		 1768 for (i = 0; i < pool->audio_count; i++) {
1769 if (pool->audios[i] == audio)
1dc90497 1770 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1771 }
1772}
1773
1774static int acquire_first_free_pipe(
1775 struct resource_context *res_ctx,
a2b8659d 1776 const struct resource_pool *pool,
0971c40e 1777 struct dc_stream_state *stream)
4562236b
HW		 1778{
1779 int i;
1780
a2b8659d 1781 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1782 if (!res_ctx->pipe_ctx[i].stream) {
1783 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1784
6b670fa9 1785 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1786 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1787 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1788 pipe_ctx->plane_res.ipp = pool->ipps[i];
1789 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1790 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1791 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1792 if (pool->dpps[i])
1793 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1794 pipe_ctx->pipe_idx = i;
1795
ff5ef992 1796
4562236b
HW		 1797 pipe_ctx->stream = stream;
1798 return i;
1799 }
1800 }
1801 return -1;
1802}
1803
a2b8659d
TC		 1804static struct audio *find_first_free_audio(
1805 struct resource_context *res_ctx,
cfb071f7 1806 const struct resource_pool *pool,
f24b0522
PH		 1807 enum engine_id id,
1808 enum dce_version dc_version)
4562236b 1809{
b5a41620
CL		 1810 int i, available_audio_count;
1811
1812 available_audio_count = pool->audio_count;
1813
1814 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1815 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1816 /*we have enough audio endpoint, find the matching inst*/
1817 if (id != i)
1818 continue;
66bfd4fd 1819 return pool->audios[i];
4562236b 1820 }
66bfd4fd 1821 }
5feb9f07 1822
b5a41620
CL		 1823 /* use engine id to find free audio */
1824 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM		 1825 return pool->audios[id];
1826 }
66bfd4fd 1827 /*not found the matching one, first come first serve*/
b5a41620 1828 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL		 1829 if (res_ctx->is_audio_acquired[i] == false) {
1830 return pool->audios[i];
4176664b
CL		 1831 }
1832 }
4562236b
HW		 1833 return 0;
1834}
1835
625a15bf 1836/*
2119aa17
DF		 1837 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1838 */
13ab1b44 1839enum dc_status dc_add_stream_to_ctx(
1dc90497 1840 struct dc *dc,
608ac7bb 1841 struct dc_state *new_ctx,
1dc90497
AG		 1842 struct dc_stream_state *stream)
1843{
1dc90497 1844 enum dc_status res;
eb9714a2 1845 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1846
ece4147f 1847 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1848 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1849 return DC_ERROR_UNEXPECTED;
1850 }
1851
1852 new_ctx->streams[new_ctx->stream_count] = stream;
1853 dc_stream_retain(stream);
1854 new_ctx->stream_count++;
1855
1856 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1857 if (res != DC_OK)
eb9714a2 1858 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1859
13ab1b44 1860 return res;
1dc90497
AG		 1861}
1862
625a15bf 1863/*
2119aa17
DF		 1864 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1865 */
62c933f9 1866enum dc_status dc_remove_stream_from_ctx(
1dc90497 1867 struct dc *dc,
608ac7bb 1868 struct dc_state *new_ctx,
1dc90497
AG		 1869 struct dc_stream_state *stream)
1870{
19f89e23 1871 int i;
1dc90497 1872 struct dc_context *dc_ctx = dc->ctx;
22498036
DL		 1873 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1874 struct pipe_ctx *odm_pipe;
1dc90497
AG		 1875
1876 if (!del_pipe) {
1877 DC_ERROR("Pipe not found for stream %p !\n", stream);
1878 return DC_ERROR_UNEXPECTED;
1879 }
1880
22498036
DL		 1881 odm_pipe = del_pipe->next_odm_pipe;
1882
1883 /* Release primary pipe */
1884 ASSERT(del_pipe->stream_res.stream_enc);
1885 update_stream_engine_usage(
1886 &new_ctx->res_ctx,
1887 dc->res_pool,
1888 del_pipe->stream_res.stream_enc,
1889 false);
1890
1891 if (del_pipe->stream_res.audio)
1892 update_audio_usage(
1893 &new_ctx->res_ctx,
1894 dc->res_pool,
1895 del_pipe->stream_res.audio,
1896 false);
1897
1898 resource_unreference_clock_source(&new_ctx->res_ctx,
1899 dc->res_pool,
1900 del_pipe->clock_source);
1901
1902 if (dc->res_pool->funcs->remove_stream_from_ctx)
1903 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1904
1905 while (odm_pipe) {
1906 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1907
1908 memset(odm_pipe, 0, sizeof(*odm_pipe));
1909 odm_pipe = next_odm_pipe;
1910 }
1911 memset(del_pipe, 0, sizeof(*del_pipe));
1912
1dc90497
AG		 1913 for (i = 0; i < new_ctx->stream_count; i++)
1914 if (new_ctx->streams[i] == stream)
1915 break;
1916
1917 if (new_ctx->streams[i] != stream) {
1918 DC_ERROR("Context doesn't have stream %p !\n", stream);
1919 return DC_ERROR_UNEXPECTED;
1920 }
1921
1922 dc_stream_release(new_ctx->streams[i]);
1923 new_ctx->stream_count--;
1924
1dc90497
AG		 1925 /* Trim back arrays */
1926 for (; i < new_ctx->stream_count; i++) {
1927 new_ctx->streams[i] = new_ctx->streams[i + 1];
1928 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1929 }
1930
1931 new_ctx->streams[new_ctx->stream_count] = NULL;
1932 memset(
1933 &new_ctx->stream_status[new_ctx->stream_count],
1934 0,
1935 sizeof(new_ctx->stream_status[0]));
1936
1937 return DC_OK;
1938}
1939
0971c40e
HW		 1940static struct dc_stream_state *find_pll_sharable_stream(
1941 struct dc_stream_state *stream_needs_pll,
608ac7bb 1942 struct dc_state *context)
4562236b 1943{
ab2541b6 1944 int i;
4562236b 1945
ab2541b6 1946 for (i = 0; i < context->stream_count; i++) {
0971c40e 1947 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1948
ab2541b6
AC		 1949 /* We are looking for non dp, non virtual stream */
1950 if (resource_are_streams_timing_synchronizable(
1951 stream_needs_pll, stream_has_pll)
1952 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1953 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1954 != SIGNAL_TYPE_VIRTUAL)
1955 return stream_has_pll;
4562236b 1956
4562236b
HW		 1957 }
1958
1959 return NULL;
1960}
1961
1962static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1963{
380604e2 1964 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1965 uint32_t normalized_pix_clk = pix_clk;
1966
1967 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1968 pix_clk /= 2;
cc4d99b8
CL		 1969 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1970 switch (timing->display_color_depth) {
8897810a 1971 case COLOR_DEPTH_666:
cc4d99b8
CL		 1972 case COLOR_DEPTH_888:
1973 normalized_pix_clk = pix_clk;
1974 break;
1975 case COLOR_DEPTH_101010:
1976 normalized_pix_clk = (pix_clk * 30) / 24;
1977 break;
1978 case COLOR_DEPTH_121212:
1979 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1980 break;
cc4d99b8
CL		 1981 case COLOR_DEPTH_161616:
1982 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1983 break;
cc4d99b8
CL		 1984 default:
1985 ASSERT(0);
4562236b 1986 break;
cc4d99b8 1987 }
4562236b 1988 }
4562236b
HW		 1989 return normalized_pix_clk;
1990}
1991
0971c40e 1992static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1993{
9345d987
AG		 1994 /* update actual pixel clock on all streams */
1995 if (dc_is_hdmi_signal(stream->signal))
1996 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1997 &stream->timing) / 10;
9345d987
AG		 1998 else
1999 stream->phy_pix_clk =
380604e2 2000 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 2001
2002 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2003 stream->phy_pix_clk *= 2;
4562236b
HW		 2004}
2005
d2d7885f
AK		 2006static int acquire_resource_from_hw_enabled_state(
2007 struct resource_context *res_ctx,
2008 const struct resource_pool *pool,
2009 struct dc_stream_state *stream)
2010{
2011 struct dc_link *link = stream->link;
08b66279 2012 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK		 2013
2014 /* Check for enabled DIG to identify enabled display */
2015 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2016 return -1;
2017
5ec43eda 2018 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 2019
7f7652ee 2020 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 2021 return -1;
d2d7885f 2022
7f7652ee
ML		 2023 for (i = 0; i < pool->stream_enc_count; i++) {
2024 if (pool->stream_enc[i]->id == inst) {
2025 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2026 pool->stream_enc[i]);
2027 break;
2028 }
2029 }
5ec43eda 2030
7f7652ee
ML		 2031 // tg_inst not found
2032 if (i == pool->stream_enc_count)
75441d9d 2033 return -1;
5ec43eda
ML		 2034
2035 if (tg_inst >= pool->timing_generator_count)
75441d9d 2036 return -1;
5ec43eda
ML		 2037
2038 if (!res_ctx->pipe_ctx[tg_inst].stream) {
2039 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2040
2041 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2042 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
2043 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
2044 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
2045 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
2046 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
2047 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 2048
ccce745c 2049 if (pool->dpps[tg_inst]) {
5ec43eda 2050 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
ccce745c
ML		 2051
2052 // Read DPP->MPCC->OPP Pipe from HW State
2053 if (pool->mpc->funcs->read_mpcc_state) {
2054 struct mpcc_state s = {0};
2055
2056 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2057
2058 if (s.dpp_id < MAX_MPCC)
2059 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
2060
2061 if (s.bot_mpcc_id < MAX_MPCC)
2062 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2063 &pool->mpc->mpcc_array[s.bot_mpcc_id];
2064
2065 if (s.opp_id < MAX_OPP)
2066 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2067 }
2068 }
5ec43eda 2069 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK		 2070
2071 pipe_ctx->stream = stream;
5ec43eda 2072 return tg_inst;
d2d7885f
AK		 2073 }
2074
2075 return -1;
2076}
2077
96b5e3e1
RY		 2078static void mark_seamless_boot_stream(
2079 const struct dc *dc,
2080 struct dc_stream_state *stream)
2081{
2082 struct dc_bios *dcb = dc->ctx->dc_bios;
2083
2084 /* TODO: Check Linux */
2085 if (dc->config.allow_seamless_boot_optimization &&
2086 !dcb->funcs->is_accelerated_mode(dcb)) {
2087 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2088 stream->apply_seamless_boot_optimization = true;
2089 }
2090}
2091
4562236b 2092enum dc_status resource_map_pool_resources(
fb3466a4 2093 const struct dc *dc,
608ac7bb 2094 struct dc_state *context,
1dc90497 2095 struct dc_stream_state *stream)
4562236b 2096{
a2b8659d 2097 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 2098 int i;
2099 struct dc_context *dc_ctx = dc->ctx;
2100 struct pipe_ctx *pipe_ctx = NULL;
2101 int pipe_idx = -1;
4562236b 2102
08e1c28d
YMM		 2103 calculate_phy_pix_clks(stream);
2104
96b5e3e1 2105 mark_seamless_boot_stream(dc, stream);
46570f09 2106
96b5e3e1 2107 if (stream->apply_seamless_boot_optimization) {
d2d7885f
AK		 2108 pipe_idx = acquire_resource_from_hw_enabled_state(
2109 &context->res_ctx,
2110 pool,
2111 stream);
96b5e3e1
RY		 2112 if (pipe_idx < 0)
2113 /* hw resource was assigned to other stream */
2114 stream->apply_seamless_boot_optimization = false;
2115 }
d2d7885f
AK		 2116
2117 if (pipe_idx < 0)
2118 /* acquire new resources */
2119 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 2120
b86a1aa3 2121#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 2122 if (pipe_idx < 0)
13ab1b44 2123 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 2124#endif
13ab1b44 2125
c5b38aec 2126 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 2127 return DC_NO_CONTROLLER_RESOURCE;
2128
2129 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2130
2131 pipe_ctx->stream_res.stream_enc =
78cc70b1 2132 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 2133 &context->res_ctx, pool, stream);
2134
2135 if (!pipe_ctx->stream_res.stream_enc)
38684e46 2136 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 2137
2138 update_stream_engine_usage(
2139 &context->res_ctx, pool,
2140 pipe_ctx->stream_res.stream_enc,
2141 true);
2142
2143 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2144 if (!stream->converter_disable_audio &&
1dc90497 2145 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2146 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2147 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 2148 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG		 2149
2150 /*
2151 * Audio assigned in order first come first get.
2152 * There are asics which has number of audio
2153 * resources less then number of pipes
2154 */
2155 if (pipe_ctx->stream_res.audio)
2156 update_audio_usage(&context->res_ctx, pool,
2157 pipe_ctx->stream_res.audio, true);
2158 }
268cadbd 2159
9aef1a31 2160 /* Add ABM to the resource if on EDP */
5dba4991 2161 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
20f2ffe5 2162#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 2163 if (pool->abm)
2164 pipe_ctx->stream_res.abm = pool->abm;
2165 else
2166 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2167#else
9aef1a31 2168 pipe_ctx->stream_res.abm = pool->abm;
5dba4991
BL		 2169#endif
2170 }
9aef1a31 2171
1dc90497
AG		 2172 for (i = 0; i < context->stream_count; i++)
2173 if (context->streams[i] == stream) {
2174 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3f0940f8 2175 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
5fdb7c4c
NK		 2176 context->stream_status[i].audio_inst =
2177 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2178
1dc90497
AG		 2179 return DC_OK;
2180 }
4562236b 2181
1dc90497
AG		 2182 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2183 return DC_ERROR_UNEXPECTED;
2184}
4562236b 2185
2119aa17
DF		 2186/**
2187 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2188 * Is a shallow copy. Increments refcounts on existing streams and planes.
2189 * @dc: copy out of dc->current_state
2190 * @dst_ctx: copy into this
2191 */
f36cc577 2192void dc_resource_state_copy_construct_current(
1dc90497 2193 const struct dc *dc,
608ac7bb 2194 struct dc_state *dst_ctx)
1dc90497 2195{
f36cc577 2196 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2197}
2198
ab8db3e1
AG		 2199
2200void dc_resource_state_construct(
2201 const struct dc *dc,
2202 struct dc_state *dst_ctx)
2203{
dc88b4a6 2204 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2205}
2206
6d822156
NC		 2207
2208bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2209{
2210 return dc->res_pool->res_cap->num_dsc > 0;
2211}
2212
2213
2119aa17
DF		 2214/**
2215 * dc_validate_global_state() - Determine if HW can support a given state
2216 * Checks HW resource availability and bandwidth requirement.
2217 * @dc: dc struct for this driver
2218 * @new_ctx: state to be validated
afcd526b 2219 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2220 *
2221 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2222 */
e750d56d 2223enum dc_status dc_validate_global_state(
1dc90497 2224 struct dc *dc,
afcd526b
JA		 2225 struct dc_state *new_ctx,
2226 bool fast_validate)
4562236b 2227{
1dc90497 2228 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2229 int i, j;
4562236b 2230
e41ab030
HW		 2231 if (!new_ctx)
2232 return DC_ERROR_UNEXPECTED;
2233
d596e5d0 2234 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2235 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2236 if (result != DC_OK)
2237 return result;
d596e5d0 2238 }
4562236b 2239
e41ab030 2240 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2241 struct dc_stream_state *stream = new_ctx->streams[i];
2242
2243 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2244 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2245
2246 if (pipe_ctx->stream != stream)
2247 continue;
2248
8d8c82b6 2249 if (dc->res_pool->funcs->patch_unknown_plane_state &&
74eac5f3
SSC		 2250 pipe_ctx->plane_state &&
2251 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
8d8c82b6 2252 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
74eac5f3
SSC		 2253 if (result != DC_OK)
2254 return result;
2255 }
2256
1dc90497
AG		 2257 /* Switch to dp clock source only if there is
2258 * no non dp stream that shares the same timing
2259 * with the dp stream.
2260 */
2261 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2262 !find_pll_sharable_stream(stream, new_ctx)) {
2263
9d0dcecd 2264 resource_unreference_clock_source(
1dc90497
AG		 2265 &new_ctx->res_ctx,
2266 dc->res_pool,
9d0dcecd 2267 pipe_ctx->clock_source);
4a629536 2268
1dc90497
AG		 2269 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2270 resource_reference_clock_source(
2271 &new_ctx->res_ctx,
2272 dc->res_pool,
2273 pipe_ctx->clock_source);
2274 }
2275 }
2276 }
2277
1dc90497
AG		 2278 result = resource_build_scaling_params_for_context(dc, new_ctx);
2279
2280 if (result == DC_OK)
afcd526b 2281 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2282 result = DC_FAIL_BANDWIDTH_VALIDATE;
2283
2284 return result;
4562236b
HW		 2285}
2286
6e4d6bee 2287static void patch_gamut_packet_checksum(
e09b6473 2288 struct dc_info_packet *gamut_packet)
4562236b 2289{
4562236b 2290 /* For gamut we recalc checksum */
6e4d6bee 2291 if (gamut_packet->valid) {
4562236b
HW		 2292 uint8_t chk_sum = 0;
2293 uint8_t *ptr;
2294 uint8_t i;
2295
4562236b 2296 /*start of the Gamut data. */
6e4d6bee 2297 ptr = &gamut_packet->sb[3];
4562236b 2298
6e4d6bee 2299 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2300 chk_sum += ptr[i];
2301
6e4d6bee 2302 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2303 }
4562236b
HW		 2304}
2305
2306static void set_avi_info_frame(
e09b6473 2307 struct dc_info_packet *info_packet,
4562236b
HW		 2308 struct pipe_ctx *pipe_ctx)
2309{
0971c40e 2310 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2311 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2312 uint32_t pixel_encoding = 0;
2313 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2314 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2315 bool itc = false;
50e27654 2316 uint8_t itc_value = 0;
4562236b 2317 uint8_t cn0_cn1 = 0;
50e27654 2318 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2319 uint8_t *check_sum = NULL;
2320 uint8_t byte_index = 0;
754e3673 2321 union hdmi_info_packet hdmi_info;
50e27654 2322 union display_content_support support = {0};
4fa086b9 2323 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2324 enum dc_timing_3d_format format;
4562236b 2325
754e3673
AK		 2326 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2327
4fa086b9 2328 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2329 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2330 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2331 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2332
2333 /* Initialize header */
e09b6473 2334 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2335 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2336 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2337 hdmi_info.bits.header.version = 2;
2338 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2339
2340 /*
2341 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2342 * according to HDMI 2.0 spec (Section 10.1)
2343 */
2344
4fa086b9 2345 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2346 case PIXEL_ENCODING_YCBCR422:
2347 pixel_encoding = 1;
2348 break;
2349
2350 case PIXEL_ENCODING_YCBCR444:
2351 pixel_encoding = 2;
2352 break;
2353 case PIXEL_ENCODING_YCBCR420:
2354 pixel_encoding = 3;
2355 break;
2356
2357 case PIXEL_ENCODING_RGB:
2358 default:
2359 pixel_encoding = 0;
2360 }
2361
2362 /* Y0_Y1_Y2 : The pixel encoding */
2363 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2364 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2365
2366 /* A0 = 1 Active Format Information valid */
e09b6473 2367 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2368
2369 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2370 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2371
e09b6473 2372 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2373
2374 /* S0, S1 : Underscan / Overscan */
2375 /* TODO: un-hardcode scan type */
2376 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2377 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2378
2379 /* C0, C1 : Colorimetry */
8fde5884 2380 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2381 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2382 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2383 else if (color_space == COLOR_SPACE_YCBCR601 ||
2384 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2385 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2386 else {
e09b6473 2387 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2388 }
534db198 2389 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2390 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2391 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2392 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2393 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2394 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2395 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2396 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2397 }
2398
4562236b 2399 /* TODO: un-hardcode aspect ratio */
4fa086b9 2400 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2401
2402 switch (aspect) {
2403 case ASPECT_RATIO_4_3:
2404 case ASPECT_RATIO_16_9:
e09b6473 2405 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2406 break;
2407
2408 case ASPECT_RATIO_NO_DATA:
2409 case ASPECT_RATIO_64_27:
2410 case ASPECT_RATIO_256_135:
2411 default:
e09b6473 2412 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2413 }
2414
2415 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2416 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2417
2418 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2419
4562236b 2420 cn0_cn1 = 0;
50e27654
ZF		 2421 cn0_cn1_value = 0;
2422
2423 itc = true;
2424 itc_value = 1;
2425
ceb3dbb4 2426 support = stream->content_support;
4562236b
HW		 2427
2428 if (itc) {
50e27654
ZF		 2429 if (!support.bits.valid_content_type) {
2430 cn0_cn1_value = 0;
2431 } else {
2432 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2433 if (support.bits.graphics_content == 1) {
2434 cn0_cn1_value = 0;
2435 }
2436 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2437 if (support.bits.photo_content == 1) {
2438 cn0_cn1_value = 1;
2439 } else {
2440 cn0_cn1_value = 0;
2441 itc_value = 0;
2442 }
2443 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2444 if (support.bits.cinema_content == 1) {
2445 cn0_cn1_value = 2;
2446 } else {
2447 cn0_cn1_value = 0;
2448 itc_value = 0;
2449 }
2450 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2451 if (support.bits.game_content == 1) {
2452 cn0_cn1_value = 3;
2453 } else {
2454 cn0_cn1_value = 0;
2455 itc_value = 0;
2456 }
2457 }
2458 }
e09b6473
AK		 2459 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2460 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2461 }
2462
2463 /* TODO : We should handle YCC quantization */
2464 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2465 if (stream->qs_bit == 1 &&
2466 stream->qy_bit == 1) {
50e27654
ZF		 2467 if (color_space == COLOR_SPACE_SRGB ||
2468 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473 2469 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
993dca3e 2470 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654
ZF		 2471 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2472 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2473 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2474 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2475 } else {
e09b6473
AK		 2476 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2477 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2478 }
4562236b 2479 } else {
e09b6473
AK		 2480 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2481 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2482 }
50e27654 2483
15e17335 2484 ///VIC
4fa086b9 2485 format = stream->timing.timing_3d_format;
15e17335
CL		 2486 /*todo, add 3DStereo support*/
2487 if (format != TIMING_3D_FORMAT_NONE) {
2488 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2489 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2490 case 1:
2491 vic = 95;
2492 break;
2493 case 2:
2494 vic = 94;
2495 break;
2496 case 3:
2497 vic = 93;
2498 break;
2499 case 4:
2500 vic = 98;
2501 break;
2502 default:
2503 break;
2504 }
2505 }
efa02336 2506 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2507 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2508 if (vic >= 128)
2509 hdmi_info.bits.header.version = 3;
2510 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2511 * the Source shall use 20 AVI InfoFrame Version 4
2512 */
2513 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2514 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2515 hdmi_info.bits.header.version = 4;
2516 hdmi_info.bits.header.length = 14;
2517 }
4562236b
HW		 2518
2519 /* pixel repetition
2520 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2521 * repetition start from 1 */
e09b6473 2522 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2523
2524 /* Bar Info
2525 * barTop: Line Number of End of Top Bar.
2526 * barBottom: Line Number of Start of Bottom Bar.
2527 * barLeft: Pixel Number of End of Left Bar.
2528 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2529 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2530 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2531 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2532 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2533 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2534 - stream->timing.h_border_right + 1);
4562236b 2535
2f482c4f
CP		 2536 /* Additional Colorimetry Extension
2537 * Used in conduction with C0-C1 and EC0-EC2
2538 * 0 = DCI-P3 RGB (D65)
2539 * 1 = DCI-P3 RGB (theater)
2540 */
2541 hdmi_info.bits.ACE0_ACE3 = 0;
2542
4562236b 2543 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2544 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2545
efa02336 2546 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2547
efa02336 2548 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2549 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2550
2551 /* one byte complement */
2552 *check_sum = (uint8_t) (0x100 - *check_sum);
2553
2554 /* Store in hw_path_mode */
e09b6473
AK		 2555 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2556 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2557 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2558
e09b6473
AK		 2559 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2560 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2561
2562 info_packet->valid = true;
2563}
2564
6e4d6bee 2565static void set_vendor_info_packet(
e09b6473 2566 struct dc_info_packet *info_packet,
0971c40e 2567 struct dc_stream_state *stream)
4562236b 2568{
ecd0136b 2569 /* SPD info packet for FreeSync */
4562236b 2570
ecd0136b
HT		 2571 /* Check if Freesync is supported. Return if false. If true,
2572 * set the corresponding bit in the info packet
2573 */
2574 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2575 return;
2576
ecd0136b 2577 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2578}
2579
6e4d6bee 2580static void set_spd_info_packet(
e09b6473 2581 struct dc_info_packet *info_packet,
0971c40e 2582 struct dc_stream_state *stream)
4562236b
HW		 2583{
2584 /* SPD info packet for FreeSync */
2585
4562236b
HW		 2586 /* Check if Freesync is supported. Return if false. If true,
2587 * set the corresponding bit in the info packet
2588 */
98e6436d 2589 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2590 return;
2591
98e6436d 2592 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2593}
2594
1646a6fe 2595static void set_hdr_static_info_packet(
e09b6473 2596 struct dc_info_packet *info_packet,
0971c40e 2597 struct dc_stream_state *stream)
1646a6fe 2598{
0eeef690 2599 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2600
a10dc97a
KK		 2601 if (!stream->hdr_static_metadata.valid ||
2602 stream->use_dynamic_meta)
10bff005
YS		 2603 return;
2604
0eeef690 2605 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2606}
2607
6e4d6bee 2608static void set_vsc_info_packet(
e09b6473 2609 struct dc_info_packet *info_packet,
0971c40e 2610 struct dc_stream_state *stream)
4562236b 2611{
1336926f 2612 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2613 return;
2614
1336926f 2615 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2616}
2617
f36cc577 2618void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2619{
2620 int i, j;
2621
ab2541b6 2622 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2623 for (j = 0; j < context->stream_status[i].plane_count; j++)
2624 dc_plane_state_release(
2625 context->stream_status[i].plane_states[j]);
4562236b 2626
3be5262e 2627 context->stream_status[i].plane_count = 0;
4fa086b9 2628 dc_stream_release(context->streams[i]);
ab2541b6 2629 context->streams[i] = NULL;
4562236b
HW		 2630 }
2631}
2632
f36cc577 2633void dc_resource_state_copy_construct(
608ac7bb
JZ		 2634 const struct dc_state *src_ctx,
2635 struct dc_state *dst_ctx)
4562236b
HW		 2636{
2637 int i, j;
8ee5702a 2638 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2639
2640 *dst_ctx = *src_ctx;
2641
a2b8659d 2642 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2643 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2644
2645 if (cur_pipe->top_pipe)
2646 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2647
2648 if (cur_pipe->bottom_pipe)
2649 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL		 2650
2651 if (cur_pipe->next_odm_pipe)
2652 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2653
2654 if (cur_pipe->prev_odm_pipe)
2655 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW		 2656 }
2657
ab2541b6 2658 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2659 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2660 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2661 dc_plane_state_retain(
2662 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2663 }
9a3afbb3
AG		 2664
2665 /* context refcount should not be overridden */
8ee5702a 2666 dst_ctx->refcount = refcount;
9a3afbb3 2667
4562236b
HW		 2668}
2669
2670struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2671 struct resource_context *res_ctx,
2672 const struct resource_pool *pool)
4562236b
HW		 2673{
2674 int i;
2675
a2b8659d 2676 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2677 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2678 return pool->clock_sources[i];
4562236b
HW		 2679 }
2680
2681 return NULL;
2682}
2683
2684void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2685{
2686 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2687 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2688
2689 /* default all packets to invalid */
6e4d6bee
TC		 2690 info->avi.valid = false;
2691 info->gamut.valid = false;
2692 info->vendor.valid = false;
630e3573 2693 info->spd.valid = false;
6e4d6bee
TC		 2694 info->hdrsmd.valid = false;
2695 info->vsc.valid = false;
4562236b
HW		 2696
2697 signal = pipe_ctx->stream->signal;
2698
2699 /* HDMi and DP have different info packets*/
2700 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2701 set_avi_info_frame(&info->avi, pipe_ctx);
2702
2703 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2704
2705 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2706
56ef6ed9 2707 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2708
a33fa99d 2709 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2710 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2711
2712 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2713
56ef6ed9 2714 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2715 }
4562236b 2716
6e4d6bee 2717 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2718}
2719
2720enum dc_status resource_map_clock_resources(
fb3466a4 2721 const struct dc *dc,
608ac7bb 2722 struct dc_state *context,
1dc90497 2723 struct dc_stream_state *stream)
4562236b 2724{
4562236b 2725 /* acquire new resources */
1dc90497
AG		 2726 const struct resource_pool *pool = dc->res_pool;
2727 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2728 &context->res_ctx, stream);
ab2541b6 2729
1dc90497
AG		 2730 if (!pipe_ctx)
2731 return DC_ERROR_UNEXPECTED;
4562236b 2732
1dc90497
AG		 2733 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2734 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2735 pipe_ctx->clock_source = pool->dp_clock_source;
2736 else {
2737 pipe_ctx->clock_source = NULL;
4562236b 2738
1dc90497 2739 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2740 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2741 &context->res_ctx,
2742 pipe_ctx);
4562236b 2743
1dc90497
AG		 2744 if (pipe_ctx->clock_source == NULL)
2745 pipe_ctx->clock_source =
2746 dc_resource_find_first_free_pll(
2747 &context->res_ctx,
2748 pool);
2749 }
4562236b 2750
1dc90497
AG		 2751 if (pipe_ctx->clock_source == NULL)
2752 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2753
1dc90497
AG		 2754 resource_reference_clock_source(
2755 &context->res_ctx, pool,
2756 pipe_ctx->clock_source);
4562236b
HW		 2757
2758 return DC_OK;
2759}
2760
2761/*
2762 * Note: We need to disable output if clock sources change,
2763 * since bios does optimization and doesn't apply if changing
2764 * PHY when not already disabled.
2765 */
2766bool pipe_need_reprogram(
2767 struct pipe_ctx *pipe_ctx_old,
2768 struct pipe_ctx *pipe_ctx)
2769{
cfe4645e
DL		 2770 if (!pipe_ctx_old->stream)
2771 return false;
2772
4562236b
HW		 2773 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2774 return true;
2775
2776 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2777 return true;
2778
afaacef4 2779 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2780 return true;
2781
2782 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2783 && pipe_ctx_old->stream != pipe_ctx->stream)
2784 return true;
2785
8e9c4c8c 2786 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2787 return true;
2788
2789 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2790 return true;
2791
1e7e86c4
ST		 2792 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2793 return true;
2794
eed928dc
CL		 2795 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2796 false == pipe_ctx_old->stream->dpms_off)
2797 return true;
2798
14e49bb3
NC		 2799 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2800 return true;
2801
4562236b
HW		 2802 return false;
2803}
529cad0f 2804
0971c40e 2805void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2806 struct bit_depth_reduction_params *fmt_bit_depth)
2807{
4fa086b9 2808 enum dc_dither_option option = stream->dither_option;
529cad0f 2809 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2810 stream->timing.pixel_encoding;
529cad0f
DW		 2811
2812 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2813
603767f9
TC		 2814 if (option == DITHER_OPTION_DEFAULT) {
2815 switch (stream->timing.display_color_depth) {
2816 case COLOR_DEPTH_666:
2817 option = DITHER_OPTION_SPATIAL6;
2818 break;
2819 case COLOR_DEPTH_888:
2820 option = DITHER_OPTION_SPATIAL8;
2821 break;
2822 case COLOR_DEPTH_101010:
2823 option = DITHER_OPTION_SPATIAL10;
2824 break;
2825 default:
2826 option = DITHER_OPTION_DISABLE;
2827 }
2828 }
2829
529cad0f
DW		 2830 if (option == DITHER_OPTION_DISABLE)
2831 return;
2832
2833 if (option == DITHER_OPTION_TRUN6) {
2834 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2835 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2836 } else if (option == DITHER_OPTION_TRUN8 ||
2837 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2838 option == DITHER_OPTION_TRUN8_FM6) {
2839 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2840 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2841 } else if (option == DITHER_OPTION_TRUN10 ||
2842 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2843 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2844 option == DITHER_OPTION_TRUN10_FM8 ||
2845 option == DITHER_OPTION_TRUN10_FM6 ||
2846 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2847 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2848 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2849 }
2850
2851 /* special case - Formatter can only reduce by 4 bits at most.
2852 * When reducing from 12 to 6 bits,
2853 * HW recommends we use trunc with round mode
2854 * (if we did nothing, trunc to 10 bits would be used)
2855 * note that any 12->10 bit reduction is ignored prior to DCE8,
2856 * as the input was 10 bits.
2857 */
2858 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2859 option == DITHER_OPTION_SPATIAL6 ||
2860 option == DITHER_OPTION_FM6) {
2861 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2862 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2863 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2864 }
2865
2866 /* spatial dither
2867 * note that spatial modes 1-3 are never used
2868 */
2869 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2870 option == DITHER_OPTION_SPATIAL6 ||
2871 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2872 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2873 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2874 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2875 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2876 fmt_bit_depth->flags.RGB_RANDOM =
2877 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2878 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2879 option == DITHER_OPTION_SPATIAL8 ||
2880 option == DITHER_OPTION_SPATIAL8_FM6 ||
2881 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2882 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2883 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2884 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2885 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2886 fmt_bit_depth->flags.RGB_RANDOM =
2887 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2888 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2889 option == DITHER_OPTION_SPATIAL10 ||
2890 option == DITHER_OPTION_SPATIAL10_FM8 ||
2891 option == DITHER_OPTION_SPATIAL10_FM6) {
2892 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2893 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2894 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2895 fmt_bit_depth->flags.RGB_RANDOM =
2896 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2897 }
2898
2899 if (option == DITHER_OPTION_SPATIAL6 ||
2900 option == DITHER_OPTION_SPATIAL8 ||
2901 option == DITHER_OPTION_SPATIAL10) {
2902 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2903 } else {
2904 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2905 }
2906
2907 //////////////////////
2908 //// temporal dither
2909 //////////////////////
2910 if (option == DITHER_OPTION_FM6 ||
2911 option == DITHER_OPTION_SPATIAL8_FM6 ||
2912 option == DITHER_OPTION_SPATIAL10_FM6 ||
2913 option == DITHER_OPTION_TRUN10_FM6 ||
2914 option == DITHER_OPTION_TRUN8_FM6 ||
2915 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2916 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2917 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2918 } else if (option == DITHER_OPTION_FM8 ||
2919 option == DITHER_OPTION_SPATIAL10_FM8 ||
2920 option == DITHER_OPTION_TRUN10_FM8) {
2921 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2922 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2923 } else if (option == DITHER_OPTION_FM10) {
2924 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2925 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2926 }
2927
2928 fmt_bit_depth->pixel_encoding = pixel_encoding;
2929}
9345d987 2930
62c933f9 2931enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2932{
ceb3dbb4 2933 struct dc_link *link = stream->link;
2b77dcc5 2934 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG		 2935 enum dc_status res = DC_OK;
2936
4fa086b9 2937 calculate_phy_pix_clks(stream);
9345d987 2938
4fa086b9 2939 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2940 res = DC_FAIL_CONTROLLER_VALIDATE;
2941
248cbed6 2942 if (res == DC_OK) {
9345d987 2943 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2944 link->link_enc, stream))
9345d987 2945 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2946 }
9345d987
AG		 2947
2948 /* TODO: validate audio ASIC caps, encoder */
2949
2950 if (res == DC_OK)
4fa086b9 2951 res = dc_link_validate_mode_timing(stream,
9345d987 2952 link,
4fa086b9 2953 &stream->timing);
9345d987 2954
62c933f9 2955 return res;
9345d987 2956}
792671d7 2957
62c933f9 2958enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2959{
62c933f9
YS		 2960 enum dc_status res = DC_OK;
2961
792671d7 2962 /* TODO For now validates pixel format only */
8e7095b9 2963 if (dc->res_pool->funcs->validate_plane)
62c933f9 2964 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2965
62c933f9 2966 return res;
792671d7 2967}
74eac5f3
SSC		 2968
2969unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2970{
2971 switch (format) {
2972 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2973 return 8;
2974 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2975 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2976 return 12;
2977 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2978 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2979 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2980 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2981 return 16;
2982 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2983 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2984 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2985 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2986 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
20f2ffe5 2987#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 2988 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
2989 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2990#endif
74eac5f3
SSC		 2991 return 32;
2992 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2993 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2994 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2995 return 64;
2996 default:
2997 ASSERT_CRITICAL(false);
2998 return -1;
2999 }
3000}
3ab4cc65
CL		 3001static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
3002{
3003 if (modes) {
3004 if (modes->sample_rates.rate.RATE_192)
3005 return 192000;
3006 if (modes->sample_rates.rate.RATE_176_4)
3007 return 176400;
3008 if (modes->sample_rates.rate.RATE_96)
3009 return 96000;
3010 if (modes->sample_rates.rate.RATE_88_2)
3011 return 88200;
3012 if (modes->sample_rates.rate.RATE_48)
3013 return 48000;
3014 if (modes->sample_rates.rate.RATE_44_1)
3015 return 44100;
3016 if (modes->sample_rates.rate.RATE_32)
3017 return 32000;
3018 }
3019 /*original logic when no audio info*/
3020 return 441000;
3021}
3022
3023void get_audio_check(struct audio_info *aud_modes,
3024 struct audio_check *audio_chk)
3025{
3026 unsigned int i;
3027 unsigned int max_sample_rate = 0;
3028
3029 if (aud_modes) {
3030 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3031
3032 audio_chk->max_audiosample_rate = 0;
3033 for (i = 0; i < aud_modes->mode_count; i++) {
3034 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3035 if (audio_chk->max_audiosample_rate < max_sample_rate)
3036 audio_chk->max_audiosample_rate = max_sample_rate;
3037 /*dts takes the same as type 2: AP = 0.25*/
3038 }
3039 /*check which one take more bandwidth*/
3040 if (audio_chk->max_audiosample_rate > 192000)
3041 audio_chk->audio_packet_type = 0x9;/*AP =1*/
3042 audio_chk->acat = 0;/*not support*/
3043 }
3044}
3045
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