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drm/amd/display: Roll sink struct into core_sink
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
5ac3d3c9 34#include "core_types.h"
4562236b 35#include "set_mode_types.h"
4562236b
HW		 36#include "virtual/virtual_stream_encoder.h"
37
38#include "dce80/dce80_resource.h"
39#include "dce100/dce100_resource.h"
40#include "dce110/dce110_resource.h"
41#include "dce112/dce112_resource.h"
ff5ef992
AD		 42#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
43#include "dcn10/dcn10_resource.h"
44#endif
2c8ad2d5 45#include "dce120/dce120_resource.h"
4562236b
HW		 46
47enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
48{
49 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
50 switch (asic_id.chip_family) {
51
52 case FAMILY_CI:
53 case FAMILY_KV:
54 dc_version = DCE_VERSION_8_0;
55 break;
56 case FAMILY_CZ:
57 dc_version = DCE_VERSION_11_0;
58 break;
59
60 case FAMILY_VI:
61 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
63 dc_version = DCE_VERSION_10_0;
64 break;
65 }
66 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 67 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 69 dc_version = DCE_VERSION_11_2;
70 }
71 break;
2c8ad2d5
AD		 72 case FAMILY_AI:
73 dc_version = DCE_VERSION_12_0;
74 break;
ff5ef992
AD		 75#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
76 case FAMILY_RV:
77 dc_version = DCN_VERSION_1_0;
78 break;
79#endif
4562236b
HW		 80 default:
81 dc_version = DCE_VERSION_UNKNOWN;
82 break;
83 }
84 return dc_version;
85}
86
87struct resource_pool *dc_create_resource_pool(
88 struct core_dc *dc,
89 int num_virtual_links,
90 enum dce_version dc_version,
91 struct hw_asic_id asic_id)
92{
5ac3d3c9 93 struct resource_pool *res_pool = NULL;
4562236b
HW		 94
95 switch (dc_version) {
96 case DCE_VERSION_8_0:
5ac3d3c9 97 res_pool = dce80_create_resource_pool(
4562236b 98 num_virtual_links, dc);
5ac3d3c9 99 break;
4562236b 100 case DCE_VERSION_10_0:
5ac3d3c9 101 res_pool = dce100_create_resource_pool(
4562236b 102 num_virtual_links, dc);
5ac3d3c9 103 break;
4562236b 104 case DCE_VERSION_11_0:
5ac3d3c9 105 res_pool = dce110_create_resource_pool(
4562236b 106 num_virtual_links, dc, asic_id);
5ac3d3c9 107 break;
4562236b 108 case DCE_VERSION_11_2:
5ac3d3c9 109 res_pool = dce112_create_resource_pool(
4562236b 110 num_virtual_links, dc);
5ac3d3c9 111 break;
2c8ad2d5
AD		 112 case DCE_VERSION_12_0:
113 res_pool = dce120_create_resource_pool(
114 num_virtual_links, dc);
115 break;
ff5ef992
AD		 116
117#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
118 case DCN_VERSION_1_0:
119 res_pool = dcn10_create_resource_pool(
120 num_virtual_links, dc);
121 break;
122#endif
4562236b
HW		 123 default:
124 break;
125 }
5ac3d3c9
CL		 126 if (res_pool != NULL) {
127 struct firmware_info fw_info = { { 0 } };
128
129 if (dc->ctx->dc_bios->funcs->get_firmware_info(
130 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
131 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
132 } else
133 ASSERT_CRITICAL(false);
134 }
4562236b 135
5ac3d3c9 136 return res_pool;
4562236b
HW		 137}
138
139void dc_destroy_resource_pool(struct core_dc *dc)
140{
141 if (dc) {
142 if (dc->res_pool)
143 dc->res_pool->funcs->destroy(&dc->res_pool);
144
145 if (dc->hwseq)
146 dm_free(dc->hwseq);
147 }
148}
149
150static void update_num_audio(
151 const struct resource_straps *straps,
152 unsigned int *num_audio,
153 struct audio_support *aud_support)
154{
155 if (straps->hdmi_disable == 0) {
156 aud_support->hdmi_audio_native = true;
157 aud_support->hdmi_audio_on_dongle = true;
158 aud_support->dp_audio = true;
159 } else {
160 if (straps->dc_pinstraps_audio & 0x2) {
161 aud_support->hdmi_audio_on_dongle = true;
162 aud_support->dp_audio = true;
163 } else {
164 aud_support->dp_audio = true;
165 }
166 }
167
168 switch (straps->audio_stream_number) {
169 case 0: /* multi streams supported */
170 break;
171 case 1: /* multi streams not supported */
172 *num_audio = 1;
173 break;
174 default:
175 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 176 }
4562236b
HW		 177}
178
179bool resource_construct(
180 unsigned int num_virtual_links,
181 struct core_dc *dc,
182 struct resource_pool *pool,
183 const struct resource_create_funcs *create_funcs)
184{
185 struct dc_context *ctx = dc->ctx;
186 const struct resource_caps *caps = pool->res_cap;
187 int i;
188 unsigned int num_audio = caps->num_audio;
189 struct resource_straps straps = {0};
190
191 if (create_funcs->read_dce_straps)
192 create_funcs->read_dce_straps(dc->ctx, &straps);
193
194 pool->audio_count = 0;
195 if (create_funcs->create_audio) {
196 /* find the total number of streams available via the
197 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
198 * registers (one for each pin) starting from pin 1
199 * up to the max number of audio pins.
200 * We stop on the first pin where
201 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
202 */
203 update_num_audio(&straps, &num_audio, &pool->audio_support);
204 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
205 struct audio *aud = create_funcs->create_audio(ctx, i);
206
207 if (aud == NULL) {
208 DC_ERR("DC: failed to create audio!\n");
209 return false;
210 }
211
212 if (!aud->funcs->endpoint_valid(aud)) {
213 aud->funcs->destroy(&aud);
214 break;
215 }
216
217 pool->audios[i] = aud;
218 pool->audio_count++;
219 }
220 }
221
222 pool->stream_enc_count = 0;
223 if (create_funcs->create_stream_encoder) {
224 for (i = 0; i < caps->num_stream_encoder; i++) {
225 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
226 if (pool->stream_enc[i] == NULL)
227 DC_ERR("DC: failed to create stream_encoder!\n");
228 pool->stream_enc_count++;
229 }
230 }
231
232 for (i = 0; i < num_virtual_links; i++) {
233 pool->stream_enc[pool->stream_enc_count] =
234 virtual_stream_encoder_create(
235 ctx, ctx->dc_bios);
236 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
237 DC_ERR("DC: failed to create stream_encoder!\n");
238 return false;
239 }
240 pool->stream_enc_count++;
241 }
242
243 dc->hwseq = create_funcs->create_hwseq(ctx);
244
245 return true;
246}
247
248
249void resource_unreference_clock_source(
250 struct resource_context *res_ctx,
a2b8659d 251 const struct resource_pool *pool,
8c737fcc 252 struct clock_source **clock_source)
4562236b
HW		 253{
254 int i;
a2b8659d
TC		 255 for (i = 0; i < pool->clk_src_count; i++) {
256 if (pool->clock_sources[i] != *clock_source)
4562236b
HW		 257 continue;
258
259 res_ctx->clock_source_ref_count[i]--;
260
261 if (res_ctx->clock_source_ref_count[i] == 0)
8c737fcc 262 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b
HW		 263
264 break;
265 }
266
a2b8659d 267 if (pool->dp_clock_source == *clock_source) {
4562236b
HW		 268 res_ctx->dp_clock_source_ref_count--;
269
270 if (res_ctx->dp_clock_source_ref_count == 0)
8c737fcc 271 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b 272 }
8c737fcc 273 *clock_source = NULL;
4562236b
HW		 274}
275
276void resource_reference_clock_source(
277 struct resource_context *res_ctx,
a2b8659d 278 const struct resource_pool *pool,
4562236b
HW		 279 struct clock_source *clock_source)
280{
281 int i;
a2b8659d
TC		 282 for (i = 0; i < pool->clk_src_count; i++) {
283 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 284 continue;
285
286 res_ctx->clock_source_ref_count[i]++;
287 break;
288 }
289
a2b8659d 290 if (pool->dp_clock_source == clock_source)
4562236b
HW		 291 res_ctx->dp_clock_source_ref_count++;
292}
293
294bool resource_are_streams_timing_synchronizable(
295 const struct core_stream *stream1,
296 const struct core_stream *stream2)
297{
298 if (stream1->public.timing.h_total != stream2->public.timing.h_total)
299 return false;
300
301 if (stream1->public.timing.v_total != stream2->public.timing.v_total)
302 return false;
303
304 if (stream1->public.timing.h_addressable
305 != stream2->public.timing.h_addressable)
306 return false;
307
308 if (stream1->public.timing.v_addressable
309 != stream2->public.timing.v_addressable)
310 return false;
311
312 if (stream1->public.timing.pix_clk_khz
313 != stream2->public.timing.pix_clk_khz)
314 return false;
315
316 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 317 && (!dc_is_dp_signal(stream1->signal)
318 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 319 return false;
320
321 return true;
322}
323
324static bool is_sharable_clk_src(
325 const struct pipe_ctx *pipe_with_clk_src,
326 const struct pipe_ctx *pipe)
327{
328 if (pipe_with_clk_src->clock_source == NULL)
329 return false;
330
331 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
332 return false;
333
334 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
335 return false;
336
337 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
338 && dc_is_dvi_signal(pipe->stream->signal))
339 return false;
340
341 if (dc_is_hdmi_signal(pipe->stream->signal)
342 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
343 return false;
344
345 if (!resource_are_streams_timing_synchronizable(
346 pipe_with_clk_src->stream, pipe->stream))
347 return false;
348
349 return true;
350}
351
352struct clock_source *resource_find_used_clk_src_for_sharing(
353 struct resource_context *res_ctx,
354 struct pipe_ctx *pipe_ctx)
355{
356 int i;
357
358 for (i = 0; i < MAX_PIPES; i++) {
359 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
360 return res_ctx->pipe_ctx[i].clock_source;
361 }
362
363 return NULL;
364}
365
366static enum pixel_format convert_pixel_format_to_dalsurface(
367 enum surface_pixel_format surface_pixel_format)
368{
369 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
370
371 switch (surface_pixel_format) {
372 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
373 dal_pixel_format = PIXEL_FORMAT_INDEX8;
374 break;
375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
376 dal_pixel_format = PIXEL_FORMAT_RGB565;
377 break;
378 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
379 dal_pixel_format = PIXEL_FORMAT_RGB565;
380 break;
381 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
382 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
383 break;
8693049a 384 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 385 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
386 break;
387 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
388 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
389 break;
390 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
391 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
392 break;
393 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
394 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
395 break;
396 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
397 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
398 dal_pixel_format = PIXEL_FORMAT_FP16;
399 break;
400 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 401 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 402 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 403 break;
ffbcd19a
VP		 404 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
405 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 406 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 407 break;
4562236b
HW		 408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
409 default:
410 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
411 break;
412 }
413 return dal_pixel_format;
414}
415
416static void rect_swap_helper(struct rect *rect)
417{
418 uint32_t temp = 0;
419
420 temp = rect->height;
421 rect->height = rect->width;
422 rect->width = temp;
423
424 temp = rect->x;
425 rect->x = rect->y;
426 rect->y = temp;
427}
428
b2d0a103 429static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 430{
e12cfcb1 431 const struct dc_surface *surface = pipe_ctx->surface;
1fbd2cfc 432 const struct dc_stream *stream = &pipe_ctx->stream->public;
b2d0a103 433 struct scaler_data *data = &pipe_ctx->scl_data;
86006a7f 434 struct rect surf_src = surface->src_rect;
1fbd2cfc 435 struct rect clip = { 0 };
87449a90
AK		 436 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
437 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc
DL		 438 bool pri_split = pipe_ctx->bottom_pipe &&
439 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
440 bool sec_split = pipe_ctx->top_pipe &&
441 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
4562236b 442
7f5c22d1
VP		 443 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
444 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 445 pri_split = false;
446 sec_split = false;
447 }
86006a7f 448
e12cfcb1
HW		 449 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
450 pipe_ctx->surface->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 451 rect_swap_helper(&surf_src);
452
4562236b
HW		 453 /* The actual clip is an intersection between stream
454 * source and surface clip
455 */
1fbd2cfc
DL		 456 clip.x = stream->src.x > surface->clip_rect.x ?
457 stream->src.x : surface->clip_rect.x;
4562236b 458
1fbd2cfc
DL		 459 clip.width = stream->src.x + stream->src.width <
460 surface->clip_rect.x + surface->clip_rect.width ?
461 stream->src.x + stream->src.width - clip.x :
462 surface->clip_rect.x + surface->clip_rect.width - clip.x ;
4562236b 463
1fbd2cfc
DL		 464 clip.y = stream->src.y > surface->clip_rect.y ?
465 stream->src.y : surface->clip_rect.y;
4562236b 466
1fbd2cfc
DL		 467 clip.height = stream->src.y + stream->src.height <
468 surface->clip_rect.y + surface->clip_rect.height ?
469 stream->src.y + stream->src.height - clip.y :
470 surface->clip_rect.y + surface->clip_rect.height - clip.y ;
4562236b 471
86006a7f 472 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 473 * num_pixels = clip.num_pix * scl_ratio
474 */
86006a7f
DL		 475 data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) *
476 surf_src.width / surface->dst_rect.width;
b2d0a103 477 data->viewport.width = clip.width *
86006a7f 478 surf_src.width / surface->dst_rect.width;
4562236b 479
86006a7f
DL		 480 data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) *
481 surf_src.height / surface->dst_rect.height;
b2d0a103 482 data->viewport.height = clip.height *
86006a7f 483 surf_src.height / surface->dst_rect.height;
4562236b 484
b2d0a103
DL		 485 /* Round down, compensate in init */
486 data->viewport_c.x = data->viewport.x / vpc_div;
487 data->viewport_c.y = data->viewport.y / vpc_div;
488 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
489 dal_fixed31_32_half : dal_fixed31_32_zero;
490 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
491 dal_fixed31_32_half : dal_fixed31_32_zero;
492 /* Round up, assume original video size always even dimensions */
493 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
494 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
495
496 /* Handle hsplit */
1fbd2cfc
DL		 497 if (pri_split || sec_split) {
498 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
499 bool right_view = (sec_split != surface->horizontal_mirror) !=
500 (surface->rotation == ROTATION_ANGLE_180);
501
502 if (surface->rotation == ROTATION_ANGLE_90
503 || surface->rotation == ROTATION_ANGLE_270)
504 /* Secondary_pipe XOR Rotation_270 */
505 right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 506
507 if (right_view) {
508 data->viewport.width /= 2;
509 data->viewport_c.width /= 2;
510 data->viewport.x += data->viewport.width;
511 data->viewport_c.x += data->viewport_c.width;
512 /* Ceil offset pipe */
513 data->viewport.width += data->viewport.width % 2;
514 data->viewport_c.width += data->viewport_c.width % 2;
515 } else {
516 data->viewport.width /= 2;
517 data->viewport_c.width /= 2;
518 }
b2d0a103 519 }
1fbd2cfc
DL		 520
521 if (surface->rotation == ROTATION_ANGLE_90 ||
522 surface->rotation == ROTATION_ANGLE_270) {
523 rect_swap_helper(&data->viewport_c);
524 rect_swap_helper(&data->viewport);
525 }
4562236b
HW		 526}
527
b2d0a103 528static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 529{
e12cfcb1 530 const struct dc_surface *surface = pipe_ctx->surface;
4562236b 531 struct core_stream *stream = pipe_ctx->stream;
86006a7f
DL		 532 struct rect surf_src = surface->src_rect;
533 struct rect surf_clip = surface->clip_rect;
c802570e 534 int recout_full_x, recout_full_y;
4562236b 535
e12cfcb1
HW		 536 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
537 pipe_ctx->surface->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 538 rect_swap_helper(&surf_src);
539
4562236b 540 pipe_ctx->scl_data.recout.x = stream->public.dst.x;
86006a7f
DL		 541 if (stream->public.src.x < surf_clip.x)
542 pipe_ctx->scl_data.recout.x += (surf_clip.x
4562236b
HW		 543 - stream->public.src.x) * stream->public.dst.width
544 / stream->public.src.width;
545
86006a7f 546 pipe_ctx->scl_data.recout.width = surf_clip.width *
4562236b
HW		 547 stream->public.dst.width / stream->public.src.width;
548 if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x >
549 stream->public.dst.x + stream->public.dst.width)
550 pipe_ctx->scl_data.recout.width =
551 stream->public.dst.x + stream->public.dst.width
552 - pipe_ctx->scl_data.recout.x;
553
554 pipe_ctx->scl_data.recout.y = stream->public.dst.y;
86006a7f
DL		 555 if (stream->public.src.y < surf_clip.y)
556 pipe_ctx->scl_data.recout.y += (surf_clip.y
4562236b
HW		 557 - stream->public.src.y) * stream->public.dst.height
558 / stream->public.src.height;
559
86006a7f 560 pipe_ctx->scl_data.recout.height = surf_clip.height *
4562236b
HW		 561 stream->public.dst.height / stream->public.src.height;
562 if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y >
563 stream->public.dst.y + stream->public.dst.height)
564 pipe_ctx->scl_data.recout.height =
565 stream->public.dst.y + stream->public.dst.height
566 - pipe_ctx->scl_data.recout.y;
b2d0a103 567
7b779c99
VP		 568 /* Handle h & vsplit */
569 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface ==
570 pipe_ctx->surface) {
7f5c22d1 571 if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 572 pipe_ctx->scl_data.recout.height /= 2;
573 pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height;
574 /* Floor primary pipe, ceil 2ndary pipe */
575 pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2;
576 } else {
577 pipe_ctx->scl_data.recout.width /= 2;
578 pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
579 pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
580 }
581 } else if (pipe_ctx->bottom_pipe &&
86006a7f 582 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
7f5c22d1 583 if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
7b779c99
VP		 584 pipe_ctx->scl_data.recout.height /= 2;
585 else
586 pipe_ctx->scl_data.recout.width /= 2;
b2d0a103
DL		 587 }
588
86006a7f
DL		 589 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
590 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 591 * ratio)
592 */
593 recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x)
594 * stream->public.dst.width / stream->public.src.width -
86006a7f 595 surf_src.x * surface->dst_rect.width / surf_src.width
c802570e
DL		 596 * stream->public.dst.width / stream->public.src.width;
597 recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y)
598 * stream->public.dst.height / stream->public.src.height -
86006a7f 599 surf_src.y * surface->dst_rect.height / surf_src.height
c802570e
DL		 600 * stream->public.dst.height / stream->public.src.height;
601
602 recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
603 recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
4562236b
HW		 604}
605
b2d0a103 606static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 607{
e12cfcb1 608 const struct dc_surface *surface = pipe_ctx->surface;
4562236b 609 struct core_stream *stream = pipe_ctx->stream;
86006a7f 610 struct rect surf_src = surface->src_rect;
1fbd2cfc
DL		 611 const int in_w = stream->public.src.width;
612 const int in_h = stream->public.src.height;
613 const int out_w = stream->public.dst.width;
614 const int out_h = stream->public.dst.height;
4562236b 615
e12cfcb1
HW		 616 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
617 pipe_ctx->surface->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 618 rect_swap_helper(&surf_src);
619
4562236b 620 pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 621 surf_src.width,
4562236b
HW		 622 surface->dst_rect.width);
623 pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 624 surf_src.height,
4562236b
HW		 625 surface->dst_rect.height);
626
7f5c22d1 627 if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
4562236b 628 pipe_ctx->scl_data.ratios.horz.value *= 2;
cdc5e048 629 else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
4562236b
HW		 630 pipe_ctx->scl_data.ratios.vert.value *= 2;
631
632 pipe_ctx->scl_data.ratios.vert.value = div64_s64(
633 pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
634 pipe_ctx->scl_data.ratios.horz.value = div64_s64(
635 pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
636
637 pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
638 pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
639
87449a90
AK		 640 if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8
641 || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) {
4562236b
HW		 642 pipe_ctx->scl_data.ratios.horz_c.value /= 2;
643 pipe_ctx->scl_data.ratios.vert_c.value /= 2;
644 }
645}
646
b2d0a103
DL		 647static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
648{
649 struct scaler_data *data = &pipe_ctx->scl_data;
e12cfcb1 650 struct rect src = pipe_ctx->surface->src_rect;
87449a90
AK		 651 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
652 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b2d0a103 653
86006a7f 654
e12cfcb1
HW		 655 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
656 pipe_ctx->surface->rotation == ROTATION_ANGLE_270) {
86006a7f 657 rect_swap_helper(&src);
1fbd2cfc
DL		 658 rect_swap_helper(&data->viewport_c);
659 rect_swap_helper(&data->viewport);
660 }
661
b2d0a103
DL		 662 /*
663 * Init calculated according to formula:
664 * init = (scaling_ratio + number_of_taps + 1) / 2
665 * init_bot = init + scaling_ratio
666 * init_c = init + truncated_vp_c_offset(from calculate viewport)
667 */
668 data->inits.h = dal_fixed31_32_div_int(
669 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
670
671 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
672 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
673
674 data->inits.v = dal_fixed31_32_div_int(
675 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
676
677 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
678 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
679
680
681 /* Adjust for viewport end clip-off */
682 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
683 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 684 int int_part = dal_fixed31_32_floor(
685 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 686
1fbd2cfc 687 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 688 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
689 }
690 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
691 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 692 int int_part = dal_fixed31_32_floor(
693 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 694
1fbd2cfc 695 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 696 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
697 }
698 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
699 int vp_clip = (src.x + src.width) / vpc_div -
700 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 701 int int_part = dal_fixed31_32_floor(
702 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 703
1fbd2cfc 704 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 705 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
706 }
707 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
708 int vp_clip = (src.y + src.height) / vpc_div -
709 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 710 int int_part = dal_fixed31_32_floor(
711 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 712
1fbd2cfc 713 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 714 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
715 }
716
717 /* Adjust for non-0 viewport offset */
718 if (data->viewport.x) {
719 int int_part;
720
721 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
722 data->ratios.horz, recout_skip->width));
723 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
724 if (int_part < data->taps.h_taps) {
725 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
726 (data->taps.h_taps - int_part) : data->viewport.x;
727 data->viewport.x -= int_adj;
728 data->viewport.width += int_adj;
729 int_part += int_adj;
730 } else if (int_part > data->taps.h_taps) {
731 data->viewport.x += int_part - data->taps.h_taps;
732 data->viewport.width -= int_part - data->taps.h_taps;
733 int_part = data->taps.h_taps;
734 }
735 data->inits.h.value &= 0xffffffff;
736 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
737 }
738
739 if (data->viewport_c.x) {
740 int int_part;
741
742 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
743 data->ratios.horz_c, recout_skip->width));
744 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
745 if (int_part < data->taps.h_taps_c) {
746 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
747 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
748 data->viewport_c.x -= int_adj;
749 data->viewport_c.width += int_adj;
750 int_part += int_adj;
751 } else if (int_part > data->taps.h_taps_c) {
752 data->viewport_c.x += int_part - data->taps.h_taps_c;
753 data->viewport_c.width -= int_part - data->taps.h_taps_c;
754 int_part = data->taps.h_taps_c;
755 }
756 data->inits.h_c.value &= 0xffffffff;
757 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
758 }
759
760 if (data->viewport.y) {
761 int int_part;
762
763 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
764 data->ratios.vert, recout_skip->height));
765 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
766 if (int_part < data->taps.v_taps) {
767 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
768 (data->taps.v_taps - int_part) : data->viewport.y;
769 data->viewport.y -= int_adj;
770 data->viewport.height += int_adj;
771 int_part += int_adj;
772 } else if (int_part > data->taps.v_taps) {
773 data->viewport.y += int_part - data->taps.v_taps;
774 data->viewport.height -= int_part - data->taps.v_taps;
775 int_part = data->taps.v_taps;
776 }
777 data->inits.v.value &= 0xffffffff;
778 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
779 }
780
781 if (data->viewport_c.y) {
782 int int_part;
783
784 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
785 data->ratios.vert_c, recout_skip->height));
786 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
787 if (int_part < data->taps.v_taps_c) {
788 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
789 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
790 data->viewport_c.y -= int_adj;
791 data->viewport_c.height += int_adj;
792 int_part += int_adj;
793 } else if (int_part > data->taps.v_taps_c) {
794 data->viewport_c.y += int_part - data->taps.v_taps_c;
795 data->viewport_c.height -= int_part - data->taps.v_taps_c;
796 int_part = data->taps.v_taps_c;
797 }
798 data->inits.v_c.value &= 0xffffffff;
799 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
800 }
801
802 /* Interlaced inits based on final vert inits */
803 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
804 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 805
e12cfcb1
HW		 806 if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 ||
807 pipe_ctx->surface->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 808 rect_swap_helper(&data->viewport_c);
809 rect_swap_helper(&data->viewport);
810 }
b2d0a103
DL		 811}
812
813bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 814{
e12cfcb1 815 const struct dc_surface *surface = pipe_ctx->surface;
4562236b 816 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
b2d0a103
DL		 817 struct view recout_skip = { 0 };
818 bool res = false;
819
4562236b
HW		 820 /* Important: scaling ratio calculation requires pixel format,
821 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 822 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 823 */
b2d0a103 824 pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
e12cfcb1 825 pipe_ctx->surface->format);
b2d0a103
DL		 826
827 calculate_scaling_ratios(pipe_ctx);
4562236b 828
b2d0a103 829 calculate_viewport(pipe_ctx);
4562236b
HW		 830
831 if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
832 return false;
833
b2d0a103 834 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 835
836 /**
837 * Setting line buffer pixel depth to 24bpp yields banding
838 * on certain displays, such as the Sharp 4k
839 */
840 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
841
842 pipe_ctx->scl_data.h_active = timing->h_addressable;
843 pipe_ctx->scl_data.v_active = timing->v_addressable;
844
845 /* Taps calculations */
846 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
847 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
848
849 if (!res) {
850 /* Try 24 bpp linebuffer */
851 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
852
853 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
854 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
855 }
856
b2d0a103 857 if (res)
1fbd2cfc 858 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 859 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
860
4562236b
HW		 861 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
862 "%s: Viewport:\nheight:%d width:%d x:%d "
863 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
864 "y:%d\n",
865 __func__,
866 pipe_ctx->scl_data.viewport.height,
867 pipe_ctx->scl_data.viewport.width,
868 pipe_ctx->scl_data.viewport.x,
869 pipe_ctx->scl_data.viewport.y,
870 surface->dst_rect.height,
871 surface->dst_rect.width,
872 surface->dst_rect.x,
873 surface->dst_rect.y);
874
875 return res;
876}
877
878
879enum dc_status resource_build_scaling_params_for_context(
880 const struct core_dc *dc,
881 struct validate_context *context)
882{
883 int i;
884
885 for (i = 0; i < MAX_PIPES; i++) {
886 if (context->res_ctx.pipe_ctx[i].surface != NULL &&
887 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 888 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 889 return DC_FAIL_SCALING;
4562236b
HW		 890 }
891
892 return DC_OK;
893}
894
a2b8659d
TC		 895struct pipe_ctx *find_idle_secondary_pipe(
896 struct resource_context *res_ctx,
897 const struct resource_pool *pool)
4562236b
HW		 898{
899 int i;
900 struct pipe_ctx *secondary_pipe = NULL;
901
902 /*
903 * search backwards for the second pipe to keep pipe
904 * assignment more consistent
905 */
906
a2b8659d 907 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 908 if (res_ctx->pipe_ctx[i].stream == NULL) {
909 secondary_pipe = &res_ctx->pipe_ctx[i];
910 secondary_pipe->pipe_idx = i;
911 break;
912 }
913 }
914
915
916 return secondary_pipe;
917}
918
919struct pipe_ctx *resource_get_head_pipe_for_stream(
920 struct resource_context *res_ctx,
921 const struct core_stream *stream)
922{
923 int i;
a2b8659d 924 for (i = 0; i < MAX_PIPES; i++) {
4562236b 925 if (res_ctx->pipe_ctx[i].stream == stream &&
e73c1efc 926 res_ctx->pipe_ctx[i].stream_enc) {
4562236b
HW		 927 return &res_ctx->pipe_ctx[i];
928 break;
929 }
930 }
931 return NULL;
932}
933
934/*
ab2541b6
AC		 935 * A free_pipe for a stream is defined here as a pipe
936 * that has no surface attached yet
4562236b 937 */
ab2541b6 938static struct pipe_ctx *acquire_free_pipe_for_stream(
745cc746 939 struct validate_context *context,
a2b8659d 940 const struct resource_pool *pool,
ab2541b6 941 const struct dc_stream *dc_stream)
4562236b
HW		 942{
943 int i;
745cc746 944 struct resource_context *res_ctx = &context->res_ctx;
ab2541b6 945 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 946
947 struct pipe_ctx *head_pipe = NULL;
948
949 /* Find head pipe, which has the back end set up*/
950
951 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
952
953 if (!head_pipe)
954 ASSERT(0);
955
956 if (!head_pipe->surface)
957 return head_pipe;
958
959 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 960 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 961 if (res_ctx->pipe_ctx[i].stream == stream &&
962 !res_ctx->pipe_ctx[i].surface) {
963 return &res_ctx->pipe_ctx[i];
964 }
965 }
966
967 /*
968 * At this point we have no re-useable pipe for this stream and we need
969 * to acquire an idle one to satisfy the request
970 */
971
a2b8659d 972 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 973 return NULL;
974
a2b8659d 975 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 976
977}
978
ab2541b6 979static void release_free_pipes_for_stream(
4562236b 980 struct resource_context *res_ctx,
ab2541b6 981 const struct dc_stream *dc_stream)
4562236b
HW		 982{
983 int i;
ab2541b6 984 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b 985
a2b8659d 986 for (i = MAX_PIPES - 1; i >= 0; i--) {
05a19c39 987 /* never release the topmost pipe*/
4562236b 988 if (res_ctx->pipe_ctx[i].stream == stream &&
05a19c39 989 res_ctx->pipe_ctx[i].top_pipe &&
4562236b 990 !res_ctx->pipe_ctx[i].surface) {
05a19c39 991 memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx));
4562236b
HW		 992 }
993 }
994}
995
0f9a536f
DL		 996#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
997static int acquire_first_split_pipe(
998 struct resource_context *res_ctx,
999 const struct resource_pool *pool,
1000 struct core_stream *stream)
1001{
1002 int i;
1003
1004 for (i = 0; i < pool->pipe_count; i++) {
1005 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1006
1007 if (pipe_ctx->top_pipe &&
1008 pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
0f9a536f
DL		 1009 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1010 if (pipe_ctx->bottom_pipe)
1011 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1012
1013 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1014 pipe_ctx->tg = pool->timing_generators[i];
1015 pipe_ctx->mi = pool->mis[i];
1016 pipe_ctx->ipp = pool->ipps[i];
1017 pipe_ctx->xfm = pool->transforms[i];
1018 pipe_ctx->opp = pool->opps[i];
1019 pipe_ctx->dis_clk = pool->display_clock;
f0558542 1020 pipe_ctx->mpcc = pool->mpcc[i];
0f9a536f 1021 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1022
1023 pipe_ctx->stream = stream;
1024 return i;
1025 }
1026 }
1027 return -1;
1028}
1029#endif
1030
4562236b 1031bool resource_attach_surfaces_to_context(
e12cfcb1 1032 struct dc_surface * const *surfaces,
4562236b 1033 int surface_count,
ab2541b6 1034 const struct dc_stream *dc_stream,
a2b8659d
TC		 1035 struct validate_context *context,
1036 const struct resource_pool *pool)
4562236b
HW		 1037{
1038 int i;
1039 struct pipe_ctx *tail_pipe;
ab2541b6 1040 struct dc_stream_status *stream_status = NULL;
05a19c39 1041 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 1042
1043
1044 if (surface_count > MAX_SURFACE_NUM) {
1045 dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
1046 surface_count, MAX_SURFACE_NUM);
1047 return false;
1048 }
1049
ab2541b6
AC		 1050 for (i = 0; i < context->stream_count; i++)
1051 if (&context->streams[i]->public == dc_stream) {
1052 stream_status = &context->stream_status[i];
4562236b
HW		 1053 break;
1054 }
ab2541b6
AC		 1055 if (stream_status == NULL) {
1056 dm_error("Existing stream not found; failed to attach surfaces\n");
4562236b
HW		 1057 return false;
1058 }
1059
1060 /* retain new surfaces */
1061 for (i = 0; i < surface_count; i++)
1062 dc_surface_retain(surfaces[i]);
1063
05a19c39
DL		 1064 /* detach surfaces from pipes */
1065 for (i = 0; i < pool->pipe_count; i++)
1066 if (context->res_ctx.pipe_ctx[i].stream == stream) {
1067 context->res_ctx.pipe_ctx[i].surface = NULL;
1068 context->res_ctx.pipe_ctx[i].bottom_pipe = NULL;
1069 }
4562236b
HW		 1070
1071 /* release existing surfaces*/
ab2541b6
AC		 1072 for (i = 0; i < stream_status->surface_count; i++)
1073 dc_surface_release(stream_status->surfaces[i]);
4562236b 1074
ab2541b6
AC		 1075 for (i = surface_count; i < stream_status->surface_count; i++)
1076 stream_status->surfaces[i] = NULL;
4562236b 1077
4562236b
HW		 1078 tail_pipe = NULL;
1079 for (i = 0; i < surface_count; i++) {
e12cfcb1 1080 struct dc_surface *surface = surfaces[i];
a2b8659d
TC		 1081 struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(
1082 context, pool, dc_stream);
4562236b 1083
0f9a536f
DL		 1084#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1085 if (!free_pipe) {
1086 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1087 if (pipe_idx >= 0)
1088 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1089 }
1090#endif
4562236b 1091 if (!free_pipe) {
ab2541b6 1092 stream_status->surfaces[i] = NULL;
4562236b
HW		 1093 return false;
1094 }
1095
1096 free_pipe->surface = surface;
1097
1098 if (tail_pipe) {
cfe4645e
DL		 1099 free_pipe->tg = tail_pipe->tg;
1100 free_pipe->stream_enc = tail_pipe->stream_enc;
1101 free_pipe->audio = tail_pipe->audio;
1102 free_pipe->clock_source = tail_pipe->clock_source;
4562236b
HW		 1103 free_pipe->top_pipe = tail_pipe;
1104 tail_pipe->bottom_pipe = free_pipe;
1105 }
1106
1107 tail_pipe = free_pipe;
1108 }
1109
ab2541b6 1110 release_free_pipes_for_stream(&context->res_ctx, dc_stream);
4562236b
HW		 1111
1112 /* assign new surfaces*/
1113 for (i = 0; i < surface_count; i++)
ab2541b6 1114 stream_status->surfaces[i] = surfaces[i];
4562236b 1115
ab2541b6 1116 stream_status->surface_count = surface_count;
4562236b
HW		 1117
1118 return true;
1119}
1120
1121
1122static bool is_timing_changed(const struct core_stream *cur_stream,
1123 const struct core_stream *new_stream)
1124{
1125 if (cur_stream == NULL)
1126 return true;
1127
1128 /* If sink pointer changed, it means this is a hotplug, we should do
1129 * full hw setting.
1130 */
1131 if (cur_stream->sink != new_stream->sink)
1132 return true;
1133
1134 /* If output color space is changed, need to reprogram info frames */
1135 if (cur_stream->public.output_color_space !=
1136 new_stream->public.output_color_space)
1137 return true;
1138
1139 return memcmp(
1140 &cur_stream->public.timing,
1141 &new_stream->public.timing,
1142 sizeof(struct dc_crtc_timing)) != 0;
1143}
1144
1145static bool are_stream_backends_same(
1146 const struct core_stream *stream_a, const struct core_stream *stream_b)
1147{
1148 if (stream_a == stream_b)
1149 return true;
1150
1151 if (stream_a == NULL || stream_b == NULL)
1152 return false;
1153
1154 if (is_timing_changed(stream_a, stream_b))
1155 return false;
1156
1157 return true;
1158}
1159
ab2541b6
AC		 1160bool is_stream_unchanged(
1161 const struct core_stream *old_stream, const struct core_stream *stream)
4562236b 1162{
4562236b 1163
ab2541b6
AC		 1164 if (!are_stream_backends_same(old_stream, stream))
1165 return false;
4562236b
HW		 1166
1167 return true;
1168}
1169
1170bool resource_validate_attach_surfaces(
1171 const struct dc_validation_set set[],
1172 int set_count,
1173 const struct validate_context *old_context,
a2b8659d
TC		 1174 struct validate_context *context,
1175 const struct resource_pool *pool)
4562236b
HW		 1176{
1177 int i, j;
1178
1179 for (i = 0; i < set_count; i++) {
430ef426 1180 for (j = 0; old_context && j < old_context->stream_count; j++)
ab2541b6
AC		 1181 if (is_stream_unchanged(
1182 old_context->streams[j],
1183 context->streams[i])) {
4562236b 1184 if (!resource_attach_surfaces_to_context(
ab2541b6
AC		 1185 old_context->stream_status[j].surfaces,
1186 old_context->stream_status[j].surface_count,
1187 &context->streams[i]->public,
a2b8659d 1188 context, pool))
4562236b 1189 return false;
ab2541b6 1190 context->stream_status[i] = old_context->stream_status[j];
4562236b
HW		 1191 }
1192 if (set[i].surface_count != 0)
1193 if (!resource_attach_surfaces_to_context(
1194 set[i].surfaces,
1195 set[i].surface_count,
ab2541b6 1196 &context->streams[i]->public,
a2b8659d 1197 context, pool))
4562236b
HW		 1198 return false;
1199
1200 }
1201
1202 return true;
1203}
1204
1205/* Maximum TMDS single link pixel clock 165MHz */
1206#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
909e8c9e 1207#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
4562236b
HW		 1208
1209static void set_stream_engine_in_use(
1210 struct resource_context *res_ctx,
a2b8659d 1211 const struct resource_pool *pool,
4562236b
HW		 1212 struct stream_encoder *stream_enc)
1213{
1214 int i;
1215
a2b8659d
TC		 1216 for (i = 0; i < pool->stream_enc_count; i++) {
1217 if (pool->stream_enc[i] == stream_enc)
4562236b
HW		 1218 res_ctx->is_stream_enc_acquired[i] = true;
1219 }
1220}
1221
1222/* TODO: release audio object */
1223static void set_audio_in_use(
1224 struct resource_context *res_ctx,
a2b8659d 1225 const struct resource_pool *pool,
4562236b
HW		 1226 struct audio *audio)
1227{
1228 int i;
a2b8659d
TC		 1229 for (i = 0; i < pool->audio_count; i++) {
1230 if (pool->audios[i] == audio)
4562236b 1231 res_ctx->is_audio_acquired[i] = true;
4562236b
HW		 1232 }
1233}
1234
1235static int acquire_first_free_pipe(
1236 struct resource_context *res_ctx,
a2b8659d 1237 const struct resource_pool *pool,
4562236b
HW		 1238 struct core_stream *stream)
1239{
1240 int i;
1241
a2b8659d 1242 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1243 if (!res_ctx->pipe_ctx[i].stream) {
1244 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1245
f0558542
DL		 1246#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1247 pipe_ctx->mpcc = pool->mpcc[i];
1248#endif
a2b8659d
TC		 1249 pipe_ctx->tg = pool->timing_generators[i];
1250 pipe_ctx->mi = pool->mis[i];
1251 pipe_ctx->ipp = pool->ipps[i];
1252 pipe_ctx->xfm = pool->transforms[i];
1253 pipe_ctx->opp = pool->opps[i];
1254 pipe_ctx->dis_clk = pool->display_clock;
4562236b
HW		 1255 pipe_ctx->pipe_idx = i;
1256
ff5ef992 1257
4562236b
HW		 1258 pipe_ctx->stream = stream;
1259 return i;
1260 }
1261 }
1262 return -1;
1263}
1264
1265static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1266 struct resource_context *res_ctx,
a2b8659d 1267 const struct resource_pool *pool,
4562236b
HW		 1268 struct core_stream *stream)
1269{
1270 int i;
1271 int j = -1;
d0778ebf 1272 struct dc_link *link = stream->sink->link;
4562236b 1273
a2b8659d 1274 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1275 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1276 pool->stream_enc[i]) {
4562236b
HW		 1277 /* Store first available for MST second display
1278 * in daisy chain use case */
1279 j = i;
a2b8659d 1280 if (pool->stream_enc[i]->id ==
4562236b 1281 link->link_enc->preferred_engine)
a2b8659d 1282 return pool->stream_enc[i];
4562236b
HW		 1283 }
1284 }
1285
1286 /*
1287 * below can happen in cases when stream encoder is acquired:
1288 * 1) for second MST display in chain, so preferred engine already
1289 * acquired;
1290 * 2) for another link, which preferred engine already acquired by any
1291 * MST configuration.
1292 *
1293 * If signal is of DP type and preferred engine not found, return last available
1294 *
1295 * TODO - This is just a patch up and a generic solution is
1296 * required for non DP connectors.
1297 */
1298
1299 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1300 return pool->stream_enc[j];
4562236b
HW		 1301
1302 return NULL;
1303}
1304
a2b8659d
TC		 1305static struct audio *find_first_free_audio(
1306 struct resource_context *res_ctx,
1307 const struct resource_pool *pool)
4562236b
HW		 1308{
1309 int i;
a2b8659d 1310 for (i = 0; i < pool->audio_count; i++) {
4562236b 1311 if (res_ctx->is_audio_acquired[i] == false) {
a2b8659d 1312 return pool->audios[i];
4562236b
HW		 1313 }
1314 }
1315
1316 return 0;
1317}
1318
1319static void update_stream_signal(struct core_stream *stream)
1320{
8b32076c
ST		 1321 if (stream->public.output_signal == SIGNAL_TYPE_NONE) {
1322 const struct dc_sink *dc_sink = stream->public.sink;
1323
1324 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
d0778ebf 1325 stream->signal = stream->sink->link->connector_signal;
4562236b 1326 else
8b32076c
ST		 1327 stream->signal = dc_sink->sink_signal;
1328 } else {
1329 stream->signal = stream->public.output_signal;
1330 }
1331
56dcade3 1332 if (dc_is_dvi_signal(stream->signal)) {
909e8c9e
CL		 1333 if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
1334 stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
56dcade3
HW		 1335 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1336 else
1337 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1338 }
4562236b
HW		 1339}
1340
1341bool resource_is_stream_unchanged(
ab2541b6 1342 const struct validate_context *old_context, const struct core_stream *stream)
4562236b 1343{
ab2541b6 1344 int i;
4562236b 1345
ab2541b6
AC		 1346 for (i = 0; i < old_context->stream_count; i++) {
1347 const struct core_stream *old_stream = old_context->streams[i];
4562236b 1348
ab2541b6 1349 if (are_stream_backends_same(old_stream, stream))
4562236b 1350 return true;
4562236b
HW		 1351 }
1352
1353 return false;
1354}
1355
1356static void copy_pipe_ctx(
1357 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1358{
e12cfcb1 1359 struct dc_surface *surface = to_pipe_ctx->surface;
4562236b
HW		 1360 struct core_stream *stream = to_pipe_ctx->stream;
1361
1362 *to_pipe_ctx = *from_pipe_ctx;
1363 to_pipe_ctx->stream = stream;
1364 if (surface != NULL)
1365 to_pipe_ctx->surface = surface;
1366}
1367
1368static struct core_stream *find_pll_sharable_stream(
1369 const struct core_stream *stream_needs_pll,
1370 struct validate_context *context)
1371{
ab2541b6 1372 int i;
4562236b 1373
ab2541b6
AC		 1374 for (i = 0; i < context->stream_count; i++) {
1375 struct core_stream *stream_has_pll = context->streams[i];
4562236b 1376
ab2541b6
AC		 1377 /* We are looking for non dp, non virtual stream */
1378 if (resource_are_streams_timing_synchronizable(
1379 stream_needs_pll, stream_has_pll)
1380 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1381 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1382 != SIGNAL_TYPE_VIRTUAL)
1383 return stream_has_pll;
4562236b 1384
4562236b
HW		 1385 }
1386
1387 return NULL;
1388}
1389
1390static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1391{
1392 uint32_t pix_clk = timing->pix_clk_khz;
1393 uint32_t normalized_pix_clk = pix_clk;
1394
1395 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1396 pix_clk /= 2;
cc4d99b8
CL		 1397 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1398 switch (timing->display_color_depth) {
1399 case COLOR_DEPTH_888:
1400 normalized_pix_clk = pix_clk;
1401 break;
1402 case COLOR_DEPTH_101010:
1403 normalized_pix_clk = (pix_clk * 30) / 24;
1404 break;
1405 case COLOR_DEPTH_121212:
1406 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1407 break;
cc4d99b8
CL		 1408 case COLOR_DEPTH_161616:
1409 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1410 break;
cc4d99b8
CL		 1411 default:
1412 ASSERT(0);
4562236b 1413 break;
cc4d99b8 1414 }
4562236b 1415 }
4562236b
HW		 1416 return normalized_pix_clk;
1417}
1418
430ef426 1419static void calculate_phy_pix_clks(struct validate_context *context)
4562236b 1420{
ab2541b6 1421 int i;
4562236b 1422
ab2541b6
AC		 1423 for (i = 0; i < context->stream_count; i++) {
1424 struct core_stream *stream = context->streams[i];
4562236b 1425
ab2541b6 1426 update_stream_signal(stream);
4562236b 1427
ab2541b6
AC		 1428 /* update actual pixel clock on all streams */
1429 if (dc_is_hdmi_signal(stream->signal))
1430 stream->phy_pix_clk = get_norm_pix_clk(
1431 &stream->public.timing);
1432 else
1433 stream->phy_pix_clk =
1434 stream->public.timing.pix_clk_khz;
4562236b
HW		 1435 }
1436}
1437
1438enum dc_status resource_map_pool_resources(
1439 const struct core_dc *dc,
430ef426
DL		 1440 struct validate_context *context,
1441 struct validate_context *old_context)
4562236b 1442{
a2b8659d 1443 const struct resource_pool *pool = dc->res_pool;
ab2541b6 1444 int i, j;
4562236b 1445
430ef426 1446 calculate_phy_pix_clks(context);
4562236b 1447
430ef426 1448 for (i = 0; old_context && i < context->stream_count; i++) {
ab2541b6 1449 struct core_stream *stream = context->streams[i];
4562236b 1450
430ef426
DL		 1451 if (!resource_is_stream_unchanged(old_context, stream)) {
1452 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1453 stream->bit_depth_params =
430ef426
DL		 1454 old_context->streams[i]->bit_depth_params;
1455 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1456 continue;
1457 }
4b679bc3 1458 }
7e2fe319 1459
ab2541b6 1460 /* mark resources used for stream that is already active */
a2b8659d 1461 for (j = 0; j < pool->pipe_count; j++) {
ab2541b6
AC		 1462 struct pipe_ctx *pipe_ctx =
1463 &context->res_ctx.pipe_ctx[j];
1464 const struct pipe_ctx *old_pipe_ctx =
430ef426 1465 &old_context->res_ctx.pipe_ctx[j];
4562236b 1466
ab2541b6
AC		 1467 if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
1468 continue;
8c737fcc 1469
268cadbd
YS		 1470 if (old_pipe_ctx->top_pipe)
1471 continue;
1472
ab2541b6
AC		 1473 pipe_ctx->stream = stream;
1474 copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
4562236b 1475
ab2541b6
AC		 1476 /* Split pipe resource, do not acquire back end */
1477 if (!pipe_ctx->stream_enc)
1478 continue;
4562236b 1479
ab2541b6 1480 set_stream_engine_in_use(
a2b8659d 1481 &context->res_ctx, pool,
ab2541b6
AC		 1482 pipe_ctx->stream_enc);
1483
1484 /* Switch to dp clock source only if there is
1485 * no non dp stream that shares the same timing
1486 * with the dp stream.
1487 */
1488 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1489 !find_pll_sharable_stream(stream, context))
a2b8659d 1490 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 1491
1492 resource_reference_clock_source(
a2b8659d 1493 &context->res_ctx, pool,
ab2541b6
AC		 1494 pipe_ctx->clock_source);
1495
a2b8659d
TC		 1496 set_audio_in_use(&context->res_ctx, pool,
1497 pipe_ctx->audio);
4562236b
HW		 1498 }
1499 }
1500
ab2541b6
AC		 1501 for (i = 0; i < context->stream_count; i++) {
1502 struct core_stream *stream = context->streams[i];
1503 struct pipe_ctx *pipe_ctx = NULL;
1504 int pipe_idx = -1;
4562236b 1505
430ef426 1506 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 1507 continue;
1508 /* acquire new resources */
5d11e9fc
DL		 1509 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
1510#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1511 if (pipe_idx < 0)
1512 acquire_first_split_pipe(&context->res_ctx, pool, stream);
1513#endif
ab2541b6
AC		 1514 if (pipe_idx < 0)
1515 return DC_NO_CONTROLLER_RESOURCE;
1516
ab2541b6
AC		 1517 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1518
1519 pipe_ctx->stream_enc =
1520 find_first_free_match_stream_enc_for_link(
a2b8659d 1521 &context->res_ctx, pool, stream);
ab2541b6
AC		 1522
1523 if (!pipe_ctx->stream_enc)
1524 return DC_NO_STREAM_ENG_RESOURCE;
1525
1526 set_stream_engine_in_use(
a2b8659d 1527 &context->res_ctx, pool,
ab2541b6
AC		 1528 pipe_ctx->stream_enc);
1529
1530 /* TODO: Add check if ASIC support and EDID audio */
4a9a5d62 1531 if (!stream->sink->public.converter_disable_audio &&
ab2541b6
AC		 1532 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1533 stream->public.audio_info.mode_count) {
1534 pipe_ctx->audio = find_first_free_audio(
a2b8659d 1535 &context->res_ctx, pool);
ab2541b6
AC		 1536
1537 /*
1538 * Audio assigned in order first come first get.
1539 * There are asics which has number of audio
1540 * resources less then number of pipes
1541 */
1542 if (pipe_ctx->audio)
1543 set_audio_in_use(
a2b8659d 1544 &context->res_ctx, pool,
ab2541b6 1545 pipe_ctx->audio);
4562236b 1546 }
ab2541b6
AC		 1547
1548 context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
4562236b
HW		 1549 }
1550
1551 return DC_OK;
1552}
1553
ab2541b6
AC		 1554/* first stream in the context is used to populate the rest */
1555void validate_guaranteed_copy_streams(
4562236b 1556 struct validate_context *context,
ab2541b6 1557 int max_streams)
4562236b
HW		 1558{
1559 int i;
1560
ab2541b6
AC		 1561 for (i = 1; i < max_streams; i++) {
1562 context->streams[i] = context->streams[0];
4562236b
HW		 1563
1564 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1565 &context->res_ctx.pipe_ctx[i]);
1566 context->res_ctx.pipe_ctx[i].stream =
1567 context->res_ctx.pipe_ctx[0].stream;
1568
ab2541b6
AC		 1569 dc_stream_retain(&context->streams[i]->public);
1570 context->stream_count++;
4562236b
HW		 1571 }
1572}
1573
6e4d6bee
TC		 1574static void patch_gamut_packet_checksum(
1575 struct encoder_info_packet *gamut_packet)
4562236b 1576{
4562236b 1577 /* For gamut we recalc checksum */
6e4d6bee 1578 if (gamut_packet->valid) {
4562236b
HW		 1579 uint8_t chk_sum = 0;
1580 uint8_t *ptr;
1581 uint8_t i;
1582
4562236b 1583 /*start of the Gamut data. */
6e4d6bee 1584 ptr = &gamut_packet->sb[3];
4562236b 1585
6e4d6bee 1586 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1587 chk_sum += ptr[i];
1588
6e4d6bee 1589 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1590 }
4562236b
HW		 1591}
1592
1593static void set_avi_info_frame(
6e4d6bee 1594 struct encoder_info_packet *info_packet,
4562236b
HW		 1595 struct pipe_ctx *pipe_ctx)
1596{
1597 struct core_stream *stream = pipe_ctx->stream;
1598 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1599 struct info_frame info_frame = { {0} };
1600 uint32_t pixel_encoding = 0;
1601 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1602 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1603 bool itc = false;
50e27654 1604 uint8_t itc_value = 0;
4562236b 1605 uint8_t cn0_cn1 = 0;
50e27654 1606 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1607 uint8_t *check_sum = NULL;
1608 uint8_t byte_index = 0;
e8d726b7 1609 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
50e27654 1610 union display_content_support support = {0};
15e17335
CL		 1611 unsigned int vic = pipe_ctx->stream->public.timing.vic;
1612 enum dc_timing_3d_format format;
4562236b 1613
4562236b 1614 color_space = pipe_ctx->stream->public.output_color_space;
e5f2038e
CL		 1615 if (color_space == COLOR_SPACE_UNKNOWN)
1616 color_space = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_RGB)?
1617 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1618
1619 /* Initialize header */
e8d726b7 1620 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1621 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1622 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1623 hdmi_info->bits.header.version = 2;
1624 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1625
1626 /*
1627 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1628 * according to HDMI 2.0 spec (Section 10.1)
1629 */
1630
1631 switch (stream->public.timing.pixel_encoding) {
1632 case PIXEL_ENCODING_YCBCR422:
1633 pixel_encoding = 1;
1634 break;
1635
1636 case PIXEL_ENCODING_YCBCR444:
1637 pixel_encoding = 2;
1638 break;
1639 case PIXEL_ENCODING_YCBCR420:
1640 pixel_encoding = 3;
1641 break;
1642
1643 case PIXEL_ENCODING_RGB:
1644 default:
1645 pixel_encoding = 0;
1646 }
1647
1648 /* Y0_Y1_Y2 : The pixel encoding */
1649 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1650 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1651
1652 /* A0 = 1 Active Format Information valid */
e8d726b7 1653 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1654
1655 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1656 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1657
e8d726b7 1658 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1659
1660 /* S0, S1 : Underscan / Overscan */
1661 /* TODO: un-hardcode scan type */
1662 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1663 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1664
1665 /* C0, C1 : Colorimetry */
8fde5884 1666 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1667 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1668 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1669 else if (color_space == COLOR_SPACE_YCBCR601 ||
1670 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1671 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884
CL		 1672 else {
1673 if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
1674 BREAK_TO_DEBUGGER();
e8d726b7 1675 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1676 }
534db198 1677 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1678 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1679 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1680 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1681 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1682 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1683 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1684 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1685 }
1686
4562236b
HW		 1687 /* TODO: un-hardcode aspect ratio */
1688 aspect = stream->public.timing.aspect_ratio;
1689
1690 switch (aspect) {
1691 case ASPECT_RATIO_4_3:
1692 case ASPECT_RATIO_16_9:
e8d726b7 1693 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1694 break;
1695
1696 case ASPECT_RATIO_NO_DATA:
1697 case ASPECT_RATIO_64_27:
1698 case ASPECT_RATIO_256_135:
1699 default:
e8d726b7 1700 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1701 }
1702
1703 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1704 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1705
1706 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1707
4562236b 1708 cn0_cn1 = 0;
50e27654
ZF		 1709 cn0_cn1_value = 0;
1710
1711 itc = true;
1712 itc_value = 1;
1713
1714 support = stream->public.sink->edid_caps.content_support;
4562236b
HW		 1715
1716 if (itc) {
50e27654
ZF		 1717 if (!support.bits.valid_content_type) {
1718 cn0_cn1_value = 0;
1719 } else {
1720 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1721 if (support.bits.graphics_content == 1) {
1722 cn0_cn1_value = 0;
1723 }
1724 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1725 if (support.bits.photo_content == 1) {
1726 cn0_cn1_value = 1;
1727 } else {
1728 cn0_cn1_value = 0;
1729 itc_value = 0;
1730 }
1731 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1732 if (support.bits.cinema_content == 1) {
1733 cn0_cn1_value = 2;
1734 } else {
1735 cn0_cn1_value = 0;
1736 itc_value = 0;
1737 }
1738 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
1739 if (support.bits.game_content == 1) {
1740 cn0_cn1_value = 3;
1741 } else {
1742 cn0_cn1_value = 0;
1743 itc_value = 0;
1744 }
1745 }
1746 }
1747 hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
1748 hdmi_info->bits.ITC = itc_value;
4562236b
HW		 1749 }
1750
1751 /* TODO : We should handle YCC quantization */
1752 /* but we do not have matrix calculation */
50e27654
ZF		 1753 if (stream->public.sink->edid_caps.qs_bit == 1 &&
1754 stream->public.sink->edid_caps.qy_bit == 1) {
1755 if (color_space == COLOR_SPACE_SRGB ||
1756 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
1757 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1758 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
1759 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
1760 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
1761 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1762 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
1763 } else {
1764 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
1765 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
1766 }
4562236b 1767 } else {
e8d726b7 1768 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
50e27654 1769 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 1770 }
50e27654 1771
15e17335
CL		 1772 ///VIC
1773 format = stream->public.timing.timing_3d_format;
1774 /*todo, add 3DStereo support*/
1775 if (format != TIMING_3D_FORMAT_NONE) {
1776 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
1777 switch (pipe_ctx->stream->public.timing.hdmi_vic) {
1778 case 1:
1779 vic = 95;
1780 break;
1781 case 2:
1782 vic = 94;
1783 break;
1784 case 3:
1785 vic = 93;
1786 break;
1787 case 4:
1788 vic = 98;
1789 break;
1790 default:
1791 break;
1792 }
1793 }
1794 hdmi_info->bits.VIC0_VIC7 = vic;
4562236b
HW		 1795
1796 /* pixel repetition
1797 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
1798 * repetition start from 1 */
e8d726b7 1799 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 1800
1801 /* Bar Info
1802 * barTop: Line Number of End of Top Bar.
1803 * barBottom: Line Number of Start of Bottom Bar.
1804 * barLeft: Pixel Number of End of Left Bar.
1805 * barRight: Pixel Number of Start of Right Bar. */
e8d726b7 1806 hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
15e17335 1807 hdmi_info->bits.bar_bottom = (stream->public.timing.v_total
4562236b 1808 - stream->public.timing.v_border_bottom + 1);
e8d726b7
RA		 1809 hdmi_info->bits.bar_left = stream->public.timing.h_border_left;
1810 hdmi_info->bits.bar_right = (stream->public.timing.h_total
4562236b
HW		 1811 - stream->public.timing.h_border_right + 1);
1812
1813 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 1814 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
1815
3e183c5f 1816 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 1817
3e183c5f 1818 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 1819 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 1820
1821 /* one byte complement */
1822 *check_sum = (uint8_t) (0x100 - *check_sum);
1823
1824 /* Store in hw_path_mode */
e8d726b7
RA		 1825 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
1826 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
1827 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 1828
e66e4d64
HW		 1829 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
1830 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 1831 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 1832 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 1833
1834 info_packet->valid = true;
1835}
1836
6e4d6bee
TC		 1837static void set_vendor_info_packet(
1838 struct encoder_info_packet *info_packet,
1839 struct core_stream *stream)
4562236b
HW		 1840{
1841 uint32_t length = 0;
1842 bool hdmi_vic_mode = false;
1843 uint8_t checksum = 0;
1844 uint32_t i = 0;
1845 enum dc_timing_3d_format format;
15e17335
CL		 1846 // Can be different depending on packet content /*todo*/
1847 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
1848
1849 info_packet->valid = false;
4562236b 1850
4562236b 1851 format = stream->public.timing.timing_3d_format;
7f5c22d1
VP		 1852 if (stream->public.view_format == VIEW_3D_FORMAT_NONE)
1853 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 1854
1855 /* Can be different depending on packet content */
1856 length = 5;
1857
1858 if (stream->public.timing.hdmi_vic != 0
1859 && stream->public.timing.h_total >= 3840
1860 && stream->public.timing.v_total >= 2160)
1861 hdmi_vic_mode = true;
1862
1863 /* According to HDMI 1.4a CTS, VSIF should be sent
1864 * for both 3D stereo and HDMI VIC modes.
1865 * For all other modes, there is no VSIF sent. */
1866
1867 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
1868 return;
1869
1870 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
1871 info_packet->sb[1] = 0x03;
1872 info_packet->sb[2] = 0x0C;
1873 info_packet->sb[3] = 0x00;
1874
1875 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
1876 * The value for HDMI_Video_Format are:
1877 * 0x0 (0b000) - No additional HDMI video format is presented in this
1878 * packet
1879 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
1880 * parameter follows
1881 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
1882 * potentially 3D_Ext_Data follows
1883 * 0x3..0x7 (0b011..0b111) - reserved for future use */
1884 if (format != TIMING_3D_FORMAT_NONE)
1885 info_packet->sb[4] = (2 << 5);
1886 else if (hdmi_vic_mode)
1887 info_packet->sb[4] = (1 << 5);
1888
1889 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
1890 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
1891 * The value for 3D_Structure are:
1892 * 0x0 - Frame Packing
1893 * 0x1 - Field Alternative
1894 * 0x2 - Line Alternative
1895 * 0x3 - Side-by-Side (full)
1896 * 0x4 - L + depth
1897 * 0x5 - L + depth + graphics + graphics-depth
1898 * 0x6 - Top-and-Bottom
1899 * 0x7 - Reserved for future use
1900 * 0x8 - Side-by-Side (Half)
1901 * 0x9..0xE - Reserved for future use
1902 * 0xF - Not used */
1903 switch (format) {
1904 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
1905 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
1906 info_packet->sb[5] = (0x0 << 4);
1907 break;
1908
1909 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
1910 case TIMING_3D_FORMAT_SBS_SW_PACKED:
1911 info_packet->sb[5] = (0x8 << 4);
1912 length = 6;
1913 break;
1914
1915 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
1916 case TIMING_3D_FORMAT_TB_SW_PACKED:
1917 info_packet->sb[5] = (0x6 << 4);
1918 break;
1919
1920 default:
1921 break;
1922 }
1923
1924 /*PB5: If PB4 is set to 0x1 (extended resolution format)
1925 * fill PB5 with the correct HDMI VIC code */
1926 if (hdmi_vic_mode)
1927 info_packet->sb[5] = stream->public.timing.hdmi_vic;
1928
1929 /* Header */
3e183c5f 1930 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 1931 info_packet->hb1 = 0x01; /* Version */
1932
1933 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
1934 info_packet->hb2 = (uint8_t) (length);
1935
1936 /* Calculate checksum */
1937 checksum = 0;
1938 checksum += info_packet->hb0;
1939 checksum += info_packet->hb1;
1940 checksum += info_packet->hb2;
1941
1942 for (i = 1; i <= length; i++)
1943 checksum += info_packet->sb[i];
1944
1945 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
1946
1947 info_packet->valid = true;
1948}
1949
6e4d6bee
TC		 1950static void set_spd_info_packet(
1951 struct encoder_info_packet *info_packet,
1952 struct core_stream *stream)
4562236b
HW		 1953{
1954 /* SPD info packet for FreeSync */
1955
1956 unsigned char checksum = 0;
1957 unsigned int idx, payload_size = 0;
1958
1959 /* Check if Freesync is supported. Return if false. If true,
1960 * set the corresponding bit in the info packet
1961 */
1962 if (stream->public.freesync_ctx.supported == false)
1963 return;
1964
1965 if (dc_is_hdmi_signal(stream->signal)) {
1966
1967 /* HEADER */
1968
1969 /* HB0 = Packet Type = 0x83 (Source Product
1970 * Descriptor InfoFrame)
1971 */
3e183c5f 1972 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1973
1974 /* HB1 = Version = 0x01 */
1975 info_packet->hb1 = 0x01;
1976
1977 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1978 info_packet->hb2 = 0x08;
1979
1980 payload_size = 0x08;
1981
1982 } else if (dc_is_dp_signal(stream->signal)) {
1983
1984 /* HEADER */
1985
1986 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1987 * when used to associate audio related info packets
1988 */
1989 info_packet->hb0 = 0x00;
1990
1991 /* HB1 = Packet Type = 0x83 (Source Product
1992 * Descriptor InfoFrame)
1993 */
3e183c5f 1994 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1995
1996 /* HB2 = [Bits 7:0 = Least significant eight bits -
1997 * For INFOFRAME, the value must be 1Bh]
1998 */
1999 info_packet->hb2 = 0x1B;
2000
2001 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2002 * [Bits 1:0 = Most significant two bits = 0x00]
2003 */
2004 info_packet->hb3 = 0x04;
2005
2006 payload_size = 0x1B;
2007 }
2008
2009 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2010 info_packet->sb[1] = 0x1A;
2011
2012 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2013 info_packet->sb[2] = 0x00;
2014
2015 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2016 info_packet->sb[3] = 0x00;
2017
2018 /* PB4 = Reserved */
2019 info_packet->sb[4] = 0x00;
2020
2021 /* PB5 = Reserved */
2022 info_packet->sb[5] = 0x00;
2023
2024 /* PB6 = [Bits 7:3 = Reserved] */
2025 info_packet->sb[6] = 0x00;
2026
2027 if (stream->public.freesync_ctx.supported == true)
2028 /* PB6 = [Bit 0 = FreeSync Supported] */
2029 info_packet->sb[6] |= 0x01;
2030
2031 if (stream->public.freesync_ctx.enabled == true)
2032 /* PB6 = [Bit 1 = FreeSync Enabled] */
2033 info_packet->sb[6] |= 0x02;
2034
2035 if (stream->public.freesync_ctx.active == true)
2036 /* PB6 = [Bit 2 = FreeSync Active] */
2037 info_packet->sb[6] |= 0x04;
2038
2039 /* PB7 = FreeSync Minimum refresh rate (Hz) */
2040 info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx.
2041 min_refresh_in_micro_hz / 1000000);
2042
2043 /* PB8 = FreeSync Maximum refresh rate (Hz)
2044 *
2045 * Note: We do not use the maximum capable refresh rate
2046 * of the panel, because we should never go above the field
2047 * rate of the mode timing set.
2048 */
2049 info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx.
2050 nominal_refresh_in_micro_hz / 1000000);
2051
2052 /* PB9 - PB27 = Reserved */
2053 for (idx = 9; idx <= 27; idx++)
2054 info_packet->sb[idx] = 0x00;
2055
2056 /* Calculate checksum */
2057 checksum += info_packet->hb0;
2058 checksum += info_packet->hb1;
2059 checksum += info_packet->hb2;
2060 checksum += info_packet->hb3;
2061
2062 for (idx = 1; idx <= payload_size; idx++)
2063 checksum += info_packet->sb[idx];
2064
2065 /* PB0 = Checksum (one byte complement) */
2066 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2067
2068 info_packet->valid = true;
2069}
2070
1646a6fe 2071static void set_hdr_static_info_packet(
6e4d6bee 2072 struct encoder_info_packet *info_packet,
e12cfcb1 2073 struct dc_surface *surface,
6e4d6bee 2074 struct core_stream *stream)
1646a6fe 2075{
e5cf325b 2076 uint16_t i = 0;
1646a6fe 2077 enum signal_type signal = stream->signal;
e5cf325b
HW		 2078 struct dc_hdr_static_metadata hdr_metadata;
2079 uint32_t data;
1646a6fe
AW		 2080
2081 if (!surface)
2082 return;
2083
e12cfcb1 2084 hdr_metadata = surface->hdr_static_ctx;
1646a6fe 2085
70063a59 2086 if (!hdr_metadata.hdr_supported)
10bff005
YS		 2087 return;
2088
1646a6fe
AW		 2089 if (dc_is_hdmi_signal(signal)) {
2090 info_packet->valid = true;
2091
2092 info_packet->hb0 = 0x87;
2093 info_packet->hb1 = 0x01;
2094 info_packet->hb2 = 0x1A;
2095 i = 1;
2096 } else if (dc_is_dp_signal(signal)) {
2097 info_packet->valid = true;
2098
2099 info_packet->hb0 = 0x00;
2100 info_packet->hb1 = 0x87;
2101 info_packet->hb2 = 0x1D;
2102 info_packet->hb3 = (0x13 << 2);
2103 i = 2;
2104 }
2105
1646a6fe
AW		 2106 data = hdr_metadata.is_hdr;
2107 info_packet->sb[i++] = data ? 0x02 : 0x00;
2108 info_packet->sb[i++] = 0x00;
2109
2110 data = hdr_metadata.chromaticity_green_x / 2;
2111 info_packet->sb[i++] = data & 0xFF;
2112 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2113
2114 data = hdr_metadata.chromaticity_green_y / 2;
2115 info_packet->sb[i++] = data & 0xFF;
2116 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2117
2118 data = hdr_metadata.chromaticity_blue_x / 2;
2119 info_packet->sb[i++] = data & 0xFF;
2120 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2121
2122 data = hdr_metadata.chromaticity_blue_y / 2;
2123 info_packet->sb[i++] = data & 0xFF;
2124 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2125
2126 data = hdr_metadata.chromaticity_red_x / 2;
2127 info_packet->sb[i++] = data & 0xFF;
2128 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2129
2130 data = hdr_metadata.chromaticity_red_y / 2;
2131 info_packet->sb[i++] = data & 0xFF;
2132 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2133
2134 data = hdr_metadata.chromaticity_white_point_x / 2;
2135 info_packet->sb[i++] = data & 0xFF;
2136 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2137
2138 data = hdr_metadata.chromaticity_white_point_y / 2;
2139 info_packet->sb[i++] = data & 0xFF;
2140 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2141
2142 data = hdr_metadata.max_luminance;
2143 info_packet->sb[i++] = data & 0xFF;
2144 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2145
2146 data = hdr_metadata.min_luminance;
2147 info_packet->sb[i++] = data & 0xFF;
2148 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2149
2150 data = hdr_metadata.maximum_content_light_level;
2151 info_packet->sb[i++] = data & 0xFF;
2152 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2153
2154 data = hdr_metadata.maximum_frame_average_light_level;
2155 info_packet->sb[i++] = data & 0xFF;
2156 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2157
2158 if (dc_is_hdmi_signal(signal)) {
2159 uint32_t checksum = 0;
2160
2161 checksum += info_packet->hb0;
2162 checksum += info_packet->hb1;
2163 checksum += info_packet->hb2;
2164
2165 for (i = 1; i <= info_packet->hb2; i++)
2166 checksum += info_packet->sb[i];
2167
2168 info_packet->sb[0] = 0x100 - checksum;
2169 } else if (dc_is_dp_signal(signal)) {
2170 info_packet->sb[0] = 0x01;
2171 info_packet->sb[1] = 0x1A;
2172 }
2173}
2174
6e4d6bee
TC		 2175static void set_vsc_info_packet(
2176 struct encoder_info_packet *info_packet,
2177 struct core_stream *stream)
4562236b
HW		 2178{
2179 unsigned int vscPacketRevision = 0;
2180 unsigned int i;
2181
94267b3d 2182 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2183 vscPacketRevision = 2;
2184 }
2185
2186 /* VSC packet not needed based on the features
2187 * supported by this DP display
2188 */
2189 if (vscPacketRevision == 0)
2190 return;
2191
2192 if (vscPacketRevision == 0x2) {
2193 /* Secondary-data Packet ID = 0*/
2194 info_packet->hb0 = 0x00;
2195 /* 07h - Packet Type Value indicating Video
2196 * Stream Configuration packet
2197 */
2198 info_packet->hb1 = 0x07;
2199 /* 02h = VSC SDP supporting 3D stereo and PSR
2200 * (applies to eDP v1.3 or higher).
2201 */
2202 info_packet->hb2 = 0x02;
2203 /* 08h = VSC packet supporting 3D stereo + PSR
2204 * (HB2 = 02h).
2205 */
2206 info_packet->hb3 = 0x08;
2207
2208 for (i = 0; i < 28; i++)
2209 info_packet->sb[i] = 0;
2210
2211 info_packet->valid = true;
2212 }
2213
2214 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2215}
2216
8122a253 2217void dc_resource_validate_ctx_destruct(struct validate_context *context)
4562236b
HW		 2218{
2219 int i, j;
2220
ab2541b6
AC		 2221 for (i = 0; i < context->stream_count; i++) {
2222 for (j = 0; j < context->stream_status[i].surface_count; j++)
4562236b 2223 dc_surface_release(
ab2541b6 2224 context->stream_status[i].surfaces[j]);
4562236b 2225
ab2541b6
AC		 2226 context->stream_status[i].surface_count = 0;
2227 dc_stream_release(&context->streams[i]->public);
2228 context->streams[i] = NULL;
4562236b
HW		 2229 }
2230}
2231
2232/*
ab2541b6 2233 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2234 * by the src_ctx
2235 */
8122a253 2236void dc_resource_validate_ctx_copy_construct(
4562236b
HW		 2237 const struct validate_context *src_ctx,
2238 struct validate_context *dst_ctx)
2239{
2240 int i, j;
9a3afbb3 2241 int ref_count = dst_ctx->ref_count;
4562236b
HW		 2242
2243 *dst_ctx = *src_ctx;
2244
a2b8659d 2245 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2246 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2247
2248 if (cur_pipe->top_pipe)
2249 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2250
2251 if (cur_pipe->bottom_pipe)
2252 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2253
2254 }
2255
ab2541b6
AC		 2256 for (i = 0; i < dst_ctx->stream_count; i++) {
2257 dc_stream_retain(&dst_ctx->streams[i]->public);
2258 for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++)
4562236b 2259 dc_surface_retain(
ab2541b6 2260 dst_ctx->stream_status[i].surfaces[j]);
4562236b 2261 }
9a3afbb3
AG		 2262
2263 /* context refcount should not be overridden */
2264 dst_ctx->ref_count = ref_count;
2265
4562236b
HW		 2266}
2267
2268struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2269 struct resource_context *res_ctx,
2270 const struct resource_pool *pool)
4562236b
HW		 2271{
2272 int i;
2273
a2b8659d 2274 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2275 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2276 return pool->clock_sources[i];
4562236b
HW		 2277 }
2278
2279 return NULL;
2280}
2281
2282void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2283{
2284 enum signal_type signal = SIGNAL_TYPE_NONE;
6e4d6bee 2285 struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
4562236b
HW		 2286
2287 /* default all packets to invalid */
6e4d6bee
TC		 2288 info->avi.valid = false;
2289 info->gamut.valid = false;
2290 info->vendor.valid = false;
630e3573 2291 info->spd.valid = false;
6e4d6bee
TC		 2292 info->hdrsmd.valid = false;
2293 info->vsc.valid = false;
4562236b
HW		 2294
2295 signal = pipe_ctx->stream->signal;
2296
2297 /* HDMi and DP have different info packets*/
2298 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2299 set_avi_info_frame(&info->avi, pipe_ctx);
2300
2301 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2302
2303 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2304
2305 set_hdr_static_info_packet(&info->hdrsmd,
2306 pipe_ctx->surface, pipe_ctx->stream);
2307
a33fa99d 2308 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2309 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2310
2311 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2312
2313 set_hdr_static_info_packet(&info->hdrsmd,
2314 pipe_ctx->surface, pipe_ctx->stream);
a33fa99d 2315 }
4562236b 2316
6e4d6bee 2317 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2318}
2319
2320enum dc_status resource_map_clock_resources(
2321 const struct core_dc *dc,
430ef426
DL		 2322 struct validate_context *context,
2323 struct validate_context *old_context)
4562236b 2324{
ab2541b6 2325 int i, j;
a2b8659d 2326 const struct resource_pool *pool = dc->res_pool;
4562236b
HW		 2327
2328 /* acquire new resources */
ab2541b6
AC		 2329 for (i = 0; i < context->stream_count; i++) {
2330 const struct core_stream *stream = context->streams[i];
4562236b 2331
430ef426 2332 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 2333 continue;
2334
2335 for (j = 0; j < MAX_PIPES; j++) {
2336 struct pipe_ctx *pipe_ctx =
2337 &context->res_ctx.pipe_ctx[j];
4562236b 2338
ab2541b6 2339 if (context->res_ctx.pipe_ctx[j].stream != stream)
4562236b
HW		 2340 continue;
2341
ab2541b6
AC		 2342 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2343 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
a2b8659d 2344 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 2345 else {
2346 pipe_ctx->clock_source = NULL;
4562236b 2347
ab2541b6
AC		 2348 if (!dc->public.config.disable_disp_pll_sharing)
2349 resource_find_used_clk_src_for_sharing(
2350 &context->res_ctx,
2351 pipe_ctx);
4562236b 2352
ab2541b6 2353 if (pipe_ctx->clock_source == NULL)
4562236b 2354 pipe_ctx->clock_source =
a2b8659d
TC		 2355 dc_resource_find_first_free_pll(
2356 &context->res_ctx,
2357 pool);
ab2541b6 2358 }
4562236b 2359
ab2541b6
AC		 2360 if (pipe_ctx->clock_source == NULL)
2361 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2362
ab2541b6 2363 resource_reference_clock_source(
a2b8659d 2364 &context->res_ctx, pool,
ab2541b6 2365 pipe_ctx->clock_source);
4562236b 2366
ab2541b6
AC		 2367 /* only one cs per stream regardless of mpo */
2368 break;
4562236b
HW		 2369 }
2370 }
2371
2372 return DC_OK;
2373}
2374
2375/*
2376 * Note: We need to disable output if clock sources change,
2377 * since bios does optimization and doesn't apply if changing
2378 * PHY when not already disabled.
2379 */
2380bool pipe_need_reprogram(
2381 struct pipe_ctx *pipe_ctx_old,
2382 struct pipe_ctx *pipe_ctx)
2383{
cfe4645e
DL		 2384 if (!pipe_ctx_old->stream)
2385 return false;
2386
4562236b
HW		 2387 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2388 return true;
2389
2390 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2391 return true;
2392
2393 if (pipe_ctx_old->audio != pipe_ctx->audio)
2394 return true;
2395
2396 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2397 && pipe_ctx_old->stream != pipe_ctx->stream)
2398 return true;
2399
2400 if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
2401 return true;
2402
2403 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2404 return true;
2405
2406
2407 return false;
2408}
529cad0f
DW		 2409
2410void resource_build_bit_depth_reduction_params(const struct core_stream *stream,
2411 struct bit_depth_reduction_params *fmt_bit_depth)
2412{
2413 enum dc_dither_option option = stream->public.dither_option;
2414 enum dc_pixel_encoding pixel_encoding =
2415 stream->public.timing.pixel_encoding;
2416
2417 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2418
2419 if (option == DITHER_OPTION_DISABLE)
2420 return;
2421
2422 if (option == DITHER_OPTION_TRUN6) {
2423 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2424 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2425 } else if (option == DITHER_OPTION_TRUN8 ||
2426 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2427 option == DITHER_OPTION_TRUN8_FM6) {
2428 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2429 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2430 } else if (option == DITHER_OPTION_TRUN10 ||
2431 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2432 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2433 option == DITHER_OPTION_TRUN10_FM8 ||
2434 option == DITHER_OPTION_TRUN10_FM6 ||
2435 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2436 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2437 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2438 }
2439
2440 /* special case - Formatter can only reduce by 4 bits at most.
2441 * When reducing from 12 to 6 bits,
2442 * HW recommends we use trunc with round mode
2443 * (if we did nothing, trunc to 10 bits would be used)
2444 * note that any 12->10 bit reduction is ignored prior to DCE8,
2445 * as the input was 10 bits.
2446 */
2447 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2448 option == DITHER_OPTION_SPATIAL6 ||
2449 option == DITHER_OPTION_FM6) {
2450 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2451 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2452 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2453 }
2454
2455 /* spatial dither
2456 * note that spatial modes 1-3 are never used
2457 */
2458 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2459 option == DITHER_OPTION_SPATIAL6 ||
2460 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2461 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2462 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2463 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2464 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2465 fmt_bit_depth->flags.RGB_RANDOM =
2466 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2467 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2468 option == DITHER_OPTION_SPATIAL8 ||
2469 option == DITHER_OPTION_SPATIAL8_FM6 ||
2470 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2471 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2472 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2473 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2474 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2475 fmt_bit_depth->flags.RGB_RANDOM =
2476 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2477 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2478 option == DITHER_OPTION_SPATIAL10 ||
2479 option == DITHER_OPTION_SPATIAL10_FM8 ||
2480 option == DITHER_OPTION_SPATIAL10_FM6) {
2481 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2482 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2483 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2484 fmt_bit_depth->flags.RGB_RANDOM =
2485 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2486 }
2487
2488 if (option == DITHER_OPTION_SPATIAL6 ||
2489 option == DITHER_OPTION_SPATIAL8 ||
2490 option == DITHER_OPTION_SPATIAL10) {
2491 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2492 } else {
2493 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2494 }
2495
2496 //////////////////////
2497 //// temporal dither
2498 //////////////////////
2499 if (option == DITHER_OPTION_FM6 ||
2500 option == DITHER_OPTION_SPATIAL8_FM6 ||
2501 option == DITHER_OPTION_SPATIAL10_FM6 ||
2502 option == DITHER_OPTION_TRUN10_FM6 ||
2503 option == DITHER_OPTION_TRUN8_FM6 ||
2504 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2505 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2506 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2507 } else if (option == DITHER_OPTION_FM8 ||
2508 option == DITHER_OPTION_SPATIAL10_FM8 ||
2509 option == DITHER_OPTION_TRUN10_FM8) {
2510 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2511 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2512 } else if (option == DITHER_OPTION_FM10) {
2513 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2514 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2515 }
2516
2517 fmt_bit_depth->pixel_encoding = pixel_encoding;
2518}
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