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drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW		 44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
dc37a9a0 49#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635
HW		 52#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
53#include "dcn20/dcn20_resource.h"
54#endif
2c8ad2d5 55#include "dce120/dce120_resource.h"
5d4b05dd
BL		 56
57#define DC_LOGGER_INIT(logger)
58
4562236b
HW		 59enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
60{
61 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
62 switch (asic_id.chip_family) {
63
64 case FAMILY_CI:
4562236b
HW		 65 dc_version = DCE_VERSION_8_0;
66 break;
ebfdf0d0
AD		 67 case FAMILY_KV:
68 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
71 dc_version = DCE_VERSION_8_3;
72 else
73 dc_version = DCE_VERSION_8_1;
74 break;
4562236b
HW		 75 case FAMILY_CZ:
76 dc_version = DCE_VERSION_11_0;
77 break;
78
79 case FAMILY_VI:
80 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
82 dc_version = DCE_VERSION_10_0;
83 break;
84 }
85 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 86 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 88 dc_version = DCE_VERSION_11_2;
89 }
0c75d5ac
JFZ		 90 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
91 dc_version = DCE_VERSION_11_22;
4562236b 92 break;
2c8ad2d5 93 case FAMILY_AI:
b8b6ce89
LL		 94 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
95 dc_version = DCE_VERSION_12_1;
96 else
97 dc_version = DCE_VERSION_12_0;
2c8ad2d5 98 break;
dc37a9a0 99#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 100 case FAMILY_RV:
101 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 102 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
103 dc_version = DCN_VERSION_1_01;
ff5ef992
AD		 104 break;
105#endif
7ed4e635
HW		 106
107#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
111#endif
4562236b
HW		 112 default:
113 dc_version = DCE_VERSION_UNKNOWN;
114 break;
115 }
116 return dc_version;
117}
118
d9673c92
HW		 119struct resource_pool *dc_create_resource_pool(struct dc *dc,
120 const struct dc_init_data *init_data,
121 enum dce_version dc_version)
4562236b 122{
5ac3d3c9 123 struct resource_pool *res_pool = NULL;
4562236b
HW		 124
125 switch (dc_version) {
126 case DCE_VERSION_8_0:
7992a629 127 res_pool = dce80_create_resource_pool(
d9673c92 128 init_data->num_virtual_links, dc);
7992a629 129 break;
ebfdf0d0 130 case DCE_VERSION_8_1:
7992a629 131 res_pool = dce81_create_resource_pool(
d9673c92 132 init_data->num_virtual_links, dc);
7992a629 133 break;
ebfdf0d0 134 case DCE_VERSION_8_3:
7992a629 135 res_pool = dce83_create_resource_pool(
d9673c92 136 init_data->num_virtual_links, dc);
5ac3d3c9 137 break;
4562236b 138 case DCE_VERSION_10_0:
5ac3d3c9 139 res_pool = dce100_create_resource_pool(
d9673c92 140 init_data->num_virtual_links, dc);
5ac3d3c9 141 break;
4562236b 142 case DCE_VERSION_11_0:
5ac3d3c9 143 res_pool = dce110_create_resource_pool(
d9673c92
HW		 144 init_data->num_virtual_links, dc,
145 init_data->asic_id);
5ac3d3c9 146 break;
4562236b 147 case DCE_VERSION_11_2:
0c75d5ac 148 case DCE_VERSION_11_22:
5ac3d3c9 149 res_pool = dce112_create_resource_pool(
d9673c92 150 init_data->num_virtual_links, dc);
5ac3d3c9 151 break;
2c8ad2d5 152 case DCE_VERSION_12_0:
b8b6ce89 153 case DCE_VERSION_12_1:
2c8ad2d5 154 res_pool = dce120_create_resource_pool(
d9673c92 155 init_data->num_virtual_links, dc);
2c8ad2d5 156 break;
ff5ef992 157
dc37a9a0 158#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 159 case DCN_VERSION_1_0:
0e3d73f1 160 case DCN_VERSION_1_01:
d9673c92 161 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992
AD		 162 break;
163#endif
3639fa68
ZF		 164
165
7ed4e635
HW		 166#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
167 case DCN_VERSION_2_0:
168 res_pool = dcn20_create_resource_pool(init_data, dc);
169 break;
170#endif
171
4562236b
HW		 172 default:
173 break;
174 }
5ac3d3c9 175 if (res_pool != NULL) {
1515a47b 176 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 177
178 if (dc->ctx->dc_bios->funcs->get_firmware_info(
179 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
33d7598d
JL		 180 res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
181
182 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
183 // On FPGA these dividers are currently not configured by GDB
184 res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
185 res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
186 } else if (res_pool->dccg && res_pool->hubbub) {
187 // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error
188 // as this value must be known for DCHUB programming
189 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
190 fw_info.pll_info.crystal_frequency,
191 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
192
193 // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error
194 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
195 res_pool->ref_clocks.dccg_ref_clock_inKhz,
196 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
197 } else {
198 // Not all ASICs have DCCG sw component
199 res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
200 res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
201 }
5ac3d3c9
CL		 202 } else
203 ASSERT_CRITICAL(false);
204 }
4562236b 205
5ac3d3c9 206 return res_pool;
4562236b
HW		 207}
208
fb3466a4 209void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 210{
211 if (dc) {
212 if (dc->res_pool)
213 dc->res_pool->funcs->destroy(&dc->res_pool);
214
d029810c 215 kfree(dc->hwseq);
4562236b
HW		 216 }
217}
218
219static void update_num_audio(
220 const struct resource_straps *straps,
221 unsigned int *num_audio,
222 struct audio_support *aud_support)
223{
b8e9eb72
CL		 224 aud_support->dp_audio = true;
225 aud_support->hdmi_audio_native = false;
226 aud_support->hdmi_audio_on_dongle = false;
227
4562236b 228 if (straps->hdmi_disable == 0) {
4562236b
HW		 229 if (straps->dc_pinstraps_audio & 0x2) {
230 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 231 aud_support->hdmi_audio_native = true;
4562236b
HW		 232 }
233 }
234
235 switch (straps->audio_stream_number) {
236 case 0: /* multi streams supported */
237 break;
238 case 1: /* multi streams not supported */
239 *num_audio = 1;
240 break;
241 default:
242 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 243 }
4562236b
HW		 244}
245
246bool resource_construct(
247 unsigned int num_virtual_links,
fb3466a4 248 struct dc *dc,
4562236b
HW		 249 struct resource_pool *pool,
250 const struct resource_create_funcs *create_funcs)
251{
252 struct dc_context *ctx = dc->ctx;
253 const struct resource_caps *caps = pool->res_cap;
254 int i;
255 unsigned int num_audio = caps->num_audio;
256 struct resource_straps straps = {0};
257
258 if (create_funcs->read_dce_straps)
259 create_funcs->read_dce_straps(dc->ctx, &straps);
260
261 pool->audio_count = 0;
262 if (create_funcs->create_audio) {
263 /* find the total number of streams available via the
264 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
265 * registers (one for each pin) starting from pin 1
266 * up to the max number of audio pins.
267 * We stop on the first pin where
268 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
269 */
270 update_num_audio(&straps, &num_audio, &pool->audio_support);
271 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
272 struct audio *aud = create_funcs->create_audio(ctx, i);
273
274 if (aud == NULL) {
275 DC_ERR("DC: failed to create audio!\n");
276 return false;
277 }
278
279 if (!aud->funcs->endpoint_valid(aud)) {
280 aud->funcs->destroy(&aud);
281 break;
282 }
283
284 pool->audios[i] = aud;
285 pool->audio_count++;
286 }
287 }
288
289 pool->stream_enc_count = 0;
290 if (create_funcs->create_stream_encoder) {
291 for (i = 0; i < caps->num_stream_encoder; i++) {
292 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
293 if (pool->stream_enc[i] == NULL)
294 DC_ERR("DC: failed to create stream_encoder!\n");
295 pool->stream_enc_count++;
296 }
297 }
929c3aaa 298
4176664b
CL		 299 dc->caps.dynamic_audio = false;
300 if (pool->audio_count < pool->stream_enc_count) {
301 dc->caps.dynamic_audio = true;
302 }
4562236b
HW		 303 for (i = 0; i < num_virtual_links; i++) {
304 pool->stream_enc[pool->stream_enc_count] =
305 virtual_stream_encoder_create(
306 ctx, ctx->dc_bios);
307 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
308 DC_ERR("DC: failed to create stream_encoder!\n");
309 return false;
310 }
311 pool->stream_enc_count++;
312 }
313
314 dc->hwseq = create_funcs->create_hwseq(ctx);
315
316 return true;
317}
ad8960a6
ML		 318static int find_matching_clock_source(
319 const struct resource_pool *pool,
320 struct clock_source *clock_source)
321{
4562236b 322
ad8960a6
ML		 323 int i;
324
325 for (i = 0; i < pool->clk_src_count; i++) {
326 if (pool->clock_sources[i] == clock_source)
327 return i;
328 }
329 return -1;
330}
4562236b 331
21e67d4d 332void resource_unreference_clock_source(
4562236b 333 struct resource_context *res_ctx,
a2b8659d 334 const struct resource_pool *pool,
4a629536 335 struct clock_source *clock_source)
4562236b 336{
ad8960a6 337 int i = find_matching_clock_source(pool, clock_source);
4562236b 338
ad8960a6 339 if (i > -1)
4562236b
HW		 340 res_ctx->clock_source_ref_count[i]--;
341
21e67d4d 342 if (pool->dp_clock_source == clock_source)
4562236b 343 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 344}
345
346void resource_reference_clock_source(
347 struct resource_context *res_ctx,
a2b8659d 348 const struct resource_pool *pool,
4562236b
HW		 349 struct clock_source *clock_source)
350{
ad8960a6 351 int i = find_matching_clock_source(pool, clock_source);
4562236b 352
ad8960a6 353 if (i > -1)
4562236b 354 res_ctx->clock_source_ref_count[i]++;
4562236b 355
a2b8659d 356 if (pool->dp_clock_source == clock_source)
4562236b
HW		 357 res_ctx->dp_clock_source_ref_count++;
358}
359
ad8960a6
ML		 360int resource_get_clock_source_reference(
361 struct resource_context *res_ctx,
362 const struct resource_pool *pool,
363 struct clock_source *clock_source)
364{
365 int i = find_matching_clock_source(pool, clock_source);
366
367 if (i > -1)
368 return res_ctx->clock_source_ref_count[i];
369
370 if (pool->dp_clock_source == clock_source)
371 return res_ctx->dp_clock_source_ref_count;
372
373 return -1;
374}
375
4562236b 376bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 377 struct dc_stream_state *stream1,
378 struct dc_stream_state *stream2)
4562236b 379{
4fa086b9 380 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 381 return false;
382
4fa086b9 383 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 384 return false;
385
4fa086b9
LSL		 386 if (stream1->timing.h_addressable
387 != stream2->timing.h_addressable)
4562236b
HW		 388 return false;
389
4fa086b9
LSL		 390 if (stream1->timing.v_addressable
391 != stream2->timing.v_addressable)
4562236b
HW		 392 return false;
393
380604e2
KC		 394 if (stream1->timing.pix_clk_100hz
395 != stream2->timing.pix_clk_100hz)
4562236b
HW		 396 return false;
397
3e27e10e
ML		 398 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
399 return false;
400
4562236b 401 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 402 && (!dc_is_dp_signal(stream1->signal)
403 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 404 return false;
405
d77f778e
CL		 406 if (stream1->view_format != stream2->view_format)
407 return false;
408
4562236b
HW		 409 return true;
410}
3e27e10e
ML		 411static bool is_dp_and_hdmi_sharable(
412 struct dc_stream_state *stream1,
413 struct dc_stream_state *stream2)
414{
415 if (stream1->ctx->dc->caps.disable_dp_clk_share)
416 return false;
417
418 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 419 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 420 return false;
3e27e10e
ML		 421
422 return true;
423
424}
4562236b
HW		 425
426static bool is_sharable_clk_src(
427 const struct pipe_ctx *pipe_with_clk_src,
428 const struct pipe_ctx *pipe)
429{
430 if (pipe_with_clk_src->clock_source == NULL)
431 return false;
432
433 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
434 return false;
435
3e27e10e
ML		 436 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
437 (dc_is_dp_signal(pipe->stream->signal) &&
438 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
439 pipe->stream)))
4562236b
HW		 440 return false;
441
442 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 443 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 444 return false;
445
446 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 447 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 448 return false;
449
450 if (!resource_are_streams_timing_synchronizable(
451 pipe_with_clk_src->stream, pipe->stream))
452 return false;
453
454 return true;
455}
456
457struct clock_source *resource_find_used_clk_src_for_sharing(
458 struct resource_context *res_ctx,
459 struct pipe_ctx *pipe_ctx)
460{
461 int i;
462
463 for (i = 0; i < MAX_PIPES; i++) {
464 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
465 return res_ctx->pipe_ctx[i].clock_source;
466 }
467
468 return NULL;
469}
470
471static enum pixel_format convert_pixel_format_to_dalsurface(
472 enum surface_pixel_format surface_pixel_format)
473{
474 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
475
476 switch (surface_pixel_format) {
477 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
478 dal_pixel_format = PIXEL_FORMAT_INDEX8;
479 break;
480 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
481 dal_pixel_format = PIXEL_FORMAT_RGB565;
482 break;
483 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
484 dal_pixel_format = PIXEL_FORMAT_RGB565;
485 break;
486 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
487 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
488 break;
8693049a 489 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 490 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
491 break;
492 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
493 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
494 break;
495 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
496 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
497 break;
498 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
499 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
500 break;
501 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
502 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
503 dal_pixel_format = PIXEL_FORMAT_FP16;
504 break;
505 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 506 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 507 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 508 break;
ffbcd19a
VP		 509 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
510 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 511 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 512 break;
4562236b
HW		 513 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
514 default:
515 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
516 break;
517 }
518 return dal_pixel_format;
519}
520
9b6067c0
DL		 521static inline void get_vp_scan_direction(
522 enum dc_rotation_angle rotation,
523 bool horizontal_mirror,
524 bool *orthogonal_rotation,
525 bool *flip_vert_scan_dir,
526 bool *flip_horz_scan_dir)
4562236b 527{
9b6067c0
DL		 528 *orthogonal_rotation = false;
529 *flip_vert_scan_dir = false;
530 *flip_horz_scan_dir = false;
531 if (rotation == ROTATION_ANGLE_180) {
532 *flip_vert_scan_dir = true;
533 *flip_horz_scan_dir = true;
534 } else if (rotation == ROTATION_ANGLE_90) {
535 *orthogonal_rotation = true;
536 *flip_horz_scan_dir = true;
537 } else if (rotation == ROTATION_ANGLE_270) {
538 *orthogonal_rotation = true;
539 *flip_vert_scan_dir = true;
540 }
541
542 if (horizontal_mirror)
543 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 544}
545
b2d0a103 546static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 547{
3be5262e 548 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 549 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 550 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 551 struct rect surf_src = plane_state->src_rect;
9b6067c0 552 struct rect clip, dest;
87449a90
AK		 553 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
554 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 555 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 556 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 557 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 558 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 559 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 560
7f5c22d1
VP		 561 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
562 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 563 pri_split = false;
564 sec_split = false;
565 }
86006a7f 566
4562236b
HW		 567 /* The actual clip is an intersection between stream
568 * source and surface clip
569 */
9b6067c0 570 dest = plane_state->dst_rect;
3be5262e
HW		 571 clip.x = stream->src.x > plane_state->clip_rect.x ?
572 stream->src.x : plane_state->clip_rect.x;
4562236b 573
1fbd2cfc 574 clip.width = stream->src.x + stream->src.width <
3be5262e 575 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 576 stream->src.x + stream->src.width - clip.x :
3be5262e 577 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 578
3be5262e
HW		 579 clip.y = stream->src.y > plane_state->clip_rect.y ?
580 stream->src.y : plane_state->clip_rect.y;
4562236b 581
1fbd2cfc 582 clip.height = stream->src.y + stream->src.height <
3be5262e 583 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 584 stream->src.y + stream->src.height - clip.y :
3be5262e 585 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 586
9b6067c0
DL		 587 /*
588 * Need to calculate how scan origin is shifted in vp space
589 * to correctly rotate clip and dst
590 */
591 get_vp_scan_direction(
592 plane_state->rotation,
593 plane_state->horizontal_mirror,
594 &orthogonal_rotation,
595 &flip_y_start,
596 &flip_x_start);
597
598 if (orthogonal_rotation) {
599 swap(clip.x, clip.y);
600 swap(clip.width, clip.height);
601 swap(dest.x, dest.y);
602 swap(dest.width, dest.height);
603 }
604 if (flip_x_start) {
605 clip.x = dest.x + dest.width - clip.x - clip.width;
606 dest.x = 0;
607 }
608 if (flip_y_start) {
609 clip.y = dest.y + dest.height - clip.y - clip.height;
610 dest.y = 0;
611 }
612
86006a7f 613 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 614 * num_pixels = clip.num_pix * scl_ratio
615 */
9b6067c0
DL		 616 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
617 data->viewport.width = clip.width * surf_src.width / dest.width;
618
619 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
620 data->viewport.height = clip.height * surf_src.height / dest.height;
621
622 /* Handle split */
623 if (pri_split || sec_split) {
624 if (orthogonal_rotation) {
625 if (flip_y_start != pri_split)
626 data->viewport.height /= 2;
627 else {
628 data->viewport.y += data->viewport.height / 2;
629 /* Ceil offset pipe */
630 data->viewport.height = (data->viewport.height + 1) / 2;
631 }
632 } else {
633 if (flip_x_start != pri_split)
634 data->viewport.width /= 2;
635 else {
636 data->viewport.x += data->viewport.width / 2;
637 /* Ceil offset pipe */
638 data->viewport.width = (data->viewport.width + 1) / 2;
639 }
640 }
641 }
9b5349f7 642
b2d0a103
DL		 643 /* Round down, compensate in init */
644 data->viewport_c.x = data->viewport.x / vpc_div;
645 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 646 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
647 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
648
b2d0a103
DL		 649 /* Round up, assume original video size always even dimensions */
650 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
651 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 652}
653
9b6067c0 654static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 655{
3be5262e 656 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 657 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 658 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS		 659 bool pri_split = pipe_ctx->bottom_pipe &&
660 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
661 bool sec_split = pipe_ctx->top_pipe &&
662 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 663 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 664
6702a9ac 665 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 666 if (stream->src.x < surf_clip.x)
6702a9ac 667 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 668 - stream->src.x) * stream->dst.width
669 / stream->src.width;
4562236b 670
6702a9ac 671 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 672 stream->dst.width / stream->src.width;
6702a9ac 673 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 674 stream->dst.x + stream->dst.width)
6702a9ac 675 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 676 stream->dst.x + stream->dst.width
6702a9ac 677 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 678
6702a9ac 679 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 680 if (stream->src.y < surf_clip.y)
6702a9ac 681 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 682 - stream->src.y) * stream->dst.height
683 / stream->src.height;
4562236b 684
6702a9ac 685 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 686 stream->dst.height / stream->src.height;
6702a9ac 687 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 688 stream->dst.y + stream->dst.height)
6702a9ac 689 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 690 stream->dst.y + stream->dst.height
6702a9ac 691 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 692
9b6067c0 693 /* Handle h & v split, handle rotation using viewport */
b0131391
DL		 694 if (sec_split && top_bottom_split) {
695 pipe_ctx->plane_res.scl_data.recout.y +=
696 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 697 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 698 pipe_ctx->plane_res.scl_data.recout.height =
699 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
700 } else if (pri_split && top_bottom_split)
0c31a821 701 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL		 702 else if (sec_split) {
703 pipe_ctx->plane_res.scl_data.recout.x +=
704 pipe_ctx->plane_res.scl_data.recout.width / 2;
705 /* Ceil offset pipe */
706 pipe_ctx->plane_res.scl_data.recout.width =
707 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
708 } else if (pri_split)
709 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW		 710}
711
b2d0a103 712static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 713{
3be5262e 714 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 715 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 716 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 717 const int in_w = stream->src.width;
718 const int in_h = stream->src.height;
719 const int out_w = stream->dst.width;
720 const int out_h = stream->dst.height;
4562236b 721
9b6067c0 722 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 723 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
724 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 725 swap(surf_src.height, surf_src.width);
86006a7f 726
eb0e5154 727 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 728 surf_src.width,
3be5262e 729 plane_state->dst_rect.width);
eb0e5154 730 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 731 surf_src.height,
3be5262e 732 plane_state->dst_rect.height);
4562236b 733
4fa086b9 734 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 735 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 736 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 737 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 738
6702a9ac
HW		 739 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
740 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
741 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
742 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 743
6702a9ac
HW		 744 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
745 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 746
6702a9ac
HW		 747 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
748 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
749 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
750 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 751 }
0002d3ac
DL		 752 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
753 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
754 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
755 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
756 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
757 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
758 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
759 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 760}
761
9b6067c0
DL		 762static inline void adjust_vp_and_init_for_seamless_clip(
763 bool flip_scan_dir,
764 int recout_skip,
765 int src_size,
766 int taps,
767 struct fixed31_32 ratio,
768 struct fixed31_32 *init,
769 int *vp_offset,
770 int *vp_size)
b2d0a103 771{
9b6067c0 772 if (!flip_scan_dir) {
9a08f51f 773 /* Adjust for viewport end clip-off */
9b6067c0
DL		 774 if ((*vp_offset + *vp_size) < src_size) {
775 int vp_clip = src_size - *vp_size - *vp_offset;
776 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 777
778 int_part = int_part > 0 ? int_part : 0;
9b6067c0 779 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 780 }
b2d0a103 781
9a08f51f 782 /* Adjust for non-0 viewport offset */
9b6067c0 783 if (*vp_offset) {
9a08f51f
DL		 784 int int_part;
785
9b6067c0
DL		 786 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
787 int_part = dc_fixpt_floor(*init) - *vp_offset;
788 if (int_part < taps) {
789 int int_adj = *vp_offset >= (taps - int_part) ?
790 (taps - int_part) : *vp_offset;
791 *vp_offset -= int_adj;
792 *vp_size += int_adj;
9a08f51f 793 int_part += int_adj;
9b6067c0
DL		 794 } else if (int_part > taps) {
795 *vp_offset += int_part - taps;
796 *vp_size -= int_part - taps;
797 int_part = taps;
9a08f51f 798 }
9b6067c0
DL		 799 init->value &= 0xffffffff;
800 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 801 }
802 } else {
803 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 804 if (*vp_offset) {
805 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 806
9a08f51f 807 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 808 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
809 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 810 }
b2d0a103 811
9a08f51f 812 /* Adjust for viewport end clip-off */
9b6067c0 813 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 814 int int_part;
9b6067c0 815 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 816
817 /*
818 * this is init if vp had no offset, keep in mind this is from the
819 * right side of vp due to scan direction
820 */
9b6067c0 821 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 822 /*
823 * this is the difference between first pixel of viewport available to read
824 * and init position, takning into account scan direction
825 */
9b6067c0
DL		 826 int_part = dc_fixpt_floor(*init) - end_offset;
827 if (int_part < taps) {
828 int int_adj = end_offset >= (taps - int_part) ?
829 (taps - int_part) : end_offset;
830 *vp_size += int_adj;
9a08f51f 831 int_part += int_adj;
9b6067c0
DL		 832 } else if (int_part > taps) {
833 *vp_size += int_part - taps;
834 int_part = taps;
9a08f51f 835 }
9b6067c0
DL		 836 init->value &= 0xffffffff;
837 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 838 }
b2d0a103 839 }
9b6067c0 840}
9a08f51f 841
9b6067c0
DL		 842static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
843{
844 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
845 const struct dc_stream_state *stream = pipe_ctx->stream;
846 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
847 struct rect src = pipe_ctx->plane_state->src_rect;
848 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
849 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
850 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
851 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 852
9b6067c0
DL		 853 /*
854 * Need to calculate the scan direction for viewport to make adjustments
855 */
856 get_vp_scan_direction(
857 plane_state->rotation,
858 plane_state->horizontal_mirror,
859 &orthogonal_rotation,
860 &flip_vert_scan_dir,
861 &flip_horz_scan_dir);
862
863 /* Calculate src rect rotation adjusted to recout space */
864 surf_size_h = src.x + src.width;
865 surf_size_v = src.y + src.height;
866 if (flip_horz_scan_dir)
867 src.x = 0;
868 if (flip_vert_scan_dir)
869 src.y = 0;
870 if (orthogonal_rotation) {
871 swap(src.x, src.y);
872 swap(src.width, src.height);
873 }
9a08f51f 874
9b6067c0
DL		 875 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
876 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
877 * - (surf surf_src offset * 1/ full scl ratio))
878 */
879 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
880 * stream->dst.width / stream->src.width -
881 src.x * plane_state->dst_rect.width / src.width
882 * stream->dst.width / stream->src.width);
883 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
884 * stream->dst.height / stream->src.height -
885 src.y * plane_state->dst_rect.height / src.height
886 * stream->dst.height / stream->src.height);
887 if (orthogonal_rotation)
888 swap(recout_skip_h, recout_skip_v);
889 /*
890 * Init calculated according to formula:
891 * init = (scaling_ratio + number_of_taps + 1) / 2
892 * init_bot = init + scaling_ratio
893 * init_c = init + truncated_vp_c_offset(from calculate viewport)
894 */
895 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
896 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 897
9b6067c0
DL		 898 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
899 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 900
9b6067c0
DL		 901 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
902 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 903
9b6067c0
DL		 904 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
905 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 906
9b6067c0
DL		 907 /*
908 * Taps, inits and scaling ratios are in recout space need to rotate
909 * to viewport rotation before adjustment
910 */
911 adjust_vp_and_init_for_seamless_clip(
912 flip_horz_scan_dir,
913 recout_skip_h,
914 surf_size_h,
915 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
916 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
917 orthogonal_rotation ? &data->inits.v : &data->inits.h,
918 &data->viewport.x,
919 &data->viewport.width);
920 adjust_vp_and_init_for_seamless_clip(
921 flip_horz_scan_dir,
922 recout_skip_h,
923 surf_size_h / vpc_div,
924 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
925 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
926 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
927 &data->viewport_c.x,
928 &data->viewport_c.width);
929 adjust_vp_and_init_for_seamless_clip(
930 flip_vert_scan_dir,
931 recout_skip_v,
932 surf_size_v,
933 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
934 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
935 orthogonal_rotation ? &data->inits.h : &data->inits.v,
936 &data->viewport.y,
937 &data->viewport.height);
938 adjust_vp_and_init_for_seamless_clip(
939 flip_vert_scan_dir,
940 recout_skip_v,
941 surf_size_v / vpc_div,
942 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
943 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
944 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
945 &data->viewport_c.y,
946 &data->viewport_c.height);
b2d0a103
DL		 947
948 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 949 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
950 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 951
b2d0a103
DL		 952}
953
954bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 955{
3be5262e 956 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 957 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 958 bool res = false;
5d4b05dd 959 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 960 /* Important: scaling ratio calculation requires pixel format,
961 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 962 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 963 */
6702a9ac 964 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 965 pipe_ctx->plane_state->format);
b2d0a103
DL		 966
967 calculate_scaling_ratios(pipe_ctx);
4562236b 968
b2d0a103 969 calculate_viewport(pipe_ctx);
4562236b 970
6702a9ac 971 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 972 return false;
973
9b6067c0 974 calculate_recout(pipe_ctx);
4562236b
HW		 975
976 /**
977 * Setting line buffer pixel depth to 24bpp yields banding
978 * on certain displays, such as the Sharp 4k
979 */
6702a9ac 980 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 981
199e458a 982 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 983 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 984
58bb0e63
AJ		 985 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
986 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 987
4562236b 988 /* Taps calculations */
d94585a0
YHL		 989 if (pipe_ctx->plane_res.xfm != NULL)
990 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
991 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
992
993 if (pipe_ctx->plane_res.dpp != NULL)
994 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
995 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 996 if (!res) {
997 /* Try 24 bpp linebuffer */
6702a9ac 998 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 999
1b6c8067
BL		 1000 if (pipe_ctx->plane_res.xfm != NULL)
1001 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1002 pipe_ctx->plane_res.xfm,
1003 &pipe_ctx->plane_res.scl_data,
1004 &plane_state->scaling_quality);
1005
1006 if (pipe_ctx->plane_res.dpp != NULL)
1007 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1008 pipe_ctx->plane_res.dpp,
1009 &pipe_ctx->plane_res.scl_data,
1010 &plane_state->scaling_quality);
4562236b
HW		 1011 }
1012
b2d0a103 1013 if (res)
1fbd2cfc 1014 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1015 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1016
1296423b 1017 DC_LOG_SCALER(
4562236b
HW		 1018 "%s: Viewport:\nheight:%d width:%d x:%d "
1019 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1020 "y:%d\n",
1021 __func__,
6702a9ac
HW		 1022 pipe_ctx->plane_res.scl_data.viewport.height,
1023 pipe_ctx->plane_res.scl_data.viewport.width,
1024 pipe_ctx->plane_res.scl_data.viewport.x,
1025 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 1026 plane_state->dst_rect.height,
1027 plane_state->dst_rect.width,
1028 plane_state->dst_rect.x,
1029 plane_state->dst_rect.y);
4562236b
HW		 1030
1031 return res;
1032}
1033
1034
1035enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1036 const struct dc *dc,
608ac7bb 1037 struct dc_state *context)
4562236b
HW		 1038{
1039 int i;
1040
1041 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1042 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1043 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1044 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1045 return DC_FAIL_SCALING;
4562236b
HW		 1046 }
1047
1048 return DC_OK;
1049}
1050
a2b8659d
TC		 1051struct pipe_ctx *find_idle_secondary_pipe(
1052 struct resource_context *res_ctx,
5581192d
JL		 1053 const struct resource_pool *pool,
1054 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1055{
1056 int i;
1057 struct pipe_ctx *secondary_pipe = NULL;
1058
1059 /*
5581192d
JL		 1060 * We add a preferred pipe mapping to avoid the chance that
1061 * MPCCs already in use will need to be reassigned to other trees.
1062 * For example, if we went with the strict, assign backwards logic:
1063 *
1064 * (State 1)
1065 * Display A on, no surface, top pipe = 0
1066 * Display B on, no surface, top pipe = 1
1067 *
1068 * (State 2)
1069 * Display A on, no surface, top pipe = 0
1070 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1071 *
1072 * (State 3)
1073 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1074 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1075 *
1076 * The state 2->3 transition requires remapping MPCC 5 from display B
1077 * to display A.
1078 *
1079 * However, with the preferred pipe logic, state 2 would look like:
1080 *
1081 * (State 2)
1082 * Display A on, no surface, top pipe = 0
1083 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1084 *
1085 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1086 */
5581192d
JL		 1087 if (primary_pipe) {
1088 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1089 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1090 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1091 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1092 }
1093 }
1094
5581192d
JL		 1095 /*
1096 * search backwards for the second pipe to keep pipe
1097 * assignment more consistent
1098 */
1099 if (!secondary_pipe)
1100 for (i = pool->pipe_count - 1; i >= 0; i--) {
1101 if (res_ctx->pipe_ctx[i].stream == NULL) {
1102 secondary_pipe = &res_ctx->pipe_ctx[i];
1103 secondary_pipe->pipe_idx = i;
1104 break;
1105 }
1106 }
4562236b
HW		 1107
1108 return secondary_pipe;
1109}
1110
1111struct pipe_ctx *resource_get_head_pipe_for_stream(
1112 struct resource_context *res_ctx,
0971c40e 1113 struct dc_stream_state *stream)
4562236b
HW		 1114{
1115 int i;
a2b8659d 1116 for (i = 0; i < MAX_PIPES; i++) {
4562236b 1117 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 1118 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 1119 return &res_ctx->pipe_ctx[i];
1120 break;
1121 }
1122 }
1123 return NULL;
1124}
1125
19f89e23
AG		 1126static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1127 struct resource_context *res_ctx,
1128 struct dc_stream_state *stream)
1129{
1130 struct pipe_ctx *head_pipe, *tail_pipe;
1131 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1132
1133 if (!head_pipe)
1134 return NULL;
1135
1136 tail_pipe = head_pipe->bottom_pipe;
1137
1138 while (tail_pipe) {
1139 head_pipe = tail_pipe;
1140 tail_pipe = tail_pipe->bottom_pipe;
1141 }
1142
1143 return head_pipe;
1144}
1145
4562236b 1146/*
ab2541b6
AC		 1147 * A free_pipe for a stream is defined here as a pipe
1148 * that has no surface attached yet
4562236b 1149 */
ab2541b6 1150static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1151 struct dc_state *context,
a2b8659d 1152 const struct resource_pool *pool,
0971c40e 1153 struct dc_stream_state *stream)
4562236b
HW		 1154{
1155 int i;
745cc746 1156 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1157
1158 struct pipe_ctx *head_pipe = NULL;
1159
1160 /* Find head pipe, which has the back end set up*/
1161
1162 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1163
e41ab030 1164 if (!head_pipe) {
4562236b 1165 ASSERT(0);
e41ab030
HW		 1166 return NULL;
1167 }
4562236b 1168
3be5262e 1169 if (!head_pipe->plane_state)
4562236b
HW		 1170 return head_pipe;
1171
1172 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1173 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1174 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1175 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1176 return &res_ctx->pipe_ctx[i];
1177 }
1178 }
1179
1180 /*
1181 * At this point we have no re-useable pipe for this stream and we need
1182 * to acquire an idle one to satisfy the request
1183 */
1184
a2b8659d 1185 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1186 return NULL;
1187
a2b8659d 1188 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1189
1190}
1191
dc37a9a0 1192#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
0f9a536f
DL		 1193static int acquire_first_split_pipe(
1194 struct resource_context *res_ctx,
1195 const struct resource_pool *pool,
0971c40e 1196 struct dc_stream_state *stream)
0f9a536f
DL		 1197{
1198 int i;
1199
1200 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1201 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1202
1203 if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
1204 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1205 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1206 if (split_pipe->bottom_pipe)
1207 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1208
1209 if (split_pipe->top_pipe->plane_state)
1210 resource_build_scaling_params(split_pipe->top_pipe);
1211
1212 memset(split_pipe, 0, sizeof(*split_pipe));
1213 split_pipe->stream_res.tg = pool->timing_generators[i];
1214 split_pipe->plane_res.hubp = pool->hubps[i];
1215 split_pipe->plane_res.ipp = pool->ipps[i];
1216 split_pipe->plane_res.dpp = pool->dpps[i];
1217 split_pipe->stream_res.opp = pool->opps[i];
1218 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1219 split_pipe->pipe_idx = i;
1220
1221 split_pipe->stream = stream;
0f9a536f
DL		 1222 return i;
1223 }
1224 }
1225 return -1;
1226}
1227#endif
1228
19f89e23
AG		 1229bool dc_add_plane_to_context(
1230 const struct dc *dc,
0971c40e 1231 struct dc_stream_state *stream,
19f89e23 1232 struct dc_plane_state *plane_state,
608ac7bb 1233 struct dc_state *context)
4562236b
HW		 1234{
1235 int i;
19f89e23
AG		 1236 struct resource_pool *pool = dc->res_pool;
1237 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1238 struct dc_stream_status *stream_status = NULL;
4562236b 1239
19f89e23
AG		 1240 for (i = 0; i < context->stream_count; i++)
1241 if (context->streams[i] == stream) {
1242 stream_status = &context->stream_status[i];
1243 break;
1244 }
1245 if (stream_status == NULL) {
1246 dm_error("Existing stream not found; failed to attach surface!\n");
1247 return false;
1248 }
1249
4562236b 1250
19f89e23
AG		 1251 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1252 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1253 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1254 return false;
1255 }
1256
19f89e23
AG		 1257 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1258
1259 if (!head_pipe) {
1260 dm_error("Head pipe not found for stream_state %p !\n", stream);
1261 return false;
1262 }
1263
00737c59
EB		 1264 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1265 ASSERT(tail_pipe);
1266
19f89e23
AG		 1267 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1268
dc37a9a0 1269#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
19f89e23
AG		 1270 if (!free_pipe) {
1271 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1272 if (pipe_idx >= 0)
1273 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1274 }
1275#endif
abb4986e 1276 if (!free_pipe)
19f89e23 1277 return false;
19f89e23 1278
abb4986e
AJ		 1279 /* retain new surfaces */
1280 dc_plane_state_retain(plane_state);
19f89e23
AG		 1281 free_pipe->plane_state = plane_state;
1282
1283 if (head_pipe != free_pipe) {
19f89e23 1284 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1285 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1286 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1287 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1288 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1289 free_pipe->clock_source = tail_pipe->clock_source;
1290 free_pipe->top_pipe = tail_pipe;
1291 tail_pipe->bottom_pipe = free_pipe;
4a797d24
DL		 1292 } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
1293 ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
1294 free_pipe->bottom_pipe->plane_state = plane_state;
19f89e23
AG		 1295 }
1296
1297 /* assign new surfaces*/
1298 stream_status->plane_states[stream_status->plane_count] = plane_state;
1299
1300 stream_status->plane_count++;
1301
1302 return true;
1303}
1304
6ffaa6fc
DL		 1305struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
1306{
1307 struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
1308
1309 /* ODM should only be updated once per otg */
1310 if (pipe_ctx->top_pipe)
1311 return NULL;
1312
1313 while (bottom_pipe) {
1314 if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
1315 break;
1316 bottom_pipe = bottom_pipe->bottom_pipe;
1317 }
1318
1319 return bottom_pipe;
1320}
1321
c0415c87 1322bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
6ffaa6fc
DL		 1323{
1324 struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
6ffaa6fc 1325
fe6382cd
DL		 1326 if (!top_pipe)
1327 return false;
6ffaa6fc
DL		 1328 if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
1329 return false;
1330
fe6382cd 1331 return true;
6ffaa6fc
DL		 1332}
1333
19f89e23
AG		 1334bool dc_remove_plane_from_context(
1335 const struct dc *dc,
1336 struct dc_stream_state *stream,
1337 struct dc_plane_state *plane_state,
608ac7bb 1338 struct dc_state *context)
19f89e23
AG		 1339{
1340 int i;
1341 struct dc_stream_status *stream_status = NULL;
1342 struct resource_pool *pool = dc->res_pool;
1343
ab2541b6 1344 for (i = 0; i < context->stream_count; i++)
4fa086b9 1345 if (context->streams[i] == stream) {
ab2541b6 1346 stream_status = &context->stream_status[i];
4562236b
HW		 1347 break;
1348 }
19f89e23 1349
ab2541b6 1350 if (stream_status == NULL) {
19f89e23 1351 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1352 return false;
1353 }
1354
19f89e23
AG		 1355 /* release pipe for plane*/
1356 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1357 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1358
6ffaa6fc 1359 if (pipe_ctx->plane_state == plane_state) {
c0415c87 1360 if (dc_res_is_odm_head_pipe(pipe_ctx)) {
6ffaa6fc
DL		 1361 pipe_ctx->plane_state = NULL;
1362 pipe_ctx->bottom_pipe = NULL;
1363 continue;
1364 }
4562236b 1365
19f89e23
AG		 1366 if (pipe_ctx->top_pipe)
1367 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1368
19f89e23
AG		 1369 /* Second condition is to avoid setting NULL to top pipe
1370 * of tail pipe making it look like head pipe in subsequent
1371 * deletes
1372 */
1373 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1374 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1375
19f89e23
AG		 1376 /*
1377 * For head pipe detach surfaces from pipe for tail
1378 * pipe just zero it out
1379 */
6ffaa6fc 1380 if (!pipe_ctx->top_pipe) {
19f89e23 1381 pipe_ctx->plane_state = NULL;
6ffaa6fc
DL		 1382 if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
1383 pipe_ctx->bottom_pipe = NULL;
bc219399 1384 } else {
19f89e23
AG		 1385 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1386 }
4562236b 1387 }
19f89e23 1388 }
4562236b 1389
4562236b 1390
19f89e23
AG		 1391 for (i = 0; i < stream_status->plane_count; i++) {
1392 if (stream_status->plane_states[i] == plane_state) {
1393
1394 dc_plane_state_release(stream_status->plane_states[i]);
1395 break;
4562236b 1396 }
19f89e23 1397 }
4562236b 1398
19f89e23
AG		 1399 if (i == stream_status->plane_count) {
1400 dm_error("Existing plane_state not found; failed to detach it!\n");
1401 return false;
4562236b
HW		 1402 }
1403
19f89e23 1404 stream_status->plane_count--;
4562236b 1405
abb4986e
AJ		 1406 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1407 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1408 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1409
1410 stream_status->plane_states[stream_status->plane_count] = NULL;
1411
1412 return true;
1413}
1414
1415bool dc_rem_all_planes_for_stream(
1416 const struct dc *dc,
1417 struct dc_stream_state *stream,
608ac7bb 1418 struct dc_state *context)
19f89e23
AG		 1419{
1420 int i, old_plane_count;
1421 struct dc_stream_status *stream_status = NULL;
1422 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1423
1424 for (i = 0; i < context->stream_count; i++)
1425 if (context->streams[i] == stream) {
1426 stream_status = &context->stream_status[i];
1427 break;
1428 }
1429
1430 if (stream_status == NULL) {
1431 dm_error("Existing stream %p not found!\n", stream);
1432 return false;
1433 }
1434
1435 old_plane_count = stream_status->plane_count;
1436
1437 for (i = 0; i < old_plane_count; i++)
1438 del_planes[i] = stream_status->plane_states[i];
1439
1440 for (i = 0; i < old_plane_count; i++)
1441 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1442 return false;
1443
1444 return true;
1445}
1446
1447static bool add_all_planes_for_stream(
1448 const struct dc *dc,
1449 struct dc_stream_state *stream,
1450 const struct dc_validation_set set[],
1451 int set_count,
608ac7bb 1452 struct dc_state *context)
19f89e23
AG		 1453{
1454 int i, j;
1455
1456 for (i = 0; i < set_count; i++)
1457 if (set[i].stream == stream)
1458 break;
1459
1460 if (i == set_count) {
1461 dm_error("Stream %p not found in set!\n", stream);
1462 return false;
1463 }
4562236b 1464
19f89e23
AG		 1465 for (j = 0; j < set[i].plane_count; j++)
1466 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1467 return false;
4562236b
HW		 1468
1469 return true;
1470}
1471
19f89e23
AG		 1472bool dc_add_all_planes_for_stream(
1473 const struct dc *dc,
1474 struct dc_stream_state *stream,
1475 struct dc_plane_state * const *plane_states,
1476 int plane_count,
608ac7bb 1477 struct dc_state *context)
19f89e23
AG		 1478{
1479 struct dc_validation_set set;
1480 int i;
1481
1482 set.stream = stream;
1483 set.plane_count = plane_count;
1484
1485 for (i = 0; i < plane_count; i++)
1486 set.plane_states[i] = plane_states[i];
1487
1488 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1489}
1490
1491
6b622181
JP		 1492static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1493 struct dc_stream_state *new_stream)
1494{
1495 if (cur_stream == NULL)
1496 return true;
1497
1498 if (memcmp(&cur_stream->hdr_static_metadata,
1499 &new_stream->hdr_static_metadata,
1500 sizeof(struct dc_info_packet)) != 0)
1501 return true;
1502
1503 return false;
1504}
4562236b 1505
1336926f
A		 1506static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1507 struct dc_stream_state *new_stream)
1508{
1509 if (cur_stream == NULL)
1510 return true;
1511
1512 if (memcmp(&cur_stream->vsc_infopacket,
1513 &new_stream->vsc_infopacket,
1514 sizeof(struct dc_info_packet)) != 0)
1515 return true;
1516
1517 return false;
1518}
1519
0971c40e
HW		 1520static bool is_timing_changed(struct dc_stream_state *cur_stream,
1521 struct dc_stream_state *new_stream)
4562236b
HW		 1522{
1523 if (cur_stream == NULL)
1524 return true;
1525
1526 /* If sink pointer changed, it means this is a hotplug, we should do
1527 * full hw setting.
1528 */
1529 if (cur_stream->sink != new_stream->sink)
1530 return true;
1531
1532 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1533 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1534 return true;
1535
1536 return memcmp(
4fa086b9
LSL		 1537 &cur_stream->timing,
1538 &new_stream->timing,
4562236b
HW		 1539 sizeof(struct dc_crtc_timing)) != 0;
1540}
1541
1542static bool are_stream_backends_same(
0971c40e 1543 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1544{
1545 if (stream_a == stream_b)
1546 return true;
1547
1548 if (stream_a == NULL || stream_b == NULL)
1549 return false;
1550
1551 if (is_timing_changed(stream_a, stream_b))
1552 return false;
1553
6b622181
JP		 1554 if (is_hdr_static_meta_changed(stream_a, stream_b))
1555 return false;
1556
1e7e86c4
ST		 1557 if (stream_a->dpms_off != stream_b->dpms_off)
1558 return false;
1559
1336926f
A		 1560 if (is_vsc_info_packet_changed(stream_a, stream_b))
1561 return false;
1562
4562236b
HW		 1563 return true;
1564}
1565
2119aa17
DF		 1566/**
1567 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1568 *
1569 * Checks if there a difference between the two states
1570 * that would require a mode change.
1571 *
1572 * Does not compare cursor position or attributes.
1573 */
d54d29db 1574bool dc_is_stream_unchanged(
0971c40e 1575 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1576{
4562236b 1577
ab2541b6
AC		 1578 if (!are_stream_backends_same(old_stream, stream))
1579 return false;
4562236b
HW		 1580
1581 return true;
1582}
1583
2119aa17
DF		 1584/**
1585 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1586 */
9a5d9c48
LSL		 1587bool dc_is_stream_scaling_unchanged(
1588 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1589{
1590 if (old_stream == stream)
1591 return true;
1592
1593 if (old_stream == NULL || stream == NULL)
1594 return false;
1595
1596 if (memcmp(&old_stream->src,
1597 &stream->src,
1598 sizeof(struct rect)) != 0)
1599 return false;
1600
1601 if (memcmp(&old_stream->dst,
1602 &stream->dst,
1603 sizeof(struct rect)) != 0)
1604 return false;
1605
1606 return true;
1607}
1608
1dc90497 1609static void update_stream_engine_usage(
4562236b 1610 struct resource_context *res_ctx,
a2b8659d 1611 const struct resource_pool *pool,
1dc90497
AG		 1612 struct stream_encoder *stream_enc,
1613 bool acquired)
4562236b
HW		 1614{
1615 int i;
1616
a2b8659d
TC		 1617 for (i = 0; i < pool->stream_enc_count; i++) {
1618 if (pool->stream_enc[i] == stream_enc)
1dc90497 1619 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1620 }
1621}
1622
1623/* TODO: release audio object */
4176664b 1624void update_audio_usage(
4562236b 1625 struct resource_context *res_ctx,
a2b8659d 1626 const struct resource_pool *pool,
1dc90497
AG		 1627 struct audio *audio,
1628 bool acquired)
4562236b
HW		 1629{
1630 int i;
a2b8659d
TC		 1631 for (i = 0; i < pool->audio_count; i++) {
1632 if (pool->audios[i] == audio)
1dc90497 1633 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1634 }
1635}
1636
1637static int acquire_first_free_pipe(
1638 struct resource_context *res_ctx,
a2b8659d 1639 const struct resource_pool *pool,
0971c40e 1640 struct dc_stream_state *stream)
4562236b
HW		 1641{
1642 int i;
1643
a2b8659d 1644 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1645 if (!res_ctx->pipe_ctx[i].stream) {
1646 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1647
6b670fa9 1648 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1649 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1650 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1651 pipe_ctx->plane_res.ipp = pool->ipps[i];
1652 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1653 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1654 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1655 if (pool->dpps[i])
1656 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1657 pipe_ctx->pipe_idx = i;
1658
ff5ef992 1659
4562236b
HW		 1660 pipe_ctx->stream = stream;
1661 return i;
1662 }
1663 }
1664 return -1;
1665}
1666
a2b8659d
TC		 1667static struct audio *find_first_free_audio(
1668 struct resource_context *res_ctx,
cfb071f7
CL		 1669 const struct resource_pool *pool,
1670 enum engine_id id)
4562236b
HW		 1671{
1672 int i;
66bfd4fd
CL		 1673 for (i = 0; i < pool->audio_count; i++) {
1674 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1675 /*we have enough audio endpoint, find the matching inst*/
1676 if (id != i)
1677 continue;
1678
66bfd4fd 1679 return pool->audios[i];
4562236b 1680 }
66bfd4fd
CL		 1681 }
1682 /*not found the matching one, first come first serve*/
1683 for (i = 0; i < pool->audio_count; i++) {
1684 if (res_ctx->is_audio_acquired[i] == false) {
1685 return pool->audios[i];
4176664b
CL		 1686 }
1687 }
4562236b
HW		 1688 return 0;
1689}
1690
4562236b 1691bool resource_is_stream_unchanged(
608ac7bb 1692 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1693{
ab2541b6 1694 int i;
4562236b 1695
ab2541b6 1696 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1697 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1698
ab2541b6 1699 if (are_stream_backends_same(old_stream, stream))
4562236b 1700 return true;
4562236b
HW		 1701 }
1702
1703 return false;
1704}
1705
2119aa17
DF		 1706/**
1707 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1708 */
13ab1b44 1709enum dc_status dc_add_stream_to_ctx(
1dc90497 1710 struct dc *dc,
608ac7bb 1711 struct dc_state *new_ctx,
1dc90497
AG		 1712 struct dc_stream_state *stream)
1713{
1dc90497 1714 enum dc_status res;
eb9714a2 1715 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1716
ece4147f 1717 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1718 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1719 return DC_ERROR_UNEXPECTED;
1720 }
1721
1722 new_ctx->streams[new_ctx->stream_count] = stream;
1723 dc_stream_retain(stream);
1724 new_ctx->stream_count++;
1725
1726 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1727 if (res != DC_OK)
eb9714a2 1728 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1729
13ab1b44 1730 return res;
1dc90497
AG		 1731}
1732
2119aa17
DF		 1733/**
1734 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1735 */
62c933f9 1736enum dc_status dc_remove_stream_from_ctx(
1dc90497 1737 struct dc *dc,
608ac7bb 1738 struct dc_state *new_ctx,
1dc90497
AG		 1739 struct dc_stream_state *stream)
1740{
19f89e23 1741 int i;
1dc90497
AG		 1742 struct dc_context *dc_ctx = dc->ctx;
1743 struct pipe_ctx *del_pipe = NULL;
1744
19f89e23 1745 /* Release primary pipe */
1dc90497 1746 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1747 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1748 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
6ffaa6fc
DL		 1749 struct pipe_ctx *odm_pipe =
1750 dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
1751
1dc90497
AG		 1752 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1753
19f89e23
AG		 1754 ASSERT(del_pipe->stream_res.stream_enc);
1755 update_stream_engine_usage(
1756 &new_ctx->res_ctx,
1dc90497 1757 dc->res_pool,
19f89e23
AG		 1758 del_pipe->stream_res.stream_enc,
1759 false);
1dc90497
AG		 1760
1761 if (del_pipe->stream_res.audio)
1762 update_audio_usage(
1763 &new_ctx->res_ctx,
1764 dc->res_pool,
1765 del_pipe->stream_res.audio,
1766 false);
1767
9d0dcecd
HW		 1768 resource_unreference_clock_source(&new_ctx->res_ctx,
1769 dc->res_pool,
1770 del_pipe->clock_source);
1771
e56ae556
NC		 1772 if (dc->res_pool->funcs->remove_stream_from_ctx)
1773 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1774
1dc90497 1775 memset(del_pipe, 0, sizeof(*del_pipe));
6ffaa6fc
DL		 1776 if (odm_pipe)
1777 memset(odm_pipe, 0, sizeof(*odm_pipe));
1778
1779 break;
1dc90497
AG		 1780 }
1781 }
1782
1783 if (!del_pipe) {
1784 DC_ERROR("Pipe not found for stream %p !\n", stream);
1785 return DC_ERROR_UNEXPECTED;
1786 }
1787
1788 for (i = 0; i < new_ctx->stream_count; i++)
1789 if (new_ctx->streams[i] == stream)
1790 break;
1791
1792 if (new_ctx->streams[i] != stream) {
1793 DC_ERROR("Context doesn't have stream %p !\n", stream);
1794 return DC_ERROR_UNEXPECTED;
1795 }
1796
1797 dc_stream_release(new_ctx->streams[i]);
1798 new_ctx->stream_count--;
1799
1dc90497
AG		 1800 /* Trim back arrays */
1801 for (; i < new_ctx->stream_count; i++) {
1802 new_ctx->streams[i] = new_ctx->streams[i + 1];
1803 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1804 }
1805
1806 new_ctx->streams[new_ctx->stream_count] = NULL;
1807 memset(
1808 &new_ctx->stream_status[new_ctx->stream_count],
1809 0,
1810 sizeof(new_ctx->stream_status[0]));
1811
1812 return DC_OK;
1813}
1814
0971c40e
HW		 1815static struct dc_stream_state *find_pll_sharable_stream(
1816 struct dc_stream_state *stream_needs_pll,
608ac7bb 1817 struct dc_state *context)
4562236b 1818{
ab2541b6 1819 int i;
4562236b 1820
ab2541b6 1821 for (i = 0; i < context->stream_count; i++) {
0971c40e 1822 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1823
ab2541b6
AC		 1824 /* We are looking for non dp, non virtual stream */
1825 if (resource_are_streams_timing_synchronizable(
1826 stream_needs_pll, stream_has_pll)
1827 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1828 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1829 != SIGNAL_TYPE_VIRTUAL)
1830 return stream_has_pll;
4562236b 1831
4562236b
HW		 1832 }
1833
1834 return NULL;
1835}
1836
1837static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1838{
380604e2 1839 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1840 uint32_t normalized_pix_clk = pix_clk;
1841
1842 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1843 pix_clk /= 2;
cc4d99b8
CL		 1844 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1845 switch (timing->display_color_depth) {
1846 case COLOR_DEPTH_888:
1847 normalized_pix_clk = pix_clk;
1848 break;
1849 case COLOR_DEPTH_101010:
1850 normalized_pix_clk = (pix_clk * 30) / 24;
1851 break;
1852 case COLOR_DEPTH_121212:
1853 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1854 break;
cc4d99b8
CL		 1855 case COLOR_DEPTH_161616:
1856 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1857 break;
cc4d99b8
CL		 1858 default:
1859 ASSERT(0);
4562236b 1860 break;
cc4d99b8 1861 }
4562236b 1862 }
4562236b
HW		 1863 return normalized_pix_clk;
1864}
1865
0971c40e 1866static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1867{
9345d987
AG		 1868 /* update actual pixel clock on all streams */
1869 if (dc_is_hdmi_signal(stream->signal))
1870 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1871 &stream->timing) / 10;
9345d987
AG		 1872 else
1873 stream->phy_pix_clk =
380604e2 1874 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1875
1876 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1877 stream->phy_pix_clk *= 2;
4562236b
HW		 1878}
1879
d2d7885f
AK		 1880static int acquire_resource_from_hw_enabled_state(
1881 struct resource_context *res_ctx,
1882 const struct resource_pool *pool,
1883 struct dc_stream_state *stream)
1884{
1885 struct dc_link *link = stream->link;
1886 unsigned int inst;
1887
1888 /* Check for enabled DIG to identify enabled display */
1889 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1890 return -1;
1891
1892 /* Check for which front end is used by this encoder.
1893 * Note the inst is 1 indexed, where 0 is undefined.
1894 * Note that DIG_FE can source from different OTG but our
1895 * current implementation always map 1-to-1, so this code makes
1896 * the same assumption and doesn't check OTG source.
1897 */
1898 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
1899
1900 /* Instance should be within the range of the pool */
1901 if (inst >= pool->pipe_count)
1902 return -1;
1903
1904 if (!res_ctx->pipe_ctx[inst].stream) {
1905 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
1906
1907 pipe_ctx->stream_res.tg = pool->timing_generators[inst];
1908 pipe_ctx->plane_res.mi = pool->mis[inst];
1909 pipe_ctx->plane_res.hubp = pool->hubps[inst];
1910 pipe_ctx->plane_res.ipp = pool->ipps[inst];
1911 pipe_ctx->plane_res.xfm = pool->transforms[inst];
1912 pipe_ctx->plane_res.dpp = pool->dpps[inst];
1913 pipe_ctx->stream_res.opp = pool->opps[inst];
1914 if (pool->dpps[inst])
1915 pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
1916 pipe_ctx->pipe_idx = inst;
1917
1918 pipe_ctx->stream = stream;
1919 return inst;
1920 }
1921
1922 return -1;
1923}
1924
4562236b 1925enum dc_status resource_map_pool_resources(
fb3466a4 1926 const struct dc *dc,
608ac7bb 1927 struct dc_state *context,
1dc90497 1928 struct dc_stream_state *stream)
4562236b 1929{
a2b8659d 1930 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1931 int i;
1932 struct dc_context *dc_ctx = dc->ctx;
1933 struct pipe_ctx *pipe_ctx = NULL;
1934 int pipe_idx = -1;
46570f09 1935 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1936
1dc90497
AG		 1937 /* TODO Check if this is needed */
1938 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1939 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1940 stream->bit_depth_params =
430ef426
DL		 1941 old_context->streams[i]->bit_depth_params;
1942 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1943 continue;
1944 }
4b679bc3 1945 }
1dc90497 1946 */
7e2fe319 1947
08e1c28d
YMM		 1948 calculate_phy_pix_clks(stream);
1949
46570f09
AK		 1950 /* TODO: Check Linux */
1951 if (dc->config.allow_seamless_boot_optimization &&
1952 !dcb->funcs->is_accelerated_mode(dcb)) {
1953 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1954 stream->apply_seamless_boot_optimization = true;
1955 }
1956
d2d7885f
AK		 1957 if (stream->apply_seamless_boot_optimization)
1958 pipe_idx = acquire_resource_from_hw_enabled_state(
1959 &context->res_ctx,
1960 pool,
1961 stream);
1962
1963 if (pipe_idx < 0)
1964 /* acquire new resources */
1965 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1966
dc37a9a0 1967#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1968 if (pipe_idx < 0)
13ab1b44 1969 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1970#endif
13ab1b44 1971
c5b38aec 1972 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1973 return DC_NO_CONTROLLER_RESOURCE;
1974
1975 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1976
1977 pipe_ctx->stream_res.stream_enc =
78cc70b1 1978 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 1979 &context->res_ctx, pool, stream);
1980
1981 if (!pipe_ctx->stream_res.stream_enc)
38684e46 1982 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 1983
1984 update_stream_engine_usage(
1985 &context->res_ctx, pool,
1986 pipe_ctx->stream_res.stream_enc,
1987 true);
1988
1989 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 1990 if (!stream->converter_disable_audio &&
1dc90497
AG		 1991 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1992 stream->audio_info.mode_count) {
1993 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1994 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1995
1996 /*
1997 * Audio assigned in order first come first get.
1998 * There are asics which has number of audio
1999 * resources less then number of pipes
2000 */
2001 if (pipe_ctx->stream_res.audio)
2002 update_audio_usage(&context->res_ctx, pool,
2003 pipe_ctx->stream_res.audio, true);
2004 }
268cadbd 2005
9aef1a31
S		 2006 /* Add ABM to the resource if on EDP */
2007 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2008 pipe_ctx->stream_res.abm = pool->abm;
2009
1dc90497
AG		 2010 for (i = 0; i < context->stream_count; i++)
2011 if (context->streams[i] == stream) {
2012 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 2013 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
5fdb7c4c
NK		 2014 context->stream_status[i].audio_inst =
2015 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2016
1dc90497
AG		 2017 return DC_OK;
2018 }
4562236b 2019
1dc90497
AG		 2020 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2021 return DC_ERROR_UNEXPECTED;
2022}
4562236b 2023
2119aa17
DF		 2024/**
2025 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2026 * Is a shallow copy. Increments refcounts on existing streams and planes.
2027 * @dc: copy out of dc->current_state
2028 * @dst_ctx: copy into this
2029 */
f36cc577 2030void dc_resource_state_copy_construct_current(
1dc90497 2031 const struct dc *dc,
608ac7bb 2032 struct dc_state *dst_ctx)
1dc90497 2033{
f36cc577 2034 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2035}
2036
ab8db3e1
AG		 2037
2038void dc_resource_state_construct(
2039 const struct dc *dc,
2040 struct dc_state *dst_ctx)
2041{
dc88b4a6 2042 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2043}
2044
2119aa17
DF		 2045/**
2046 * dc_validate_global_state() - Determine if HW can support a given state
2047 * Checks HW resource availability and bandwidth requirement.
2048 * @dc: dc struct for this driver
2049 * @new_ctx: state to be validated
afcd526b 2050 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2051 *
2052 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2053 */
e750d56d 2054enum dc_status dc_validate_global_state(
1dc90497 2055 struct dc *dc,
afcd526b
JA		 2056 struct dc_state *new_ctx,
2057 bool fast_validate)
4562236b 2058{
1dc90497 2059 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2060 int i, j;
4562236b 2061
e41ab030
HW		 2062 if (!new_ctx)
2063 return DC_ERROR_UNEXPECTED;
2064
d596e5d0 2065 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2066 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2067 if (result != DC_OK)
2068 return result;
d596e5d0 2069 }
4562236b 2070
e41ab030 2071 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2072 struct dc_stream_state *stream = new_ctx->streams[i];
2073
2074 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2075 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2076
2077 if (pipe_ctx->stream != stream)
2078 continue;
2079
74eac5f3
SSC		 2080 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2081 pipe_ctx->plane_state &&
2082 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2083 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2084 if (result != DC_OK)
2085 return result;
2086 }
2087
1dc90497
AG		 2088 /* Switch to dp clock source only if there is
2089 * no non dp stream that shares the same timing
2090 * with the dp stream.
2091 */
2092 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2093 !find_pll_sharable_stream(stream, new_ctx)) {
2094
9d0dcecd 2095 resource_unreference_clock_source(
1dc90497
AG		 2096 &new_ctx->res_ctx,
2097 dc->res_pool,
9d0dcecd 2098 pipe_ctx->clock_source);
4a629536 2099
1dc90497
AG		 2100 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2101 resource_reference_clock_source(
2102 &new_ctx->res_ctx,
2103 dc->res_pool,
2104 pipe_ctx->clock_source);
2105 }
2106 }
2107 }
2108
1dc90497
AG		 2109 result = resource_build_scaling_params_for_context(dc, new_ctx);
2110
2111 if (result == DC_OK)
afcd526b 2112 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2113 result = DC_FAIL_BANDWIDTH_VALIDATE;
2114
2115 return result;
4562236b
HW		 2116}
2117
6e4d6bee 2118static void patch_gamut_packet_checksum(
e09b6473 2119 struct dc_info_packet *gamut_packet)
4562236b 2120{
4562236b 2121 /* For gamut we recalc checksum */
6e4d6bee 2122 if (gamut_packet->valid) {
4562236b
HW		 2123 uint8_t chk_sum = 0;
2124 uint8_t *ptr;
2125 uint8_t i;
2126
4562236b 2127 /*start of the Gamut data. */
6e4d6bee 2128 ptr = &gamut_packet->sb[3];
4562236b 2129
6e4d6bee 2130 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2131 chk_sum += ptr[i];
2132
6e4d6bee 2133 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2134 }
4562236b
HW		 2135}
2136
2137static void set_avi_info_frame(
e09b6473 2138 struct dc_info_packet *info_packet,
4562236b
HW		 2139 struct pipe_ctx *pipe_ctx)
2140{
0971c40e 2141 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2142 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2143 uint32_t pixel_encoding = 0;
2144 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2145 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2146 bool itc = false;
50e27654 2147 uint8_t itc_value = 0;
4562236b 2148 uint8_t cn0_cn1 = 0;
50e27654 2149 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2150 uint8_t *check_sum = NULL;
2151 uint8_t byte_index = 0;
754e3673 2152 union hdmi_info_packet hdmi_info;
50e27654 2153 union display_content_support support = {0};
4fa086b9 2154 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2155 enum dc_timing_3d_format format;
4562236b 2156
754e3673
AK		 2157 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2158
4fa086b9 2159 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2160 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2161 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2162 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2163
2164 /* Initialize header */
e09b6473 2165 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2166 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2167 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2168 hdmi_info.bits.header.version = 2;
2169 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2170
2171 /*
2172 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2173 * according to HDMI 2.0 spec (Section 10.1)
2174 */
2175
4fa086b9 2176 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2177 case PIXEL_ENCODING_YCBCR422:
2178 pixel_encoding = 1;
2179 break;
2180
2181 case PIXEL_ENCODING_YCBCR444:
2182 pixel_encoding = 2;
2183 break;
2184 case PIXEL_ENCODING_YCBCR420:
2185 pixel_encoding = 3;
2186 break;
2187
2188 case PIXEL_ENCODING_RGB:
2189 default:
2190 pixel_encoding = 0;
2191 }
2192
2193 /* Y0_Y1_Y2 : The pixel encoding */
2194 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2195 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2196
2197 /* A0 = 1 Active Format Information valid */
e09b6473 2198 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2199
2200 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2201 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2202
e09b6473 2203 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2204
2205 /* S0, S1 : Underscan / Overscan */
2206 /* TODO: un-hardcode scan type */
2207 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2208 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2209
2210 /* C0, C1 : Colorimetry */
8fde5884 2211 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2212 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2213 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2214 else if (color_space == COLOR_SPACE_YCBCR601 ||
2215 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2216 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2217 else {
e09b6473 2218 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2219 }
534db198 2220 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2221 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2222 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2223 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2224 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2225 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2226 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2227 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2228 }
2229
4562236b 2230 /* TODO: un-hardcode aspect ratio */
4fa086b9 2231 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2232
2233 switch (aspect) {
2234 case ASPECT_RATIO_4_3:
2235 case ASPECT_RATIO_16_9:
e09b6473 2236 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2237 break;
2238
2239 case ASPECT_RATIO_NO_DATA:
2240 case ASPECT_RATIO_64_27:
2241 case ASPECT_RATIO_256_135:
2242 default:
e09b6473 2243 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2244 }
2245
2246 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2247 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2248
2249 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2250
4562236b 2251 cn0_cn1 = 0;
50e27654
ZF		 2252 cn0_cn1_value = 0;
2253
2254 itc = true;
2255 itc_value = 1;
2256
ceb3dbb4 2257 support = stream->content_support;
4562236b
HW		 2258
2259 if (itc) {
50e27654
ZF		 2260 if (!support.bits.valid_content_type) {
2261 cn0_cn1_value = 0;
2262 } else {
2263 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2264 if (support.bits.graphics_content == 1) {
2265 cn0_cn1_value = 0;
2266 }
2267 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2268 if (support.bits.photo_content == 1) {
2269 cn0_cn1_value = 1;
2270 } else {
2271 cn0_cn1_value = 0;
2272 itc_value = 0;
2273 }
2274 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2275 if (support.bits.cinema_content == 1) {
2276 cn0_cn1_value = 2;
2277 } else {
2278 cn0_cn1_value = 0;
2279 itc_value = 0;
2280 }
2281 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2282 if (support.bits.game_content == 1) {
2283 cn0_cn1_value = 3;
2284 } else {
2285 cn0_cn1_value = 0;
2286 itc_value = 0;
2287 }
2288 }
2289 }
e09b6473
AK		 2290 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2291 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2292 }
2293
2294 /* TODO : We should handle YCC quantization */
2295 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2296 if (stream->qs_bit == 1 &&
2297 stream->qy_bit == 1) {
50e27654
ZF		 2298 if (color_space == COLOR_SPACE_SRGB ||
2299 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2300 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2301 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2302 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2303 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2304 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2305 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2306 } else {
e09b6473
AK		 2307 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2308 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2309 }
4562236b 2310 } else {
e09b6473
AK		 2311 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2312 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2313 }
50e27654 2314
15e17335 2315 ///VIC
4fa086b9 2316 format = stream->timing.timing_3d_format;
15e17335
CL		 2317 /*todo, add 3DStereo support*/
2318 if (format != TIMING_3D_FORMAT_NONE) {
2319 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2320 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2321 case 1:
2322 vic = 95;
2323 break;
2324 case 2:
2325 vic = 94;
2326 break;
2327 case 3:
2328 vic = 93;
2329 break;
2330 case 4:
2331 vic = 98;
2332 break;
2333 default:
2334 break;
2335 }
2336 }
efa02336 2337 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2338 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2339 if (vic >= 128)
2340 hdmi_info.bits.header.version = 3;
2341 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2342 * the Source shall use 20 AVI InfoFrame Version 4
2343 */
2344 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2345 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2346 hdmi_info.bits.header.version = 4;
2347 hdmi_info.bits.header.length = 14;
2348 }
4562236b
HW		 2349
2350 /* pixel repetition
2351 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2352 * repetition start from 1 */
e09b6473 2353 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2354
2355 /* Bar Info
2356 * barTop: Line Number of End of Top Bar.
2357 * barBottom: Line Number of Start of Bottom Bar.
2358 * barLeft: Pixel Number of End of Left Bar.
2359 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2360 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2361 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2362 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2363 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2364 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2365 - stream->timing.h_border_right + 1);
4562236b 2366
2f482c4f
CP		 2367 /* Additional Colorimetry Extension
2368 * Used in conduction with C0-C1 and EC0-EC2
2369 * 0 = DCI-P3 RGB (D65)
2370 * 1 = DCI-P3 RGB (theater)
2371 */
2372 hdmi_info.bits.ACE0_ACE3 = 0;
2373
4562236b 2374 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2375 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2376
efa02336 2377 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2378
efa02336 2379 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2380 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2381
2382 /* one byte complement */
2383 *check_sum = (uint8_t) (0x100 - *check_sum);
2384
2385 /* Store in hw_path_mode */
e09b6473
AK		 2386 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2387 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2388 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2389
e09b6473
AK		 2390 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2391 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2392
2393 info_packet->valid = true;
2394}
2395
6e4d6bee 2396static void set_vendor_info_packet(
e09b6473 2397 struct dc_info_packet *info_packet,
0971c40e 2398 struct dc_stream_state *stream)
4562236b 2399{
ecd0136b 2400 /* SPD info packet for FreeSync */
4562236b 2401
ecd0136b
HT		 2402 /* Check if Freesync is supported. Return if false. If true,
2403 * set the corresponding bit in the info packet
2404 */
2405 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2406 return;
2407
ecd0136b 2408 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2409}
2410
6e4d6bee 2411static void set_spd_info_packet(
e09b6473 2412 struct dc_info_packet *info_packet,
0971c40e 2413 struct dc_stream_state *stream)
4562236b
HW		 2414{
2415 /* SPD info packet for FreeSync */
2416
4562236b
HW		 2417 /* Check if Freesync is supported. Return if false. If true,
2418 * set the corresponding bit in the info packet
2419 */
98e6436d 2420 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2421 return;
2422
98e6436d 2423 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2424}
2425
1646a6fe 2426static void set_hdr_static_info_packet(
e09b6473 2427 struct dc_info_packet *info_packet,
0971c40e 2428 struct dc_stream_state *stream)
1646a6fe 2429{
0eeef690 2430 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2431
a10dc97a
KK		 2432 if (!stream->hdr_static_metadata.valid ||
2433 stream->use_dynamic_meta)
10bff005
YS		 2434 return;
2435
0eeef690 2436 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2437}
2438
6e4d6bee 2439static void set_vsc_info_packet(
e09b6473 2440 struct dc_info_packet *info_packet,
0971c40e 2441 struct dc_stream_state *stream)
4562236b 2442{
1336926f 2443 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2444 return;
2445
1336926f 2446 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2447}
2448
f36cc577 2449void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2450{
2451 int i, j;
2452
ab2541b6 2453 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2454 for (j = 0; j < context->stream_status[i].plane_count; j++)
2455 dc_plane_state_release(
2456 context->stream_status[i].plane_states[j]);
4562236b 2457
3be5262e 2458 context->stream_status[i].plane_count = 0;
4fa086b9 2459 dc_stream_release(context->streams[i]);
ab2541b6 2460 context->streams[i] = NULL;
4562236b
HW		 2461 }
2462}
2463
f36cc577 2464void dc_resource_state_copy_construct(
608ac7bb
JZ		 2465 const struct dc_state *src_ctx,
2466 struct dc_state *dst_ctx)
4562236b
HW		 2467{
2468 int i, j;
8ee5702a 2469 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2470
2471 *dst_ctx = *src_ctx;
2472
a2b8659d 2473 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2474 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2475
2476 if (cur_pipe->top_pipe)
2477 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2478
2479 if (cur_pipe->bottom_pipe)
2480 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
4562236b
HW		 2481 }
2482
ab2541b6 2483 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2484 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2485 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2486 dc_plane_state_retain(
2487 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2488 }
9a3afbb3
AG		 2489
2490 /* context refcount should not be overridden */
8ee5702a 2491 dst_ctx->refcount = refcount;
9a3afbb3 2492
4562236b
HW		 2493}
2494
2495struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2496 struct resource_context *res_ctx,
2497 const struct resource_pool *pool)
4562236b
HW		 2498{
2499 int i;
2500
a2b8659d 2501 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2502 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2503 return pool->clock_sources[i];
4562236b
HW		 2504 }
2505
2506 return NULL;
2507}
2508
2509void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2510{
2511 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2512 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2513
2514 /* default all packets to invalid */
6e4d6bee
TC		 2515 info->avi.valid = false;
2516 info->gamut.valid = false;
2517 info->vendor.valid = false;
630e3573 2518 info->spd.valid = false;
6e4d6bee
TC		 2519 info->hdrsmd.valid = false;
2520 info->vsc.valid = false;
4562236b
HW		 2521
2522 signal = pipe_ctx->stream->signal;
2523
2524 /* HDMi and DP have different info packets*/
2525 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2526 set_avi_info_frame(&info->avi, pipe_ctx);
2527
2528 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2529
2530 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2531
56ef6ed9 2532 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2533
a33fa99d 2534 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2535 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2536
2537 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2538
56ef6ed9 2539 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2540 }
4562236b 2541
6e4d6bee 2542 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2543}
2544
2545enum dc_status resource_map_clock_resources(
fb3466a4 2546 const struct dc *dc,
608ac7bb 2547 struct dc_state *context,
1dc90497 2548 struct dc_stream_state *stream)
4562236b 2549{
4562236b 2550 /* acquire new resources */
1dc90497
AG		 2551 const struct resource_pool *pool = dc->res_pool;
2552 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2553 &context->res_ctx, stream);
ab2541b6 2554
1dc90497
AG		 2555 if (!pipe_ctx)
2556 return DC_ERROR_UNEXPECTED;
4562236b 2557
1dc90497
AG		 2558 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2559 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2560 pipe_ctx->clock_source = pool->dp_clock_source;
2561 else {
2562 pipe_ctx->clock_source = NULL;
4562236b 2563
1dc90497 2564 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2565 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2566 &context->res_ctx,
2567 pipe_ctx);
4562236b 2568
1dc90497
AG		 2569 if (pipe_ctx->clock_source == NULL)
2570 pipe_ctx->clock_source =
2571 dc_resource_find_first_free_pll(
2572 &context->res_ctx,
2573 pool);
2574 }
4562236b 2575
1dc90497
AG		 2576 if (pipe_ctx->clock_source == NULL)
2577 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2578
1dc90497
AG		 2579 resource_reference_clock_source(
2580 &context->res_ctx, pool,
2581 pipe_ctx->clock_source);
4562236b
HW		 2582
2583 return DC_OK;
2584}
2585
2586/*
2587 * Note: We need to disable output if clock sources change,
2588 * since bios does optimization and doesn't apply if changing
2589 * PHY when not already disabled.
2590 */
2591bool pipe_need_reprogram(
2592 struct pipe_ctx *pipe_ctx_old,
2593 struct pipe_ctx *pipe_ctx)
2594{
cfe4645e
DL		 2595 if (!pipe_ctx_old->stream)
2596 return false;
2597
4562236b
HW		 2598 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2599 return true;
2600
2601 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2602 return true;
2603
afaacef4 2604 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2605 return true;
2606
2607 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2608 && pipe_ctx_old->stream != pipe_ctx->stream)
2609 return true;
2610
8e9c4c8c 2611 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2612 return true;
2613
2614 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2615 return true;
2616
6b622181
JP		 2617 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2618 return true;
4562236b 2619
1e7e86c4
ST		 2620 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2621 return true;
2622
1336926f
A		 2623 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2624 return true;
2625
eed928dc
CL		 2626 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2627 false == pipe_ctx_old->stream->dpms_off)
2628 return true;
2629
4562236b
HW		 2630 return false;
2631}
529cad0f 2632
0971c40e 2633void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2634 struct bit_depth_reduction_params *fmt_bit_depth)
2635{
4fa086b9 2636 enum dc_dither_option option = stream->dither_option;
529cad0f 2637 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2638 stream->timing.pixel_encoding;
529cad0f
DW		 2639
2640 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2641
603767f9
TC		 2642 if (option == DITHER_OPTION_DEFAULT) {
2643 switch (stream->timing.display_color_depth) {
2644 case COLOR_DEPTH_666:
2645 option = DITHER_OPTION_SPATIAL6;
2646 break;
2647 case COLOR_DEPTH_888:
2648 option = DITHER_OPTION_SPATIAL8;
2649 break;
2650 case COLOR_DEPTH_101010:
2651 option = DITHER_OPTION_SPATIAL10;
2652 break;
2653 default:
2654 option = DITHER_OPTION_DISABLE;
2655 }
2656 }
2657
529cad0f
DW		 2658 if (option == DITHER_OPTION_DISABLE)
2659 return;
2660
2661 if (option == DITHER_OPTION_TRUN6) {
2662 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2663 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2664 } else if (option == DITHER_OPTION_TRUN8 ||
2665 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2666 option == DITHER_OPTION_TRUN8_FM6) {
2667 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2668 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2669 } else if (option == DITHER_OPTION_TRUN10 ||
2670 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2671 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2672 option == DITHER_OPTION_TRUN10_FM8 ||
2673 option == DITHER_OPTION_TRUN10_FM6 ||
2674 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2675 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2676 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2677 }
2678
2679 /* special case - Formatter can only reduce by 4 bits at most.
2680 * When reducing from 12 to 6 bits,
2681 * HW recommends we use trunc with round mode
2682 * (if we did nothing, trunc to 10 bits would be used)
2683 * note that any 12->10 bit reduction is ignored prior to DCE8,
2684 * as the input was 10 bits.
2685 */
2686 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2687 option == DITHER_OPTION_SPATIAL6 ||
2688 option == DITHER_OPTION_FM6) {
2689 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2690 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2691 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2692 }
2693
2694 /* spatial dither
2695 * note that spatial modes 1-3 are never used
2696 */
2697 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2698 option == DITHER_OPTION_SPATIAL6 ||
2699 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2700 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2701 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2702 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2703 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2704 fmt_bit_depth->flags.RGB_RANDOM =
2705 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2706 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2707 option == DITHER_OPTION_SPATIAL8 ||
2708 option == DITHER_OPTION_SPATIAL8_FM6 ||
2709 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2710 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2711 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2712 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2713 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2714 fmt_bit_depth->flags.RGB_RANDOM =
2715 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2716 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2717 option == DITHER_OPTION_SPATIAL10 ||
2718 option == DITHER_OPTION_SPATIAL10_FM8 ||
2719 option == DITHER_OPTION_SPATIAL10_FM6) {
2720 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2721 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2722 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2723 fmt_bit_depth->flags.RGB_RANDOM =
2724 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2725 }
2726
2727 if (option == DITHER_OPTION_SPATIAL6 ||
2728 option == DITHER_OPTION_SPATIAL8 ||
2729 option == DITHER_OPTION_SPATIAL10) {
2730 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2731 } else {
2732 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2733 }
2734
2735 //////////////////////
2736 //// temporal dither
2737 //////////////////////
2738 if (option == DITHER_OPTION_FM6 ||
2739 option == DITHER_OPTION_SPATIAL8_FM6 ||
2740 option == DITHER_OPTION_SPATIAL10_FM6 ||
2741 option == DITHER_OPTION_TRUN10_FM6 ||
2742 option == DITHER_OPTION_TRUN8_FM6 ||
2743 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2744 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2745 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2746 } else if (option == DITHER_OPTION_FM8 ||
2747 option == DITHER_OPTION_SPATIAL10_FM8 ||
2748 option == DITHER_OPTION_TRUN10_FM8) {
2749 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2750 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2751 } else if (option == DITHER_OPTION_FM10) {
2752 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2753 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2754 }
2755
2756 fmt_bit_depth->pixel_encoding = pixel_encoding;
2757}
9345d987 2758
62c933f9 2759enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2760{
fb3466a4 2761 struct dc *core_dc = dc;
ceb3dbb4 2762 struct dc_link *link = stream->link;
9345d987
AG		 2763 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2764 enum dc_status res = DC_OK;
2765
4fa086b9 2766 calculate_phy_pix_clks(stream);
9345d987 2767
4fa086b9 2768 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2769 res = DC_FAIL_CONTROLLER_VALIDATE;
2770
248cbed6 2771 if (res == DC_OK) {
9345d987 2772 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2773 link->link_enc, stream))
9345d987 2774 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2775 }
9345d987
AG		 2776
2777 /* TODO: validate audio ASIC caps, encoder */
2778
2779 if (res == DC_OK)
4fa086b9 2780 res = dc_link_validate_mode_timing(stream,
9345d987 2781 link,
4fa086b9 2782 &stream->timing);
9345d987 2783
62c933f9 2784 return res;
9345d987 2785}
792671d7 2786
62c933f9 2787enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2788{
62c933f9
YS		 2789 enum dc_status res = DC_OK;
2790
792671d7 2791 /* TODO For now validates pixel format only */
8e7095b9 2792 if (dc->res_pool->funcs->validate_plane)
62c933f9 2793 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2794
62c933f9 2795 return res;
792671d7 2796}
74eac5f3
SSC		 2797
2798unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2799{
2800 switch (format) {
2801 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2802 return 8;
2803 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2804 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2805 return 12;
2806 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2807 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2808 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2809 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2810 return 16;
2811 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2812 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2813 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2814 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2815 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2816 return 32;
2817 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2818 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2819 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2820 return 64;
2821 default:
2822 ASSERT_CRITICAL(false);
2823 return -1;
2824 }
2825}
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