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4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b 37#include "virtual/virtual_stream_encoder.h"
3b94a400 38#include "dpcd_defs.h"
4562236b
HW
39
40#include "dce80/dce80_resource.h"
41#include "dce100/dce100_resource.h"
42#include "dce110/dce110_resource.h"
43#include "dce112/dce112_resource.h"
48412031 44#ifdef CONFIG_X86
ff5ef992
AD
45#include "dcn10/dcn10_resource.h"
46#endif
2c8ad2d5 47#include "dce120/dce120_resource.h"
5d4b05dd
BL
48
49#define DC_LOGGER_INIT(logger)
50
4562236b
HW
51enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
52{
53 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
54 switch (asic_id.chip_family) {
55
56 case FAMILY_CI:
4562236b
HW
57 dc_version = DCE_VERSION_8_0;
58 break;
ebfdf0d0
AD
59 case FAMILY_KV:
60 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
61 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
63 dc_version = DCE_VERSION_8_3;
64 else
65 dc_version = DCE_VERSION_8_1;
66 break;
4562236b
HW
67 case FAMILY_CZ:
68 dc_version = DCE_VERSION_11_0;
69 break;
70
71 case FAMILY_VI:
72 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
74 dc_version = DCE_VERSION_10_0;
75 break;
76 }
77 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL
78 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
79 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW
80 dc_version = DCE_VERSION_11_2;
81 }
0c75d5ac
JFZ
82 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
83 dc_version = DCE_VERSION_11_22;
4562236b 84 break;
2c8ad2d5
AD
85 case FAMILY_AI:
86 dc_version = DCE_VERSION_12_0;
87 break;
48412031 88#ifdef CONFIG_X86
ff5ef992
AD
89 case FAMILY_RV:
90 dc_version = DCN_VERSION_1_0;
91 break;
92#endif
4562236b
HW
93 default:
94 dc_version = DCE_VERSION_UNKNOWN;
95 break;
96 }
97 return dc_version;
98}
99
100struct resource_pool *dc_create_resource_pool(
fb3466a4 101 struct dc *dc,
4562236b
HW
102 int num_virtual_links,
103 enum dce_version dc_version,
104 struct hw_asic_id asic_id)
105{
5ac3d3c9 106 struct resource_pool *res_pool = NULL;
4562236b
HW
107
108 switch (dc_version) {
109 case DCE_VERSION_8_0:
7992a629
AD
110 res_pool = dce80_create_resource_pool(
111 num_virtual_links, dc);
112 break;
ebfdf0d0 113 case DCE_VERSION_8_1:
7992a629
AD
114 res_pool = dce81_create_resource_pool(
115 num_virtual_links, dc);
116 break;
ebfdf0d0 117 case DCE_VERSION_8_3:
7992a629 118 res_pool = dce83_create_resource_pool(
4562236b 119 num_virtual_links, dc);
5ac3d3c9 120 break;
4562236b 121 case DCE_VERSION_10_0:
5ac3d3c9 122 res_pool = dce100_create_resource_pool(
4562236b 123 num_virtual_links, dc);
5ac3d3c9 124 break;
4562236b 125 case DCE_VERSION_11_0:
5ac3d3c9 126 res_pool = dce110_create_resource_pool(
4562236b 127 num_virtual_links, dc, asic_id);
5ac3d3c9 128 break;
4562236b 129 case DCE_VERSION_11_2:
0c75d5ac 130 case DCE_VERSION_11_22:
5ac3d3c9 131 res_pool = dce112_create_resource_pool(
4562236b 132 num_virtual_links, dc);
5ac3d3c9 133 break;
2c8ad2d5
AD
134 case DCE_VERSION_12_0:
135 res_pool = dce120_create_resource_pool(
136 num_virtual_links, dc);
137 break;
ff5ef992 138
48412031 139#ifdef CONFIG_X86
ff5ef992
AD
140 case DCN_VERSION_1_0:
141 res_pool = dcn10_create_resource_pool(
503a7c6f 142 num_virtual_links, dc);
ff5ef992
AD
143 break;
144#endif
3639fa68
ZF
145
146
4562236b
HW
147 default:
148 break;
149 }
5ac3d3c9 150 if (res_pool != NULL) {
1515a47b 151 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL
152
153 if (dc->ctx->dc_bios->funcs->get_firmware_info(
154 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
155 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
156 } else
157 ASSERT_CRITICAL(false);
158 }
4562236b 159
5ac3d3c9 160 return res_pool;
4562236b
HW
161}
162
fb3466a4 163void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW
164{
165 if (dc) {
166 if (dc->res_pool)
167 dc->res_pool->funcs->destroy(&dc->res_pool);
168
d029810c 169 kfree(dc->hwseq);
4562236b
HW
170 }
171}
172
173static void update_num_audio(
174 const struct resource_straps *straps,
175 unsigned int *num_audio,
176 struct audio_support *aud_support)
177{
b8e9eb72
CL
178 aud_support->dp_audio = true;
179 aud_support->hdmi_audio_native = false;
180 aud_support->hdmi_audio_on_dongle = false;
181
4562236b 182 if (straps->hdmi_disable == 0) {
4562236b
HW
183 if (straps->dc_pinstraps_audio & 0x2) {
184 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 185 aud_support->hdmi_audio_native = true;
4562236b
HW
186 }
187 }
188
189 switch (straps->audio_stream_number) {
190 case 0: /* multi streams supported */
191 break;
192 case 1: /* multi streams not supported */
193 *num_audio = 1;
194 break;
195 default:
196 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 197 }
4562236b
HW
198}
199
200bool resource_construct(
201 unsigned int num_virtual_links,
fb3466a4 202 struct dc *dc,
4562236b
HW
203 struct resource_pool *pool,
204 const struct resource_create_funcs *create_funcs)
205{
206 struct dc_context *ctx = dc->ctx;
207 const struct resource_caps *caps = pool->res_cap;
208 int i;
209 unsigned int num_audio = caps->num_audio;
210 struct resource_straps straps = {0};
211
212 if (create_funcs->read_dce_straps)
213 create_funcs->read_dce_straps(dc->ctx, &straps);
214
215 pool->audio_count = 0;
216 if (create_funcs->create_audio) {
217 /* find the total number of streams available via the
218 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
219 * registers (one for each pin) starting from pin 1
220 * up to the max number of audio pins.
221 * We stop on the first pin where
222 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
223 */
224 update_num_audio(&straps, &num_audio, &pool->audio_support);
225 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
226 struct audio *aud = create_funcs->create_audio(ctx, i);
227
228 if (aud == NULL) {
229 DC_ERR("DC: failed to create audio!\n");
230 return false;
231 }
232
233 if (!aud->funcs->endpoint_valid(aud)) {
234 aud->funcs->destroy(&aud);
235 break;
236 }
237
238 pool->audios[i] = aud;
239 pool->audio_count++;
240 }
241 }
242
243 pool->stream_enc_count = 0;
244 if (create_funcs->create_stream_encoder) {
245 for (i = 0; i < caps->num_stream_encoder; i++) {
246 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
247 if (pool->stream_enc[i] == NULL)
248 DC_ERR("DC: failed to create stream_encoder!\n");
249 pool->stream_enc_count++;
250 }
251 }
4176664b
CL
252 dc->caps.dynamic_audio = false;
253 if (pool->audio_count < pool->stream_enc_count) {
254 dc->caps.dynamic_audio = true;
255 }
4562236b
HW
256 for (i = 0; i < num_virtual_links; i++) {
257 pool->stream_enc[pool->stream_enc_count] =
258 virtual_stream_encoder_create(
259 ctx, ctx->dc_bios);
260 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
261 DC_ERR("DC: failed to create stream_encoder!\n");
262 return false;
263 }
264 pool->stream_enc_count++;
265 }
266
267 dc->hwseq = create_funcs->create_hwseq(ctx);
268
269 return true;
270}
271
272
21e67d4d 273void resource_unreference_clock_source(
4562236b 274 struct resource_context *res_ctx,
a2b8659d 275 const struct resource_pool *pool,
4a629536 276 struct clock_source *clock_source)
4562236b
HW
277{
278 int i;
4a629536 279
a2b8659d 280 for (i = 0; i < pool->clk_src_count; i++) {
4a629536 281 if (pool->clock_sources[i] != clock_source)
4562236b
HW
282 continue;
283
284 res_ctx->clock_source_ref_count[i]--;
285
4562236b
HW
286 break;
287 }
288
21e67d4d 289 if (pool->dp_clock_source == clock_source)
4562236b 290 res_ctx->dp_clock_source_ref_count--;
4562236b
HW
291}
292
293void resource_reference_clock_source(
294 struct resource_context *res_ctx,
a2b8659d 295 const struct resource_pool *pool,
4562236b
HW
296 struct clock_source *clock_source)
297{
298 int i;
a2b8659d
TC
299 for (i = 0; i < pool->clk_src_count; i++) {
300 if (pool->clock_sources[i] != clock_source)
4562236b
HW
301 continue;
302
303 res_ctx->clock_source_ref_count[i]++;
304 break;
305 }
306
a2b8659d 307 if (pool->dp_clock_source == clock_source)
4562236b
HW
308 res_ctx->dp_clock_source_ref_count++;
309}
310
311bool resource_are_streams_timing_synchronizable(
0971c40e
HW
312 struct dc_stream_state *stream1,
313 struct dc_stream_state *stream2)
4562236b 314{
4fa086b9 315 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW
316 return false;
317
4fa086b9 318 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW
319 return false;
320
4fa086b9
LSL
321 if (stream1->timing.h_addressable
322 != stream2->timing.h_addressable)
4562236b
HW
323 return false;
324
4fa086b9
LSL
325 if (stream1->timing.v_addressable
326 != stream2->timing.v_addressable)
4562236b
HW
327 return false;
328
4fa086b9
LSL
329 if (stream1->timing.pix_clk_khz
330 != stream2->timing.pix_clk_khz)
4562236b
HW
331 return false;
332
333 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL
334 && (!dc_is_dp_signal(stream1->signal)
335 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW
336 return false;
337
338 return true;
339}
340
341static bool is_sharable_clk_src(
342 const struct pipe_ctx *pipe_with_clk_src,
343 const struct pipe_ctx *pipe)
344{
345 if (pipe_with_clk_src->clock_source == NULL)
346 return false;
347
348 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
349 return false;
350
351 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
352 return false;
353
354 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
355 && dc_is_dvi_signal(pipe->stream->signal))
356 return false;
357
358 if (dc_is_hdmi_signal(pipe->stream->signal)
359 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
360 return false;
361
362 if (!resource_are_streams_timing_synchronizable(
363 pipe_with_clk_src->stream, pipe->stream))
364 return false;
365
366 return true;
367}
368
369struct clock_source *resource_find_used_clk_src_for_sharing(
370 struct resource_context *res_ctx,
371 struct pipe_ctx *pipe_ctx)
372{
373 int i;
374
375 for (i = 0; i < MAX_PIPES; i++) {
376 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
377 return res_ctx->pipe_ctx[i].clock_source;
378 }
379
380 return NULL;
381}
382
383static enum pixel_format convert_pixel_format_to_dalsurface(
384 enum surface_pixel_format surface_pixel_format)
385{
386 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
387
388 switch (surface_pixel_format) {
389 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
390 dal_pixel_format = PIXEL_FORMAT_INDEX8;
391 break;
392 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
393 dal_pixel_format = PIXEL_FORMAT_RGB565;
394 break;
395 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
396 dal_pixel_format = PIXEL_FORMAT_RGB565;
397 break;
398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
399 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
400 break;
8693049a 401 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW
402 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
403 break;
404 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
406 break;
407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
408 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
409 break;
410 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
411 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
412 break;
413 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
414 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
415 dal_pixel_format = PIXEL_FORMAT_FP16;
416 break;
417 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 418 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 419 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 420 break;
ffbcd19a
VP
421 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
422 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 423 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 424 break;
4562236b
HW
425 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
426 default:
427 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
428 break;
429 }
430 return dal_pixel_format;
431}
432
433static void rect_swap_helper(struct rect *rect)
434{
99676f20
GS
435 swap(rect->height, rect->width);
436 swap(rect->x, rect->y);
4562236b
HW
437}
438
b2d0a103 439static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 440{
3be5262e 441 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 442 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 443 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 444 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 445 struct rect clip = { 0 };
87449a90
AK
446 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
447 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 448 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 449 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 450 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 451 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 452
7f5c22d1
VP
453 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
454 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP
455 pri_split = false;
456 sec_split = false;
457 }
86006a7f 458
3be5262e
HW
459 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
460 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL
461 rect_swap_helper(&surf_src);
462
4562236b
HW
463 /* The actual clip is an intersection between stream
464 * source and surface clip
465 */
3be5262e
HW
466 clip.x = stream->src.x > plane_state->clip_rect.x ?
467 stream->src.x : plane_state->clip_rect.x;
4562236b 468
1fbd2cfc 469 clip.width = stream->src.x + stream->src.width <
3be5262e 470 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 471 stream->src.x + stream->src.width - clip.x :
3be5262e 472 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 473
3be5262e
HW
474 clip.y = stream->src.y > plane_state->clip_rect.y ?
475 stream->src.y : plane_state->clip_rect.y;
4562236b 476
1fbd2cfc 477 clip.height = stream->src.y + stream->src.height <
3be5262e 478 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 479 stream->src.y + stream->src.height - clip.y :
3be5262e 480 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 481
86006a7f 482 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW
483 * num_pixels = clip.num_pix * scl_ratio
484 */
3be5262e
HW
485 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
486 surf_src.width / plane_state->dst_rect.width;
b2d0a103 487 data->viewport.width = clip.width *
3be5262e 488 surf_src.width / plane_state->dst_rect.width;
4562236b 489
3be5262e
HW
490 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
491 surf_src.height / plane_state->dst_rect.height;
b2d0a103 492 data->viewport.height = clip.height *
3be5262e 493 surf_src.height / plane_state->dst_rect.height;
4562236b 494
b2d0a103
DL
495 /* Round down, compensate in init */
496 data->viewport_c.x = data->viewport.x / vpc_div;
497 data->viewport_c.y = data->viewport.y / vpc_div;
498 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
eb0e5154 499 dc_fixpt_half : dc_fixpt_zero;
b2d0a103 500 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
eb0e5154 501 dc_fixpt_half : dc_fixpt_zero;
b2d0a103
DL
502 /* Round up, assume original video size always even dimensions */
503 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
504 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
505
506 /* Handle hsplit */
0c31a821
YS
507 if (sec_split) {
508 data->viewport.x += data->viewport.width / 2;
509 data->viewport_c.x += data->viewport_c.width / 2;
510 /* Ceil offset pipe */
511 data->viewport.width = (data->viewport.width + 1) / 2;
512 data->viewport_c.width = (data->viewport_c.width + 1) / 2;
513 } else if (pri_split) {
514 data->viewport.width /= 2;
515 data->viewport_c.width /= 2;
b2d0a103 516 }
1fbd2cfc 517
3be5262e
HW
518 if (plane_state->rotation == ROTATION_ANGLE_90 ||
519 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL
520 rect_swap_helper(&data->viewport_c);
521 rect_swap_helper(&data->viewport);
522 }
4562236b
HW
523}
524
9a08f51f 525static void calculate_recout(struct pipe_ctx *pipe_ctx, struct rect *recout_full)
4562236b 526{
3be5262e 527 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 528 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW
529 struct rect surf_src = plane_state->src_rect;
530 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS
531 bool pri_split = pipe_ctx->bottom_pipe &&
532 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
533 bool sec_split = pipe_ctx->top_pipe &&
534 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 535 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 536
3be5262e
HW
537 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
538 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL
539 rect_swap_helper(&surf_src);
540
6702a9ac 541 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 542 if (stream->src.x < surf_clip.x)
6702a9ac 543 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL
544 - stream->src.x) * stream->dst.width
545 / stream->src.width;
4562236b 546
6702a9ac 547 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 548 stream->dst.width / stream->src.width;
6702a9ac 549 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 550 stream->dst.x + stream->dst.width)
6702a9ac 551 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 552 stream->dst.x + stream->dst.width
6702a9ac 553 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 554
6702a9ac 555 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 556 if (stream->src.y < surf_clip.y)
6702a9ac 557 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL
558 - stream->src.y) * stream->dst.height
559 / stream->src.height;
4562236b 560
6702a9ac 561 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 562 stream->dst.height / stream->src.height;
6702a9ac 563 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 564 stream->dst.y + stream->dst.height)
6702a9ac 565 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 566 stream->dst.y + stream->dst.height
6702a9ac 567 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 568
7b779c99 569 /* Handle h & vsplit */
b0131391
DL
570 if (sec_split && top_bottom_split) {
571 pipe_ctx->plane_res.scl_data.recout.y +=
572 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 573 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL
574 pipe_ctx->plane_res.scl_data.recout.height =
575 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
576 } else if (pri_split && top_bottom_split)
0c31a821 577 pipe_ctx->plane_res.scl_data.recout.height /= 2;
b0131391 578 else if (pri_split || sec_split) {
0c31a821
YS
579 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
580 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
581 (plane_state->rotation == ROTATION_ANGLE_180);
582
583 if (plane_state->rotation == ROTATION_ANGLE_90
584 || plane_state->rotation == ROTATION_ANGLE_270)
585 /* Secondary_pipe XOR Rotation_270 */
586 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
587
588 if (right_view) {
589 pipe_ctx->plane_res.scl_data.recout.x +=
590 pipe_ctx->plane_res.scl_data.recout.width / 2;
591 /* Ceil offset pipe */
592 pipe_ctx->plane_res.scl_data.recout.width =
593 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
594 } else {
6702a9ac 595 pipe_ctx->plane_res.scl_data.recout.width /= 2;
0c31a821 596 }
b2d0a103 597 }
86006a7f 598 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
9a08f51f
DL
599 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
600 * ratio)
c802570e 601 */
9a08f51f 602 recout_full->x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 603 * stream->dst.width / stream->src.width -
3be5262e 604 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 605 * stream->dst.width / stream->src.width;
9a08f51f 606 recout_full->y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 607 * stream->dst.height / stream->src.height -
3be5262e 608 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 609 * stream->dst.height / stream->src.height;
c802570e 610
9a08f51f
DL
611 recout_full->width = plane_state->dst_rect.width
612 * stream->dst.width / stream->src.width;
613 recout_full->height = plane_state->dst_rect.height
614 * stream->dst.height / stream->src.height;
4562236b
HW
615}
616
b2d0a103 617static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 618{
3be5262e 619 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 620 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 621 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL
622 const int in_w = stream->src.width;
623 const int in_h = stream->src.height;
624 const int out_w = stream->dst.width;
625 const int out_h = stream->dst.height;
4562236b 626
3be5262e
HW
627 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
628 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL
629 rect_swap_helper(&surf_src);
630
eb0e5154 631 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 632 surf_src.width,
3be5262e 633 plane_state->dst_rect.width);
eb0e5154 634 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 635 surf_src.height,
3be5262e 636 plane_state->dst_rect.height);
4562236b 637
4fa086b9 638 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 639 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 640 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 641 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 642
6702a9ac
HW
643 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
644 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
645 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
646 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 647
6702a9ac
HW
648 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
649 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 650
6702a9ac
HW
651 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
652 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
653 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
654 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 655 }
0002d3ac
DL
656 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
657 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
658 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
659 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
660 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
661 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
662 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
663 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW
664}
665
9a08f51f 666static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct rect *recout_full)
b2d0a103 667{
6702a9ac 668 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 669 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK
670 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
671 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b0131391 672 bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
b2d0a103 673
b0131391
DL
674 /*
675 * Need to calculate the scan direction for viewport to make adjustments
676 */
677 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
678 flip_vert_scan_dir = true;
679 flip_horz_scan_dir = true;
680 } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
681 flip_vert_scan_dir = true;
682 else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
683 flip_horz_scan_dir = true;
b0131391 684
3be5262e
HW
685 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
686 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 687 rect_swap_helper(&src);
1fbd2cfc
DL
688 rect_swap_helper(&data->viewport_c);
689 rect_swap_helper(&data->viewport);
9a08f51f
DL
690 } else if (pipe_ctx->plane_state->horizontal_mirror)
691 flip_horz_scan_dir = !flip_horz_scan_dir;
1fbd2cfc 692
b2d0a103
DL
693 /*
694 * Init calculated according to formula:
695 * init = (scaling_ratio + number_of_taps + 1) / 2
696 * init_bot = init + scaling_ratio
697 * init_c = init + truncated_vp_c_offset(from calculate viewport)
698 */
0002d3ac
DL
699 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
700 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 701
0002d3ac
DL
702 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
703 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
b2d0a103 704
0002d3ac
DL
705 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
706 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
707
708 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
709 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
b2d0a103 710
9a08f51f
DL
711 if (!flip_horz_scan_dir) {
712 /* Adjust for viewport end clip-off */
713 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
714 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
715 int int_part = dc_fixpt_floor(
716 dc_fixpt_sub(data->inits.h, data->ratios.horz));
b2d0a103 717
9a08f51f
DL
718 int_part = int_part > 0 ? int_part : 0;
719 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
720 }
721 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
722 int vp_clip = (src.x + src.width) / vpc_div -
723 data->viewport_c.width - data->viewport_c.x;
724 int int_part = dc_fixpt_floor(
725 dc_fixpt_sub(data->inits.h_c, data->ratios.horz_c));
726
727 int_part = int_part > 0 ? int_part : 0;
728 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
729 }
b2d0a103 730
9a08f51f
DL
731 /* Adjust for non-0 viewport offset */
732 if (data->viewport.x) {
733 int int_part;
734
735 data->inits.h = dc_fixpt_add(data->inits.h, dc_fixpt_mul_int(
736 data->ratios.horz, data->recout.x - recout_full->x));
737 int_part = dc_fixpt_floor(data->inits.h) - data->viewport.x;
738 if (int_part < data->taps.h_taps) {
739 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
740 (data->taps.h_taps - int_part) : data->viewport.x;
741 data->viewport.x -= int_adj;
742 data->viewport.width += int_adj;
743 int_part += int_adj;
744 } else if (int_part > data->taps.h_taps) {
745 data->viewport.x += int_part - data->taps.h_taps;
746 data->viewport.width -= int_part - data->taps.h_taps;
747 int_part = data->taps.h_taps;
748 }
749 data->inits.h.value &= 0xffffffff;
750 data->inits.h = dc_fixpt_add_int(data->inits.h, int_part);
751 }
b2d0a103 752
9a08f51f
DL
753 if (data->viewport_c.x) {
754 int int_part;
755
756 data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_mul_int(
757 data->ratios.horz_c, data->recout.x - recout_full->x));
758 int_part = dc_fixpt_floor(data->inits.h_c) - data->viewport_c.x;
759 if (int_part < data->taps.h_taps_c) {
760 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
761 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
762 data->viewport_c.x -= int_adj;
763 data->viewport_c.width += int_adj;
764 int_part += int_adj;
765 } else if (int_part > data->taps.h_taps_c) {
766 data->viewport_c.x += int_part - data->taps.h_taps_c;
767 data->viewport_c.width -= int_part - data->taps.h_taps_c;
768 int_part = data->taps.h_taps_c;
769 }
770 data->inits.h_c.value &= 0xffffffff;
771 data->inits.h_c = dc_fixpt_add_int(data->inits.h_c, int_part);
772 }
773 } else {
774 /* Adjust for non-0 viewport offset */
775 if (data->viewport.x) {
776 int int_part = dc_fixpt_floor(
777 dc_fixpt_sub(data->inits.h, data->ratios.horz));
778
779 int_part = int_part > 0 ? int_part : 0;
780 data->viewport.width += int_part < data->viewport.x ? int_part : data->viewport.x;
781 data->viewport.x -= int_part < data->viewport.x ? int_part : data->viewport.x;
782 }
783 if (data->viewport_c.x) {
784 int int_part = dc_fixpt_floor(
785 dc_fixpt_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 786
9a08f51f
DL
787 int_part = int_part > 0 ? int_part : 0;
788 data->viewport_c.width += int_part < data->viewport_c.x ? int_part : data->viewport_c.x;
789 data->viewport_c.x -= int_part < data->viewport_c.x ? int_part : data->viewport_c.x;
790 }
b2d0a103 791
9a08f51f
DL
792 /* Adjust for viewport end clip-off */
793 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
794 int int_part;
795 int end_offset = src.x + src.width
796 - data->viewport.x - data->viewport.width;
797
798 /*
799 * this is init if vp had no offset, keep in mind this is from the
800 * right side of vp due to scan direction
801 */
802 data->inits.h = dc_fixpt_add(data->inits.h, dc_fixpt_mul_int(
803 data->ratios.horz, data->recout.x - recout_full->x));
804 /*
805 * this is the difference between first pixel of viewport available to read
806 * and init position, takning into account scan direction
807 */
808 int_part = dc_fixpt_floor(data->inits.h) - end_offset;
809 if (int_part < data->taps.h_taps) {
810 int int_adj = end_offset >= (data->taps.h_taps - int_part) ?
811 (data->taps.h_taps - int_part) : end_offset;
812 data->viewport.width += int_adj;
813 int_part += int_adj;
814 } else if (int_part > data->taps.h_taps) {
815 data->viewport.width += int_part - data->taps.h_taps;
816 int_part = data->taps.h_taps;
817 }
818 data->inits.h.value &= 0xffffffff;
819 data->inits.h = dc_fixpt_add_int(data->inits.h, int_part);
b2d0a103 820 }
b2d0a103 821
9a08f51f
DL
822 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
823 int int_part;
824 int end_offset = (src.x + src.width) / vpc_div
825 - data->viewport_c.x - data->viewport_c.width;
826
827 /*
828 * this is init if vp had no offset, keep in mind this is from the
829 * right side of vp due to scan direction
830 */
831 data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_mul_int(
832 data->ratios.horz_c, data->recout.x - recout_full->x));
833 /*
834 * this is the difference between first pixel of viewport available to read
835 * and init position, takning into account scan direction
836 */
837 int_part = dc_fixpt_floor(data->inits.h_c) - end_offset;
838 if (int_part < data->taps.h_taps_c) {
839 int int_adj = end_offset >= (data->taps.h_taps_c - int_part) ?
840 (data->taps.h_taps_c - int_part) : end_offset;
841 data->viewport_c.width += int_adj;
842 int_part += int_adj;
843 } else if (int_part > data->taps.h_taps_c) {
844 data->viewport_c.width += int_part - data->taps.h_taps_c;
845 int_part = data->taps.h_taps_c;
846 }
847 data->inits.h_c.value &= 0xffffffff;
848 data->inits.h_c = dc_fixpt_add_int(data->inits.h_c, int_part);
b2d0a103 849 }
9a08f51f 850
b2d0a103 851 }
9a08f51f
DL
852 if (!flip_vert_scan_dir) {
853 /* Adjust for viewport end clip-off */
854 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
855 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
856 int int_part = dc_fixpt_floor(
857 dc_fixpt_sub(data->inits.v, data->ratios.vert));
858
859 int_part = int_part > 0 ? int_part : 0;
860 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
861 }
862 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
863 int vp_clip = (src.y + src.height) / vpc_div -
864 data->viewport_c.height - data->viewport_c.y;
865 int int_part = dc_fixpt_floor(
866 dc_fixpt_sub(data->inits.v_c, data->ratios.vert_c));
867
868 int_part = int_part > 0 ? int_part : 0;
869 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
870 }
b2d0a103 871
9a08f51f
DL
872 /* Adjust for non-0 viewport offset */
873 if (data->viewport.y) {
874 int int_part;
875
876 data->inits.v = dc_fixpt_add(data->inits.v, dc_fixpt_mul_int(
877 data->ratios.vert, data->recout.y - recout_full->y));
878 int_part = dc_fixpt_floor(data->inits.v) - data->viewport.y;
879 if (int_part < data->taps.v_taps) {
880 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
881 (data->taps.v_taps - int_part) : data->viewport.y;
882 data->viewport.y -= int_adj;
883 data->viewport.height += int_adj;
884 int_part += int_adj;
885 } else if (int_part > data->taps.v_taps) {
886 data->viewport.y += int_part - data->taps.v_taps;
887 data->viewport.height -= int_part - data->taps.v_taps;
888 int_part = data->taps.v_taps;
889 }
890 data->inits.v.value &= 0xffffffff;
891 data->inits.v = dc_fixpt_add_int(data->inits.v, int_part);
892 }
893
894 if (data->viewport_c.y) {
895 int int_part;
896
897 data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_mul_int(
898 data->ratios.vert_c, data->recout.y - recout_full->y));
899 int_part = dc_fixpt_floor(data->inits.v_c) - data->viewport_c.y;
900 if (int_part < data->taps.v_taps_c) {
901 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
902 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
903 data->viewport_c.y -= int_adj;
904 data->viewport_c.height += int_adj;
905 int_part += int_adj;
906 } else if (int_part > data->taps.v_taps_c) {
907 data->viewport_c.y += int_part - data->taps.v_taps_c;
908 data->viewport_c.height -= int_part - data->taps.v_taps_c;
909 int_part = data->taps.v_taps_c;
910 }
911 data->inits.v_c.value &= 0xffffffff;
912 data->inits.v_c = dc_fixpt_add_int(data->inits.v_c, int_part);
913 }
914 } else {
915 /* Adjust for non-0 viewport offset */
916 if (data->viewport.y) {
917 int int_part = dc_fixpt_floor(
918 dc_fixpt_sub(data->inits.v, data->ratios.vert));
919
920 int_part = int_part > 0 ? int_part : 0;
921 data->viewport.height += int_part < data->viewport.y ? int_part : data->viewport.y;
922 data->viewport.y -= int_part < data->viewport.y ? int_part : data->viewport.y;
923 }
924 if (data->viewport_c.y) {
925 int int_part = dc_fixpt_floor(
926 dc_fixpt_sub(data->inits.v_c, data->ratios.vert_c));
927
928 int_part = int_part > 0 ? int_part : 0;
929 data->viewport_c.height += int_part < data->viewport_c.y ? int_part : data->viewport_c.y;
930 data->viewport_c.y -= int_part < data->viewport_c.y ? int_part : data->viewport_c.y;
b2d0a103 931 }
b2d0a103 932
9a08f51f
DL
933 /* Adjust for viewport end clip-off */
934 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
935 int int_part;
936 int end_offset = src.y + src.height
937 - data->viewport.y - data->viewport.height;
938
939 /*
940 * this is init if vp had no offset, keep in mind this is from the
941 * right side of vp due to scan direction
942 */
943 data->inits.v = dc_fixpt_add(data->inits.v, dc_fixpt_mul_int(
944 data->ratios.vert, data->recout.y - recout_full->y));
945 /*
946 * this is the difference between first pixel of viewport available to read
947 * and init position, taking into account scan direction
948 */
949 int_part = dc_fixpt_floor(data->inits.v) - end_offset;
950 if (int_part < data->taps.v_taps) {
951 int int_adj = end_offset >= (data->taps.v_taps - int_part) ?
952 (data->taps.v_taps - int_part) : end_offset;
953 data->viewport.height += int_adj;
954 int_part += int_adj;
955 } else if (int_part > data->taps.v_taps) {
956 data->viewport.height += int_part - data->taps.v_taps;
957 int_part = data->taps.v_taps;
958 }
959 data->inits.v.value &= 0xffffffff;
960 data->inits.v = dc_fixpt_add_int(data->inits.v, int_part);
961 }
962
963 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
964 int int_part;
965 int end_offset = (src.y + src.height) / vpc_div
966 - data->viewport_c.y - data->viewport_c.height;
967
968 /*
969 * this is init if vp had no offset, keep in mind this is from the
970 * right side of vp due to scan direction
971 */
972 data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_mul_int(
973 data->ratios.vert_c, data->recout.y - recout_full->y));
974 /*
975 * this is the difference between first pixel of viewport available to read
976 * and init position, taking into account scan direction
977 */
978 int_part = dc_fixpt_floor(data->inits.v_c) - end_offset;
979 if (int_part < data->taps.v_taps_c) {
980 int int_adj = end_offset >= (data->taps.v_taps_c - int_part) ?
981 (data->taps.v_taps_c - int_part) : end_offset;
982 data->viewport_c.height += int_adj;
983 int_part += int_adj;
984 } else if (int_part > data->taps.v_taps_c) {
985 data->viewport_c.height += int_part - data->taps.v_taps_c;
986 int_part = data->taps.v_taps_c;
987 }
988 data->inits.v_c.value &= 0xffffffff;
989 data->inits.v_c = dc_fixpt_add_int(data->inits.v_c, int_part);
b2d0a103 990 }
b2d0a103
DL
991 }
992
993 /* Interlaced inits based on final vert inits */
eb0e5154
DL
994 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
995 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 996
3be5262e
HW
997 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
998 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL
999 rect_swap_helper(&data->viewport_c);
1000 rect_swap_helper(&data->viewport);
1001 }
b2d0a103
DL
1002}
1003
1004bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 1005{
3be5262e 1006 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 1007 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
9a08f51f 1008 struct rect recout_full = { 0 };
b2d0a103 1009 bool res = false;
5d4b05dd 1010 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW
1011 /* Important: scaling ratio calculation requires pixel format,
1012 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 1013 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 1014 */
6702a9ac 1015 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 1016 pipe_ctx->plane_state->format);
b2d0a103 1017
dc002a2e
DL
1018 if (pipe_ctx->stream->timing.flags.INTERLACE)
1019 pipe_ctx->stream->dst.height *= 2;
1020
b2d0a103 1021 calculate_scaling_ratios(pipe_ctx);
4562236b 1022
b2d0a103 1023 calculate_viewport(pipe_ctx);
4562236b 1024
6702a9ac 1025 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW
1026 return false;
1027
9a08f51f 1028 calculate_recout(pipe_ctx, &recout_full);
4562236b
HW
1029
1030 /**
1031 * Setting line buffer pixel depth to 24bpp yields banding
1032 * on certain displays, such as the Sharp 4k
1033 */
6702a9ac 1034 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 1035
199e458a 1036 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1037 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1038
58bb0e63
AJ
1039 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
1040 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
dc002a2e
DL
1041 if (pipe_ctx->stream->timing.flags.INTERLACE)
1042 pipe_ctx->plane_res.scl_data.v_active *= 2;
4562236b 1043
1b6c8067 1044
4562236b 1045 /* Taps calculations */
d94585a0
YHL
1046 if (pipe_ctx->plane_res.xfm != NULL)
1047 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1048 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1049
1050 if (pipe_ctx->plane_res.dpp != NULL)
1051 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1052 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW
1053 if (!res) {
1054 /* Try 24 bpp linebuffer */
6702a9ac 1055 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1056
1b6c8067
BL
1057 if (pipe_ctx->plane_res.xfm != NULL)
1058 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1059 pipe_ctx->plane_res.xfm,
1060 &pipe_ctx->plane_res.scl_data,
1061 &plane_state->scaling_quality);
1062
1063 if (pipe_ctx->plane_res.dpp != NULL)
1064 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1065 pipe_ctx->plane_res.dpp,
1066 &pipe_ctx->plane_res.scl_data,
1067 &plane_state->scaling_quality);
4562236b
HW
1068 }
1069
b2d0a103 1070 if (res)
1fbd2cfc 1071 /* May need to re-check lb size after this in some obscure scenario */
9a08f51f 1072 calculate_inits_and_adj_vp(pipe_ctx, &recout_full);
b2d0a103 1073
1296423b 1074 DC_LOG_SCALER(
4562236b
HW
1075 "%s: Viewport:\nheight:%d width:%d x:%d "
1076 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1077 "y:%d\n",
1078 __func__,
6702a9ac
HW
1079 pipe_ctx->plane_res.scl_data.viewport.height,
1080 pipe_ctx->plane_res.scl_data.viewport.width,
1081 pipe_ctx->plane_res.scl_data.viewport.x,
1082 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW
1083 plane_state->dst_rect.height,
1084 plane_state->dst_rect.width,
1085 plane_state->dst_rect.x,
1086 plane_state->dst_rect.y);
4562236b 1087
dc002a2e
DL
1088 if (pipe_ctx->stream->timing.flags.INTERLACE)
1089 pipe_ctx->stream->dst.height /= 2;
1090
4562236b
HW
1091 return res;
1092}
1093
1094
1095enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1096 const struct dc *dc,
608ac7bb 1097 struct dc_state *context)
4562236b
HW
1098{
1099 int i;
1100
1101 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1102 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1103 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1104 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1105 return DC_FAIL_SCALING;
4562236b
HW
1106 }
1107
1108 return DC_OK;
1109}
1110
a2b8659d
TC
1111struct pipe_ctx *find_idle_secondary_pipe(
1112 struct resource_context *res_ctx,
1113 const struct resource_pool *pool)
4562236b
HW
1114{
1115 int i;
1116 struct pipe_ctx *secondary_pipe = NULL;
1117
1118 /*
1119 * search backwards for the second pipe to keep pipe
1120 * assignment more consistent
1121 */
1122
a2b8659d 1123 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW
1124 if (res_ctx->pipe_ctx[i].stream == NULL) {
1125 secondary_pipe = &res_ctx->pipe_ctx[i];
1126 secondary_pipe->pipe_idx = i;
1127 break;
1128 }
1129 }
1130
1131
1132 return secondary_pipe;
1133}
1134
1135struct pipe_ctx *resource_get_head_pipe_for_stream(
1136 struct resource_context *res_ctx,
0971c40e 1137 struct dc_stream_state *stream)
4562236b
HW
1138{
1139 int i;
a2b8659d 1140 for (i = 0; i < MAX_PIPES; i++) {
4562236b 1141 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 1142 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW
1143 return &res_ctx->pipe_ctx[i];
1144 break;
1145 }
1146 }
1147 return NULL;
1148}
1149
19f89e23
AG
1150static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1151 struct resource_context *res_ctx,
1152 struct dc_stream_state *stream)
1153{
1154 struct pipe_ctx *head_pipe, *tail_pipe;
1155 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1156
1157 if (!head_pipe)
1158 return NULL;
1159
1160 tail_pipe = head_pipe->bottom_pipe;
1161
1162 while (tail_pipe) {
1163 head_pipe = tail_pipe;
1164 tail_pipe = tail_pipe->bottom_pipe;
1165 }
1166
1167 return head_pipe;
1168}
1169
4562236b 1170/*
ab2541b6
AC
1171 * A free_pipe for a stream is defined here as a pipe
1172 * that has no surface attached yet
4562236b 1173 */
ab2541b6 1174static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1175 struct dc_state *context,
a2b8659d 1176 const struct resource_pool *pool,
0971c40e 1177 struct dc_stream_state *stream)
4562236b
HW
1178{
1179 int i;
745cc746 1180 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW
1181
1182 struct pipe_ctx *head_pipe = NULL;
1183
1184 /* Find head pipe, which has the back end set up*/
1185
1186 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1187
e41ab030 1188 if (!head_pipe) {
4562236b 1189 ASSERT(0);
e41ab030
HW
1190 return NULL;
1191 }
4562236b 1192
3be5262e 1193 if (!head_pipe->plane_state)
4562236b
HW
1194 return head_pipe;
1195
1196 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1197 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1198 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1199 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW
1200 return &res_ctx->pipe_ctx[i];
1201 }
1202 }
1203
1204 /*
1205 * At this point we have no re-useable pipe for this stream and we need
1206 * to acquire an idle one to satisfy the request
1207 */
1208
a2b8659d 1209 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW
1210 return NULL;
1211
a2b8659d 1212 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW
1213
1214}
1215
48412031 1216#ifdef CONFIG_X86
0f9a536f
DL
1217static int acquire_first_split_pipe(
1218 struct resource_context *res_ctx,
1219 const struct resource_pool *pool,
0971c40e 1220 struct dc_stream_state *stream)
0f9a536f
DL
1221{
1222 int i;
1223
1224 for (i = 0; i < pool->pipe_count; i++) {
1225 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1226
1227 if (pipe_ctx->top_pipe &&
3be5262e 1228 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL
1229 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1230 if (pipe_ctx->bottom_pipe)
1231 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1232
1233 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1234 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1235 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1236 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1237 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1238 pipe_ctx->stream_res.opp = pool->opps[i];
e07f541f 1239 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
0f9a536f 1240 pipe_ctx->pipe_idx = i;
0f9a536f
DL
1241
1242 pipe_ctx->stream = stream;
1243 return i;
1244 }
1245 }
1246 return -1;
1247}
1248#endif
1249
19f89e23
AG
1250bool dc_add_plane_to_context(
1251 const struct dc *dc,
0971c40e 1252 struct dc_stream_state *stream,
19f89e23 1253 struct dc_plane_state *plane_state,
608ac7bb 1254 struct dc_state *context)
4562236b
HW
1255{
1256 int i;
19f89e23
AG
1257 struct resource_pool *pool = dc->res_pool;
1258 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1259 struct dc_stream_status *stream_status = NULL;
4562236b 1260
19f89e23
AG
1261 for (i = 0; i < context->stream_count; i++)
1262 if (context->streams[i] == stream) {
1263 stream_status = &context->stream_status[i];
1264 break;
1265 }
1266 if (stream_status == NULL) {
1267 dm_error("Existing stream not found; failed to attach surface!\n");
1268 return false;
1269 }
1270
4562236b 1271
19f89e23
AG
1272 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1273 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1274 plane_state, MAX_SURFACE_NUM);
4562236b
HW
1275 return false;
1276 }
1277
19f89e23
AG
1278 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1279
1280 if (!head_pipe) {
1281 dm_error("Head pipe not found for stream_state %p !\n", stream);
1282 return false;
1283 }
1284
19f89e23
AG
1285 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1286
48412031 1287#ifdef CONFIG_X86
19f89e23
AG
1288 if (!free_pipe) {
1289 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1290 if (pipe_idx >= 0)
1291 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1292 }
1293#endif
abb4986e 1294 if (!free_pipe)
19f89e23 1295 return false;
19f89e23 1296
abb4986e
AJ
1297 /* retain new surfaces */
1298 dc_plane_state_retain(plane_state);
19f89e23
AG
1299 free_pipe->plane_state = plane_state;
1300
1301 if (head_pipe != free_pipe) {
1302
1303 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1304 ASSERT(tail_pipe);
1305
1306 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1307 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG
1308 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1309 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1310 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1311 free_pipe->clock_source = tail_pipe->clock_source;
1312 free_pipe->top_pipe = tail_pipe;
1313 tail_pipe->bottom_pipe = free_pipe;
1314 }
1315
1316 /* assign new surfaces*/
1317 stream_status->plane_states[stream_status->plane_count] = plane_state;
1318
1319 stream_status->plane_count++;
1320
1321 return true;
1322}
1323
1324bool dc_remove_plane_from_context(
1325 const struct dc *dc,
1326 struct dc_stream_state *stream,
1327 struct dc_plane_state *plane_state,
608ac7bb 1328 struct dc_state *context)
19f89e23
AG
1329{
1330 int i;
1331 struct dc_stream_status *stream_status = NULL;
1332 struct resource_pool *pool = dc->res_pool;
1333
ab2541b6 1334 for (i = 0; i < context->stream_count; i++)
4fa086b9 1335 if (context->streams[i] == stream) {
ab2541b6 1336 stream_status = &context->stream_status[i];
4562236b
HW
1337 break;
1338 }
19f89e23 1339
ab2541b6 1340 if (stream_status == NULL) {
19f89e23 1341 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW
1342 return false;
1343 }
1344
19f89e23
AG
1345 /* release pipe for plane*/
1346 for (i = pool->pipe_count - 1; i >= 0; i--) {
1347 struct pipe_ctx *pipe_ctx;
4562236b 1348
19f89e23
AG
1349 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1350 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1351
19f89e23
AG
1352 if (pipe_ctx->top_pipe)
1353 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1354
19f89e23
AG
1355 /* Second condition is to avoid setting NULL to top pipe
1356 * of tail pipe making it look like head pipe in subsequent
1357 * deletes
1358 */
1359 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1360 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1361
19f89e23
AG
1362 /*
1363 * For head pipe detach surfaces from pipe for tail
1364 * pipe just zero it out
1365 */
1366 if (!pipe_ctx->top_pipe) {
1367 pipe_ctx->plane_state = NULL;
1368 pipe_ctx->bottom_pipe = NULL;
1369 } else {
1370 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1371 }
4562236b 1372 }
19f89e23 1373 }
4562236b 1374
4562236b 1375
19f89e23
AG
1376 for (i = 0; i < stream_status->plane_count; i++) {
1377 if (stream_status->plane_states[i] == plane_state) {
1378
1379 dc_plane_state_release(stream_status->plane_states[i]);
1380 break;
4562236b 1381 }
19f89e23 1382 }
4562236b 1383
19f89e23
AG
1384 if (i == stream_status->plane_count) {
1385 dm_error("Existing plane_state not found; failed to detach it!\n");
1386 return false;
4562236b
HW
1387 }
1388
19f89e23 1389 stream_status->plane_count--;
4562236b 1390
abb4986e
AJ
1391 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1392 for (; i < stream_status->plane_count; i++)
19f89e23
AG
1393 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1394
1395 stream_status->plane_states[stream_status->plane_count] = NULL;
1396
1397 return true;
1398}
1399
1400bool dc_rem_all_planes_for_stream(
1401 const struct dc *dc,
1402 struct dc_stream_state *stream,
608ac7bb 1403 struct dc_state *context)
19f89e23
AG
1404{
1405 int i, old_plane_count;
1406 struct dc_stream_status *stream_status = NULL;
1407 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1408
1409 for (i = 0; i < context->stream_count; i++)
1410 if (context->streams[i] == stream) {
1411 stream_status = &context->stream_status[i];
1412 break;
1413 }
1414
1415 if (stream_status == NULL) {
1416 dm_error("Existing stream %p not found!\n", stream);
1417 return false;
1418 }
1419
1420 old_plane_count = stream_status->plane_count;
1421
1422 for (i = 0; i < old_plane_count; i++)
1423 del_planes[i] = stream_status->plane_states[i];
1424
1425 for (i = 0; i < old_plane_count; i++)
1426 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1427 return false;
1428
1429 return true;
1430}
1431
1432static bool add_all_planes_for_stream(
1433 const struct dc *dc,
1434 struct dc_stream_state *stream,
1435 const struct dc_validation_set set[],
1436 int set_count,
608ac7bb 1437 struct dc_state *context)
19f89e23
AG
1438{
1439 int i, j;
1440
1441 for (i = 0; i < set_count; i++)
1442 if (set[i].stream == stream)
1443 break;
1444
1445 if (i == set_count) {
1446 dm_error("Stream %p not found in set!\n", stream);
1447 return false;
1448 }
4562236b 1449
19f89e23
AG
1450 for (j = 0; j < set[i].plane_count; j++)
1451 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1452 return false;
4562236b
HW
1453
1454 return true;
1455}
1456
19f89e23
AG
1457bool dc_add_all_planes_for_stream(
1458 const struct dc *dc,
1459 struct dc_stream_state *stream,
1460 struct dc_plane_state * const *plane_states,
1461 int plane_count,
608ac7bb 1462 struct dc_state *context)
19f89e23
AG
1463{
1464 struct dc_validation_set set;
1465 int i;
1466
1467 set.stream = stream;
1468 set.plane_count = plane_count;
1469
1470 for (i = 0; i < plane_count; i++)
1471 set.plane_states[i] = plane_states[i];
1472
1473 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1474}
1475
1476
6b622181
JP
1477static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1478 struct dc_stream_state *new_stream)
1479{
1480 if (cur_stream == NULL)
1481 return true;
1482
1483 if (memcmp(&cur_stream->hdr_static_metadata,
1484 &new_stream->hdr_static_metadata,
1485 sizeof(struct dc_info_packet)) != 0)
1486 return true;
1487
1488 return false;
1489}
4562236b 1490
0971c40e
HW
1491static bool is_timing_changed(struct dc_stream_state *cur_stream,
1492 struct dc_stream_state *new_stream)
4562236b
HW
1493{
1494 if (cur_stream == NULL)
1495 return true;
1496
1497 /* If sink pointer changed, it means this is a hotplug, we should do
1498 * full hw setting.
1499 */
1500 if (cur_stream->sink != new_stream->sink)
1501 return true;
1502
1503 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1504 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW
1505 return true;
1506
1507 return memcmp(
4fa086b9
LSL
1508 &cur_stream->timing,
1509 &new_stream->timing,
4562236b
HW
1510 sizeof(struct dc_crtc_timing)) != 0;
1511}
1512
1513static bool are_stream_backends_same(
0971c40e 1514 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW
1515{
1516 if (stream_a == stream_b)
1517 return true;
1518
1519 if (stream_a == NULL || stream_b == NULL)
1520 return false;
1521
1522 if (is_timing_changed(stream_a, stream_b))
1523 return false;
1524
6b622181
JP
1525 if (is_hdr_static_meta_changed(stream_a, stream_b))
1526 return false;
1527
4562236b
HW
1528 return true;
1529}
1530
d54d29db 1531bool dc_is_stream_unchanged(
0971c40e 1532 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1533{
4562236b 1534
ab2541b6
AC
1535 if (!are_stream_backends_same(old_stream, stream))
1536 return false;
4562236b
HW
1537
1538 return true;
1539}
1540
9a5d9c48
LSL
1541bool dc_is_stream_scaling_unchanged(
1542 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1543{
1544 if (old_stream == stream)
1545 return true;
1546
1547 if (old_stream == NULL || stream == NULL)
1548 return false;
1549
1550 if (memcmp(&old_stream->src,
1551 &stream->src,
1552 sizeof(struct rect)) != 0)
1553 return false;
1554
1555 if (memcmp(&old_stream->dst,
1556 &stream->dst,
1557 sizeof(struct rect)) != 0)
1558 return false;
1559
1560 return true;
1561}
1562
1dc90497 1563static void update_stream_engine_usage(
4562236b 1564 struct resource_context *res_ctx,
a2b8659d 1565 const struct resource_pool *pool,
1dc90497
AG
1566 struct stream_encoder *stream_enc,
1567 bool acquired)
4562236b
HW
1568{
1569 int i;
1570
a2b8659d
TC
1571 for (i = 0; i < pool->stream_enc_count; i++) {
1572 if (pool->stream_enc[i] == stream_enc)
1dc90497 1573 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW
1574 }
1575}
1576
1577/* TODO: release audio object */
4176664b 1578void update_audio_usage(
4562236b 1579 struct resource_context *res_ctx,
a2b8659d 1580 const struct resource_pool *pool,
1dc90497
AG
1581 struct audio *audio,
1582 bool acquired)
4562236b
HW
1583{
1584 int i;
a2b8659d
TC
1585 for (i = 0; i < pool->audio_count; i++) {
1586 if (pool->audios[i] == audio)
1dc90497 1587 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW
1588 }
1589}
1590
1591static int acquire_first_free_pipe(
1592 struct resource_context *res_ctx,
a2b8659d 1593 const struct resource_pool *pool,
0971c40e 1594 struct dc_stream_state *stream)
4562236b
HW
1595{
1596 int i;
1597
a2b8659d 1598 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW
1599 if (!res_ctx->pipe_ctx[i].stream) {
1600 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1601
6b670fa9 1602 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1603 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1604 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW
1605 pipe_ctx->plane_res.ipp = pool->ipps[i];
1606 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1607 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1608 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL
1609 if (pool->dpps[i])
1610 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW
1611 pipe_ctx->pipe_idx = i;
1612
ff5ef992 1613
4562236b
HW
1614 pipe_ctx->stream = stream;
1615 return i;
1616 }
1617 }
1618 return -1;
1619}
1620
1621static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1622 struct resource_context *res_ctx,
a2b8659d 1623 const struct resource_pool *pool,
0971c40e 1624 struct dc_stream_state *stream)
4562236b
HW
1625{
1626 int i;
1627 int j = -1;
d0778ebf 1628 struct dc_link *link = stream->sink->link;
4562236b 1629
a2b8659d 1630 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1631 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1632 pool->stream_enc[i]) {
4562236b
HW
1633 /* Store first available for MST second display
1634 * in daisy chain use case */
1635 j = i;
a2b8659d 1636 if (pool->stream_enc[i]->id ==
4562236b 1637 link->link_enc->preferred_engine)
a2b8659d 1638 return pool->stream_enc[i];
4562236b
HW
1639 }
1640 }
1641
1642 /*
1643 * below can happen in cases when stream encoder is acquired:
1644 * 1) for second MST display in chain, so preferred engine already
1645 * acquired;
1646 * 2) for another link, which preferred engine already acquired by any
1647 * MST configuration.
1648 *
1649 * If signal is of DP type and preferred engine not found, return last available
1650 *
1651 * TODO - This is just a patch up and a generic solution is
1652 * required for non DP connectors.
1653 */
1654
1655 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1656 return pool->stream_enc[j];
4562236b
HW
1657
1658 return NULL;
1659}
1660
a2b8659d
TC
1661static struct audio *find_first_free_audio(
1662 struct resource_context *res_ctx,
cfb071f7
CL
1663 const struct resource_pool *pool,
1664 enum engine_id id)
4562236b
HW
1665{
1666 int i;
66bfd4fd
CL
1667 for (i = 0; i < pool->audio_count; i++) {
1668 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL
1669 /*we have enough audio endpoint, find the matching inst*/
1670 if (id != i)
1671 continue;
1672
66bfd4fd 1673 return pool->audios[i];
4562236b 1674 }
66bfd4fd
CL
1675 }
1676 /*not found the matching one, first come first serve*/
1677 for (i = 0; i < pool->audio_count; i++) {
1678 if (res_ctx->is_audio_acquired[i] == false) {
1679 return pool->audios[i];
4176664b
CL
1680 }
1681 }
4562236b
HW
1682 return 0;
1683}
1684
4562236b 1685bool resource_is_stream_unchanged(
608ac7bb 1686 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1687{
ab2541b6 1688 int i;
4562236b 1689
ab2541b6 1690 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1691 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1692
ab2541b6 1693 if (are_stream_backends_same(old_stream, stream))
4562236b 1694 return true;
4562236b
HW
1695 }
1696
1697 return false;
1698}
1699
13ab1b44 1700enum dc_status dc_add_stream_to_ctx(
1dc90497 1701 struct dc *dc,
608ac7bb 1702 struct dc_state *new_ctx,
1dc90497
AG
1703 struct dc_stream_state *stream)
1704{
1705 struct dc_context *dc_ctx = dc->ctx;
1706 enum dc_status res;
1707
ece4147f
KC
1708 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1709 DC_ERROR("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG
1710 return DC_ERROR_UNEXPECTED;
1711 }
1712
1713 new_ctx->streams[new_ctx->stream_count] = stream;
1714 dc_stream_retain(stream);
1715 new_ctx->stream_count++;
1716
1717 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1718 if (res != DC_OK)
1719 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1720
13ab1b44 1721 return res;
1dc90497
AG
1722}
1723
62c933f9 1724enum dc_status dc_remove_stream_from_ctx(
1dc90497 1725 struct dc *dc,
608ac7bb 1726 struct dc_state *new_ctx,
1dc90497
AG
1727 struct dc_stream_state *stream)
1728{
19f89e23 1729 int i;
1dc90497
AG
1730 struct dc_context *dc_ctx = dc->ctx;
1731 struct pipe_ctx *del_pipe = NULL;
1732
19f89e23 1733 /* Release primary pipe */
1dc90497 1734 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG
1735 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1736 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG
1737 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1738
19f89e23
AG
1739 ASSERT(del_pipe->stream_res.stream_enc);
1740 update_stream_engine_usage(
1741 &new_ctx->res_ctx,
1dc90497 1742 dc->res_pool,
19f89e23
AG
1743 del_pipe->stream_res.stream_enc,
1744 false);
1dc90497
AG
1745
1746 if (del_pipe->stream_res.audio)
1747 update_audio_usage(
1748 &new_ctx->res_ctx,
1749 dc->res_pool,
1750 del_pipe->stream_res.audio,
1751 false);
1752
9d0dcecd
HW
1753 resource_unreference_clock_source(&new_ctx->res_ctx,
1754 dc->res_pool,
1755 del_pipe->clock_source);
1756
e56ae556
NC
1757 if (dc->res_pool->funcs->remove_stream_from_ctx)
1758 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1759
1dc90497 1760 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG
1761
1762 break;
1dc90497
AG
1763 }
1764 }
1765
1766 if (!del_pipe) {
1767 DC_ERROR("Pipe not found for stream %p !\n", stream);
1768 return DC_ERROR_UNEXPECTED;
1769 }
1770
1771 for (i = 0; i < new_ctx->stream_count; i++)
1772 if (new_ctx->streams[i] == stream)
1773 break;
1774
1775 if (new_ctx->streams[i] != stream) {
1776 DC_ERROR("Context doesn't have stream %p !\n", stream);
1777 return DC_ERROR_UNEXPECTED;
1778 }
1779
1780 dc_stream_release(new_ctx->streams[i]);
1781 new_ctx->stream_count--;
1782
1dc90497
AG
1783 /* Trim back arrays */
1784 for (; i < new_ctx->stream_count; i++) {
1785 new_ctx->streams[i] = new_ctx->streams[i + 1];
1786 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1787 }
1788
1789 new_ctx->streams[new_ctx->stream_count] = NULL;
1790 memset(
1791 &new_ctx->stream_status[new_ctx->stream_count],
1792 0,
1793 sizeof(new_ctx->stream_status[0]));
1794
1795 return DC_OK;
1796}
1797
0971c40e
HW
1798static struct dc_stream_state *find_pll_sharable_stream(
1799 struct dc_stream_state *stream_needs_pll,
608ac7bb 1800 struct dc_state *context)
4562236b 1801{
ab2541b6 1802 int i;
4562236b 1803
ab2541b6 1804 for (i = 0; i < context->stream_count; i++) {
0971c40e 1805 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1806
ab2541b6
AC
1807 /* We are looking for non dp, non virtual stream */
1808 if (resource_are_streams_timing_synchronizable(
1809 stream_needs_pll, stream_has_pll)
1810 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1811 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC
1812 != SIGNAL_TYPE_VIRTUAL)
1813 return stream_has_pll;
4562236b 1814
4562236b
HW
1815 }
1816
1817 return NULL;
1818}
1819
1820static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1821{
1822 uint32_t pix_clk = timing->pix_clk_khz;
1823 uint32_t normalized_pix_clk = pix_clk;
1824
1825 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1826 pix_clk /= 2;
cc4d99b8
CL
1827 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1828 switch (timing->display_color_depth) {
1829 case COLOR_DEPTH_888:
1830 normalized_pix_clk = pix_clk;
1831 break;
1832 case COLOR_DEPTH_101010:
1833 normalized_pix_clk = (pix_clk * 30) / 24;
1834 break;
1835 case COLOR_DEPTH_121212:
1836 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1837 break;
cc4d99b8
CL
1838 case COLOR_DEPTH_161616:
1839 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1840 break;
cc4d99b8
CL
1841 default:
1842 ASSERT(0);
4562236b 1843 break;
cc4d99b8 1844 }
4562236b 1845 }
4562236b
HW
1846 return normalized_pix_clk;
1847}
1848
0971c40e 1849static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1850{
9345d987
AG
1851 /* update actual pixel clock on all streams */
1852 if (dc_is_hdmi_signal(stream->signal))
1853 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1854 &stream->timing);
9345d987
AG
1855 else
1856 stream->phy_pix_clk =
4fa086b9 1857 stream->timing.pix_clk_khz;
4562236b
HW
1858}
1859
1860enum dc_status resource_map_pool_resources(
fb3466a4 1861 const struct dc *dc,
608ac7bb 1862 struct dc_state *context,
1dc90497 1863 struct dc_stream_state *stream)
4562236b 1864{
a2b8659d 1865 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG
1866 int i;
1867 struct dc_context *dc_ctx = dc->ctx;
1868 struct pipe_ctx *pipe_ctx = NULL;
1869 int pipe_idx = -1;
4562236b 1870
1dc90497
AG
1871 /* TODO Check if this is needed */
1872 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1873 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1874 stream->bit_depth_params =
430ef426
DL
1875 old_context->streams[i]->bit_depth_params;
1876 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC
1877 continue;
1878 }
4b679bc3 1879 }
1dc90497 1880 */
7e2fe319 1881
1dc90497
AG
1882 /* acquire new resources */
1883 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1884
48412031 1885#ifdef CONFIG_X86
1dc90497 1886 if (pipe_idx < 0)
13ab1b44 1887 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1888#endif
13ab1b44 1889
c5b38aec 1890 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG
1891 return DC_NO_CONTROLLER_RESOURCE;
1892
1893 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1894
1895 pipe_ctx->stream_res.stream_enc =
1896 find_first_free_match_stream_enc_for_link(
1897 &context->res_ctx, pool, stream);
1898
1899 if (!pipe_ctx->stream_res.stream_enc)
1900 return DC_NO_STREAM_ENG_RESOURCE;
1901
1902 update_stream_engine_usage(
1903 &context->res_ctx, pool,
1904 pipe_ctx->stream_res.stream_enc,
1905 true);
1906
1907 /* TODO: Add check if ASIC support and EDID audio */
1908 if (!stream->sink->converter_disable_audio &&
1909 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1910 stream->audio_info.mode_count) {
1911 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1912 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG
1913
1914 /*
1915 * Audio assigned in order first come first get.
1916 * There are asics which has number of audio
1917 * resources less then number of pipes
1918 */
1919 if (pipe_ctx->stream_res.audio)
1920 update_audio_usage(&context->res_ctx, pool,
1921 pipe_ctx->stream_res.audio, true);
1922 }
268cadbd 1923
9aef1a31
S
1924 /* Add ABM to the resource if on EDP */
1925 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1926 pipe_ctx->stream_res.abm = pool->abm;
1927
1dc90497
AG
1928 for (i = 0; i < context->stream_count; i++)
1929 if (context->streams[i] == stream) {
1930 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1931 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG
1932 return DC_OK;
1933 }
4562236b 1934
1dc90497
AG
1935 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1936 return DC_ERROR_UNEXPECTED;
1937}
4562236b 1938
f36cc577 1939void dc_resource_state_copy_construct_current(
1dc90497 1940 const struct dc *dc,
608ac7bb 1941 struct dc_state *dst_ctx)
1dc90497 1942{
f36cc577 1943 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG
1944}
1945
ab8db3e1
AG
1946
1947void dc_resource_state_construct(
1948 const struct dc *dc,
1949 struct dc_state *dst_ctx)
1950{
6ca11246 1951 dst_ctx->dis_clk = dc->res_pool->dccg;
ab8db3e1
AG
1952}
1953
e750d56d 1954enum dc_status dc_validate_global_state(
1dc90497 1955 struct dc *dc,
608ac7bb 1956 struct dc_state *new_ctx)
4562236b 1957{
1dc90497 1958 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1959 int i, j;
4562236b 1960
e41ab030
HW
1961 if (!new_ctx)
1962 return DC_ERROR_UNEXPECTED;
1963
d596e5d0 1964 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW
1965 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1966 if (result != DC_OK)
1967 return result;
d596e5d0 1968 }
4562236b 1969
e41ab030 1970 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG
1971 struct dc_stream_state *stream = new_ctx->streams[i];
1972
1973 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1974 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1975
1976 if (pipe_ctx->stream != stream)
1977 continue;
1978
1979 /* Switch to dp clock source only if there is
1980 * no non dp stream that shares the same timing
1981 * with the dp stream.
1982 */
1983 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1984 !find_pll_sharable_stream(stream, new_ctx)) {
1985
9d0dcecd 1986 resource_unreference_clock_source(
1dc90497
AG
1987 &new_ctx->res_ctx,
1988 dc->res_pool,
9d0dcecd 1989 pipe_ctx->clock_source);
4a629536 1990
1dc90497
AG
1991 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1992 resource_reference_clock_source(
1993 &new_ctx->res_ctx,
1994 dc->res_pool,
1995 pipe_ctx->clock_source);
1996 }
1997 }
1998 }
1999
1dc90497
AG
2000 result = resource_build_scaling_params_for_context(dc, new_ctx);
2001
2002 if (result == DC_OK)
2003 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
2004 result = DC_FAIL_BANDWIDTH_VALIDATE;
2005
2006 return result;
4562236b
HW
2007}
2008
6e4d6bee 2009static void patch_gamut_packet_checksum(
e09b6473 2010 struct dc_info_packet *gamut_packet)
4562236b 2011{
4562236b 2012 /* For gamut we recalc checksum */
6e4d6bee 2013 if (gamut_packet->valid) {
4562236b
HW
2014 uint8_t chk_sum = 0;
2015 uint8_t *ptr;
2016 uint8_t i;
2017
4562236b 2018 /*start of the Gamut data. */
6e4d6bee 2019 ptr = &gamut_packet->sb[3];
4562236b 2020
6e4d6bee 2021 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW
2022 chk_sum += ptr[i];
2023
6e4d6bee 2024 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2025 }
4562236b
HW
2026}
2027
2028static void set_avi_info_frame(
e09b6473 2029 struct dc_info_packet *info_packet,
4562236b
HW
2030 struct pipe_ctx *pipe_ctx)
2031{
0971c40e 2032 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2033 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW
2034 uint32_t pixel_encoding = 0;
2035 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2036 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2037 bool itc = false;
50e27654 2038 uint8_t itc_value = 0;
4562236b 2039 uint8_t cn0_cn1 = 0;
50e27654 2040 unsigned int cn0_cn1_value = 0;
4562236b
HW
2041 uint8_t *check_sum = NULL;
2042 uint8_t byte_index = 0;
754e3673 2043 union hdmi_info_packet hdmi_info;
50e27654 2044 union display_content_support support = {0};
4fa086b9 2045 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2046 enum dc_timing_3d_format format;
4562236b 2047
754e3673
AK
2048 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2049
4fa086b9 2050 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2051 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2052 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2053 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW
2054
2055 /* Initialize header */
e09b6473 2056 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW
2057 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2058 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK
2059 hdmi_info.bits.header.version = 2;
2060 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW
2061
2062 /*
2063 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2064 * according to HDMI 2.0 spec (Section 10.1)
2065 */
2066
4fa086b9 2067 switch (stream->timing.pixel_encoding) {
4562236b
HW
2068 case PIXEL_ENCODING_YCBCR422:
2069 pixel_encoding = 1;
2070 break;
2071
2072 case PIXEL_ENCODING_YCBCR444:
2073 pixel_encoding = 2;
2074 break;
2075 case PIXEL_ENCODING_YCBCR420:
2076 pixel_encoding = 3;
2077 break;
2078
2079 case PIXEL_ENCODING_RGB:
2080 default:
2081 pixel_encoding = 0;
2082 }
2083
2084 /* Y0_Y1_Y2 : The pixel encoding */
2085 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2086 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW
2087
2088 /* A0 = 1 Active Format Information valid */
e09b6473 2089 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW
2090
2091 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2092 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2093
e09b6473 2094 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW
2095
2096 /* S0, S1 : Underscan / Overscan */
2097 /* TODO: un-hardcode scan type */
2098 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2099 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW
2100
2101 /* C0, C1 : Colorimetry */
8fde5884 2102 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2103 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2104 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL
2105 else if (color_space == COLOR_SPACE_YCBCR601 ||
2106 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2107 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2108 else {
e09b6473 2109 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2110 }
534db198 2111 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL
2112 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2113 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK
2114 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2115 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2116 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK
2117 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2118 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ
2119 }
2120
4562236b 2121 /* TODO: un-hardcode aspect ratio */
4fa086b9 2122 aspect = stream->timing.aspect_ratio;
4562236b
HW
2123
2124 switch (aspect) {
2125 case ASPECT_RATIO_4_3:
2126 case ASPECT_RATIO_16_9:
e09b6473 2127 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW
2128 break;
2129
2130 case ASPECT_RATIO_NO_DATA:
2131 case ASPECT_RATIO_64_27:
2132 case ASPECT_RATIO_256_135:
2133 default:
e09b6473 2134 hdmi_info.bits.M0_M1 = 0;
4562236b
HW
2135 }
2136
2137 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2138 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW
2139
2140 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2141
4562236b 2142 cn0_cn1 = 0;
50e27654
ZF
2143 cn0_cn1_value = 0;
2144
2145 itc = true;
2146 itc_value = 1;
2147
4fa086b9 2148 support = stream->sink->edid_caps.content_support;
4562236b
HW
2149
2150 if (itc) {
50e27654
ZF
2151 if (!support.bits.valid_content_type) {
2152 cn0_cn1_value = 0;
2153 } else {
2154 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2155 if (support.bits.graphics_content == 1) {
2156 cn0_cn1_value = 0;
2157 }
2158 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2159 if (support.bits.photo_content == 1) {
2160 cn0_cn1_value = 1;
2161 } else {
2162 cn0_cn1_value = 0;
2163 itc_value = 0;
2164 }
2165 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2166 if (support.bits.cinema_content == 1) {
2167 cn0_cn1_value = 2;
2168 } else {
2169 cn0_cn1_value = 0;
2170 itc_value = 0;
2171 }
2172 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2173 if (support.bits.game_content == 1) {
2174 cn0_cn1_value = 3;
2175 } else {
2176 cn0_cn1_value = 0;
2177 itc_value = 0;
2178 }
2179 }
2180 }
e09b6473
AK
2181 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2182 hdmi_info.bits.ITC = itc_value;
4562236b
HW
2183 }
2184
2185 /* TODO : We should handle YCC quantization */
2186 /* but we do not have matrix calculation */
4fa086b9
LSL
2187 if (stream->sink->edid_caps.qs_bit == 1 &&
2188 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF
2189 if (color_space == COLOR_SPACE_SRGB ||
2190 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK
2191 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2192 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF
2193 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2194 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK
2195 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2196 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2197 } else {
e09b6473
AK
2198 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2199 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2200 }
4562236b 2201 } else {
e09b6473
AK
2202 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2203 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2204 }
50e27654 2205
15e17335 2206 ///VIC
4fa086b9 2207 format = stream->timing.timing_3d_format;
15e17335
CL
2208 /*todo, add 3DStereo support*/
2209 if (format != TIMING_3D_FORMAT_NONE) {
2210 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2211 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL
2212 case 1:
2213 vic = 95;
2214 break;
2215 case 2:
2216 vic = 94;
2217 break;
2218 case 3:
2219 vic = 93;
2220 break;
2221 case 4:
2222 vic = 98;
2223 break;
2224 default:
2225 break;
2226 }
2227 }
e09b6473 2228 hdmi_info.bits.VIC0_VIC7 = vic;
4562236b
HW
2229
2230 /* pixel repetition
2231 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2232 * repetition start from 1 */
e09b6473 2233 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW
2234
2235 /* Bar Info
2236 * barTop: Line Number of End of Top Bar.
2237 * barBottom: Line Number of Start of Bottom Bar.
2238 * barLeft: Pixel Number of End of Left Bar.
2239 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK
2240 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2241 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2242 - stream->timing.v_border_bottom + 1);
e09b6473
AK
2243 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2244 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2245 - stream->timing.h_border_right + 1);
4562236b
HW
2246
2247 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2248 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2249
3e183c5f 2250 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2251
3e183c5f 2252 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e09b6473 2253 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2254
2255 /* one byte complement */
2256 *check_sum = (uint8_t) (0x100 - *check_sum);
2257
2258 /* Store in hw_path_mode */
e09b6473
AK
2259 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2260 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2261 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2262
e09b6473
AK
2263 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2264 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2265
2266 info_packet->valid = true;
2267}
2268
6e4d6bee 2269static void set_vendor_info_packet(
e09b6473 2270 struct dc_info_packet *info_packet,
0971c40e 2271 struct dc_stream_state *stream)
4562236b
HW
2272{
2273 uint32_t length = 0;
2274 bool hdmi_vic_mode = false;
2275 uint8_t checksum = 0;
2276 uint32_t i = 0;
2277 enum dc_timing_3d_format format;
15e17335
CL
2278 // Can be different depending on packet content /*todo*/
2279 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2280
2281 info_packet->valid = false;
4562236b 2282
4fa086b9
LSL
2283 format = stream->timing.timing_3d_format;
2284 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2285 format = TIMING_3D_FORMAT_NONE;
4562236b
HW
2286
2287 /* Can be different depending on packet content */
2288 length = 5;
2289
4fa086b9
LSL
2290 if (stream->timing.hdmi_vic != 0
2291 && stream->timing.h_total >= 3840
2292 && stream->timing.v_total >= 2160)
4562236b
HW
2293 hdmi_vic_mode = true;
2294
2295 /* According to HDMI 1.4a CTS, VSIF should be sent
2296 * for both 3D stereo and HDMI VIC modes.
2297 * For all other modes, there is no VSIF sent. */
2298
2299 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2300 return;
2301
2302 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2303 info_packet->sb[1] = 0x03;
2304 info_packet->sb[2] = 0x0C;
2305 info_packet->sb[3] = 0x00;
2306
2307 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2308 * The value for HDMI_Video_Format are:
2309 * 0x0 (0b000) - No additional HDMI video format is presented in this
2310 * packet
2311 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2312 * parameter follows
2313 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2314 * potentially 3D_Ext_Data follows
2315 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2316 if (format != TIMING_3D_FORMAT_NONE)
2317 info_packet->sb[4] = (2 << 5);
2318 else if (hdmi_vic_mode)
2319 info_packet->sb[4] = (1 << 5);
2320
2321 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2322 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2323 * The value for 3D_Structure are:
2324 * 0x0 - Frame Packing
2325 * 0x1 - Field Alternative
2326 * 0x2 - Line Alternative
2327 * 0x3 - Side-by-Side (full)
2328 * 0x4 - L + depth
2329 * 0x5 - L + depth + graphics + graphics-depth
2330 * 0x6 - Top-and-Bottom
2331 * 0x7 - Reserved for future use
2332 * 0x8 - Side-by-Side (Half)
2333 * 0x9..0xE - Reserved for future use
2334 * 0xF - Not used */
2335 switch (format) {
2336 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2337 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2338 info_packet->sb[5] = (0x0 << 4);
2339 break;
2340
2341 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2342 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2343 info_packet->sb[5] = (0x8 << 4);
2344 length = 6;
2345 break;
2346
2347 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2348 case TIMING_3D_FORMAT_TB_SW_PACKED:
2349 info_packet->sb[5] = (0x6 << 4);
2350 break;
2351
2352 default:
2353 break;
2354 }
2355
2356 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2357 * fill PB5 with the correct HDMI VIC code */
2358 if (hdmi_vic_mode)
4fa086b9 2359 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW
2360
2361 /* Header */
3e183c5f 2362 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW
2363 info_packet->hb1 = 0x01; /* Version */
2364
2365 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2366 info_packet->hb2 = (uint8_t) (length);
2367
2368 /* Calculate checksum */
2369 checksum = 0;
2370 checksum += info_packet->hb0;
2371 checksum += info_packet->hb1;
2372 checksum += info_packet->hb2;
2373
2374 for (i = 1; i <= length; i++)
2375 checksum += info_packet->sb[i];
2376
2377 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2378
2379 info_packet->valid = true;
2380}
2381
6e4d6bee 2382static void set_spd_info_packet(
e09b6473 2383 struct dc_info_packet *info_packet,
0971c40e 2384 struct dc_stream_state *stream)
4562236b
HW
2385{
2386 /* SPD info packet for FreeSync */
2387
2388 unsigned char checksum = 0;
2389 unsigned int idx, payload_size = 0;
2390
2391 /* Check if Freesync is supported. Return if false. If true,
2392 * set the corresponding bit in the info packet
2393 */
4fa086b9 2394 if (stream->freesync_ctx.supported == false)
4562236b
HW
2395 return;
2396
2397 if (dc_is_hdmi_signal(stream->signal)) {
2398
2399 /* HEADER */
2400
2401 /* HB0 = Packet Type = 0x83 (Source Product
2402 * Descriptor InfoFrame)
2403 */
3e183c5f 2404 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW
2405
2406 /* HB1 = Version = 0x01 */
2407 info_packet->hb1 = 0x01;
2408
2409 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2410 info_packet->hb2 = 0x08;
2411
2412 payload_size = 0x08;
2413
2414 } else if (dc_is_dp_signal(stream->signal)) {
2415
2416 /* HEADER */
2417
2418 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2419 * when used to associate audio related info packets
2420 */
2421 info_packet->hb0 = 0x00;
2422
2423 /* HB1 = Packet Type = 0x83 (Source Product
2424 * Descriptor InfoFrame)
2425 */
3e183c5f 2426 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW
2427
2428 /* HB2 = [Bits 7:0 = Least significant eight bits -
2429 * For INFOFRAME, the value must be 1Bh]
2430 */
2431 info_packet->hb2 = 0x1B;
2432
2433 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2434 * [Bits 1:0 = Most significant two bits = 0x00]
2435 */
2436 info_packet->hb3 = 0x04;
2437
2438 payload_size = 0x1B;
2439 }
2440
2441 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2442 info_packet->sb[1] = 0x1A;
2443
2444 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2445 info_packet->sb[2] = 0x00;
2446
2447 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2448 info_packet->sb[3] = 0x00;
2449
2450 /* PB4 = Reserved */
2451 info_packet->sb[4] = 0x00;
2452
2453 /* PB5 = Reserved */
2454 info_packet->sb[5] = 0x00;
2455
2456 /* PB6 = [Bits 7:3 = Reserved] */
2457 info_packet->sb[6] = 0x00;
2458
4fa086b9 2459 if (stream->freesync_ctx.supported == true)
4562236b
HW
2460 /* PB6 = [Bit 0 = FreeSync Supported] */
2461 info_packet->sb[6] |= 0x01;
2462
4fa086b9 2463 if (stream->freesync_ctx.enabled == true)
4562236b
HW
2464 /* PB6 = [Bit 1 = FreeSync Enabled] */
2465 info_packet->sb[6] |= 0x02;
2466
4fa086b9 2467 if (stream->freesync_ctx.active == true)
4562236b
HW
2468 /* PB6 = [Bit 2 = FreeSync Active] */
2469 info_packet->sb[6] |= 0x04;
2470
2471 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2472 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW
2473 min_refresh_in_micro_hz / 1000000);
2474
2475 /* PB8 = FreeSync Maximum refresh rate (Hz)
2476 *
2477 * Note: We do not use the maximum capable refresh rate
2478 * of the panel, because we should never go above the field
2479 * rate of the mode timing set.
2480 */
4fa086b9 2481 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW
2482 nominal_refresh_in_micro_hz / 1000000);
2483
2484 /* PB9 - PB27 = Reserved */
2485 for (idx = 9; idx <= 27; idx++)
2486 info_packet->sb[idx] = 0x00;
2487
2488 /* Calculate checksum */
2489 checksum += info_packet->hb0;
2490 checksum += info_packet->hb1;
2491 checksum += info_packet->hb2;
2492 checksum += info_packet->hb3;
2493
2494 for (idx = 1; idx <= payload_size; idx++)
2495 checksum += info_packet->sb[idx];
2496
2497 /* PB0 = Checksum (one byte complement) */
2498 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2499
2500 info_packet->valid = true;
2501}
2502
1646a6fe 2503static void set_hdr_static_info_packet(
e09b6473 2504 struct dc_info_packet *info_packet,
0971c40e 2505 struct dc_stream_state *stream)
1646a6fe 2506{
0eeef690 2507 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2508
a10dc97a
KK
2509 if (!stream->hdr_static_metadata.valid ||
2510 stream->use_dynamic_meta)
10bff005
YS
2511 return;
2512
0eeef690 2513 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW
2514}
2515
6e4d6bee 2516static void set_vsc_info_packet(
e09b6473 2517 struct dc_info_packet *info_packet,
0971c40e 2518 struct dc_stream_state *stream)
4562236b
HW
2519{
2520 unsigned int vscPacketRevision = 0;
2521 unsigned int i;
2522
3b94a400 2523 /*VSC packet set to 2 when DP revision >= 1.2*/
85075fa0 2524 if (stream->psr_version != 0) {
4562236b
HW
2525 vscPacketRevision = 2;
2526 }
2527
2528 /* VSC packet not needed based on the features
2529 * supported by this DP display
2530 */
2531 if (vscPacketRevision == 0)
2532 return;
2533
2534 if (vscPacketRevision == 0x2) {
2535 /* Secondary-data Packet ID = 0*/
2536 info_packet->hb0 = 0x00;
2537 /* 07h - Packet Type Value indicating Video
2538 * Stream Configuration packet
2539 */
2540 info_packet->hb1 = 0x07;
2541 /* 02h = VSC SDP supporting 3D stereo and PSR
2542 * (applies to eDP v1.3 or higher).
2543 */
2544 info_packet->hb2 = 0x02;
2545 /* 08h = VSC packet supporting 3D stereo + PSR
2546 * (HB2 = 02h).
2547 */
2548 info_packet->hb3 = 0x08;
2549
2550 for (i = 0; i < 28; i++)
2551 info_packet->sb[i] = 0;
2552
2553 info_packet->valid = true;
2554 }
2555
2556 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2557}
2558
f36cc577 2559void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW
2560{
2561 int i, j;
2562
ab2541b6 2563 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW
2564 for (j = 0; j < context->stream_status[i].plane_count; j++)
2565 dc_plane_state_release(
2566 context->stream_status[i].plane_states[j]);
4562236b 2567
3be5262e 2568 context->stream_status[i].plane_count = 0;
4fa086b9 2569 dc_stream_release(context->streams[i]);
ab2541b6 2570 context->streams[i] = NULL;
4562236b
HW
2571 }
2572}
2573
2574/*
ab2541b6 2575 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW
2576 * by the src_ctx
2577 */
f36cc577 2578void dc_resource_state_copy_construct(
608ac7bb
JZ
2579 const struct dc_state *src_ctx,
2580 struct dc_state *dst_ctx)
4562236b
HW
2581{
2582 int i, j;
8ee5702a 2583 struct kref refcount = dst_ctx->refcount;
4562236b
HW
2584
2585 *dst_ctx = *src_ctx;
2586
a2b8659d 2587 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW
2588 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2589
2590 if (cur_pipe->top_pipe)
2591 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2592
2593 if (cur_pipe->bottom_pipe)
2594 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2595
2596 }
2597
ab2541b6 2598 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2599 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW
2600 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2601 dc_plane_state_retain(
2602 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2603 }
9a3afbb3
AG
2604
2605 /* context refcount should not be overridden */
8ee5702a 2606 dst_ctx->refcount = refcount;
9a3afbb3 2607
4562236b
HW
2608}
2609
2610struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC
2611 struct resource_context *res_ctx,
2612 const struct resource_pool *pool)
4562236b
HW
2613{
2614 int i;
2615
a2b8659d 2616 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2617 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2618 return pool->clock_sources[i];
4562236b
HW
2619 }
2620
2621 return NULL;
2622}
2623
2624void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2625{
2626 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2627 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW
2628
2629 /* default all packets to invalid */
6e4d6bee
TC
2630 info->avi.valid = false;
2631 info->gamut.valid = false;
2632 info->vendor.valid = false;
630e3573 2633 info->spd.valid = false;
6e4d6bee
TC
2634 info->hdrsmd.valid = false;
2635 info->vsc.valid = false;
4562236b
HW
2636
2637 signal = pipe_ctx->stream->signal;
2638
2639 /* HDMi and DP have different info packets*/
2640 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC
2641 set_avi_info_frame(&info->avi, pipe_ctx);
2642
2643 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2644
2645 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2646
56ef6ed9 2647 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2648
a33fa99d 2649 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC
2650 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2651
2652 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2653
56ef6ed9 2654 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2655 }
4562236b 2656
6e4d6bee 2657 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW
2658}
2659
2660enum dc_status resource_map_clock_resources(
fb3466a4 2661 const struct dc *dc,
608ac7bb 2662 struct dc_state *context,
1dc90497 2663 struct dc_stream_state *stream)
4562236b 2664{
4562236b 2665 /* acquire new resources */
1dc90497
AG
2666 const struct resource_pool *pool = dc->res_pool;
2667 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2668 &context->res_ctx, stream);
ab2541b6 2669
1dc90497
AG
2670 if (!pipe_ctx)
2671 return DC_ERROR_UNEXPECTED;
4562236b 2672
1dc90497
AG
2673 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2674 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2675 pipe_ctx->clock_source = pool->dp_clock_source;
2676 else {
2677 pipe_ctx->clock_source = NULL;
4562236b 2678
1dc90497 2679 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2680 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG
2681 &context->res_ctx,
2682 pipe_ctx);
4562236b 2683
1dc90497
AG
2684 if (pipe_ctx->clock_source == NULL)
2685 pipe_ctx->clock_source =
2686 dc_resource_find_first_free_pll(
2687 &context->res_ctx,
2688 pool);
2689 }
4562236b 2690
1dc90497
AG
2691 if (pipe_ctx->clock_source == NULL)
2692 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2693
1dc90497
AG
2694 resource_reference_clock_source(
2695 &context->res_ctx, pool,
2696 pipe_ctx->clock_source);
4562236b
HW
2697
2698 return DC_OK;
2699}
2700
2701/*
2702 * Note: We need to disable output if clock sources change,
2703 * since bios does optimization and doesn't apply if changing
2704 * PHY when not already disabled.
2705 */
2706bool pipe_need_reprogram(
2707 struct pipe_ctx *pipe_ctx_old,
2708 struct pipe_ctx *pipe_ctx)
2709{
cfe4645e
DL
2710 if (!pipe_ctx_old->stream)
2711 return false;
2712
4562236b
HW
2713 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2714 return true;
2715
2716 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2717 return true;
2718
afaacef4 2719 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW
2720 return true;
2721
2722 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2723 && pipe_ctx_old->stream != pipe_ctx->stream)
2724 return true;
2725
8e9c4c8c 2726 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW
2727 return true;
2728
2729 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2730 return true;
2731
6b622181
JP
2732 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2733 return true;
4562236b
HW
2734
2735 return false;
2736}
529cad0f 2737
0971c40e 2738void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW
2739 struct bit_depth_reduction_params *fmt_bit_depth)
2740{
4fa086b9 2741 enum dc_dither_option option = stream->dither_option;
529cad0f 2742 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2743 stream->timing.pixel_encoding;
529cad0f
DW
2744
2745 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2746
603767f9
TC
2747 if (option == DITHER_OPTION_DEFAULT) {
2748 switch (stream->timing.display_color_depth) {
2749 case COLOR_DEPTH_666:
2750 option = DITHER_OPTION_SPATIAL6;
2751 break;
2752 case COLOR_DEPTH_888:
2753 option = DITHER_OPTION_SPATIAL8;
2754 break;
2755 case COLOR_DEPTH_101010:
2756 option = DITHER_OPTION_SPATIAL10;
2757 break;
2758 default:
2759 option = DITHER_OPTION_DISABLE;
2760 }
2761 }
2762
529cad0f
DW
2763 if (option == DITHER_OPTION_DISABLE)
2764 return;
2765
2766 if (option == DITHER_OPTION_TRUN6) {
2767 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2768 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2769 } else if (option == DITHER_OPTION_TRUN8 ||
2770 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2771 option == DITHER_OPTION_TRUN8_FM6) {
2772 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2773 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2774 } else if (option == DITHER_OPTION_TRUN10 ||
2775 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2776 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2777 option == DITHER_OPTION_TRUN10_FM8 ||
2778 option == DITHER_OPTION_TRUN10_FM6 ||
2779 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2780 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2781 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2782 }
2783
2784 /* special case - Formatter can only reduce by 4 bits at most.
2785 * When reducing from 12 to 6 bits,
2786 * HW recommends we use trunc with round mode
2787 * (if we did nothing, trunc to 10 bits would be used)
2788 * note that any 12->10 bit reduction is ignored prior to DCE8,
2789 * as the input was 10 bits.
2790 */
2791 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2792 option == DITHER_OPTION_SPATIAL6 ||
2793 option == DITHER_OPTION_FM6) {
2794 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2795 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2796 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2797 }
2798
2799 /* spatial dither
2800 * note that spatial modes 1-3 are never used
2801 */
2802 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2803 option == DITHER_OPTION_SPATIAL6 ||
2804 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2805 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2806 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2807 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2808 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2809 fmt_bit_depth->flags.RGB_RANDOM =
2810 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2811 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2812 option == DITHER_OPTION_SPATIAL8 ||
2813 option == DITHER_OPTION_SPATIAL8_FM6 ||
2814 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2815 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2816 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2817 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2818 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2819 fmt_bit_depth->flags.RGB_RANDOM =
2820 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2821 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2822 option == DITHER_OPTION_SPATIAL10 ||
2823 option == DITHER_OPTION_SPATIAL10_FM8 ||
2824 option == DITHER_OPTION_SPATIAL10_FM6) {
2825 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2826 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2827 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2828 fmt_bit_depth->flags.RGB_RANDOM =
2829 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2830 }
2831
2832 if (option == DITHER_OPTION_SPATIAL6 ||
2833 option == DITHER_OPTION_SPATIAL8 ||
2834 option == DITHER_OPTION_SPATIAL10) {
2835 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2836 } else {
2837 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2838 }
2839
2840 //////////////////////
2841 //// temporal dither
2842 //////////////////////
2843 if (option == DITHER_OPTION_FM6 ||
2844 option == DITHER_OPTION_SPATIAL8_FM6 ||
2845 option == DITHER_OPTION_SPATIAL10_FM6 ||
2846 option == DITHER_OPTION_TRUN10_FM6 ||
2847 option == DITHER_OPTION_TRUN8_FM6 ||
2848 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2849 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2850 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2851 } else if (option == DITHER_OPTION_FM8 ||
2852 option == DITHER_OPTION_SPATIAL10_FM8 ||
2853 option == DITHER_OPTION_TRUN10_FM8) {
2854 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2855 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2856 } else if (option == DITHER_OPTION_FM10) {
2857 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2858 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2859 }
2860
2861 fmt_bit_depth->pixel_encoding = pixel_encoding;
2862}
9345d987 2863
62c933f9 2864enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2865{
fb3466a4 2866 struct dc *core_dc = dc;
4fa086b9 2867 struct dc_link *link = stream->sink->link;
9345d987
AG
2868 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2869 enum dc_status res = DC_OK;
2870
4fa086b9 2871 calculate_phy_pix_clks(stream);
9345d987 2872
4fa086b9 2873 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG
2874 res = DC_FAIL_CONTROLLER_VALIDATE;
2875
2876 if (res == DC_OK)
2877 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2878 link->link_enc, stream))
9345d987
AG
2879 res = DC_FAIL_ENC_VALIDATE;
2880
2881 /* TODO: validate audio ASIC caps, encoder */
2882
2883 if (res == DC_OK)
4fa086b9 2884 res = dc_link_validate_mode_timing(stream,
9345d987 2885 link,
4fa086b9 2886 &stream->timing);
9345d987 2887
62c933f9 2888 return res;
9345d987 2889}
792671d7 2890
62c933f9 2891enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2892{
62c933f9
YS
2893 enum dc_status res = DC_OK;
2894
792671d7 2895 /* TODO For now validates pixel format only */
8e7095b9 2896 if (dc->res_pool->funcs->validate_plane)
62c933f9 2897 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2898
62c933f9 2899 return res;
792671d7 2900}