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drm/amd/display: Add definition for number of backlight data points
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW		 44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
b86a1aa3 49#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635 52#include "dcn20/dcn20_resource.h"
e22ece54 53#include "dcn21/dcn21_resource.h"
2c8ad2d5 54#include "dce120/dce120_resource.h"
5d4b05dd
BL		 55
56#define DC_LOGGER_INIT(logger)
57
4562236b
HW		 58enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
59{
60 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
61 switch (asic_id.chip_family) {
62
63 case FAMILY_CI:
4562236b
HW		 64 dc_version = DCE_VERSION_8_0;
65 break;
ebfdf0d0
AD		 66 case FAMILY_KV:
67 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
70 dc_version = DCE_VERSION_8_3;
71 else
72 dc_version = DCE_VERSION_8_1;
73 break;
4562236b
HW		 74 case FAMILY_CZ:
75 dc_version = DCE_VERSION_11_0;
76 break;
77
78 case FAMILY_VI:
79 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
80 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
81 dc_version = DCE_VERSION_10_0;
82 break;
83 }
84 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 85 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 87 dc_version = DCE_VERSION_11_2;
88 }
0c75d5ac
JFZ		 89 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
90 dc_version = DCE_VERSION_11_22;
4562236b 91 break;
2c8ad2d5 92 case FAMILY_AI:
b8b6ce89
LL		 93 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
94 dc_version = DCE_VERSION_12_1;
95 else
96 dc_version = DCE_VERSION_12_0;
2c8ad2d5 97 break;
b86a1aa3 98#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 99 case FAMILY_RV:
100 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 101 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
102 dc_version = DCN_VERSION_1_01;
e22ece54
BL		 103 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
104 dc_version = DCN_VERSION_2_1;
ff5ef992
AD		 105 break;
106#endif
7ed4e635 107
7ed4e635
HW		 108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
4562236b
HW		 111 default:
112 dc_version = DCE_VERSION_UNKNOWN;
113 break;
114 }
115 return dc_version;
116}
117
d9673c92
HW		 118struct resource_pool *dc_create_resource_pool(struct dc *dc,
119 const struct dc_init_data *init_data,
120 enum dce_version dc_version)
4562236b 121{
5ac3d3c9 122 struct resource_pool *res_pool = NULL;
4562236b
HW		 123
124 switch (dc_version) {
125 case DCE_VERSION_8_0:
7992a629 126 res_pool = dce80_create_resource_pool(
d9673c92 127 init_data->num_virtual_links, dc);
7992a629 128 break;
ebfdf0d0 129 case DCE_VERSION_8_1:
7992a629 130 res_pool = dce81_create_resource_pool(
d9673c92 131 init_data->num_virtual_links, dc);
7992a629 132 break;
ebfdf0d0 133 case DCE_VERSION_8_3:
7992a629 134 res_pool = dce83_create_resource_pool(
d9673c92 135 init_data->num_virtual_links, dc);
5ac3d3c9 136 break;
4562236b 137 case DCE_VERSION_10_0:
5ac3d3c9 138 res_pool = dce100_create_resource_pool(
d9673c92 139 init_data->num_virtual_links, dc);
5ac3d3c9 140 break;
4562236b 141 case DCE_VERSION_11_0:
5ac3d3c9 142 res_pool = dce110_create_resource_pool(
d9673c92
HW		 143 init_data->num_virtual_links, dc,
144 init_data->asic_id);
5ac3d3c9 145 break;
4562236b 146 case DCE_VERSION_11_2:
0c75d5ac 147 case DCE_VERSION_11_22:
5ac3d3c9 148 res_pool = dce112_create_resource_pool(
d9673c92 149 init_data->num_virtual_links, dc);
5ac3d3c9 150 break;
2c8ad2d5 151 case DCE_VERSION_12_0:
b8b6ce89 152 case DCE_VERSION_12_1:
2c8ad2d5 153 res_pool = dce120_create_resource_pool(
d9673c92 154 init_data->num_virtual_links, dc);
2c8ad2d5 155 break;
ff5ef992 156
b86a1aa3 157#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 158 case DCN_VERSION_1_0:
0e3d73f1 159 case DCN_VERSION_1_01:
d9673c92 160 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 161 break;
3639fa68
ZF		 162
163
7ed4e635
HW		 164 case DCN_VERSION_2_0:
165 res_pool = dcn20_create_resource_pool(init_data, dc);
166 break;
e22ece54
BL		 167 case DCN_VERSION_2_1:
168 res_pool = dcn21_create_resource_pool(init_data, dc);
169 break;
170#endif
7ed4e635 171
4562236b
HW		 172 default:
173 break;
174 }
f49cfa27 175
5ac3d3c9 176 if (res_pool != NULL) {
9adc8050 177 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 178 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 179 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 180 /* initialize with firmware data first, no all
181 * ASIC have DCCG SW component. FPGA or
182 * simulation need initialization of
183 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
184 * with xtalin_clock_inKhz
185 */
186 res_pool->ref_clocks.dccg_ref_clock_inKhz =
187 res_pool->ref_clocks.xtalin_clock_inKhz;
188 res_pool->ref_clocks.dchub_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 } else
191 ASSERT_CRITICAL(false);
5ac3d3c9 192 }
4562236b 193
5ac3d3c9 194 return res_pool;
4562236b
HW		 195}
196
fb3466a4 197void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 198{
199 if (dc) {
200 if (dc->res_pool)
201 dc->res_pool->funcs->destroy(&dc->res_pool);
202
d029810c 203 kfree(dc->hwseq);
4562236b
HW		 204 }
205}
206
207static void update_num_audio(
208 const struct resource_straps *straps,
209 unsigned int *num_audio,
210 struct audio_support *aud_support)
211{
b8e9eb72
CL		 212 aud_support->dp_audio = true;
213 aud_support->hdmi_audio_native = false;
214 aud_support->hdmi_audio_on_dongle = false;
215
4562236b 216 if (straps->hdmi_disable == 0) {
4562236b
HW		 217 if (straps->dc_pinstraps_audio & 0x2) {
218 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 219 aud_support->hdmi_audio_native = true;
4562236b
HW		 220 }
221 }
222
223 switch (straps->audio_stream_number) {
224 case 0: /* multi streams supported */
225 break;
226 case 1: /* multi streams not supported */
227 *num_audio = 1;
228 break;
229 default:
230 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 231 }
4562236b
HW		 232}
233
234bool resource_construct(
235 unsigned int num_virtual_links,
fb3466a4 236 struct dc *dc,
4562236b
HW		 237 struct resource_pool *pool,
238 const struct resource_create_funcs *create_funcs)
239{
240 struct dc_context *ctx = dc->ctx;
241 const struct resource_caps *caps = pool->res_cap;
242 int i;
243 unsigned int num_audio = caps->num_audio;
244 struct resource_straps straps = {0};
245
246 if (create_funcs->read_dce_straps)
247 create_funcs->read_dce_straps(dc->ctx, &straps);
248
249 pool->audio_count = 0;
250 if (create_funcs->create_audio) {
251 /* find the total number of streams available via the
252 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
253 * registers (one for each pin) starting from pin 1
254 * up to the max number of audio pins.
255 * We stop on the first pin where
256 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
257 */
258 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 259 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 260 struct audio *aud = create_funcs->create_audio(ctx, i);
261
262 if (aud == NULL) {
263 DC_ERR("DC: failed to create audio!\n");
264 return false;
265 }
4562236b
HW		 266 if (!aud->funcs->endpoint_valid(aud)) {
267 aud->funcs->destroy(&aud);
268 break;
269 }
4562236b
HW		 270 pool->audios[i] = aud;
271 pool->audio_count++;
272 }
273 }
274
275 pool->stream_enc_count = 0;
276 if (create_funcs->create_stream_encoder) {
277 for (i = 0; i < caps->num_stream_encoder; i++) {
278 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
279 if (pool->stream_enc[i] == NULL)
280 DC_ERR("DC: failed to create stream_encoder!\n");
281 pool->stream_enc_count++;
282 }
283 }
929c3aaa 284
4176664b
CL		 285 dc->caps.dynamic_audio = false;
286 if (pool->audio_count < pool->stream_enc_count) {
287 dc->caps.dynamic_audio = true;
288 }
4562236b
HW		 289 for (i = 0; i < num_virtual_links; i++) {
290 pool->stream_enc[pool->stream_enc_count] =
291 virtual_stream_encoder_create(
292 ctx, ctx->dc_bios);
293 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
294 DC_ERR("DC: failed to create stream_encoder!\n");
295 return false;
296 }
297 pool->stream_enc_count++;
298 }
299
300 dc->hwseq = create_funcs->create_hwseq(ctx);
301
302 return true;
303}
ad8960a6
ML		 304static int find_matching_clock_source(
305 const struct resource_pool *pool,
306 struct clock_source *clock_source)
307{
4562236b 308
ad8960a6
ML		 309 int i;
310
311 for (i = 0; i < pool->clk_src_count; i++) {
312 if (pool->clock_sources[i] == clock_source)
313 return i;
314 }
315 return -1;
316}
4562236b 317
21e67d4d 318void resource_unreference_clock_source(
4562236b 319 struct resource_context *res_ctx,
a2b8659d 320 const struct resource_pool *pool,
4a629536 321 struct clock_source *clock_source)
4562236b 322{
ad8960a6 323 int i = find_matching_clock_source(pool, clock_source);
4562236b 324
ad8960a6 325 if (i > -1)
4562236b
HW		 326 res_ctx->clock_source_ref_count[i]--;
327
21e67d4d 328 if (pool->dp_clock_source == clock_source)
4562236b 329 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 330}
331
332void resource_reference_clock_source(
333 struct resource_context *res_ctx,
a2b8659d 334 const struct resource_pool *pool,
4562236b
HW		 335 struct clock_source *clock_source)
336{
ad8960a6 337 int i = find_matching_clock_source(pool, clock_source);
4562236b 338
ad8960a6 339 if (i > -1)
4562236b 340 res_ctx->clock_source_ref_count[i]++;
4562236b 341
a2b8659d 342 if (pool->dp_clock_source == clock_source)
4562236b
HW		 343 res_ctx->dp_clock_source_ref_count++;
344}
345
ad8960a6
ML		 346int resource_get_clock_source_reference(
347 struct resource_context *res_ctx,
348 const struct resource_pool *pool,
349 struct clock_source *clock_source)
350{
351 int i = find_matching_clock_source(pool, clock_source);
352
353 if (i > -1)
354 return res_ctx->clock_source_ref_count[i];
355
356 if (pool->dp_clock_source == clock_source)
357 return res_ctx->dp_clock_source_ref_count;
358
359 return -1;
360}
361
4562236b 362bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 363 struct dc_stream_state *stream1,
364 struct dc_stream_state *stream2)
4562236b 365{
4fa086b9 366 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 367 return false;
368
4fa086b9 369 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 370 return false;
371
4fa086b9
LSL		 372 if (stream1->timing.h_addressable
373 != stream2->timing.h_addressable)
4562236b
HW		 374 return false;
375
4fa086b9
LSL		 376 if (stream1->timing.v_addressable
377 != stream2->timing.v_addressable)
4562236b
HW		 378 return false;
379
380604e2
KC		 380 if (stream1->timing.pix_clk_100hz
381 != stream2->timing.pix_clk_100hz)
4562236b
HW		 382 return false;
383
3e27e10e
ML		 384 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
385 return false;
386
4562236b 387 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 388 && (!dc_is_dp_signal(stream1->signal)
389 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 390 return false;
391
d77f778e
CL		 392 if (stream1->view_format != stream2->view_format)
393 return false;
394
0460f9ab
JL		 395 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
396 return false;
397
4562236b
HW		 398 return true;
399}
3e27e10e
ML		 400static bool is_dp_and_hdmi_sharable(
401 struct dc_stream_state *stream1,
402 struct dc_stream_state *stream2)
403{
404 if (stream1->ctx->dc->caps.disable_dp_clk_share)
405 return false;
406
407 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 408 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 409 return false;
3e27e10e
ML		 410
411 return true;
412
413}
4562236b
HW		 414
415static bool is_sharable_clk_src(
416 const struct pipe_ctx *pipe_with_clk_src,
417 const struct pipe_ctx *pipe)
418{
419 if (pipe_with_clk_src->clock_source == NULL)
420 return false;
421
422 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
423 return false;
424
3e27e10e
ML		 425 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
426 (dc_is_dp_signal(pipe->stream->signal) &&
427 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
428 pipe->stream)))
4562236b
HW		 429 return false;
430
431 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 432 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 433 return false;
434
435 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 436 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 437 return false;
438
439 if (!resource_are_streams_timing_synchronizable(
440 pipe_with_clk_src->stream, pipe->stream))
441 return false;
442
443 return true;
444}
445
446struct clock_source *resource_find_used_clk_src_for_sharing(
447 struct resource_context *res_ctx,
448 struct pipe_ctx *pipe_ctx)
449{
450 int i;
451
452 for (i = 0; i < MAX_PIPES; i++) {
453 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
454 return res_ctx->pipe_ctx[i].clock_source;
455 }
456
457 return NULL;
458}
459
460static enum pixel_format convert_pixel_format_to_dalsurface(
461 enum surface_pixel_format surface_pixel_format)
462{
463 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
464
465 switch (surface_pixel_format) {
466 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
467 dal_pixel_format = PIXEL_FORMAT_INDEX8;
468 break;
469 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
470 dal_pixel_format = PIXEL_FORMAT_RGB565;
471 break;
472 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
473 dal_pixel_format = PIXEL_FORMAT_RGB565;
474 break;
475 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
476 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
477 break;
8693049a 478 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 479 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
480 break;
481 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
482 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
483 break;
484 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
485 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
486 break;
487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
488 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
489 break;
490 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
491 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
492 dal_pixel_format = PIXEL_FORMAT_FP16;
493 break;
494 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 495 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 496 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 497 break;
ffbcd19a
VP		 498 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
499 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 500 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 501 break;
4562236b
HW		 502 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
503 default:
504 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
505 break;
506 }
507 return dal_pixel_format;
508}
509
9b6067c0
DL		 510static inline void get_vp_scan_direction(
511 enum dc_rotation_angle rotation,
512 bool horizontal_mirror,
513 bool *orthogonal_rotation,
514 bool *flip_vert_scan_dir,
515 bool *flip_horz_scan_dir)
4562236b 516{
9b6067c0
DL		 517 *orthogonal_rotation = false;
518 *flip_vert_scan_dir = false;
519 *flip_horz_scan_dir = false;
520 if (rotation == ROTATION_ANGLE_180) {
521 *flip_vert_scan_dir = true;
522 *flip_horz_scan_dir = true;
523 } else if (rotation == ROTATION_ANGLE_90) {
524 *orthogonal_rotation = true;
525 *flip_horz_scan_dir = true;
526 } else if (rotation == ROTATION_ANGLE_270) {
527 *orthogonal_rotation = true;
528 *flip_vert_scan_dir = true;
529 }
530
531 if (horizontal_mirror)
532 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 533}
534
b2d0a103 535static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 536{
3be5262e 537 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 538 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 539 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 540 struct rect surf_src = plane_state->src_rect;
9b6067c0 541 struct rect clip, dest;
87449a90
AK		 542 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
543 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 544 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 545 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 546 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 547 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 548 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 549
7f5c22d1
VP		 550 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
551 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 552 pri_split = false;
553 sec_split = false;
554 }
86006a7f 555
4562236b
HW		 556 /* The actual clip is an intersection between stream
557 * source and surface clip
558 */
9b6067c0 559 dest = plane_state->dst_rect;
3be5262e
HW		 560 clip.x = stream->src.x > plane_state->clip_rect.x ?
561 stream->src.x : plane_state->clip_rect.x;
4562236b 562
1fbd2cfc 563 clip.width = stream->src.x + stream->src.width <
3be5262e 564 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 565 stream->src.x + stream->src.width - clip.x :
3be5262e 566 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 567
3be5262e
HW		 568 clip.y = stream->src.y > plane_state->clip_rect.y ?
569 stream->src.y : plane_state->clip_rect.y;
4562236b 570
1fbd2cfc 571 clip.height = stream->src.y + stream->src.height <
3be5262e 572 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 573 stream->src.y + stream->src.height - clip.y :
3be5262e 574 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 575
9b6067c0
DL		 576 /*
577 * Need to calculate how scan origin is shifted in vp space
578 * to correctly rotate clip and dst
579 */
580 get_vp_scan_direction(
581 plane_state->rotation,
582 plane_state->horizontal_mirror,
583 &orthogonal_rotation,
584 &flip_y_start,
585 &flip_x_start);
586
587 if (orthogonal_rotation) {
588 swap(clip.x, clip.y);
589 swap(clip.width, clip.height);
590 swap(dest.x, dest.y);
591 swap(dest.width, dest.height);
592 }
593 if (flip_x_start) {
594 clip.x = dest.x + dest.width - clip.x - clip.width;
595 dest.x = 0;
596 }
597 if (flip_y_start) {
598 clip.y = dest.y + dest.height - clip.y - clip.height;
599 dest.y = 0;
600 }
601
86006a7f 602 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 603 * num_pixels = clip.num_pix * scl_ratio
604 */
9b6067c0
DL		 605 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
606 data->viewport.width = clip.width * surf_src.width / dest.width;
607
608 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
609 data->viewport.height = clip.height * surf_src.height / dest.height;
610
611 /* Handle split */
612 if (pri_split || sec_split) {
613 if (orthogonal_rotation) {
614 if (flip_y_start != pri_split)
615 data->viewport.height /= 2;
616 else {
617 data->viewport.y += data->viewport.height / 2;
618 /* Ceil offset pipe */
619 data->viewport.height = (data->viewport.height + 1) / 2;
620 }
621 } else {
622 if (flip_x_start != pri_split)
623 data->viewport.width /= 2;
624 else {
625 data->viewport.x += data->viewport.width / 2;
626 /* Ceil offset pipe */
627 data->viewport.width = (data->viewport.width + 1) / 2;
628 }
629 }
630 }
9b5349f7 631
b2d0a103
DL		 632 /* Round down, compensate in init */
633 data->viewport_c.x = data->viewport.x / vpc_div;
634 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 635 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
636 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
637
b2d0a103
DL		 638 /* Round up, assume original video size always even dimensions */
639 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
640 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 641}
642
9b6067c0 643static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 644{
3be5262e 645 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 646 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 647 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS		 648 bool pri_split = pipe_ctx->bottom_pipe &&
649 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
650 bool sec_split = pipe_ctx->top_pipe &&
651 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 652 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 653
6702a9ac 654 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 655 if (stream->src.x < surf_clip.x)
6702a9ac 656 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 657 - stream->src.x) * stream->dst.width
658 / stream->src.width;
4562236b 659
6702a9ac 660 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 661 stream->dst.width / stream->src.width;
6702a9ac 662 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 663 stream->dst.x + stream->dst.width)
6702a9ac 664 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 665 stream->dst.x + stream->dst.width
6702a9ac 666 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 667
6702a9ac 668 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 669 if (stream->src.y < surf_clip.y)
6702a9ac 670 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 671 - stream->src.y) * stream->dst.height
672 / stream->src.height;
4562236b 673
6702a9ac 674 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 675 stream->dst.height / stream->src.height;
6702a9ac 676 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 677 stream->dst.y + stream->dst.height)
6702a9ac 678 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 679 stream->dst.y + stream->dst.height
6702a9ac 680 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 681
9b6067c0 682 /* Handle h & v split, handle rotation using viewport */
b0131391
DL		 683 if (sec_split && top_bottom_split) {
684 pipe_ctx->plane_res.scl_data.recout.y +=
685 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 686 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 687 pipe_ctx->plane_res.scl_data.recout.height =
688 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
689 } else if (pri_split && top_bottom_split)
0c31a821 690 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL		 691 else if (sec_split) {
692 pipe_ctx->plane_res.scl_data.recout.x +=
693 pipe_ctx->plane_res.scl_data.recout.width / 2;
694 /* Ceil offset pipe */
695 pipe_ctx->plane_res.scl_data.recout.width =
696 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
697 } else if (pri_split)
698 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW		 699}
700
b2d0a103 701static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 702{
3be5262e 703 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 704 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 705 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 706 const int in_w = stream->src.width;
707 const int in_h = stream->src.height;
708 const int out_w = stream->dst.width;
709 const int out_h = stream->dst.height;
4562236b 710
9b6067c0 711 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 712 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
713 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 714 swap(surf_src.height, surf_src.width);
86006a7f 715
eb0e5154 716 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 717 surf_src.width,
3be5262e 718 plane_state->dst_rect.width);
eb0e5154 719 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 720 surf_src.height,
3be5262e 721 plane_state->dst_rect.height);
4562236b 722
4fa086b9 723 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 724 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 725 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 726 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 727
6702a9ac
HW		 728 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
729 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
730 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
731 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 732
6702a9ac
HW		 733 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
734 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 735
6702a9ac
HW		 736 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
737 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
738 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
739 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 740 }
0002d3ac
DL		 741 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
742 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
743 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
744 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
745 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
746 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
747 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
748 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 749}
750
9b6067c0
DL		 751static inline void adjust_vp_and_init_for_seamless_clip(
752 bool flip_scan_dir,
753 int recout_skip,
754 int src_size,
755 int taps,
756 struct fixed31_32 ratio,
757 struct fixed31_32 *init,
758 int *vp_offset,
759 int *vp_size)
b2d0a103 760{
9b6067c0 761 if (!flip_scan_dir) {
9a08f51f 762 /* Adjust for viewport end clip-off */
9b6067c0
DL		 763 if ((*vp_offset + *vp_size) < src_size) {
764 int vp_clip = src_size - *vp_size - *vp_offset;
765 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 766
767 int_part = int_part > 0 ? int_part : 0;
9b6067c0 768 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 769 }
b2d0a103 770
9a08f51f 771 /* Adjust for non-0 viewport offset */
9b6067c0 772 if (*vp_offset) {
9a08f51f
DL		 773 int int_part;
774
9b6067c0
DL		 775 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
776 int_part = dc_fixpt_floor(*init) - *vp_offset;
777 if (int_part < taps) {
778 int int_adj = *vp_offset >= (taps - int_part) ?
779 (taps - int_part) : *vp_offset;
780 *vp_offset -= int_adj;
781 *vp_size += int_adj;
9a08f51f 782 int_part += int_adj;
9b6067c0
DL		 783 } else if (int_part > taps) {
784 *vp_offset += int_part - taps;
785 *vp_size -= int_part - taps;
786 int_part = taps;
9a08f51f 787 }
9b6067c0
DL		 788 init->value &= 0xffffffff;
789 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 790 }
791 } else {
792 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 793 if (*vp_offset) {
794 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 795
9a08f51f 796 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 797 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
798 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 799 }
b2d0a103 800
9a08f51f 801 /* Adjust for viewport end clip-off */
9b6067c0 802 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 803 int int_part;
9b6067c0 804 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 805
806 /*
807 * this is init if vp had no offset, keep in mind this is from the
808 * right side of vp due to scan direction
809 */
9b6067c0 810 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 811 /*
812 * this is the difference between first pixel of viewport available to read
813 * and init position, takning into account scan direction
814 */
9b6067c0
DL		 815 int_part = dc_fixpt_floor(*init) - end_offset;
816 if (int_part < taps) {
817 int int_adj = end_offset >= (taps - int_part) ?
818 (taps - int_part) : end_offset;
819 *vp_size += int_adj;
9a08f51f 820 int_part += int_adj;
9b6067c0
DL		 821 } else if (int_part > taps) {
822 *vp_size += int_part - taps;
823 int_part = taps;
9a08f51f 824 }
9b6067c0
DL		 825 init->value &= 0xffffffff;
826 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 827 }
b2d0a103 828 }
9b6067c0 829}
9a08f51f 830
9b6067c0
DL		 831static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
832{
833 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
834 const struct dc_stream_state *stream = pipe_ctx->stream;
835 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
836 struct rect src = pipe_ctx->plane_state->src_rect;
837 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
838 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
839 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
840 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 841
9b6067c0
DL		 842 /*
843 * Need to calculate the scan direction for viewport to make adjustments
844 */
845 get_vp_scan_direction(
846 plane_state->rotation,
847 plane_state->horizontal_mirror,
848 &orthogonal_rotation,
849 &flip_vert_scan_dir,
850 &flip_horz_scan_dir);
851
852 /* Calculate src rect rotation adjusted to recout space */
853 surf_size_h = src.x + src.width;
854 surf_size_v = src.y + src.height;
855 if (flip_horz_scan_dir)
856 src.x = 0;
857 if (flip_vert_scan_dir)
858 src.y = 0;
859 if (orthogonal_rotation) {
860 swap(src.x, src.y);
861 swap(src.width, src.height);
862 }
9a08f51f 863
9b6067c0
DL		 864 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
865 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
866 * - (surf surf_src offset * 1/ full scl ratio))
867 */
868 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
869 * stream->dst.width / stream->src.width -
870 src.x * plane_state->dst_rect.width / src.width
871 * stream->dst.width / stream->src.width);
872 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
873 * stream->dst.height / stream->src.height -
874 src.y * plane_state->dst_rect.height / src.height
875 * stream->dst.height / stream->src.height);
876 if (orthogonal_rotation)
877 swap(recout_skip_h, recout_skip_v);
878 /*
879 * Init calculated according to formula:
880 * init = (scaling_ratio + number_of_taps + 1) / 2
881 * init_bot = init + scaling_ratio
882 * init_c = init + truncated_vp_c_offset(from calculate viewport)
883 */
884 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
885 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 886
9b6067c0
DL		 887 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
888 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 889
9b6067c0
DL		 890 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
891 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 892
9b6067c0
DL		 893 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
894 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 895
9b6067c0
DL		 896 /*
897 * Taps, inits and scaling ratios are in recout space need to rotate
898 * to viewport rotation before adjustment
899 */
900 adjust_vp_and_init_for_seamless_clip(
901 flip_horz_scan_dir,
902 recout_skip_h,
903 surf_size_h,
904 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
905 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
906 orthogonal_rotation ? &data->inits.v : &data->inits.h,
907 &data->viewport.x,
908 &data->viewport.width);
909 adjust_vp_and_init_for_seamless_clip(
910 flip_horz_scan_dir,
911 recout_skip_h,
912 surf_size_h / vpc_div,
913 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
914 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
915 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
916 &data->viewport_c.x,
917 &data->viewport_c.width);
918 adjust_vp_and_init_for_seamless_clip(
919 flip_vert_scan_dir,
920 recout_skip_v,
921 surf_size_v,
922 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
923 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
924 orthogonal_rotation ? &data->inits.h : &data->inits.v,
925 &data->viewport.y,
926 &data->viewport.height);
927 adjust_vp_and_init_for_seamless_clip(
928 flip_vert_scan_dir,
929 recout_skip_v,
930 surf_size_v / vpc_div,
931 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
932 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
933 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
934 &data->viewport_c.y,
935 &data->viewport_c.height);
b2d0a103
DL		 936
937 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 938 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
939 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 940
b2d0a103 941}
3b733278 942
663bfef0
AY		 943static bool is_downscaled(const struct rect *src_rect, const struct rect *dst_rect)
944{
945 if (src_rect->width > dst_rect->width || src_rect->height > dst_rect->height)
946 return true;
947 return false;
948}
949
950static bool is_mpo(int layer_index)
951{
952 if (layer_index > 0)
953 return true;
954 return false;
955}
956
4ef0b9d0 957static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
3b733278 958{
00ada9d1 959 unsigned int integer_multiple = 1;
3b733278 960
663bfef0
AY		 961 if (pipe_ctx->plane_state->scaling_quality.integer_scaling &&
962 !is_downscaled(&pipe_ctx->plane_state->src_rect, &pipe_ctx->plane_state->dst_rect) &&
963 !is_mpo(pipe_ctx->plane_state->layer_index)) {
3b733278 964 // calculate maximum # of replication of src onto addressable
00ada9d1 965 integer_multiple = min(
3b733278
RA		 966 pipe_ctx->stream->timing.h_addressable / pipe_ctx->stream->src.width,
967 pipe_ctx->stream->timing.v_addressable / pipe_ctx->stream->src.height);
968
969 //scale dst
970 pipe_ctx->stream->dst.width = integer_multiple * pipe_ctx->stream->src.width;
971 pipe_ctx->stream->dst.height = integer_multiple * pipe_ctx->stream->src.height;
972
973 //center dst onto addressable
974 pipe_ctx->stream->dst.x = (pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
975 pipe_ctx->stream->dst.y = (pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
3b733278 976
00ada9d1 977 //We are guaranteed that we are scaling in integer ratio
3b733278
RA		 978 pipe_ctx->plane_state->scaling_quality.v_taps = 1;
979 pipe_ctx->plane_state->scaling_quality.h_taps = 1;
980 pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
981 pipe_ctx->plane_state->scaling_quality.h_taps_c = 1;
982 }
983}
984
b2d0a103 985bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 986{
3be5262e 987 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 988 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 989 bool res = false;
5d4b05dd 990 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 991 /* Important: scaling ratio calculation requires pixel format,
992 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 993 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 994 */
6702a9ac 995 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 996 pipe_ctx->plane_state->format);
b2d0a103 997
3b733278
RA		 998 calculate_integer_scaling(pipe_ctx);
999
b2d0a103 1000 calculate_scaling_ratios(pipe_ctx);
4562236b 1001
b2d0a103 1002 calculate_viewport(pipe_ctx);
4562236b 1003
6702a9ac 1004 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 1005 return false;
1006
9b6067c0 1007 calculate_recout(pipe_ctx);
4562236b
HW		 1008
1009 /**
1010 * Setting line buffer pixel depth to 24bpp yields banding
1011 * on certain displays, such as the Sharp 4k
1012 */
6702a9ac 1013 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 1014
199e458a 1015 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1016 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1017
58bb0e63
AJ		 1018 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
1019 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 1020
4562236b 1021 /* Taps calculations */
d94585a0
YHL		 1022 if (pipe_ctx->plane_res.xfm != NULL)
1023 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1024 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1025
1026 if (pipe_ctx->plane_res.dpp != NULL)
1027 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1028 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1029
f7938bc0 1030
4562236b
HW		 1031 if (!res) {
1032 /* Try 24 bpp linebuffer */
6702a9ac 1033 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1034
1b6c8067
BL		 1035 if (pipe_ctx->plane_res.xfm != NULL)
1036 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1037 pipe_ctx->plane_res.xfm,
1038 &pipe_ctx->plane_res.scl_data,
1039 &plane_state->scaling_quality);
1040
1041 if (pipe_ctx->plane_res.dpp != NULL)
1042 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1043 pipe_ctx->plane_res.dpp,
1044 &pipe_ctx->plane_res.scl_data,
1045 &plane_state->scaling_quality);
4562236b
HW		 1046 }
1047
b2d0a103 1048 if (res)
1fbd2cfc 1049 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1050 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1051
1296423b 1052 DC_LOG_SCALER(
4562236b
HW		 1053 "%s: Viewport:\nheight:%d width:%d x:%d "
1054 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1055 "y:%d\n",
1056 __func__,
6702a9ac
HW		 1057 pipe_ctx->plane_res.scl_data.viewport.height,
1058 pipe_ctx->plane_res.scl_data.viewport.width,
1059 pipe_ctx->plane_res.scl_data.viewport.x,
1060 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 1061 plane_state->dst_rect.height,
1062 plane_state->dst_rect.width,
1063 plane_state->dst_rect.x,
1064 plane_state->dst_rect.y);
4562236b
HW		 1065
1066 return res;
1067}
1068
1069
1070enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1071 const struct dc *dc,
608ac7bb 1072 struct dc_state *context)
4562236b
HW		 1073{
1074 int i;
1075
1076 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1077 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1078 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1079 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1080 return DC_FAIL_SCALING;
4562236b
HW		 1081 }
1082
1083 return DC_OK;
1084}
1085
a2b8659d
TC		 1086struct pipe_ctx *find_idle_secondary_pipe(
1087 struct resource_context *res_ctx,
5581192d
JL		 1088 const struct resource_pool *pool,
1089 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1090{
1091 int i;
1092 struct pipe_ctx *secondary_pipe = NULL;
1093
1094 /*
5581192d
JL		 1095 * We add a preferred pipe mapping to avoid the chance that
1096 * MPCCs already in use will need to be reassigned to other trees.
1097 * For example, if we went with the strict, assign backwards logic:
1098 *
1099 * (State 1)
1100 * Display A on, no surface, top pipe = 0
1101 * Display B on, no surface, top pipe = 1
1102 *
1103 * (State 2)
1104 * Display A on, no surface, top pipe = 0
1105 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1106 *
1107 * (State 3)
1108 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1109 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1110 *
1111 * The state 2->3 transition requires remapping MPCC 5 from display B
1112 * to display A.
1113 *
1114 * However, with the preferred pipe logic, state 2 would look like:
1115 *
1116 * (State 2)
1117 * Display A on, no surface, top pipe = 0
1118 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1119 *
1120 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1121 */
5581192d
JL		 1122 if (primary_pipe) {
1123 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1124 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1125 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1126 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1127 }
1128 }
1129
5581192d
JL		 1130 /*
1131 * search backwards for the second pipe to keep pipe
1132 * assignment more consistent
1133 */
1134 if (!secondary_pipe)
1135 for (i = pool->pipe_count - 1; i >= 0; i--) {
1136 if (res_ctx->pipe_ctx[i].stream == NULL) {
1137 secondary_pipe = &res_ctx->pipe_ctx[i];
1138 secondary_pipe->pipe_idx = i;
1139 break;
1140 }
1141 }
4562236b
HW		 1142
1143 return secondary_pipe;
1144}
1145
1146struct pipe_ctx *resource_get_head_pipe_for_stream(
1147 struct resource_context *res_ctx,
0971c40e 1148 struct dc_stream_state *stream)
4562236b
HW		 1149{
1150 int i;
22498036 1151
a2b8659d 1152 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL		 1153 if (res_ctx->pipe_ctx[i].stream == stream
1154 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1155 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1156 return &res_ctx->pipe_ctx[i];
4562236b
HW		 1157 }
1158 return NULL;
1159}
1160
b1f6d01c 1161static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1162 struct resource_context *res_ctx,
b1f6d01c 1163 struct pipe_ctx *head_pipe)
19f89e23 1164{
b1f6d01c 1165 struct pipe_ctx *tail_pipe;
19f89e23
AG		 1166
1167 tail_pipe = head_pipe->bottom_pipe;
1168
1169 while (tail_pipe) {
1170 head_pipe = tail_pipe;
1171 tail_pipe = tail_pipe->bottom_pipe;
1172 }
1173
1174 return head_pipe;
1175}
1176
4562236b 1177/*
ab2541b6
AC		 1178 * A free_pipe for a stream is defined here as a pipe
1179 * that has no surface attached yet
4562236b 1180 */
b1f6d01c 1181static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1182 struct dc_state *context,
a2b8659d 1183 const struct resource_pool *pool,
b1f6d01c 1184 struct pipe_ctx *head_pipe)
4562236b
HW		 1185{
1186 int i;
745cc746 1187 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1188
3be5262e 1189 if (!head_pipe->plane_state)
4562236b
HW		 1190 return head_pipe;
1191
1192 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1193 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1194 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1195 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1196 return &res_ctx->pipe_ctx[i];
1197 }
1198 }
1199
1200 /*
1201 * At this point we have no re-useable pipe for this stream and we need
1202 * to acquire an idle one to satisfy the request
1203 */
1204
a2b8659d 1205 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1206 return NULL;
1207
b1f6d01c 1208 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW		 1209}
1210
b86a1aa3 1211#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL		 1212static int acquire_first_split_pipe(
1213 struct resource_context *res_ctx,
1214 const struct resource_pool *pool,
0971c40e 1215 struct dc_stream_state *stream)
0f9a536f
DL		 1216{
1217 int i;
1218
1219 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1220 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1221
b1f6d01c 1222 if (split_pipe->top_pipe &&
79592db3
DL		 1223 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1224 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1225 if (split_pipe->bottom_pipe)
1226 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1227
1228 if (split_pipe->top_pipe->plane_state)
1229 resource_build_scaling_params(split_pipe->top_pipe);
1230
1231 memset(split_pipe, 0, sizeof(*split_pipe));
1232 split_pipe->stream_res.tg = pool->timing_generators[i];
1233 split_pipe->plane_res.hubp = pool->hubps[i];
1234 split_pipe->plane_res.ipp = pool->ipps[i];
1235 split_pipe->plane_res.dpp = pool->dpps[i];
1236 split_pipe->stream_res.opp = pool->opps[i];
1237 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1238 split_pipe->pipe_idx = i;
1239
1240 split_pipe->stream = stream;
0f9a536f
DL		 1241 return i;
1242 }
1243 }
1244 return -1;
1245}
1246#endif
1247
19f89e23
AG		 1248bool dc_add_plane_to_context(
1249 const struct dc *dc,
0971c40e 1250 struct dc_stream_state *stream,
19f89e23 1251 struct dc_plane_state *plane_state,
608ac7bb 1252 struct dc_state *context)
4562236b
HW		 1253{
1254 int i;
19f89e23
AG		 1255 struct resource_pool *pool = dc->res_pool;
1256 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1257 struct dc_stream_status *stream_status = NULL;
4562236b 1258
19f89e23
AG		 1259 for (i = 0; i < context->stream_count; i++)
1260 if (context->streams[i] == stream) {
1261 stream_status = &context->stream_status[i];
1262 break;
1263 }
1264 if (stream_status == NULL) {
1265 dm_error("Existing stream not found; failed to attach surface!\n");
1266 return false;
1267 }
1268
4562236b 1269
19f89e23
AG		 1270 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1271 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1272 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1273 return false;
1274 }
1275
19f89e23
AG		 1276 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1277
1278 if (!head_pipe) {
1279 dm_error("Head pipe not found for stream_state %p !\n", stream);
1280 return false;
1281 }
1282
b1f6d01c
DL		 1283 /* retain new surface, but only once per stream */
1284 dc_plane_state_retain(plane_state);
00737c59 1285
b1f6d01c
DL		 1286 while (head_pipe) {
1287 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1288 ASSERT(tail_pipe);
19f89e23 1289
b1f6d01c 1290 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1291
b86a1aa3 1292 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL		 1293 if (!free_pipe) {
1294 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1295 if (pipe_idx >= 0)
1296 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1297 }
1298 #endif
1299 if (!free_pipe) {
1300 dc_plane_state_release(plane_state);
1301 return false;
1302 }
19f89e23 1303
b1f6d01c
DL		 1304 free_pipe->plane_state = plane_state;
1305
1306 if (head_pipe != free_pipe) {
1307 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1308 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1309 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1310 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1311 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1312 free_pipe->clock_source = tail_pipe->clock_source;
1313 free_pipe->top_pipe = tail_pipe;
1314 tail_pipe->bottom_pipe = free_pipe;
1315 }
1316 head_pipe = head_pipe->next_odm_pipe;
1317 }
19f89e23
AG		 1318 /* assign new surfaces*/
1319 stream_status->plane_states[stream_status->plane_count] = plane_state;
1320
1321 stream_status->plane_count++;
1322
1323 return true;
1324}
1325
1326bool dc_remove_plane_from_context(
1327 const struct dc *dc,
1328 struct dc_stream_state *stream,
1329 struct dc_plane_state *plane_state,
608ac7bb 1330 struct dc_state *context)
19f89e23
AG		 1331{
1332 int i;
1333 struct dc_stream_status *stream_status = NULL;
1334 struct resource_pool *pool = dc->res_pool;
1335
ab2541b6 1336 for (i = 0; i < context->stream_count; i++)
4fa086b9 1337 if (context->streams[i] == stream) {
ab2541b6 1338 stream_status = &context->stream_status[i];
4562236b
HW		 1339 break;
1340 }
19f89e23 1341
ab2541b6 1342 if (stream_status == NULL) {
19f89e23 1343 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1344 return false;
1345 }
1346
19f89e23
AG		 1347 /* release pipe for plane*/
1348 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1349 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1350
6ffaa6fc 1351 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG		 1352 if (pipe_ctx->top_pipe)
1353 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1354
19f89e23
AG		 1355 /* Second condition is to avoid setting NULL to top pipe
1356 * of tail pipe making it look like head pipe in subsequent
1357 * deletes
1358 */
1359 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1360 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1361
19f89e23
AG		 1362 /*
1363 * For head pipe detach surfaces from pipe for tail
1364 * pipe just zero it out
1365 */
b1f6d01c 1366 if (!pipe_ctx->top_pipe)
19f89e23 1367 pipe_ctx->plane_state = NULL;
b1f6d01c 1368 else
19f89e23 1369 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1370 }
19f89e23 1371 }
4562236b 1372
4562236b 1373
19f89e23
AG		 1374 for (i = 0; i < stream_status->plane_count; i++) {
1375 if (stream_status->plane_states[i] == plane_state) {
1376
1377 dc_plane_state_release(stream_status->plane_states[i]);
1378 break;
4562236b 1379 }
19f89e23 1380 }
4562236b 1381
19f89e23
AG		 1382 if (i == stream_status->plane_count) {
1383 dm_error("Existing plane_state not found; failed to detach it!\n");
1384 return false;
4562236b
HW		 1385 }
1386
19f89e23 1387 stream_status->plane_count--;
4562236b 1388
abb4986e
AJ		 1389 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1390 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1391 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1392
1393 stream_status->plane_states[stream_status->plane_count] = NULL;
1394
1395 return true;
1396}
1397
1398bool dc_rem_all_planes_for_stream(
1399 const struct dc *dc,
1400 struct dc_stream_state *stream,
608ac7bb 1401 struct dc_state *context)
19f89e23
AG		 1402{
1403 int i, old_plane_count;
1404 struct dc_stream_status *stream_status = NULL;
1405 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1406
1407 for (i = 0; i < context->stream_count; i++)
1408 if (context->streams[i] == stream) {
1409 stream_status = &context->stream_status[i];
1410 break;
1411 }
1412
1413 if (stream_status == NULL) {
1414 dm_error("Existing stream %p not found!\n", stream);
1415 return false;
1416 }
1417
1418 old_plane_count = stream_status->plane_count;
1419
1420 for (i = 0; i < old_plane_count; i++)
1421 del_planes[i] = stream_status->plane_states[i];
1422
1423 for (i = 0; i < old_plane_count; i++)
1424 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1425 return false;
1426
1427 return true;
1428}
1429
1430static bool add_all_planes_for_stream(
1431 const struct dc *dc,
1432 struct dc_stream_state *stream,
1433 const struct dc_validation_set set[],
1434 int set_count,
608ac7bb 1435 struct dc_state *context)
19f89e23
AG		 1436{
1437 int i, j;
1438
1439 for (i = 0; i < set_count; i++)
1440 if (set[i].stream == stream)
1441 break;
1442
1443 if (i == set_count) {
1444 dm_error("Stream %p not found in set!\n", stream);
1445 return false;
1446 }
4562236b 1447
19f89e23
AG		 1448 for (j = 0; j < set[i].plane_count; j++)
1449 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1450 return false;
4562236b
HW		 1451
1452 return true;
1453}
1454
19f89e23
AG		 1455bool dc_add_all_planes_for_stream(
1456 const struct dc *dc,
1457 struct dc_stream_state *stream,
1458 struct dc_plane_state * const *plane_states,
1459 int plane_count,
608ac7bb 1460 struct dc_state *context)
19f89e23
AG		 1461{
1462 struct dc_validation_set set;
1463 int i;
1464
1465 set.stream = stream;
1466 set.plane_count = plane_count;
1467
1468 for (i = 0; i < plane_count; i++)
1469 set.plane_states[i] = plane_states[i];
1470
1471 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1472}
1473
1474
6b622181
JP		 1475static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1476 struct dc_stream_state *new_stream)
1477{
1478 if (cur_stream == NULL)
1479 return true;
1480
1481 if (memcmp(&cur_stream->hdr_static_metadata,
1482 &new_stream->hdr_static_metadata,
1483 sizeof(struct dc_info_packet)) != 0)
1484 return true;
1485
1486 return false;
1487}
4562236b 1488
1336926f
A		 1489static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1490 struct dc_stream_state *new_stream)
1491{
1492 if (cur_stream == NULL)
1493 return true;
1494
1495 if (memcmp(&cur_stream->vsc_infopacket,
1496 &new_stream->vsc_infopacket,
1497 sizeof(struct dc_info_packet)) != 0)
1498 return true;
1499
1500 return false;
1501}
1502
0971c40e
HW		 1503static bool is_timing_changed(struct dc_stream_state *cur_stream,
1504 struct dc_stream_state *new_stream)
4562236b
HW		 1505{
1506 if (cur_stream == NULL)
1507 return true;
1508
1509 /* If sink pointer changed, it means this is a hotplug, we should do
1510 * full hw setting.
1511 */
1512 if (cur_stream->sink != new_stream->sink)
1513 return true;
1514
1515 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1516 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1517 return true;
1518
1519 return memcmp(
4fa086b9
LSL		 1520 &cur_stream->timing,
1521 &new_stream->timing,
4562236b
HW		 1522 sizeof(struct dc_crtc_timing)) != 0;
1523}
1524
1525static bool are_stream_backends_same(
0971c40e 1526 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1527{
1528 if (stream_a == stream_b)
1529 return true;
1530
1531 if (stream_a == NULL || stream_b == NULL)
1532 return false;
1533
1534 if (is_timing_changed(stream_a, stream_b))
1535 return false;
1536
6b622181
JP		 1537 if (is_hdr_static_meta_changed(stream_a, stream_b))
1538 return false;
1539
1e7e86c4
ST		 1540 if (stream_a->dpms_off != stream_b->dpms_off)
1541 return false;
1542
1336926f
A		 1543 if (is_vsc_info_packet_changed(stream_a, stream_b))
1544 return false;
1545
4562236b
HW		 1546 return true;
1547}
1548
2119aa17
DF		 1549/**
1550 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1551 *
1552 * Checks if there a difference between the two states
1553 * that would require a mode change.
1554 *
1555 * Does not compare cursor position or attributes.
1556 */
d54d29db 1557bool dc_is_stream_unchanged(
0971c40e 1558 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1559{
4562236b 1560
ab2541b6
AC		 1561 if (!are_stream_backends_same(old_stream, stream))
1562 return false;
4562236b 1563
0460f9ab
JL		 1564 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1565 return false;
1566
4562236b
HW		 1567 return true;
1568}
1569
2119aa17
DF		 1570/**
1571 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1572 */
9a5d9c48
LSL		 1573bool dc_is_stream_scaling_unchanged(
1574 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1575{
1576 if (old_stream == stream)
1577 return true;
1578
1579 if (old_stream == NULL || stream == NULL)
1580 return false;
1581
1582 if (memcmp(&old_stream->src,
1583 &stream->src,
1584 sizeof(struct rect)) != 0)
1585 return false;
1586
1587 if (memcmp(&old_stream->dst,
1588 &stream->dst,
1589 sizeof(struct rect)) != 0)
1590 return false;
1591
1592 return true;
1593}
1594
1dc90497 1595static void update_stream_engine_usage(
4562236b 1596 struct resource_context *res_ctx,
a2b8659d 1597 const struct resource_pool *pool,
1dc90497
AG		 1598 struct stream_encoder *stream_enc,
1599 bool acquired)
4562236b
HW		 1600{
1601 int i;
1602
a2b8659d
TC		 1603 for (i = 0; i < pool->stream_enc_count; i++) {
1604 if (pool->stream_enc[i] == stream_enc)
1dc90497 1605 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1606 }
1607}
1608
1609/* TODO: release audio object */
4176664b 1610void update_audio_usage(
4562236b 1611 struct resource_context *res_ctx,
a2b8659d 1612 const struct resource_pool *pool,
1dc90497
AG		 1613 struct audio *audio,
1614 bool acquired)
4562236b
HW		 1615{
1616 int i;
a2b8659d
TC		 1617 for (i = 0; i < pool->audio_count; i++) {
1618 if (pool->audios[i] == audio)
1dc90497 1619 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1620 }
1621}
1622
1623static int acquire_first_free_pipe(
1624 struct resource_context *res_ctx,
a2b8659d 1625 const struct resource_pool *pool,
0971c40e 1626 struct dc_stream_state *stream)
4562236b
HW		 1627{
1628 int i;
1629
a2b8659d 1630 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1631 if (!res_ctx->pipe_ctx[i].stream) {
1632 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1633
6b670fa9 1634 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1635 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1636 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1637 pipe_ctx->plane_res.ipp = pool->ipps[i];
1638 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1639 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1640 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1641 if (pool->dpps[i])
1642 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1643 pipe_ctx->pipe_idx = i;
1644
ff5ef992 1645
4562236b
HW		 1646 pipe_ctx->stream = stream;
1647 return i;
1648 }
1649 }
1650 return -1;
1651}
1652
a2b8659d
TC		 1653static struct audio *find_first_free_audio(
1654 struct resource_context *res_ctx,
cfb071f7 1655 const struct resource_pool *pool,
f24b0522
PH		 1656 enum engine_id id,
1657 enum dce_version dc_version)
4562236b 1658{
b5a41620
CL		 1659 int i, available_audio_count;
1660
1661 available_audio_count = pool->audio_count;
1662
1663 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1664 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1665 /*we have enough audio endpoint, find the matching inst*/
1666 if (id != i)
1667 continue;
66bfd4fd 1668 return pool->audios[i];
4562236b 1669 }
66bfd4fd 1670 }
5feb9f07 1671
b5a41620
CL		 1672 /* use engine id to find free audio */
1673 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM		 1674 return pool->audios[id];
1675 }
66bfd4fd 1676 /*not found the matching one, first come first serve*/
b5a41620 1677 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL		 1678 if (res_ctx->is_audio_acquired[i] == false) {
1679 return pool->audios[i];
4176664b
CL		 1680 }
1681 }
4562236b
HW		 1682 return 0;
1683}
1684
4562236b 1685bool resource_is_stream_unchanged(
608ac7bb 1686 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1687{
ab2541b6 1688 int i;
4562236b 1689
ab2541b6 1690 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1691 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1692
ab2541b6 1693 if (are_stream_backends_same(old_stream, stream))
4562236b 1694 return true;
4562236b
HW		 1695 }
1696
1697 return false;
1698}
1699
2119aa17
DF		 1700/**
1701 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1702 */
13ab1b44 1703enum dc_status dc_add_stream_to_ctx(
1dc90497 1704 struct dc *dc,
608ac7bb 1705 struct dc_state *new_ctx,
1dc90497
AG		 1706 struct dc_stream_state *stream)
1707{
1dc90497 1708 enum dc_status res;
eb9714a2 1709 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1710
ece4147f 1711 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1712 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1713 return DC_ERROR_UNEXPECTED;
1714 }
1715
1716 new_ctx->streams[new_ctx->stream_count] = stream;
1717 dc_stream_retain(stream);
1718 new_ctx->stream_count++;
1719
1720 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1721 if (res != DC_OK)
eb9714a2 1722 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1723
13ab1b44 1724 return res;
1dc90497
AG		 1725}
1726
2119aa17
DF		 1727/**
1728 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1729 */
62c933f9 1730enum dc_status dc_remove_stream_from_ctx(
1dc90497 1731 struct dc *dc,
608ac7bb 1732 struct dc_state *new_ctx,
1dc90497
AG		 1733 struct dc_stream_state *stream)
1734{
19f89e23 1735 int i;
1dc90497 1736 struct dc_context *dc_ctx = dc->ctx;
22498036
DL		 1737 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1738 struct pipe_ctx *odm_pipe;
1dc90497
AG		 1739
1740 if (!del_pipe) {
1741 DC_ERROR("Pipe not found for stream %p !\n", stream);
1742 return DC_ERROR_UNEXPECTED;
1743 }
1744
22498036
DL		 1745 odm_pipe = del_pipe->next_odm_pipe;
1746
1747 /* Release primary pipe */
1748 ASSERT(del_pipe->stream_res.stream_enc);
1749 update_stream_engine_usage(
1750 &new_ctx->res_ctx,
1751 dc->res_pool,
1752 del_pipe->stream_res.stream_enc,
1753 false);
1754
1755 if (del_pipe->stream_res.audio)
1756 update_audio_usage(
1757 &new_ctx->res_ctx,
1758 dc->res_pool,
1759 del_pipe->stream_res.audio,
1760 false);
1761
1762 resource_unreference_clock_source(&new_ctx->res_ctx,
1763 dc->res_pool,
1764 del_pipe->clock_source);
1765
1766 if (dc->res_pool->funcs->remove_stream_from_ctx)
1767 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1768
1769 while (odm_pipe) {
1770 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1771
1772 memset(odm_pipe, 0, sizeof(*odm_pipe));
1773 odm_pipe = next_odm_pipe;
1774 }
1775 memset(del_pipe, 0, sizeof(*del_pipe));
1776
1dc90497
AG		 1777 for (i = 0; i < new_ctx->stream_count; i++)
1778 if (new_ctx->streams[i] == stream)
1779 break;
1780
1781 if (new_ctx->streams[i] != stream) {
1782 DC_ERROR("Context doesn't have stream %p !\n", stream);
1783 return DC_ERROR_UNEXPECTED;
1784 }
1785
1786 dc_stream_release(new_ctx->streams[i]);
1787 new_ctx->stream_count--;
1788
1dc90497
AG		 1789 /* Trim back arrays */
1790 for (; i < new_ctx->stream_count; i++) {
1791 new_ctx->streams[i] = new_ctx->streams[i + 1];
1792 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1793 }
1794
1795 new_ctx->streams[new_ctx->stream_count] = NULL;
1796 memset(
1797 &new_ctx->stream_status[new_ctx->stream_count],
1798 0,
1799 sizeof(new_ctx->stream_status[0]));
1800
1801 return DC_OK;
1802}
1803
0971c40e
HW		 1804static struct dc_stream_state *find_pll_sharable_stream(
1805 struct dc_stream_state *stream_needs_pll,
608ac7bb 1806 struct dc_state *context)
4562236b 1807{
ab2541b6 1808 int i;
4562236b 1809
ab2541b6 1810 for (i = 0; i < context->stream_count; i++) {
0971c40e 1811 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1812
ab2541b6
AC		 1813 /* We are looking for non dp, non virtual stream */
1814 if (resource_are_streams_timing_synchronizable(
1815 stream_needs_pll, stream_has_pll)
1816 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1817 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1818 != SIGNAL_TYPE_VIRTUAL)
1819 return stream_has_pll;
4562236b 1820
4562236b
HW		 1821 }
1822
1823 return NULL;
1824}
1825
1826static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1827{
380604e2 1828 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1829 uint32_t normalized_pix_clk = pix_clk;
1830
1831 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1832 pix_clk /= 2;
cc4d99b8
CL		 1833 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1834 switch (timing->display_color_depth) {
8897810a 1835 case COLOR_DEPTH_666:
cc4d99b8
CL		 1836 case COLOR_DEPTH_888:
1837 normalized_pix_clk = pix_clk;
1838 break;
1839 case COLOR_DEPTH_101010:
1840 normalized_pix_clk = (pix_clk * 30) / 24;
1841 break;
1842 case COLOR_DEPTH_121212:
1843 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1844 break;
cc4d99b8
CL		 1845 case COLOR_DEPTH_161616:
1846 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1847 break;
cc4d99b8
CL		 1848 default:
1849 ASSERT(0);
4562236b 1850 break;
cc4d99b8 1851 }
4562236b 1852 }
4562236b
HW		 1853 return normalized_pix_clk;
1854}
1855
0971c40e 1856static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1857{
9345d987
AG		 1858 /* update actual pixel clock on all streams */
1859 if (dc_is_hdmi_signal(stream->signal))
1860 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1861 &stream->timing) / 10;
9345d987
AG		 1862 else
1863 stream->phy_pix_clk =
380604e2 1864 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1865
1866 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1867 stream->phy_pix_clk *= 2;
4562236b
HW		 1868}
1869
d2d7885f
AK		 1870static int acquire_resource_from_hw_enabled_state(
1871 struct resource_context *res_ctx,
1872 const struct resource_pool *pool,
1873 struct dc_stream_state *stream)
1874{
1875 struct dc_link *link = stream->link;
08b66279 1876 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK		 1877
1878 /* Check for enabled DIG to identify enabled display */
1879 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1880 return -1;
1881
5ec43eda 1882 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 1883
7f7652ee 1884 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 1885 return -1;
d2d7885f 1886
7f7652ee
ML		 1887 for (i = 0; i < pool->stream_enc_count; i++) {
1888 if (pool->stream_enc[i]->id == inst) {
1889 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
1890 pool->stream_enc[i]);
1891 break;
1892 }
1893 }
5ec43eda 1894
7f7652ee
ML		 1895 // tg_inst not found
1896 if (i == pool->stream_enc_count)
75441d9d 1897 return -1;
5ec43eda
ML		 1898
1899 if (tg_inst >= pool->timing_generator_count)
75441d9d 1900 return -1;
5ec43eda
ML		 1901
1902 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1903 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1904
1905 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1906 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1907 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1908 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1909 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1910 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1911 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1912
5ec43eda
ML		 1913 if (pool->dpps[tg_inst])
1914 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
1915 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK		 1916
1917 pipe_ctx->stream = stream;
5ec43eda 1918 return tg_inst;
d2d7885f
AK		 1919 }
1920
1921 return -1;
1922}
1923
4562236b 1924enum dc_status resource_map_pool_resources(
fb3466a4 1925 const struct dc *dc,
608ac7bb 1926 struct dc_state *context,
1dc90497 1927 struct dc_stream_state *stream)
4562236b 1928{
a2b8659d 1929 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1930 int i;
1931 struct dc_context *dc_ctx = dc->ctx;
1932 struct pipe_ctx *pipe_ctx = NULL;
1933 int pipe_idx = -1;
46570f09 1934 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1935
1dc90497
AG		 1936 /* TODO Check if this is needed */
1937 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1938 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1939 stream->bit_depth_params =
430ef426
DL		 1940 old_context->streams[i]->bit_depth_params;
1941 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1942 continue;
1943 }
4b679bc3 1944 }
1dc90497 1945 */
7e2fe319 1946
08e1c28d
YMM		 1947 calculate_phy_pix_clks(stream);
1948
46570f09
AK		 1949 /* TODO: Check Linux */
1950 if (dc->config.allow_seamless_boot_optimization &&
1951 !dcb->funcs->is_accelerated_mode(dcb)) {
1952 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1953 stream->apply_seamless_boot_optimization = true;
1954 }
1955
d2d7885f
AK		 1956 if (stream->apply_seamless_boot_optimization)
1957 pipe_idx = acquire_resource_from_hw_enabled_state(
1958 &context->res_ctx,
1959 pool,
1960 stream);
1961
1962 if (pipe_idx < 0)
1963 /* acquire new resources */
1964 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1965
b86a1aa3 1966#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 1967 if (pipe_idx < 0)
13ab1b44 1968 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1969#endif
13ab1b44 1970
c5b38aec 1971 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1972 return DC_NO_CONTROLLER_RESOURCE;
1973
1974 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1975
1976 pipe_ctx->stream_res.stream_enc =
78cc70b1 1977 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 1978 &context->res_ctx, pool, stream);
1979
1980 if (!pipe_ctx->stream_res.stream_enc)
38684e46 1981 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 1982
1983 update_stream_engine_usage(
1984 &context->res_ctx, pool,
1985 pipe_ctx->stream_res.stream_enc,
1986 true);
1987
1988 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 1989 if (!stream->converter_disable_audio &&
1dc90497 1990 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 1991 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 1992 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 1993 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG		 1994
1995 /*
1996 * Audio assigned in order first come first get.
1997 * There are asics which has number of audio
1998 * resources less then number of pipes
1999 */
2000 if (pipe_ctx->stream_res.audio)
2001 update_audio_usage(&context->res_ctx, pool,
2002 pipe_ctx->stream_res.audio, true);
2003 }
268cadbd 2004
9aef1a31
S		 2005 /* Add ABM to the resource if on EDP */
2006 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2007 pipe_ctx->stream_res.abm = pool->abm;
2008
1dc90497
AG		 2009 for (i = 0; i < context->stream_count; i++)
2010 if (context->streams[i] == stream) {
2011 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 2012 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
5fdb7c4c
NK		 2013 context->stream_status[i].audio_inst =
2014 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2015
1dc90497
AG		 2016 return DC_OK;
2017 }
4562236b 2018
1dc90497
AG		 2019 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2020 return DC_ERROR_UNEXPECTED;
2021}
4562236b 2022
2119aa17
DF		 2023/**
2024 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2025 * Is a shallow copy. Increments refcounts on existing streams and planes.
2026 * @dc: copy out of dc->current_state
2027 * @dst_ctx: copy into this
2028 */
f36cc577 2029void dc_resource_state_copy_construct_current(
1dc90497 2030 const struct dc *dc,
608ac7bb 2031 struct dc_state *dst_ctx)
1dc90497 2032{
f36cc577 2033 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2034}
2035
ab8db3e1
AG		 2036
2037void dc_resource_state_construct(
2038 const struct dc *dc,
2039 struct dc_state *dst_ctx)
2040{
dc88b4a6 2041 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2042}
2043
2119aa17
DF		 2044/**
2045 * dc_validate_global_state() - Determine if HW can support a given state
2046 * Checks HW resource availability and bandwidth requirement.
2047 * @dc: dc struct for this driver
2048 * @new_ctx: state to be validated
afcd526b 2049 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2050 *
2051 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2052 */
e750d56d 2053enum dc_status dc_validate_global_state(
1dc90497 2054 struct dc *dc,
afcd526b
JA		 2055 struct dc_state *new_ctx,
2056 bool fast_validate)
4562236b 2057{
1dc90497 2058 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2059 int i, j;
4562236b 2060
e41ab030
HW		 2061 if (!new_ctx)
2062 return DC_ERROR_UNEXPECTED;
2063
d596e5d0 2064 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2065 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2066 if (result != DC_OK)
2067 return result;
d596e5d0 2068 }
4562236b 2069
e41ab030 2070 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2071 struct dc_stream_state *stream = new_ctx->streams[i];
2072
2073 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2074 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2075
2076 if (pipe_ctx->stream != stream)
2077 continue;
2078
74eac5f3
SSC		 2079 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2080 pipe_ctx->plane_state &&
2081 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2082 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2083 if (result != DC_OK)
2084 return result;
2085 }
2086
1dc90497
AG		 2087 /* Switch to dp clock source only if there is
2088 * no non dp stream that shares the same timing
2089 * with the dp stream.
2090 */
2091 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2092 !find_pll_sharable_stream(stream, new_ctx)) {
2093
9d0dcecd 2094 resource_unreference_clock_source(
1dc90497
AG		 2095 &new_ctx->res_ctx,
2096 dc->res_pool,
9d0dcecd 2097 pipe_ctx->clock_source);
4a629536 2098
1dc90497
AG		 2099 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2100 resource_reference_clock_source(
2101 &new_ctx->res_ctx,
2102 dc->res_pool,
2103 pipe_ctx->clock_source);
2104 }
2105 }
2106 }
2107
1dc90497
AG		 2108 result = resource_build_scaling_params_for_context(dc, new_ctx);
2109
2110 if (result == DC_OK)
afcd526b 2111 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2112 result = DC_FAIL_BANDWIDTH_VALIDATE;
2113
2114 return result;
4562236b
HW		 2115}
2116
6e4d6bee 2117static void patch_gamut_packet_checksum(
e09b6473 2118 struct dc_info_packet *gamut_packet)
4562236b 2119{
4562236b 2120 /* For gamut we recalc checksum */
6e4d6bee 2121 if (gamut_packet->valid) {
4562236b
HW		 2122 uint8_t chk_sum = 0;
2123 uint8_t *ptr;
2124 uint8_t i;
2125
4562236b 2126 /*start of the Gamut data. */
6e4d6bee 2127 ptr = &gamut_packet->sb[3];
4562236b 2128
6e4d6bee 2129 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2130 chk_sum += ptr[i];
2131
6e4d6bee 2132 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2133 }
4562236b
HW		 2134}
2135
2136static void set_avi_info_frame(
e09b6473 2137 struct dc_info_packet *info_packet,
4562236b
HW		 2138 struct pipe_ctx *pipe_ctx)
2139{
0971c40e 2140 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2141 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2142 uint32_t pixel_encoding = 0;
2143 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2144 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2145 bool itc = false;
50e27654 2146 uint8_t itc_value = 0;
4562236b 2147 uint8_t cn0_cn1 = 0;
50e27654 2148 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2149 uint8_t *check_sum = NULL;
2150 uint8_t byte_index = 0;
754e3673 2151 union hdmi_info_packet hdmi_info;
50e27654 2152 union display_content_support support = {0};
4fa086b9 2153 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2154 enum dc_timing_3d_format format;
4562236b 2155
754e3673
AK		 2156 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2157
4fa086b9 2158 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2159 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2160 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2161 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2162
2163 /* Initialize header */
e09b6473 2164 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2165 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2166 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2167 hdmi_info.bits.header.version = 2;
2168 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2169
2170 /*
2171 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2172 * according to HDMI 2.0 spec (Section 10.1)
2173 */
2174
4fa086b9 2175 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2176 case PIXEL_ENCODING_YCBCR422:
2177 pixel_encoding = 1;
2178 break;
2179
2180 case PIXEL_ENCODING_YCBCR444:
2181 pixel_encoding = 2;
2182 break;
2183 case PIXEL_ENCODING_YCBCR420:
2184 pixel_encoding = 3;
2185 break;
2186
2187 case PIXEL_ENCODING_RGB:
2188 default:
2189 pixel_encoding = 0;
2190 }
2191
2192 /* Y0_Y1_Y2 : The pixel encoding */
2193 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2194 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2195
2196 /* A0 = 1 Active Format Information valid */
e09b6473 2197 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2198
2199 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2200 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2201
e09b6473 2202 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2203
2204 /* S0, S1 : Underscan / Overscan */
2205 /* TODO: un-hardcode scan type */
2206 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2207 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2208
2209 /* C0, C1 : Colorimetry */
8fde5884 2210 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2211 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2212 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2213 else if (color_space == COLOR_SPACE_YCBCR601 ||
2214 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2215 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2216 else {
e09b6473 2217 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2218 }
534db198 2219 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2220 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2221 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2222 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2223 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2224 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2225 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2226 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2227 }
2228
4562236b 2229 /* TODO: un-hardcode aspect ratio */
4fa086b9 2230 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2231
2232 switch (aspect) {
2233 case ASPECT_RATIO_4_3:
2234 case ASPECT_RATIO_16_9:
e09b6473 2235 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2236 break;
2237
2238 case ASPECT_RATIO_NO_DATA:
2239 case ASPECT_RATIO_64_27:
2240 case ASPECT_RATIO_256_135:
2241 default:
e09b6473 2242 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2243 }
2244
2245 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2246 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2247
2248 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2249
4562236b 2250 cn0_cn1 = 0;
50e27654
ZF		 2251 cn0_cn1_value = 0;
2252
2253 itc = true;
2254 itc_value = 1;
2255
ceb3dbb4 2256 support = stream->content_support;
4562236b
HW		 2257
2258 if (itc) {
50e27654
ZF		 2259 if (!support.bits.valid_content_type) {
2260 cn0_cn1_value = 0;
2261 } else {
2262 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2263 if (support.bits.graphics_content == 1) {
2264 cn0_cn1_value = 0;
2265 }
2266 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2267 if (support.bits.photo_content == 1) {
2268 cn0_cn1_value = 1;
2269 } else {
2270 cn0_cn1_value = 0;
2271 itc_value = 0;
2272 }
2273 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2274 if (support.bits.cinema_content == 1) {
2275 cn0_cn1_value = 2;
2276 } else {
2277 cn0_cn1_value = 0;
2278 itc_value = 0;
2279 }
2280 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2281 if (support.bits.game_content == 1) {
2282 cn0_cn1_value = 3;
2283 } else {
2284 cn0_cn1_value = 0;
2285 itc_value = 0;
2286 }
2287 }
2288 }
e09b6473
AK		 2289 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2290 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2291 }
2292
2293 /* TODO : We should handle YCC quantization */
2294 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2295 if (stream->qs_bit == 1 &&
2296 stream->qy_bit == 1) {
50e27654
ZF		 2297 if (color_space == COLOR_SPACE_SRGB ||
2298 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2299 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2300 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2301 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2302 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2303 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2304 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2305 } else {
e09b6473
AK		 2306 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2307 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2308 }
4562236b 2309 } else {
e09b6473
AK		 2310 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2311 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2312 }
50e27654 2313
15e17335 2314 ///VIC
4fa086b9 2315 format = stream->timing.timing_3d_format;
15e17335
CL		 2316 /*todo, add 3DStereo support*/
2317 if (format != TIMING_3D_FORMAT_NONE) {
2318 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2319 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2320 case 1:
2321 vic = 95;
2322 break;
2323 case 2:
2324 vic = 94;
2325 break;
2326 case 3:
2327 vic = 93;
2328 break;
2329 case 4:
2330 vic = 98;
2331 break;
2332 default:
2333 break;
2334 }
2335 }
efa02336 2336 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2337 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2338 if (vic >= 128)
2339 hdmi_info.bits.header.version = 3;
2340 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2341 * the Source shall use 20 AVI InfoFrame Version 4
2342 */
2343 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2344 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2345 hdmi_info.bits.header.version = 4;
2346 hdmi_info.bits.header.length = 14;
2347 }
4562236b
HW		 2348
2349 /* pixel repetition
2350 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2351 * repetition start from 1 */
e09b6473 2352 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2353
2354 /* Bar Info
2355 * barTop: Line Number of End of Top Bar.
2356 * barBottom: Line Number of Start of Bottom Bar.
2357 * barLeft: Pixel Number of End of Left Bar.
2358 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2359 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2360 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2361 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2362 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2363 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2364 - stream->timing.h_border_right + 1);
4562236b 2365
2f482c4f
CP		 2366 /* Additional Colorimetry Extension
2367 * Used in conduction with C0-C1 and EC0-EC2
2368 * 0 = DCI-P3 RGB (D65)
2369 * 1 = DCI-P3 RGB (theater)
2370 */
2371 hdmi_info.bits.ACE0_ACE3 = 0;
2372
4562236b 2373 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2374 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2375
efa02336 2376 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2377
efa02336 2378 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2379 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2380
2381 /* one byte complement */
2382 *check_sum = (uint8_t) (0x100 - *check_sum);
2383
2384 /* Store in hw_path_mode */
e09b6473
AK		 2385 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2386 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2387 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2388
e09b6473
AK		 2389 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2390 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2391
2392 info_packet->valid = true;
2393}
2394
6e4d6bee 2395static void set_vendor_info_packet(
e09b6473 2396 struct dc_info_packet *info_packet,
0971c40e 2397 struct dc_stream_state *stream)
4562236b 2398{
ecd0136b 2399 /* SPD info packet for FreeSync */
4562236b 2400
ecd0136b
HT		 2401 /* Check if Freesync is supported. Return if false. If true,
2402 * set the corresponding bit in the info packet
2403 */
2404 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2405 return;
2406
ecd0136b 2407 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2408}
2409
6e4d6bee 2410static void set_spd_info_packet(
e09b6473 2411 struct dc_info_packet *info_packet,
0971c40e 2412 struct dc_stream_state *stream)
4562236b
HW		 2413{
2414 /* SPD info packet for FreeSync */
2415
4562236b
HW		 2416 /* Check if Freesync is supported. Return if false. If true,
2417 * set the corresponding bit in the info packet
2418 */
98e6436d 2419 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2420 return;
2421
98e6436d 2422 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2423}
2424
1646a6fe 2425static void set_hdr_static_info_packet(
e09b6473 2426 struct dc_info_packet *info_packet,
0971c40e 2427 struct dc_stream_state *stream)
1646a6fe 2428{
0eeef690 2429 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2430
a10dc97a
KK		 2431 if (!stream->hdr_static_metadata.valid ||
2432 stream->use_dynamic_meta)
10bff005
YS		 2433 return;
2434
0eeef690 2435 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2436}
2437
6e4d6bee 2438static void set_vsc_info_packet(
e09b6473 2439 struct dc_info_packet *info_packet,
0971c40e 2440 struct dc_stream_state *stream)
4562236b 2441{
1336926f 2442 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2443 return;
2444
1336926f 2445 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2446}
2447
f36cc577 2448void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2449{
2450 int i, j;
2451
ab2541b6 2452 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2453 for (j = 0; j < context->stream_status[i].plane_count; j++)
2454 dc_plane_state_release(
2455 context->stream_status[i].plane_states[j]);
4562236b 2456
3be5262e 2457 context->stream_status[i].plane_count = 0;
4fa086b9 2458 dc_stream_release(context->streams[i]);
ab2541b6 2459 context->streams[i] = NULL;
4562236b
HW		 2460 }
2461}
2462
f36cc577 2463void dc_resource_state_copy_construct(
608ac7bb
JZ		 2464 const struct dc_state *src_ctx,
2465 struct dc_state *dst_ctx)
4562236b
HW		 2466{
2467 int i, j;
8ee5702a 2468 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2469
2470 *dst_ctx = *src_ctx;
2471
a2b8659d 2472 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2473 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2474
2475 if (cur_pipe->top_pipe)
2476 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2477
2478 if (cur_pipe->bottom_pipe)
2479 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL		 2480
2481 if (cur_pipe->next_odm_pipe)
2482 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2483
2484 if (cur_pipe->prev_odm_pipe)
2485 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW		 2486 }
2487
ab2541b6 2488 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2489 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2490 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2491 dc_plane_state_retain(
2492 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2493 }
9a3afbb3
AG		 2494
2495 /* context refcount should not be overridden */
8ee5702a 2496 dst_ctx->refcount = refcount;
9a3afbb3 2497
4562236b
HW		 2498}
2499
2500struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2501 struct resource_context *res_ctx,
2502 const struct resource_pool *pool)
4562236b
HW		 2503{
2504 int i;
2505
a2b8659d 2506 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2507 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2508 return pool->clock_sources[i];
4562236b
HW		 2509 }
2510
2511 return NULL;
2512}
2513
2514void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2515{
2516 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2517 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2518
2519 /* default all packets to invalid */
6e4d6bee
TC		 2520 info->avi.valid = false;
2521 info->gamut.valid = false;
2522 info->vendor.valid = false;
630e3573 2523 info->spd.valid = false;
6e4d6bee
TC		 2524 info->hdrsmd.valid = false;
2525 info->vsc.valid = false;
4562236b
HW		 2526
2527 signal = pipe_ctx->stream->signal;
2528
2529 /* HDMi and DP have different info packets*/
2530 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2531 set_avi_info_frame(&info->avi, pipe_ctx);
2532
2533 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2534
2535 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2536
56ef6ed9 2537 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2538
a33fa99d 2539 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2540 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2541
2542 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2543
56ef6ed9 2544 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2545 }
4562236b 2546
6e4d6bee 2547 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2548}
2549
2550enum dc_status resource_map_clock_resources(
fb3466a4 2551 const struct dc *dc,
608ac7bb 2552 struct dc_state *context,
1dc90497 2553 struct dc_stream_state *stream)
4562236b 2554{
4562236b 2555 /* acquire new resources */
1dc90497
AG		 2556 const struct resource_pool *pool = dc->res_pool;
2557 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2558 &context->res_ctx, stream);
ab2541b6 2559
1dc90497
AG		 2560 if (!pipe_ctx)
2561 return DC_ERROR_UNEXPECTED;
4562236b 2562
1dc90497
AG		 2563 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2564 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2565 pipe_ctx->clock_source = pool->dp_clock_source;
2566 else {
2567 pipe_ctx->clock_source = NULL;
4562236b 2568
1dc90497 2569 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2570 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2571 &context->res_ctx,
2572 pipe_ctx);
4562236b 2573
1dc90497
AG		 2574 if (pipe_ctx->clock_source == NULL)
2575 pipe_ctx->clock_source =
2576 dc_resource_find_first_free_pll(
2577 &context->res_ctx,
2578 pool);
2579 }
4562236b 2580
1dc90497
AG		 2581 if (pipe_ctx->clock_source == NULL)
2582 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2583
1dc90497
AG		 2584 resource_reference_clock_source(
2585 &context->res_ctx, pool,
2586 pipe_ctx->clock_source);
4562236b
HW		 2587
2588 return DC_OK;
2589}
2590
2591/*
2592 * Note: We need to disable output if clock sources change,
2593 * since bios does optimization and doesn't apply if changing
2594 * PHY when not already disabled.
2595 */
2596bool pipe_need_reprogram(
2597 struct pipe_ctx *pipe_ctx_old,
2598 struct pipe_ctx *pipe_ctx)
2599{
cfe4645e
DL		 2600 if (!pipe_ctx_old->stream)
2601 return false;
2602
4562236b
HW		 2603 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2604 return true;
2605
2606 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2607 return true;
2608
afaacef4 2609 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2610 return true;
2611
2612 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2613 && pipe_ctx_old->stream != pipe_ctx->stream)
2614 return true;
2615
8e9c4c8c 2616 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2617 return true;
2618
2619 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2620 return true;
2621
6b622181
JP		 2622 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2623 return true;
4562236b 2624
1e7e86c4
ST		 2625 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2626 return true;
2627
1336926f
A		 2628 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2629 return true;
2630
eed928dc
CL		 2631 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2632 false == pipe_ctx_old->stream->dpms_off)
2633 return true;
2634
4562236b
HW		 2635 return false;
2636}
529cad0f 2637
0971c40e 2638void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2639 struct bit_depth_reduction_params *fmt_bit_depth)
2640{
4fa086b9 2641 enum dc_dither_option option = stream->dither_option;
529cad0f 2642 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2643 stream->timing.pixel_encoding;
529cad0f
DW		 2644
2645 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2646
603767f9
TC		 2647 if (option == DITHER_OPTION_DEFAULT) {
2648 switch (stream->timing.display_color_depth) {
2649 case COLOR_DEPTH_666:
2650 option = DITHER_OPTION_SPATIAL6;
2651 break;
2652 case COLOR_DEPTH_888:
2653 option = DITHER_OPTION_SPATIAL8;
2654 break;
2655 case COLOR_DEPTH_101010:
2656 option = DITHER_OPTION_SPATIAL10;
2657 break;
2658 default:
2659 option = DITHER_OPTION_DISABLE;
2660 }
2661 }
2662
529cad0f
DW		 2663 if (option == DITHER_OPTION_DISABLE)
2664 return;
2665
2666 if (option == DITHER_OPTION_TRUN6) {
2667 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2668 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2669 } else if (option == DITHER_OPTION_TRUN8 ||
2670 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2671 option == DITHER_OPTION_TRUN8_FM6) {
2672 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2673 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2674 } else if (option == DITHER_OPTION_TRUN10 ||
2675 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2676 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2677 option == DITHER_OPTION_TRUN10_FM8 ||
2678 option == DITHER_OPTION_TRUN10_FM6 ||
2679 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2680 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2681 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2682 }
2683
2684 /* special case - Formatter can only reduce by 4 bits at most.
2685 * When reducing from 12 to 6 bits,
2686 * HW recommends we use trunc with round mode
2687 * (if we did nothing, trunc to 10 bits would be used)
2688 * note that any 12->10 bit reduction is ignored prior to DCE8,
2689 * as the input was 10 bits.
2690 */
2691 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2692 option == DITHER_OPTION_SPATIAL6 ||
2693 option == DITHER_OPTION_FM6) {
2694 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2695 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2696 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2697 }
2698
2699 /* spatial dither
2700 * note that spatial modes 1-3 are never used
2701 */
2702 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2703 option == DITHER_OPTION_SPATIAL6 ||
2704 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2705 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2706 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2707 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2708 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2709 fmt_bit_depth->flags.RGB_RANDOM =
2710 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2711 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2712 option == DITHER_OPTION_SPATIAL8 ||
2713 option == DITHER_OPTION_SPATIAL8_FM6 ||
2714 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2715 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2716 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2717 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2718 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2719 fmt_bit_depth->flags.RGB_RANDOM =
2720 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2721 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2722 option == DITHER_OPTION_SPATIAL10 ||
2723 option == DITHER_OPTION_SPATIAL10_FM8 ||
2724 option == DITHER_OPTION_SPATIAL10_FM6) {
2725 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2726 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2727 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2728 fmt_bit_depth->flags.RGB_RANDOM =
2729 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2730 }
2731
2732 if (option == DITHER_OPTION_SPATIAL6 ||
2733 option == DITHER_OPTION_SPATIAL8 ||
2734 option == DITHER_OPTION_SPATIAL10) {
2735 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2736 } else {
2737 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2738 }
2739
2740 //////////////////////
2741 //// temporal dither
2742 //////////////////////
2743 if (option == DITHER_OPTION_FM6 ||
2744 option == DITHER_OPTION_SPATIAL8_FM6 ||
2745 option == DITHER_OPTION_SPATIAL10_FM6 ||
2746 option == DITHER_OPTION_TRUN10_FM6 ||
2747 option == DITHER_OPTION_TRUN8_FM6 ||
2748 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2749 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2750 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2751 } else if (option == DITHER_OPTION_FM8 ||
2752 option == DITHER_OPTION_SPATIAL10_FM8 ||
2753 option == DITHER_OPTION_TRUN10_FM8) {
2754 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2755 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2756 } else if (option == DITHER_OPTION_FM10) {
2757 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2758 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2759 }
2760
2761 fmt_bit_depth->pixel_encoding = pixel_encoding;
2762}
9345d987 2763
62c933f9 2764enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2765{
ceb3dbb4 2766 struct dc_link *link = stream->link;
2b77dcc5 2767 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG		 2768 enum dc_status res = DC_OK;
2769
4fa086b9 2770 calculate_phy_pix_clks(stream);
9345d987 2771
4fa086b9 2772 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2773 res = DC_FAIL_CONTROLLER_VALIDATE;
2774
248cbed6 2775 if (res == DC_OK) {
9345d987 2776 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2777 link->link_enc, stream))
9345d987 2778 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2779 }
9345d987
AG		 2780
2781 /* TODO: validate audio ASIC caps, encoder */
2782
2783 if (res == DC_OK)
4fa086b9 2784 res = dc_link_validate_mode_timing(stream,
9345d987 2785 link,
4fa086b9 2786 &stream->timing);
9345d987 2787
62c933f9 2788 return res;
9345d987 2789}
792671d7 2790
62c933f9 2791enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2792{
62c933f9
YS		 2793 enum dc_status res = DC_OK;
2794
792671d7 2795 /* TODO For now validates pixel format only */
8e7095b9 2796 if (dc->res_pool->funcs->validate_plane)
62c933f9 2797 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2798
62c933f9 2799 return res;
792671d7 2800}
74eac5f3
SSC		 2801
2802unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2803{
2804 switch (format) {
2805 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2806 return 8;
2807 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2808 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2809 return 12;
2810 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2811 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2812 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2813 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2814 return 16;
2815 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2816 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2817 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2818 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2819 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2820 return 32;
2821 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2822 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2823 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2824 return 64;
2825 default:
2826 ASSERT_CRITICAL(false);
2827 return -1;
2828 }
2829}
3ab4cc65
CL		 2830static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
2831{
2832 if (modes) {
2833 if (modes->sample_rates.rate.RATE_192)
2834 return 192000;
2835 if (modes->sample_rates.rate.RATE_176_4)
2836 return 176400;
2837 if (modes->sample_rates.rate.RATE_96)
2838 return 96000;
2839 if (modes->sample_rates.rate.RATE_88_2)
2840 return 88200;
2841 if (modes->sample_rates.rate.RATE_48)
2842 return 48000;
2843 if (modes->sample_rates.rate.RATE_44_1)
2844 return 44100;
2845 if (modes->sample_rates.rate.RATE_32)
2846 return 32000;
2847 }
2848 /*original logic when no audio info*/
2849 return 441000;
2850}
2851
2852void get_audio_check(struct audio_info *aud_modes,
2853 struct audio_check *audio_chk)
2854{
2855 unsigned int i;
2856 unsigned int max_sample_rate = 0;
2857
2858 if (aud_modes) {
2859 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
2860
2861 audio_chk->max_audiosample_rate = 0;
2862 for (i = 0; i < aud_modes->mode_count; i++) {
2863 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
2864 if (audio_chk->max_audiosample_rate < max_sample_rate)
2865 audio_chk->max_audiosample_rate = max_sample_rate;
2866 /*dts takes the same as type 2: AP = 0.25*/
2867 }
2868 /*check which one take more bandwidth*/
2869 if (audio_chk->max_audiosample_rate > 192000)
2870 audio_chk->audio_packet_type = 0x9;/*AP =1*/
2871 audio_chk->acat = 0;/*not support*/
2872 }
2873}
2874
2875
2876
2877
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