]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drm/amd/display: Fix register names
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR
25
26#include <linux/slab.h>
27
4562236b
HW
28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL
37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW
44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
dc37a9a0 49#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD
50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635
HW
52#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
53#include "dcn20/dcn20_resource.h"
54#endif
2c8ad2d5 55#include "dce120/dce120_resource.h"
5d4b05dd
BL
56
57#define DC_LOGGER_INIT(logger)
58
4562236b
HW
59enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
60{
61 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
62 switch (asic_id.chip_family) {
63
64 case FAMILY_CI:
4562236b
HW
65 dc_version = DCE_VERSION_8_0;
66 break;
ebfdf0d0
AD
67 case FAMILY_KV:
68 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
71 dc_version = DCE_VERSION_8_3;
72 else
73 dc_version = DCE_VERSION_8_1;
74 break;
4562236b
HW
75 case FAMILY_CZ:
76 dc_version = DCE_VERSION_11_0;
77 break;
78
79 case FAMILY_VI:
80 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
82 dc_version = DCE_VERSION_10_0;
83 break;
84 }
85 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL
86 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW
88 dc_version = DCE_VERSION_11_2;
89 }
0c75d5ac
JFZ
90 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
91 dc_version = DCE_VERSION_11_22;
4562236b 92 break;
2c8ad2d5 93 case FAMILY_AI:
b8b6ce89
LL
94 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
95 dc_version = DCE_VERSION_12_1;
96 else
97 dc_version = DCE_VERSION_12_0;
2c8ad2d5 98 break;
dc37a9a0 99#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD
100 case FAMILY_RV:
101 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL
102 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
103 dc_version = DCN_VERSION_1_01;
ff5ef992
AD
104 break;
105#endif
7ed4e635
HW
106
107#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
111#endif
4562236b
HW
112 default:
113 dc_version = DCE_VERSION_UNKNOWN;
114 break;
115 }
116 return dc_version;
117}
118
d9673c92
HW
119struct resource_pool *dc_create_resource_pool(struct dc *dc,
120 const struct dc_init_data *init_data,
121 enum dce_version dc_version)
4562236b 122{
5ac3d3c9 123 struct resource_pool *res_pool = NULL;
4562236b
HW
124
125 switch (dc_version) {
126 case DCE_VERSION_8_0:
7992a629 127 res_pool = dce80_create_resource_pool(
d9673c92 128 init_data->num_virtual_links, dc);
7992a629 129 break;
ebfdf0d0 130 case DCE_VERSION_8_1:
7992a629 131 res_pool = dce81_create_resource_pool(
d9673c92 132 init_data->num_virtual_links, dc);
7992a629 133 break;
ebfdf0d0 134 case DCE_VERSION_8_3:
7992a629 135 res_pool = dce83_create_resource_pool(
d9673c92 136 init_data->num_virtual_links, dc);
5ac3d3c9 137 break;
4562236b 138 case DCE_VERSION_10_0:
5ac3d3c9 139 res_pool = dce100_create_resource_pool(
d9673c92 140 init_data->num_virtual_links, dc);
5ac3d3c9 141 break;
4562236b 142 case DCE_VERSION_11_0:
5ac3d3c9 143 res_pool = dce110_create_resource_pool(
d9673c92
HW
144 init_data->num_virtual_links, dc,
145 init_data->asic_id);
5ac3d3c9 146 break;
4562236b 147 case DCE_VERSION_11_2:
0c75d5ac 148 case DCE_VERSION_11_22:
5ac3d3c9 149 res_pool = dce112_create_resource_pool(
d9673c92 150 init_data->num_virtual_links, dc);
5ac3d3c9 151 break;
2c8ad2d5 152 case DCE_VERSION_12_0:
b8b6ce89 153 case DCE_VERSION_12_1:
2c8ad2d5 154 res_pool = dce120_create_resource_pool(
d9673c92 155 init_data->num_virtual_links, dc);
2c8ad2d5 156 break;
ff5ef992 157
dc37a9a0 158#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 159 case DCN_VERSION_1_0:
0e3d73f1 160 case DCN_VERSION_1_01:
d9673c92 161 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992
AD
162 break;
163#endif
3639fa68
ZF
164
165
7ed4e635
HW
166#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
167 case DCN_VERSION_2_0:
168 res_pool = dcn20_create_resource_pool(init_data, dc);
169 break;
170#endif
171
4562236b
HW
172 default:
173 break;
174 }
f49cfa27 175
5ac3d3c9 176 if (res_pool != NULL) {
9adc8050 177 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 178 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 179 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 180 /* initialize with firmware data first, no all
181 * ASIC have DCCG SW component. FPGA or
182 * simulation need initialization of
183 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
184 * with xtalin_clock_inKhz
185 */
186 res_pool->ref_clocks.dccg_ref_clock_inKhz =
187 res_pool->ref_clocks.xtalin_clock_inKhz;
188 res_pool->ref_clocks.dchub_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 } else
191 ASSERT_CRITICAL(false);
5ac3d3c9 192 }
4562236b 193
5ac3d3c9 194 return res_pool;
4562236b
HW
195}
196
fb3466a4 197void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW
198{
199 if (dc) {
200 if (dc->res_pool)
201 dc->res_pool->funcs->destroy(&dc->res_pool);
202
d029810c 203 kfree(dc->hwseq);
4562236b
HW
204 }
205}
206
207static void update_num_audio(
208 const struct resource_straps *straps,
209 unsigned int *num_audio,
210 struct audio_support *aud_support)
211{
b8e9eb72
CL
212 aud_support->dp_audio = true;
213 aud_support->hdmi_audio_native = false;
214 aud_support->hdmi_audio_on_dongle = false;
215
4562236b 216 if (straps->hdmi_disable == 0) {
4562236b
HW
217 if (straps->dc_pinstraps_audio & 0x2) {
218 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 219 aud_support->hdmi_audio_native = true;
4562236b
HW
220 }
221 }
222
223 switch (straps->audio_stream_number) {
224 case 0: /* multi streams supported */
225 break;
226 case 1: /* multi streams not supported */
227 *num_audio = 1;
228 break;
229 default:
230 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 231 }
4562236b
HW
232}
233
234bool resource_construct(
235 unsigned int num_virtual_links,
fb3466a4 236 struct dc *dc,
4562236b
HW
237 struct resource_pool *pool,
238 const struct resource_create_funcs *create_funcs)
239{
240 struct dc_context *ctx = dc->ctx;
241 const struct resource_caps *caps = pool->res_cap;
242 int i;
243 unsigned int num_audio = caps->num_audio;
244 struct resource_straps straps = {0};
245
246 if (create_funcs->read_dce_straps)
247 create_funcs->read_dce_straps(dc->ctx, &straps);
248
249 pool->audio_count = 0;
250 if (create_funcs->create_audio) {
251 /* find the total number of streams available via the
252 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
253 * registers (one for each pin) starting from pin 1
254 * up to the max number of audio pins.
255 * We stop on the first pin where
256 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
257 */
258 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 259 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW
260 struct audio *aud = create_funcs->create_audio(ctx, i);
261
262 if (aud == NULL) {
263 DC_ERR("DC: failed to create audio!\n");
264 return false;
265 }
4562236b
HW
266 if (!aud->funcs->endpoint_valid(aud)) {
267 aud->funcs->destroy(&aud);
268 break;
269 }
4562236b
HW
270 pool->audios[i] = aud;
271 pool->audio_count++;
272 }
273 }
274
275 pool->stream_enc_count = 0;
276 if (create_funcs->create_stream_encoder) {
277 for (i = 0; i < caps->num_stream_encoder; i++) {
278 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
279 if (pool->stream_enc[i] == NULL)
280 DC_ERR("DC: failed to create stream_encoder!\n");
281 pool->stream_enc_count++;
282 }
283 }
929c3aaa 284
4176664b
CL
285 dc->caps.dynamic_audio = false;
286 if (pool->audio_count < pool->stream_enc_count) {
287 dc->caps.dynamic_audio = true;
288 }
4562236b
HW
289 for (i = 0; i < num_virtual_links; i++) {
290 pool->stream_enc[pool->stream_enc_count] =
291 virtual_stream_encoder_create(
292 ctx, ctx->dc_bios);
293 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
294 DC_ERR("DC: failed to create stream_encoder!\n");
295 return false;
296 }
297 pool->stream_enc_count++;
298 }
299
300 dc->hwseq = create_funcs->create_hwseq(ctx);
301
302 return true;
303}
ad8960a6
ML
304static int find_matching_clock_source(
305 const struct resource_pool *pool,
306 struct clock_source *clock_source)
307{
4562236b 308
ad8960a6
ML
309 int i;
310
311 for (i = 0; i < pool->clk_src_count; i++) {
312 if (pool->clock_sources[i] == clock_source)
313 return i;
314 }
315 return -1;
316}
4562236b 317
21e67d4d 318void resource_unreference_clock_source(
4562236b 319 struct resource_context *res_ctx,
a2b8659d 320 const struct resource_pool *pool,
4a629536 321 struct clock_source *clock_source)
4562236b 322{
ad8960a6 323 int i = find_matching_clock_source(pool, clock_source);
4562236b 324
ad8960a6 325 if (i > -1)
4562236b
HW
326 res_ctx->clock_source_ref_count[i]--;
327
21e67d4d 328 if (pool->dp_clock_source == clock_source)
4562236b 329 res_ctx->dp_clock_source_ref_count--;
4562236b
HW
330}
331
332void resource_reference_clock_source(
333 struct resource_context *res_ctx,
a2b8659d 334 const struct resource_pool *pool,
4562236b
HW
335 struct clock_source *clock_source)
336{
ad8960a6 337 int i = find_matching_clock_source(pool, clock_source);
4562236b 338
ad8960a6 339 if (i > -1)
4562236b 340 res_ctx->clock_source_ref_count[i]++;
4562236b 341
a2b8659d 342 if (pool->dp_clock_source == clock_source)
4562236b
HW
343 res_ctx->dp_clock_source_ref_count++;
344}
345
ad8960a6
ML
346int resource_get_clock_source_reference(
347 struct resource_context *res_ctx,
348 const struct resource_pool *pool,
349 struct clock_source *clock_source)
350{
351 int i = find_matching_clock_source(pool, clock_source);
352
353 if (i > -1)
354 return res_ctx->clock_source_ref_count[i];
355
356 if (pool->dp_clock_source == clock_source)
357 return res_ctx->dp_clock_source_ref_count;
358
359 return -1;
360}
361
4562236b 362bool resource_are_streams_timing_synchronizable(
0971c40e
HW
363 struct dc_stream_state *stream1,
364 struct dc_stream_state *stream2)
4562236b 365{
4fa086b9 366 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW
367 return false;
368
4fa086b9 369 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW
370 return false;
371
4fa086b9
LSL
372 if (stream1->timing.h_addressable
373 != stream2->timing.h_addressable)
4562236b
HW
374 return false;
375
4fa086b9
LSL
376 if (stream1->timing.v_addressable
377 != stream2->timing.v_addressable)
4562236b
HW
378 return false;
379
380604e2
KC
380 if (stream1->timing.pix_clk_100hz
381 != stream2->timing.pix_clk_100hz)
4562236b
HW
382 return false;
383
3e27e10e
ML
384 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
385 return false;
386
4562236b 387 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL
388 && (!dc_is_dp_signal(stream1->signal)
389 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW
390 return false;
391
d77f778e
CL
392 if (stream1->view_format != stream2->view_format)
393 return false;
394
4562236b
HW
395 return true;
396}
3e27e10e
ML
397static bool is_dp_and_hdmi_sharable(
398 struct dc_stream_state *stream1,
399 struct dc_stream_state *stream2)
400{
401 if (stream1->ctx->dc->caps.disable_dp_clk_share)
402 return false;
403
404 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 405 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 406 return false;
3e27e10e
ML
407
408 return true;
409
410}
4562236b
HW
411
412static bool is_sharable_clk_src(
413 const struct pipe_ctx *pipe_with_clk_src,
414 const struct pipe_ctx *pipe)
415{
416 if (pipe_with_clk_src->clock_source == NULL)
417 return false;
418
419 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
420 return false;
421
3e27e10e
ML
422 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
423 (dc_is_dp_signal(pipe->stream->signal) &&
424 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
425 pipe->stream)))
4562236b
HW
426 return false;
427
428 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 429 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW
430 return false;
431
432 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 433 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW
434 return false;
435
436 if (!resource_are_streams_timing_synchronizable(
437 pipe_with_clk_src->stream, pipe->stream))
438 return false;
439
440 return true;
441}
442
443struct clock_source *resource_find_used_clk_src_for_sharing(
444 struct resource_context *res_ctx,
445 struct pipe_ctx *pipe_ctx)
446{
447 int i;
448
449 for (i = 0; i < MAX_PIPES; i++) {
450 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
451 return res_ctx->pipe_ctx[i].clock_source;
452 }
453
454 return NULL;
455}
456
457static enum pixel_format convert_pixel_format_to_dalsurface(
458 enum surface_pixel_format surface_pixel_format)
459{
460 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
461
462 switch (surface_pixel_format) {
463 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
464 dal_pixel_format = PIXEL_FORMAT_INDEX8;
465 break;
466 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
467 dal_pixel_format = PIXEL_FORMAT_RGB565;
468 break;
469 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
470 dal_pixel_format = PIXEL_FORMAT_RGB565;
471 break;
472 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
473 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
474 break;
8693049a 475 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW
476 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
477 break;
478 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
479 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
480 break;
481 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
482 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
483 break;
484 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
485 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
486 break;
487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
488 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
489 dal_pixel_format = PIXEL_FORMAT_FP16;
490 break;
491 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 492 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 493 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 494 break;
ffbcd19a
VP
495 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
496 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 497 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 498 break;
4562236b
HW
499 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
500 default:
501 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
502 break;
503 }
504 return dal_pixel_format;
505}
506
9b6067c0
DL
507static inline void get_vp_scan_direction(
508 enum dc_rotation_angle rotation,
509 bool horizontal_mirror,
510 bool *orthogonal_rotation,
511 bool *flip_vert_scan_dir,
512 bool *flip_horz_scan_dir)
4562236b 513{
9b6067c0
DL
514 *orthogonal_rotation = false;
515 *flip_vert_scan_dir = false;
516 *flip_horz_scan_dir = false;
517 if (rotation == ROTATION_ANGLE_180) {
518 *flip_vert_scan_dir = true;
519 *flip_horz_scan_dir = true;
520 } else if (rotation == ROTATION_ANGLE_90) {
521 *orthogonal_rotation = true;
522 *flip_horz_scan_dir = true;
523 } else if (rotation == ROTATION_ANGLE_270) {
524 *orthogonal_rotation = true;
525 *flip_vert_scan_dir = true;
526 }
527
528 if (horizontal_mirror)
529 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW
530}
531
b2d0a103 532static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 533{
3be5262e 534 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 535 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 536 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 537 struct rect surf_src = plane_state->src_rect;
9b6067c0 538 struct rect clip, dest;
87449a90
AK
539 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
540 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 541 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 542 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 543 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 544 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 545 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 546
7f5c22d1
VP
547 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
548 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP
549 pri_split = false;
550 sec_split = false;
551 }
86006a7f 552
4562236b
HW
553 /* The actual clip is an intersection between stream
554 * source and surface clip
555 */
9b6067c0 556 dest = plane_state->dst_rect;
3be5262e
HW
557 clip.x = stream->src.x > plane_state->clip_rect.x ?
558 stream->src.x : plane_state->clip_rect.x;
4562236b 559
1fbd2cfc 560 clip.width = stream->src.x + stream->src.width <
3be5262e 561 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 562 stream->src.x + stream->src.width - clip.x :
3be5262e 563 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 564
3be5262e
HW
565 clip.y = stream->src.y > plane_state->clip_rect.y ?
566 stream->src.y : plane_state->clip_rect.y;
4562236b 567
1fbd2cfc 568 clip.height = stream->src.y + stream->src.height <
3be5262e 569 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 570 stream->src.y + stream->src.height - clip.y :
3be5262e 571 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 572
9b6067c0
DL
573 /*
574 * Need to calculate how scan origin is shifted in vp space
575 * to correctly rotate clip and dst
576 */
577 get_vp_scan_direction(
578 plane_state->rotation,
579 plane_state->horizontal_mirror,
580 &orthogonal_rotation,
581 &flip_y_start,
582 &flip_x_start);
583
584 if (orthogonal_rotation) {
585 swap(clip.x, clip.y);
586 swap(clip.width, clip.height);
587 swap(dest.x, dest.y);
588 swap(dest.width, dest.height);
589 }
590 if (flip_x_start) {
591 clip.x = dest.x + dest.width - clip.x - clip.width;
592 dest.x = 0;
593 }
594 if (flip_y_start) {
595 clip.y = dest.y + dest.height - clip.y - clip.height;
596 dest.y = 0;
597 }
598
86006a7f 599 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW
600 * num_pixels = clip.num_pix * scl_ratio
601 */
9b6067c0
DL
602 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
603 data->viewport.width = clip.width * surf_src.width / dest.width;
604
605 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
606 data->viewport.height = clip.height * surf_src.height / dest.height;
607
608 /* Handle split */
609 if (pri_split || sec_split) {
610 if (orthogonal_rotation) {
611 if (flip_y_start != pri_split)
612 data->viewport.height /= 2;
613 else {
614 data->viewport.y += data->viewport.height / 2;
615 /* Ceil offset pipe */
616 data->viewport.height = (data->viewport.height + 1) / 2;
617 }
618 } else {
619 if (flip_x_start != pri_split)
620 data->viewport.width /= 2;
621 else {
622 data->viewport.x += data->viewport.width / 2;
623 /* Ceil offset pipe */
624 data->viewport.width = (data->viewport.width + 1) / 2;
625 }
626 }
627 }
9b5349f7 628
b2d0a103
DL
629 /* Round down, compensate in init */
630 data->viewport_c.x = data->viewport.x / vpc_div;
631 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL
632 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
633 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
634
b2d0a103
DL
635 /* Round up, assume original video size always even dimensions */
636 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
637 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW
638}
639
9b6067c0 640static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 641{
3be5262e 642 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 643 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 644 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS
645 bool pri_split = pipe_ctx->bottom_pipe &&
646 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
647 bool sec_split = pipe_ctx->top_pipe &&
648 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 649 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 650
6702a9ac 651 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 652 if (stream->src.x < surf_clip.x)
6702a9ac 653 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL
654 - stream->src.x) * stream->dst.width
655 / stream->src.width;
4562236b 656
6702a9ac 657 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 658 stream->dst.width / stream->src.width;
6702a9ac 659 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 660 stream->dst.x + stream->dst.width)
6702a9ac 661 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 662 stream->dst.x + stream->dst.width
6702a9ac 663 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 664
6702a9ac 665 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 666 if (stream->src.y < surf_clip.y)
6702a9ac 667 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL
668 - stream->src.y) * stream->dst.height
669 / stream->src.height;
4562236b 670
6702a9ac 671 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 672 stream->dst.height / stream->src.height;
6702a9ac 673 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 674 stream->dst.y + stream->dst.height)
6702a9ac 675 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 676 stream->dst.y + stream->dst.height
6702a9ac 677 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 678
9b6067c0 679 /* Handle h & v split, handle rotation using viewport */
b0131391
DL
680 if (sec_split && top_bottom_split) {
681 pipe_ctx->plane_res.scl_data.recout.y +=
682 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 683 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL
684 pipe_ctx->plane_res.scl_data.recout.height =
685 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
686 } else if (pri_split && top_bottom_split)
0c31a821 687 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL
688 else if (sec_split) {
689 pipe_ctx->plane_res.scl_data.recout.x +=
690 pipe_ctx->plane_res.scl_data.recout.width / 2;
691 /* Ceil offset pipe */
692 pipe_ctx->plane_res.scl_data.recout.width =
693 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
694 } else if (pri_split)
695 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW
696}
697
b2d0a103 698static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 699{
3be5262e 700 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 701 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 702 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL
703 const int in_w = stream->src.width;
704 const int in_h = stream->src.height;
705 const int out_w = stream->dst.width;
706 const int out_h = stream->dst.height;
4562236b 707
9b6067c0 708 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW
709 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
710 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 711 swap(surf_src.height, surf_src.width);
86006a7f 712
eb0e5154 713 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 714 surf_src.width,
3be5262e 715 plane_state->dst_rect.width);
eb0e5154 716 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 717 surf_src.height,
3be5262e 718 plane_state->dst_rect.height);
4562236b 719
4fa086b9 720 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 721 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 722 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 723 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 724
6702a9ac
HW
725 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
726 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
727 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
728 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 729
6702a9ac
HW
730 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
731 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 732
6702a9ac
HW
733 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
734 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
735 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
736 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 737 }
0002d3ac
DL
738 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
739 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
740 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
741 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
742 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
743 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
744 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
745 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW
746}
747
9b6067c0
DL
748static inline void adjust_vp_and_init_for_seamless_clip(
749 bool flip_scan_dir,
750 int recout_skip,
751 int src_size,
752 int taps,
753 struct fixed31_32 ratio,
754 struct fixed31_32 *init,
755 int *vp_offset,
756 int *vp_size)
b2d0a103 757{
9b6067c0 758 if (!flip_scan_dir) {
9a08f51f 759 /* Adjust for viewport end clip-off */
9b6067c0
DL
760 if ((*vp_offset + *vp_size) < src_size) {
761 int vp_clip = src_size - *vp_size - *vp_offset;
762 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL
763
764 int_part = int_part > 0 ? int_part : 0;
9b6067c0 765 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 766 }
b2d0a103 767
9a08f51f 768 /* Adjust for non-0 viewport offset */
9b6067c0 769 if (*vp_offset) {
9a08f51f
DL
770 int int_part;
771
9b6067c0
DL
772 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
773 int_part = dc_fixpt_floor(*init) - *vp_offset;
774 if (int_part < taps) {
775 int int_adj = *vp_offset >= (taps - int_part) ?
776 (taps - int_part) : *vp_offset;
777 *vp_offset -= int_adj;
778 *vp_size += int_adj;
9a08f51f 779 int_part += int_adj;
9b6067c0
DL
780 } else if (int_part > taps) {
781 *vp_offset += int_part - taps;
782 *vp_size -= int_part - taps;
783 int_part = taps;
9a08f51f 784 }
9b6067c0
DL
785 init->value &= 0xffffffff;
786 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL
787 }
788 } else {
789 /* Adjust for non-0 viewport offset */
9b6067c0
DL
790 if (*vp_offset) {
791 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 792
9a08f51f 793 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL
794 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
795 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 796 }
b2d0a103 797
9a08f51f 798 /* Adjust for viewport end clip-off */
9b6067c0 799 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 800 int int_part;
9b6067c0 801 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL
802
803 /*
804 * this is init if vp had no offset, keep in mind this is from the
805 * right side of vp due to scan direction
806 */
9b6067c0 807 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL
808 /*
809 * this is the difference between first pixel of viewport available to read
810 * and init position, takning into account scan direction
811 */
9b6067c0
DL
812 int_part = dc_fixpt_floor(*init) - end_offset;
813 if (int_part < taps) {
814 int int_adj = end_offset >= (taps - int_part) ?
815 (taps - int_part) : end_offset;
816 *vp_size += int_adj;
9a08f51f 817 int_part += int_adj;
9b6067c0
DL
818 } else if (int_part > taps) {
819 *vp_size += int_part - taps;
820 int_part = taps;
9a08f51f 821 }
9b6067c0
DL
822 init->value &= 0xffffffff;
823 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 824 }
b2d0a103 825 }
9b6067c0 826}
9a08f51f 827
9b6067c0
DL
828static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
829{
830 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
831 const struct dc_stream_state *stream = pipe_ctx->stream;
832 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
833 struct rect src = pipe_ctx->plane_state->src_rect;
834 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
835 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
836 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
837 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 838
9b6067c0
DL
839 /*
840 * Need to calculate the scan direction for viewport to make adjustments
841 */
842 get_vp_scan_direction(
843 plane_state->rotation,
844 plane_state->horizontal_mirror,
845 &orthogonal_rotation,
846 &flip_vert_scan_dir,
847 &flip_horz_scan_dir);
848
849 /* Calculate src rect rotation adjusted to recout space */
850 surf_size_h = src.x + src.width;
851 surf_size_v = src.y + src.height;
852 if (flip_horz_scan_dir)
853 src.x = 0;
854 if (flip_vert_scan_dir)
855 src.y = 0;
856 if (orthogonal_rotation) {
857 swap(src.x, src.y);
858 swap(src.width, src.height);
859 }
9a08f51f 860
9b6067c0
DL
861 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
862 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
863 * - (surf surf_src offset * 1/ full scl ratio))
864 */
865 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
866 * stream->dst.width / stream->src.width -
867 src.x * plane_state->dst_rect.width / src.width
868 * stream->dst.width / stream->src.width);
869 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
870 * stream->dst.height / stream->src.height -
871 src.y * plane_state->dst_rect.height / src.height
872 * stream->dst.height / stream->src.height);
873 if (orthogonal_rotation)
874 swap(recout_skip_h, recout_skip_v);
875 /*
876 * Init calculated according to formula:
877 * init = (scaling_ratio + number_of_taps + 1) / 2
878 * init_bot = init + scaling_ratio
879 * init_c = init + truncated_vp_c_offset(from calculate viewport)
880 */
881 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
882 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 883
9b6067c0
DL
884 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
885 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 886
9b6067c0
DL
887 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
888 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 889
9b6067c0
DL
890 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
891 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 892
9b6067c0
DL
893 /*
894 * Taps, inits and scaling ratios are in recout space need to rotate
895 * to viewport rotation before adjustment
896 */
897 adjust_vp_and_init_for_seamless_clip(
898 flip_horz_scan_dir,
899 recout_skip_h,
900 surf_size_h,
901 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
902 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
903 orthogonal_rotation ? &data->inits.v : &data->inits.h,
904 &data->viewport.x,
905 &data->viewport.width);
906 adjust_vp_and_init_for_seamless_clip(
907 flip_horz_scan_dir,
908 recout_skip_h,
909 surf_size_h / vpc_div,
910 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
911 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
912 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
913 &data->viewport_c.x,
914 &data->viewport_c.width);
915 adjust_vp_and_init_for_seamless_clip(
916 flip_vert_scan_dir,
917 recout_skip_v,
918 surf_size_v,
919 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
920 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
921 orthogonal_rotation ? &data->inits.h : &data->inits.v,
922 &data->viewport.y,
923 &data->viewport.height);
924 adjust_vp_and_init_for_seamless_clip(
925 flip_vert_scan_dir,
926 recout_skip_v,
927 surf_size_v / vpc_div,
928 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
929 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
930 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
931 &data->viewport_c.y,
932 &data->viewport_c.height);
b2d0a103
DL
933
934 /* Interlaced inits based on final vert inits */
eb0e5154
DL
935 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
936 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 937
b2d0a103 938}
f7938bc0
RA
939static bool are_rect_integer_multiples(struct rect src, struct rect dest)
940{
941 if (dest.width >= src.width && dest.width % src.width == 0 &&
942 dest.height >= src.height && dest.height % src.height == 0)
943 return true;
b2d0a103 944
f7938bc0
RA
945 return false;
946}
b2d0a103 947bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 948{
3be5262e 949 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 950 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 951 bool res = false;
5d4b05dd 952 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW
953 /* Important: scaling ratio calculation requires pixel format,
954 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 955 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 956 */
6702a9ac 957 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 958 pipe_ctx->plane_state->format);
b2d0a103
DL
959
960 calculate_scaling_ratios(pipe_ctx);
4562236b 961
b2d0a103 962 calculate_viewport(pipe_ctx);
4562236b 963
6702a9ac 964 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW
965 return false;
966
9b6067c0 967 calculate_recout(pipe_ctx);
4562236b
HW
968
969 /**
970 * Setting line buffer pixel depth to 24bpp yields banding
971 * on certain displays, such as the Sharp 4k
972 */
6702a9ac 973 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 974
199e458a 975 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 976 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 977
58bb0e63
AJ
978 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
979 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 980
4562236b 981 /* Taps calculations */
d94585a0
YHL
982 if (pipe_ctx->plane_res.xfm != NULL)
983 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
984 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
985
986 if (pipe_ctx->plane_res.dpp != NULL)
987 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
988 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0
RA
989
990 if (res &&
991 plane_state->scaling_quality.integer_scaling &&
992 are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
993 pipe_ctx->plane_res.scl_data.recout)) {
994 pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
995 pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
996 }
997
4562236b
HW
998 if (!res) {
999 /* Try 24 bpp linebuffer */
6702a9ac 1000 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1001
1b6c8067
BL
1002 if (pipe_ctx->plane_res.xfm != NULL)
1003 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1004 pipe_ctx->plane_res.xfm,
1005 &pipe_ctx->plane_res.scl_data,
1006 &plane_state->scaling_quality);
1007
1008 if (pipe_ctx->plane_res.dpp != NULL)
1009 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1010 pipe_ctx->plane_res.dpp,
1011 &pipe_ctx->plane_res.scl_data,
1012 &plane_state->scaling_quality);
4562236b
HW
1013 }
1014
b2d0a103 1015 if (res)
1fbd2cfc 1016 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1017 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1018
1296423b 1019 DC_LOG_SCALER(
4562236b
HW
1020 "%s: Viewport:\nheight:%d width:%d x:%d "
1021 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1022 "y:%d\n",
1023 __func__,
6702a9ac
HW
1024 pipe_ctx->plane_res.scl_data.viewport.height,
1025 pipe_ctx->plane_res.scl_data.viewport.width,
1026 pipe_ctx->plane_res.scl_data.viewport.x,
1027 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW
1028 plane_state->dst_rect.height,
1029 plane_state->dst_rect.width,
1030 plane_state->dst_rect.x,
1031 plane_state->dst_rect.y);
4562236b
HW
1032
1033 return res;
1034}
1035
1036
1037enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1038 const struct dc *dc,
608ac7bb 1039 struct dc_state *context)
4562236b
HW
1040{
1041 int i;
1042
1043 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1044 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1045 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1046 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1047 return DC_FAIL_SCALING;
4562236b
HW
1048 }
1049
1050 return DC_OK;
1051}
1052
a2b8659d
TC
1053struct pipe_ctx *find_idle_secondary_pipe(
1054 struct resource_context *res_ctx,
5581192d
JL
1055 const struct resource_pool *pool,
1056 const struct pipe_ctx *primary_pipe)
4562236b
HW
1057{
1058 int i;
1059 struct pipe_ctx *secondary_pipe = NULL;
1060
1061 /*
5581192d
JL
1062 * We add a preferred pipe mapping to avoid the chance that
1063 * MPCCs already in use will need to be reassigned to other trees.
1064 * For example, if we went with the strict, assign backwards logic:
1065 *
1066 * (State 1)
1067 * Display A on, no surface, top pipe = 0
1068 * Display B on, no surface, top pipe = 1
1069 *
1070 * (State 2)
1071 * Display A on, no surface, top pipe = 0
1072 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1073 *
1074 * (State 3)
1075 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1076 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1077 *
1078 * The state 2->3 transition requires remapping MPCC 5 from display B
1079 * to display A.
1080 *
1081 * However, with the preferred pipe logic, state 2 would look like:
1082 *
1083 * (State 2)
1084 * Display A on, no surface, top pipe = 0
1085 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1086 *
1087 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1088 */
5581192d
JL
1089 if (primary_pipe) {
1090 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1091 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1092 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1093 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW
1094 }
1095 }
1096
5581192d
JL
1097 /*
1098 * search backwards for the second pipe to keep pipe
1099 * assignment more consistent
1100 */
1101 if (!secondary_pipe)
1102 for (i = pool->pipe_count - 1; i >= 0; i--) {
1103 if (res_ctx->pipe_ctx[i].stream == NULL) {
1104 secondary_pipe = &res_ctx->pipe_ctx[i];
1105 secondary_pipe->pipe_idx = i;
1106 break;
1107 }
1108 }
4562236b
HW
1109
1110 return secondary_pipe;
1111}
1112
1113struct pipe_ctx *resource_get_head_pipe_for_stream(
1114 struct resource_context *res_ctx,
0971c40e 1115 struct dc_stream_state *stream)
4562236b
HW
1116{
1117 int i;
22498036 1118
a2b8659d 1119 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL
1120 if (res_ctx->pipe_ctx[i].stream == stream
1121 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1122 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1123 return &res_ctx->pipe_ctx[i];
4562236b
HW
1124 }
1125 return NULL;
1126}
1127
b1f6d01c 1128static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1129 struct resource_context *res_ctx,
b1f6d01c 1130 struct pipe_ctx *head_pipe)
19f89e23 1131{
b1f6d01c 1132 struct pipe_ctx *tail_pipe;
19f89e23
AG
1133
1134 tail_pipe = head_pipe->bottom_pipe;
1135
1136 while (tail_pipe) {
1137 head_pipe = tail_pipe;
1138 tail_pipe = tail_pipe->bottom_pipe;
1139 }
1140
1141 return head_pipe;
1142}
1143
4562236b 1144/*
ab2541b6
AC
1145 * A free_pipe for a stream is defined here as a pipe
1146 * that has no surface attached yet
4562236b 1147 */
b1f6d01c 1148static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1149 struct dc_state *context,
a2b8659d 1150 const struct resource_pool *pool,
b1f6d01c 1151 struct pipe_ctx *head_pipe)
4562236b
HW
1152{
1153 int i;
745cc746 1154 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1155
3be5262e 1156 if (!head_pipe->plane_state)
4562236b
HW
1157 return head_pipe;
1158
1159 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1160 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1161 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1162 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW
1163 return &res_ctx->pipe_ctx[i];
1164 }
1165 }
1166
1167 /*
1168 * At this point we have no re-useable pipe for this stream and we need
1169 * to acquire an idle one to satisfy the request
1170 */
1171
a2b8659d 1172 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW
1173 return NULL;
1174
b1f6d01c 1175 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW
1176}
1177
dc37a9a0 1178#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
0f9a536f
DL
1179static int acquire_first_split_pipe(
1180 struct resource_context *res_ctx,
1181 const struct resource_pool *pool,
0971c40e 1182 struct dc_stream_state *stream)
0f9a536f
DL
1183{
1184 int i;
1185
1186 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL
1187 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1188
b1f6d01c 1189 if (split_pipe->top_pipe &&
79592db3
DL
1190 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1191 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1192 if (split_pipe->bottom_pipe)
1193 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1194
1195 if (split_pipe->top_pipe->plane_state)
1196 resource_build_scaling_params(split_pipe->top_pipe);
1197
1198 memset(split_pipe, 0, sizeof(*split_pipe));
1199 split_pipe->stream_res.tg = pool->timing_generators[i];
1200 split_pipe->plane_res.hubp = pool->hubps[i];
1201 split_pipe->plane_res.ipp = pool->ipps[i];
1202 split_pipe->plane_res.dpp = pool->dpps[i];
1203 split_pipe->stream_res.opp = pool->opps[i];
1204 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1205 split_pipe->pipe_idx = i;
1206
1207 split_pipe->stream = stream;
0f9a536f
DL
1208 return i;
1209 }
1210 }
1211 return -1;
1212}
1213#endif
1214
19f89e23
AG
1215bool dc_add_plane_to_context(
1216 const struct dc *dc,
0971c40e 1217 struct dc_stream_state *stream,
19f89e23 1218 struct dc_plane_state *plane_state,
608ac7bb 1219 struct dc_state *context)
4562236b
HW
1220{
1221 int i;
19f89e23
AG
1222 struct resource_pool *pool = dc->res_pool;
1223 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1224 struct dc_stream_status *stream_status = NULL;
4562236b 1225
19f89e23
AG
1226 for (i = 0; i < context->stream_count; i++)
1227 if (context->streams[i] == stream) {
1228 stream_status = &context->stream_status[i];
1229 break;
1230 }
1231 if (stream_status == NULL) {
1232 dm_error("Existing stream not found; failed to attach surface!\n");
1233 return false;
1234 }
1235
4562236b 1236
19f89e23
AG
1237 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1238 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1239 plane_state, MAX_SURFACE_NUM);
4562236b
HW
1240 return false;
1241 }
1242
19f89e23
AG
1243 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1244
1245 if (!head_pipe) {
1246 dm_error("Head pipe not found for stream_state %p !\n", stream);
1247 return false;
1248 }
1249
b1f6d01c
DL
1250 /* retain new surface, but only once per stream */
1251 dc_plane_state_retain(plane_state);
00737c59 1252
b1f6d01c
DL
1253 while (head_pipe) {
1254 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1255 ASSERT(tail_pipe);
19f89e23 1256
b1f6d01c 1257 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1258
b1f6d01c
DL
1259 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1260 if (!free_pipe) {
1261 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1262 if (pipe_idx >= 0)
1263 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1264 }
1265 #endif
1266 if (!free_pipe) {
1267 dc_plane_state_release(plane_state);
1268 return false;
1269 }
19f89e23 1270
b1f6d01c
DL
1271 free_pipe->plane_state = plane_state;
1272
1273 if (head_pipe != free_pipe) {
1274 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1275 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1276 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1277 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1278 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1279 free_pipe->clock_source = tail_pipe->clock_source;
1280 free_pipe->top_pipe = tail_pipe;
1281 tail_pipe->bottom_pipe = free_pipe;
1282 }
1283 head_pipe = head_pipe->next_odm_pipe;
1284 }
19f89e23
AG
1285 /* assign new surfaces*/
1286 stream_status->plane_states[stream_status->plane_count] = plane_state;
1287
1288 stream_status->plane_count++;
1289
1290 return true;
1291}
1292
1293bool dc_remove_plane_from_context(
1294 const struct dc *dc,
1295 struct dc_stream_state *stream,
1296 struct dc_plane_state *plane_state,
608ac7bb 1297 struct dc_state *context)
19f89e23
AG
1298{
1299 int i;
1300 struct dc_stream_status *stream_status = NULL;
1301 struct resource_pool *pool = dc->res_pool;
1302
ab2541b6 1303 for (i = 0; i < context->stream_count; i++)
4fa086b9 1304 if (context->streams[i] == stream) {
ab2541b6 1305 stream_status = &context->stream_status[i];
4562236b
HW
1306 break;
1307 }
19f89e23 1308
ab2541b6 1309 if (stream_status == NULL) {
19f89e23 1310 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW
1311 return false;
1312 }
1313
19f89e23
AG
1314 /* release pipe for plane*/
1315 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1316 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1317
6ffaa6fc 1318 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG
1319 if (pipe_ctx->top_pipe)
1320 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1321
19f89e23
AG
1322 /* Second condition is to avoid setting NULL to top pipe
1323 * of tail pipe making it look like head pipe in subsequent
1324 * deletes
1325 */
1326 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1327 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1328
19f89e23
AG
1329 /*
1330 * For head pipe detach surfaces from pipe for tail
1331 * pipe just zero it out
1332 */
b1f6d01c 1333 if (!pipe_ctx->top_pipe)
19f89e23 1334 pipe_ctx->plane_state = NULL;
b1f6d01c 1335 else
19f89e23 1336 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1337 }
19f89e23 1338 }
4562236b 1339
4562236b 1340
19f89e23
AG
1341 for (i = 0; i < stream_status->plane_count; i++) {
1342 if (stream_status->plane_states[i] == plane_state) {
1343
1344 dc_plane_state_release(stream_status->plane_states[i]);
1345 break;
4562236b 1346 }
19f89e23 1347 }
4562236b 1348
19f89e23
AG
1349 if (i == stream_status->plane_count) {
1350 dm_error("Existing plane_state not found; failed to detach it!\n");
1351 return false;
4562236b
HW
1352 }
1353
19f89e23 1354 stream_status->plane_count--;
4562236b 1355
abb4986e
AJ
1356 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1357 for (; i < stream_status->plane_count; i++)
19f89e23
AG
1358 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1359
1360 stream_status->plane_states[stream_status->plane_count] = NULL;
1361
1362 return true;
1363}
1364
1365bool dc_rem_all_planes_for_stream(
1366 const struct dc *dc,
1367 struct dc_stream_state *stream,
608ac7bb 1368 struct dc_state *context)
19f89e23
AG
1369{
1370 int i, old_plane_count;
1371 struct dc_stream_status *stream_status = NULL;
1372 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1373
1374 for (i = 0; i < context->stream_count; i++)
1375 if (context->streams[i] == stream) {
1376 stream_status = &context->stream_status[i];
1377 break;
1378 }
1379
1380 if (stream_status == NULL) {
1381 dm_error("Existing stream %p not found!\n", stream);
1382 return false;
1383 }
1384
1385 old_plane_count = stream_status->plane_count;
1386
1387 for (i = 0; i < old_plane_count; i++)
1388 del_planes[i] = stream_status->plane_states[i];
1389
1390 for (i = 0; i < old_plane_count; i++)
1391 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1392 return false;
1393
1394 return true;
1395}
1396
1397static bool add_all_planes_for_stream(
1398 const struct dc *dc,
1399 struct dc_stream_state *stream,
1400 const struct dc_validation_set set[],
1401 int set_count,
608ac7bb 1402 struct dc_state *context)
19f89e23
AG
1403{
1404 int i, j;
1405
1406 for (i = 0; i < set_count; i++)
1407 if (set[i].stream == stream)
1408 break;
1409
1410 if (i == set_count) {
1411 dm_error("Stream %p not found in set!\n", stream);
1412 return false;
1413 }
4562236b 1414
19f89e23
AG
1415 for (j = 0; j < set[i].plane_count; j++)
1416 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1417 return false;
4562236b
HW
1418
1419 return true;
1420}
1421
19f89e23
AG
1422bool dc_add_all_planes_for_stream(
1423 const struct dc *dc,
1424 struct dc_stream_state *stream,
1425 struct dc_plane_state * const *plane_states,
1426 int plane_count,
608ac7bb 1427 struct dc_state *context)
19f89e23
AG
1428{
1429 struct dc_validation_set set;
1430 int i;
1431
1432 set.stream = stream;
1433 set.plane_count = plane_count;
1434
1435 for (i = 0; i < plane_count; i++)
1436 set.plane_states[i] = plane_states[i];
1437
1438 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1439}
1440
1441
6b622181
JP
1442static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1443 struct dc_stream_state *new_stream)
1444{
1445 if (cur_stream == NULL)
1446 return true;
1447
1448 if (memcmp(&cur_stream->hdr_static_metadata,
1449 &new_stream->hdr_static_metadata,
1450 sizeof(struct dc_info_packet)) != 0)
1451 return true;
1452
1453 return false;
1454}
4562236b 1455
1336926f
A
1456static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1457 struct dc_stream_state *new_stream)
1458{
1459 if (cur_stream == NULL)
1460 return true;
1461
1462 if (memcmp(&cur_stream->vsc_infopacket,
1463 &new_stream->vsc_infopacket,
1464 sizeof(struct dc_info_packet)) != 0)
1465 return true;
1466
1467 return false;
1468}
1469
0971c40e
HW
1470static bool is_timing_changed(struct dc_stream_state *cur_stream,
1471 struct dc_stream_state *new_stream)
4562236b
HW
1472{
1473 if (cur_stream == NULL)
1474 return true;
1475
1476 /* If sink pointer changed, it means this is a hotplug, we should do
1477 * full hw setting.
1478 */
1479 if (cur_stream->sink != new_stream->sink)
1480 return true;
1481
1482 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1483 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW
1484 return true;
1485
1486 return memcmp(
4fa086b9
LSL
1487 &cur_stream->timing,
1488 &new_stream->timing,
4562236b
HW
1489 sizeof(struct dc_crtc_timing)) != 0;
1490}
1491
1492static bool are_stream_backends_same(
0971c40e 1493 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW
1494{
1495 if (stream_a == stream_b)
1496 return true;
1497
1498 if (stream_a == NULL || stream_b == NULL)
1499 return false;
1500
1501 if (is_timing_changed(stream_a, stream_b))
1502 return false;
1503
6b622181
JP
1504 if (is_hdr_static_meta_changed(stream_a, stream_b))
1505 return false;
1506
1e7e86c4
ST
1507 if (stream_a->dpms_off != stream_b->dpms_off)
1508 return false;
1509
1336926f
A
1510 if (is_vsc_info_packet_changed(stream_a, stream_b))
1511 return false;
1512
4562236b
HW
1513 return true;
1514}
1515
2119aa17
DF
1516/**
1517 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1518 *
1519 * Checks if there a difference between the two states
1520 * that would require a mode change.
1521 *
1522 * Does not compare cursor position or attributes.
1523 */
d54d29db 1524bool dc_is_stream_unchanged(
0971c40e 1525 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1526{
4562236b 1527
ab2541b6
AC
1528 if (!are_stream_backends_same(old_stream, stream))
1529 return false;
4562236b
HW
1530
1531 return true;
1532}
1533
2119aa17
DF
1534/**
1535 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1536 */
9a5d9c48
LSL
1537bool dc_is_stream_scaling_unchanged(
1538 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1539{
1540 if (old_stream == stream)
1541 return true;
1542
1543 if (old_stream == NULL || stream == NULL)
1544 return false;
1545
1546 if (memcmp(&old_stream->src,
1547 &stream->src,
1548 sizeof(struct rect)) != 0)
1549 return false;
1550
1551 if (memcmp(&old_stream->dst,
1552 &stream->dst,
1553 sizeof(struct rect)) != 0)
1554 return false;
1555
1556 return true;
1557}
1558
1dc90497 1559static void update_stream_engine_usage(
4562236b 1560 struct resource_context *res_ctx,
a2b8659d 1561 const struct resource_pool *pool,
1dc90497
AG
1562 struct stream_encoder *stream_enc,
1563 bool acquired)
4562236b
HW
1564{
1565 int i;
1566
a2b8659d
TC
1567 for (i = 0; i < pool->stream_enc_count; i++) {
1568 if (pool->stream_enc[i] == stream_enc)
1dc90497 1569 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW
1570 }
1571}
1572
1573/* TODO: release audio object */
4176664b 1574void update_audio_usage(
4562236b 1575 struct resource_context *res_ctx,
a2b8659d 1576 const struct resource_pool *pool,
1dc90497
AG
1577 struct audio *audio,
1578 bool acquired)
4562236b
HW
1579{
1580 int i;
a2b8659d
TC
1581 for (i = 0; i < pool->audio_count; i++) {
1582 if (pool->audios[i] == audio)
1dc90497 1583 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW
1584 }
1585}
1586
1587static int acquire_first_free_pipe(
1588 struct resource_context *res_ctx,
a2b8659d 1589 const struct resource_pool *pool,
0971c40e 1590 struct dc_stream_state *stream)
4562236b
HW
1591{
1592 int i;
1593
a2b8659d 1594 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW
1595 if (!res_ctx->pipe_ctx[i].stream) {
1596 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1597
6b670fa9 1598 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1599 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1600 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW
1601 pipe_ctx->plane_res.ipp = pool->ipps[i];
1602 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1603 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1604 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL
1605 if (pool->dpps[i])
1606 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW
1607 pipe_ctx->pipe_idx = i;
1608
ff5ef992 1609
4562236b
HW
1610 pipe_ctx->stream = stream;
1611 return i;
1612 }
1613 }
1614 return -1;
1615}
1616
a2b8659d
TC
1617static struct audio *find_first_free_audio(
1618 struct resource_context *res_ctx,
cfb071f7
CL
1619 const struct resource_pool *pool,
1620 enum engine_id id)
4562236b 1621{
b5a41620
CL
1622 int i, available_audio_count;
1623
1624 available_audio_count = pool->audio_count;
1625
1626 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1627 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL
1628 /*we have enough audio endpoint, find the matching inst*/
1629 if (id != i)
1630 continue;
66bfd4fd 1631 return pool->audios[i];
4562236b 1632 }
66bfd4fd 1633 }
5feb9f07 1634
b5a41620
CL
1635 /* use engine id to find free audio */
1636 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM
1637 return pool->audios[id];
1638 }
66bfd4fd 1639 /*not found the matching one, first come first serve*/
b5a41620 1640 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL
1641 if (res_ctx->is_audio_acquired[i] == false) {
1642 return pool->audios[i];
4176664b
CL
1643 }
1644 }
4562236b
HW
1645 return 0;
1646}
1647
4562236b 1648bool resource_is_stream_unchanged(
608ac7bb 1649 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1650{
ab2541b6 1651 int i;
4562236b 1652
ab2541b6 1653 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1654 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1655
ab2541b6 1656 if (are_stream_backends_same(old_stream, stream))
4562236b 1657 return true;
4562236b
HW
1658 }
1659
1660 return false;
1661}
1662
2119aa17
DF
1663/**
1664 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1665 */
13ab1b44 1666enum dc_status dc_add_stream_to_ctx(
1dc90497 1667 struct dc *dc,
608ac7bb 1668 struct dc_state *new_ctx,
1dc90497
AG
1669 struct dc_stream_state *stream)
1670{
1dc90497 1671 enum dc_status res;
eb9714a2 1672 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1673
ece4147f 1674 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1675 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG
1676 return DC_ERROR_UNEXPECTED;
1677 }
1678
1679 new_ctx->streams[new_ctx->stream_count] = stream;
1680 dc_stream_retain(stream);
1681 new_ctx->stream_count++;
1682
1683 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1684 if (res != DC_OK)
eb9714a2 1685 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1686
13ab1b44 1687 return res;
1dc90497
AG
1688}
1689
2119aa17
DF
1690/**
1691 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1692 */
62c933f9 1693enum dc_status dc_remove_stream_from_ctx(
1dc90497 1694 struct dc *dc,
608ac7bb 1695 struct dc_state *new_ctx,
1dc90497
AG
1696 struct dc_stream_state *stream)
1697{
19f89e23 1698 int i;
1dc90497 1699 struct dc_context *dc_ctx = dc->ctx;
22498036
DL
1700 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1701 struct pipe_ctx *odm_pipe;
1dc90497
AG
1702
1703 if (!del_pipe) {
1704 DC_ERROR("Pipe not found for stream %p !\n", stream);
1705 return DC_ERROR_UNEXPECTED;
1706 }
1707
22498036
DL
1708 odm_pipe = del_pipe->next_odm_pipe;
1709
1710 /* Release primary pipe */
1711 ASSERT(del_pipe->stream_res.stream_enc);
1712 update_stream_engine_usage(
1713 &new_ctx->res_ctx,
1714 dc->res_pool,
1715 del_pipe->stream_res.stream_enc,
1716 false);
1717
1718 if (del_pipe->stream_res.audio)
1719 update_audio_usage(
1720 &new_ctx->res_ctx,
1721 dc->res_pool,
1722 del_pipe->stream_res.audio,
1723 false);
1724
1725 resource_unreference_clock_source(&new_ctx->res_ctx,
1726 dc->res_pool,
1727 del_pipe->clock_source);
1728
1729 if (dc->res_pool->funcs->remove_stream_from_ctx)
1730 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1731
1732 while (odm_pipe) {
1733 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1734
1735 memset(odm_pipe, 0, sizeof(*odm_pipe));
1736 odm_pipe = next_odm_pipe;
1737 }
1738 memset(del_pipe, 0, sizeof(*del_pipe));
1739
1dc90497
AG
1740 for (i = 0; i < new_ctx->stream_count; i++)
1741 if (new_ctx->streams[i] == stream)
1742 break;
1743
1744 if (new_ctx->streams[i] != stream) {
1745 DC_ERROR("Context doesn't have stream %p !\n", stream);
1746 return DC_ERROR_UNEXPECTED;
1747 }
1748
1749 dc_stream_release(new_ctx->streams[i]);
1750 new_ctx->stream_count--;
1751
1dc90497
AG
1752 /* Trim back arrays */
1753 for (; i < new_ctx->stream_count; i++) {
1754 new_ctx->streams[i] = new_ctx->streams[i + 1];
1755 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1756 }
1757
1758 new_ctx->streams[new_ctx->stream_count] = NULL;
1759 memset(
1760 &new_ctx->stream_status[new_ctx->stream_count],
1761 0,
1762 sizeof(new_ctx->stream_status[0]));
1763
1764 return DC_OK;
1765}
1766
0971c40e
HW
1767static struct dc_stream_state *find_pll_sharable_stream(
1768 struct dc_stream_state *stream_needs_pll,
608ac7bb 1769 struct dc_state *context)
4562236b 1770{
ab2541b6 1771 int i;
4562236b 1772
ab2541b6 1773 for (i = 0; i < context->stream_count; i++) {
0971c40e 1774 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1775
ab2541b6
AC
1776 /* We are looking for non dp, non virtual stream */
1777 if (resource_are_streams_timing_synchronizable(
1778 stream_needs_pll, stream_has_pll)
1779 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1780 && stream_has_pll->link->connector_signal
ab2541b6
AC
1781 != SIGNAL_TYPE_VIRTUAL)
1782 return stream_has_pll;
4562236b 1783
4562236b
HW
1784 }
1785
1786 return NULL;
1787}
1788
1789static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1790{
380604e2 1791 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW
1792 uint32_t normalized_pix_clk = pix_clk;
1793
1794 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1795 pix_clk /= 2;
cc4d99b8
CL
1796 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1797 switch (timing->display_color_depth) {
8897810a 1798 case COLOR_DEPTH_666:
cc4d99b8
CL
1799 case COLOR_DEPTH_888:
1800 normalized_pix_clk = pix_clk;
1801 break;
1802 case COLOR_DEPTH_101010:
1803 normalized_pix_clk = (pix_clk * 30) / 24;
1804 break;
1805 case COLOR_DEPTH_121212:
1806 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1807 break;
cc4d99b8
CL
1808 case COLOR_DEPTH_161616:
1809 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1810 break;
cc4d99b8
CL
1811 default:
1812 ASSERT(0);
4562236b 1813 break;
cc4d99b8 1814 }
4562236b 1815 }
4562236b
HW
1816 return normalized_pix_clk;
1817}
1818
0971c40e 1819static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1820{
9345d987
AG
1821 /* update actual pixel clock on all streams */
1822 if (dc_is_hdmi_signal(stream->signal))
1823 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1824 &stream->timing) / 10;
9345d987
AG
1825 else
1826 stream->phy_pix_clk =
380604e2 1827 stream->timing.pix_clk_100hz / 10;
39c03e00
CL
1828
1829 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1830 stream->phy_pix_clk *= 2;
4562236b
HW
1831}
1832
d2d7885f
AK
1833static int acquire_resource_from_hw_enabled_state(
1834 struct resource_context *res_ctx,
1835 const struct resource_pool *pool,
1836 struct dc_stream_state *stream)
1837{
1838 struct dc_link *link = stream->link;
5ec43eda 1839 unsigned int inst, tg_inst;
d2d7885f
AK
1840
1841 /* Check for enabled DIG to identify enabled display */
1842 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1843 return -1;
1844
1845 /* Check for which front end is used by this encoder.
1846 * Note the inst is 1 indexed, where 0 is undefined.
1847 * Note that DIG_FE can source from different OTG but our
1848 * current implementation always map 1-to-1, so this code makes
1849 * the same assumption and doesn't check OTG source.
1850 */
5ec43eda 1851 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f
AK
1852
1853 /* Instance should be within the range of the pool */
1854 if (inst >= pool->pipe_count)
1855 return -1;
1856
5ec43eda
ML
1857 if (inst >= pool->stream_enc_count)
1858 return -1;
1859
1860 tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
1861
1862 if (tg_inst >= pool->timing_generator_count)
1863 return false;
1864
1865 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1866 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1867
1868 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1869 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1870 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1871 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1872 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1873 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1874 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1875
5ec43eda
ML
1876 if (pool->dpps[tg_inst])
1877 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
1878 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK
1879
1880 pipe_ctx->stream = stream;
5ec43eda 1881 return tg_inst;
d2d7885f
AK
1882 }
1883
1884 return -1;
1885}
1886
4562236b 1887enum dc_status resource_map_pool_resources(
fb3466a4 1888 const struct dc *dc,
608ac7bb 1889 struct dc_state *context,
1dc90497 1890 struct dc_stream_state *stream)
4562236b 1891{
a2b8659d 1892 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG
1893 int i;
1894 struct dc_context *dc_ctx = dc->ctx;
1895 struct pipe_ctx *pipe_ctx = NULL;
1896 int pipe_idx = -1;
46570f09 1897 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1898
1dc90497
AG
1899 /* TODO Check if this is needed */
1900 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1901 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1902 stream->bit_depth_params =
430ef426
DL
1903 old_context->streams[i]->bit_depth_params;
1904 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC
1905 continue;
1906 }
4b679bc3 1907 }
1dc90497 1908 */
7e2fe319 1909
08e1c28d
YMM
1910 calculate_phy_pix_clks(stream);
1911
46570f09
AK
1912 /* TODO: Check Linux */
1913 if (dc->config.allow_seamless_boot_optimization &&
1914 !dcb->funcs->is_accelerated_mode(dcb)) {
1915 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1916 stream->apply_seamless_boot_optimization = true;
1917 }
1918
d2d7885f
AK
1919 if (stream->apply_seamless_boot_optimization)
1920 pipe_idx = acquire_resource_from_hw_enabled_state(
1921 &context->res_ctx,
1922 pool,
1923 stream);
1924
1925 if (pipe_idx < 0)
1926 /* acquire new resources */
1927 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1928
dc37a9a0 1929#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1930 if (pipe_idx < 0)
13ab1b44 1931 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1932#endif
13ab1b44 1933
c5b38aec 1934 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG
1935 return DC_NO_CONTROLLER_RESOURCE;
1936
1937 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1938
1939 pipe_ctx->stream_res.stream_enc =
78cc70b1 1940 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG
1941 &context->res_ctx, pool, stream);
1942
1943 if (!pipe_ctx->stream_res.stream_enc)
38684e46 1944 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG
1945
1946 update_stream_engine_usage(
1947 &context->res_ctx, pool,
1948 pipe_ctx->stream_res.stream_enc,
1949 true);
1950
1951 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 1952 if (!stream->converter_disable_audio &&
1dc90497 1953 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 1954 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 1955 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1956 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG
1957
1958 /*
1959 * Audio assigned in order first come first get.
1960 * There are asics which has number of audio
1961 * resources less then number of pipes
1962 */
1963 if (pipe_ctx->stream_res.audio)
1964 update_audio_usage(&context->res_ctx, pool,
1965 pipe_ctx->stream_res.audio, true);
1966 }
268cadbd 1967
9aef1a31
S
1968 /* Add ABM to the resource if on EDP */
1969 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1970 pipe_ctx->stream_res.abm = pool->abm;
1971
1dc90497
AG
1972 for (i = 0; i < context->stream_count; i++)
1973 if (context->streams[i] == stream) {
1974 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1975 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
5fdb7c4c
NK
1976 context->stream_status[i].audio_inst =
1977 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
1978
1dc90497
AG
1979 return DC_OK;
1980 }
4562236b 1981
1dc90497
AG
1982 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1983 return DC_ERROR_UNEXPECTED;
1984}
4562236b 1985
2119aa17
DF
1986/**
1987 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
1988 * Is a shallow copy. Increments refcounts on existing streams and planes.
1989 * @dc: copy out of dc->current_state
1990 * @dst_ctx: copy into this
1991 */
f36cc577 1992void dc_resource_state_copy_construct_current(
1dc90497 1993 const struct dc *dc,
608ac7bb 1994 struct dc_state *dst_ctx)
1dc90497 1995{
f36cc577 1996 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG
1997}
1998
ab8db3e1
AG
1999
2000void dc_resource_state_construct(
2001 const struct dc *dc,
2002 struct dc_state *dst_ctx)
2003{
dc88b4a6 2004 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG
2005}
2006
2119aa17
DF
2007/**
2008 * dc_validate_global_state() - Determine if HW can support a given state
2009 * Checks HW resource availability and bandwidth requirement.
2010 * @dc: dc struct for this driver
2011 * @new_ctx: state to be validated
afcd526b 2012 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF
2013 *
2014 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2015 */
e750d56d 2016enum dc_status dc_validate_global_state(
1dc90497 2017 struct dc *dc,
afcd526b
JA
2018 struct dc_state *new_ctx,
2019 bool fast_validate)
4562236b 2020{
1dc90497 2021 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2022 int i, j;
4562236b 2023
e41ab030
HW
2024 if (!new_ctx)
2025 return DC_ERROR_UNEXPECTED;
2026
d596e5d0 2027 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW
2028 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2029 if (result != DC_OK)
2030 return result;
d596e5d0 2031 }
4562236b 2032
e41ab030 2033 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG
2034 struct dc_stream_state *stream = new_ctx->streams[i];
2035
2036 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2037 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2038
2039 if (pipe_ctx->stream != stream)
2040 continue;
2041
74eac5f3
SSC
2042 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2043 pipe_ctx->plane_state &&
2044 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2045 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2046 if (result != DC_OK)
2047 return result;
2048 }
2049
1dc90497
AG
2050 /* Switch to dp clock source only if there is
2051 * no non dp stream that shares the same timing
2052 * with the dp stream.
2053 */
2054 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2055 !find_pll_sharable_stream(stream, new_ctx)) {
2056
9d0dcecd 2057 resource_unreference_clock_source(
1dc90497
AG
2058 &new_ctx->res_ctx,
2059 dc->res_pool,
9d0dcecd 2060 pipe_ctx->clock_source);
4a629536 2061
1dc90497
AG
2062 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2063 resource_reference_clock_source(
2064 &new_ctx->res_ctx,
2065 dc->res_pool,
2066 pipe_ctx->clock_source);
2067 }
2068 }
2069 }
2070
1dc90497
AG
2071 result = resource_build_scaling_params_for_context(dc, new_ctx);
2072
2073 if (result == DC_OK)
afcd526b 2074 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG
2075 result = DC_FAIL_BANDWIDTH_VALIDATE;
2076
2077 return result;
4562236b
HW
2078}
2079
6e4d6bee 2080static void patch_gamut_packet_checksum(
e09b6473 2081 struct dc_info_packet *gamut_packet)
4562236b 2082{
4562236b 2083 /* For gamut we recalc checksum */
6e4d6bee 2084 if (gamut_packet->valid) {
4562236b
HW
2085 uint8_t chk_sum = 0;
2086 uint8_t *ptr;
2087 uint8_t i;
2088
4562236b 2089 /*start of the Gamut data. */
6e4d6bee 2090 ptr = &gamut_packet->sb[3];
4562236b 2091
6e4d6bee 2092 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW
2093 chk_sum += ptr[i];
2094
6e4d6bee 2095 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2096 }
4562236b
HW
2097}
2098
2099static void set_avi_info_frame(
e09b6473 2100 struct dc_info_packet *info_packet,
4562236b
HW
2101 struct pipe_ctx *pipe_ctx)
2102{
0971c40e 2103 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2104 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW
2105 uint32_t pixel_encoding = 0;
2106 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2107 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2108 bool itc = false;
50e27654 2109 uint8_t itc_value = 0;
4562236b 2110 uint8_t cn0_cn1 = 0;
50e27654 2111 unsigned int cn0_cn1_value = 0;
4562236b
HW
2112 uint8_t *check_sum = NULL;
2113 uint8_t byte_index = 0;
754e3673 2114 union hdmi_info_packet hdmi_info;
50e27654 2115 union display_content_support support = {0};
4fa086b9 2116 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2117 enum dc_timing_3d_format format;
4562236b 2118
754e3673
AK
2119 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2120
4fa086b9 2121 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2122 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2123 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2124 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW
2125
2126 /* Initialize header */
e09b6473 2127 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW
2128 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2129 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK
2130 hdmi_info.bits.header.version = 2;
2131 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW
2132
2133 /*
2134 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2135 * according to HDMI 2.0 spec (Section 10.1)
2136 */
2137
4fa086b9 2138 switch (stream->timing.pixel_encoding) {
4562236b
HW
2139 case PIXEL_ENCODING_YCBCR422:
2140 pixel_encoding = 1;
2141 break;
2142
2143 case PIXEL_ENCODING_YCBCR444:
2144 pixel_encoding = 2;
2145 break;
2146 case PIXEL_ENCODING_YCBCR420:
2147 pixel_encoding = 3;
2148 break;
2149
2150 case PIXEL_ENCODING_RGB:
2151 default:
2152 pixel_encoding = 0;
2153 }
2154
2155 /* Y0_Y1_Y2 : The pixel encoding */
2156 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2157 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW
2158
2159 /* A0 = 1 Active Format Information valid */
e09b6473 2160 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW
2161
2162 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2163 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2164
e09b6473 2165 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW
2166
2167 /* S0, S1 : Underscan / Overscan */
2168 /* TODO: un-hardcode scan type */
2169 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2170 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW
2171
2172 /* C0, C1 : Colorimetry */
8fde5884 2173 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2174 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2175 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL
2176 else if (color_space == COLOR_SPACE_YCBCR601 ||
2177 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2178 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2179 else {
e09b6473 2180 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2181 }
534db198 2182 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL
2183 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2184 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK
2185 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2186 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2187 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK
2188 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2189 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ
2190 }
2191
4562236b 2192 /* TODO: un-hardcode aspect ratio */
4fa086b9 2193 aspect = stream->timing.aspect_ratio;
4562236b
HW
2194
2195 switch (aspect) {
2196 case ASPECT_RATIO_4_3:
2197 case ASPECT_RATIO_16_9:
e09b6473 2198 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW
2199 break;
2200
2201 case ASPECT_RATIO_NO_DATA:
2202 case ASPECT_RATIO_64_27:
2203 case ASPECT_RATIO_256_135:
2204 default:
e09b6473 2205 hdmi_info.bits.M0_M1 = 0;
4562236b
HW
2206 }
2207
2208 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2209 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW
2210
2211 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2212
4562236b 2213 cn0_cn1 = 0;
50e27654
ZF
2214 cn0_cn1_value = 0;
2215
2216 itc = true;
2217 itc_value = 1;
2218
ceb3dbb4 2219 support = stream->content_support;
4562236b
HW
2220
2221 if (itc) {
50e27654
ZF
2222 if (!support.bits.valid_content_type) {
2223 cn0_cn1_value = 0;
2224 } else {
2225 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2226 if (support.bits.graphics_content == 1) {
2227 cn0_cn1_value = 0;
2228 }
2229 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2230 if (support.bits.photo_content == 1) {
2231 cn0_cn1_value = 1;
2232 } else {
2233 cn0_cn1_value = 0;
2234 itc_value = 0;
2235 }
2236 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2237 if (support.bits.cinema_content == 1) {
2238 cn0_cn1_value = 2;
2239 } else {
2240 cn0_cn1_value = 0;
2241 itc_value = 0;
2242 }
2243 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2244 if (support.bits.game_content == 1) {
2245 cn0_cn1_value = 3;
2246 } else {
2247 cn0_cn1_value = 0;
2248 itc_value = 0;
2249 }
2250 }
2251 }
e09b6473
AK
2252 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2253 hdmi_info.bits.ITC = itc_value;
4562236b
HW
2254 }
2255
2256 /* TODO : We should handle YCC quantization */
2257 /* but we do not have matrix calculation */
ceb3dbb4
JL
2258 if (stream->qs_bit == 1 &&
2259 stream->qy_bit == 1) {
50e27654
ZF
2260 if (color_space == COLOR_SPACE_SRGB ||
2261 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK
2262 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2263 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF
2264 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2265 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK
2266 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2267 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2268 } else {
e09b6473
AK
2269 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2270 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2271 }
4562236b 2272 } else {
e09b6473
AK
2273 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2274 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2275 }
50e27654 2276
15e17335 2277 ///VIC
4fa086b9 2278 format = stream->timing.timing_3d_format;
15e17335
CL
2279 /*todo, add 3DStereo support*/
2280 if (format != TIMING_3D_FORMAT_NONE) {
2281 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2282 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL
2283 case 1:
2284 vic = 95;
2285 break;
2286 case 2:
2287 vic = 94;
2288 break;
2289 case 3:
2290 vic = 93;
2291 break;
2292 case 4:
2293 vic = 98;
2294 break;
2295 default:
2296 break;
2297 }
2298 }
efa02336 2299 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2300 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP
2301 if (vic >= 128)
2302 hdmi_info.bits.header.version = 3;
2303 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2304 * the Source shall use 20 AVI InfoFrame Version 4
2305 */
2306 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2307 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2308 hdmi_info.bits.header.version = 4;
2309 hdmi_info.bits.header.length = 14;
2310 }
4562236b
HW
2311
2312 /* pixel repetition
2313 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2314 * repetition start from 1 */
e09b6473 2315 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW
2316
2317 /* Bar Info
2318 * barTop: Line Number of End of Top Bar.
2319 * barBottom: Line Number of Start of Bottom Bar.
2320 * barLeft: Pixel Number of End of Left Bar.
2321 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK
2322 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2323 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2324 - stream->timing.v_border_bottom + 1);
e09b6473
AK
2325 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2326 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2327 - stream->timing.h_border_right + 1);
4562236b 2328
2f482c4f
CP
2329 /* Additional Colorimetry Extension
2330 * Used in conduction with C0-C1 and EC0-EC2
2331 * 0 = DCI-P3 RGB (D65)
2332 * 1 = DCI-P3 RGB (theater)
2333 */
2334 hdmi_info.bits.ACE0_ACE3 = 0;
2335
4562236b 2336 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2337 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2338
efa02336 2339 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2340
efa02336 2341 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2342 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2343
2344 /* one byte complement */
2345 *check_sum = (uint8_t) (0x100 - *check_sum);
2346
2347 /* Store in hw_path_mode */
e09b6473
AK
2348 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2349 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2350 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2351
e09b6473
AK
2352 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2353 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW
2354
2355 info_packet->valid = true;
2356}
2357
6e4d6bee 2358static void set_vendor_info_packet(
e09b6473 2359 struct dc_info_packet *info_packet,
0971c40e 2360 struct dc_stream_state *stream)
4562236b 2361{
ecd0136b 2362 /* SPD info packet for FreeSync */
4562236b 2363
ecd0136b
HT
2364 /* Check if Freesync is supported. Return if false. If true,
2365 * set the corresponding bit in the info packet
2366 */
2367 if (!stream->vsp_infopacket.valid)
4562236b
HW
2368 return;
2369
ecd0136b 2370 *info_packet = stream->vsp_infopacket;
4562236b
HW
2371}
2372
6e4d6bee 2373static void set_spd_info_packet(
e09b6473 2374 struct dc_info_packet *info_packet,
0971c40e 2375 struct dc_stream_state *stream)
4562236b
HW
2376{
2377 /* SPD info packet for FreeSync */
2378
4562236b
HW
2379 /* Check if Freesync is supported. Return if false. If true,
2380 * set the corresponding bit in the info packet
2381 */
98e6436d 2382 if (!stream->vrr_infopacket.valid)
4562236b
HW
2383 return;
2384
98e6436d 2385 *info_packet = stream->vrr_infopacket;
4562236b
HW
2386}
2387
1646a6fe 2388static void set_hdr_static_info_packet(
e09b6473 2389 struct dc_info_packet *info_packet,
0971c40e 2390 struct dc_stream_state *stream)
1646a6fe 2391{
0eeef690 2392 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2393
a10dc97a
KK
2394 if (!stream->hdr_static_metadata.valid ||
2395 stream->use_dynamic_meta)
10bff005
YS
2396 return;
2397
0eeef690 2398 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW
2399}
2400
6e4d6bee 2401static void set_vsc_info_packet(
e09b6473 2402 struct dc_info_packet *info_packet,
0971c40e 2403 struct dc_stream_state *stream)
4562236b 2404{
1336926f 2405 if (!stream->vsc_infopacket.valid)
4562236b
HW
2406 return;
2407
1336926f 2408 *info_packet = stream->vsc_infopacket;
4562236b
HW
2409}
2410
f36cc577 2411void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW
2412{
2413 int i, j;
2414
ab2541b6 2415 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW
2416 for (j = 0; j < context->stream_status[i].plane_count; j++)
2417 dc_plane_state_release(
2418 context->stream_status[i].plane_states[j]);
4562236b 2419
3be5262e 2420 context->stream_status[i].plane_count = 0;
4fa086b9 2421 dc_stream_release(context->streams[i]);
ab2541b6 2422 context->streams[i] = NULL;
4562236b
HW
2423 }
2424}
2425
f36cc577 2426void dc_resource_state_copy_construct(
608ac7bb
JZ
2427 const struct dc_state *src_ctx,
2428 struct dc_state *dst_ctx)
4562236b
HW
2429{
2430 int i, j;
8ee5702a 2431 struct kref refcount = dst_ctx->refcount;
4562236b
HW
2432
2433 *dst_ctx = *src_ctx;
2434
a2b8659d 2435 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW
2436 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2437
2438 if (cur_pipe->top_pipe)
2439 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2440
2441 if (cur_pipe->bottom_pipe)
2442 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL
2443
2444 if (cur_pipe->next_odm_pipe)
2445 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2446
2447 if (cur_pipe->prev_odm_pipe)
2448 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW
2449 }
2450
ab2541b6 2451 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2452 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW
2453 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2454 dc_plane_state_retain(
2455 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2456 }
9a3afbb3
AG
2457
2458 /* context refcount should not be overridden */
8ee5702a 2459 dst_ctx->refcount = refcount;
9a3afbb3 2460
4562236b
HW
2461}
2462
2463struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC
2464 struct resource_context *res_ctx,
2465 const struct resource_pool *pool)
4562236b
HW
2466{
2467 int i;
2468
a2b8659d 2469 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2470 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2471 return pool->clock_sources[i];
4562236b
HW
2472 }
2473
2474 return NULL;
2475}
2476
2477void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2478{
2479 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2480 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW
2481
2482 /* default all packets to invalid */
6e4d6bee
TC
2483 info->avi.valid = false;
2484 info->gamut.valid = false;
2485 info->vendor.valid = false;
630e3573 2486 info->spd.valid = false;
6e4d6bee
TC
2487 info->hdrsmd.valid = false;
2488 info->vsc.valid = false;
4562236b
HW
2489
2490 signal = pipe_ctx->stream->signal;
2491
2492 /* HDMi and DP have different info packets*/
2493 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC
2494 set_avi_info_frame(&info->avi, pipe_ctx);
2495
2496 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2497
2498 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2499
56ef6ed9 2500 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2501
a33fa99d 2502 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC
2503 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2504
2505 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2506
56ef6ed9 2507 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2508 }
4562236b 2509
6e4d6bee 2510 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW
2511}
2512
2513enum dc_status resource_map_clock_resources(
fb3466a4 2514 const struct dc *dc,
608ac7bb 2515 struct dc_state *context,
1dc90497 2516 struct dc_stream_state *stream)
4562236b 2517{
4562236b 2518 /* acquire new resources */
1dc90497
AG
2519 const struct resource_pool *pool = dc->res_pool;
2520 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2521 &context->res_ctx, stream);
ab2541b6 2522
1dc90497
AG
2523 if (!pipe_ctx)
2524 return DC_ERROR_UNEXPECTED;
4562236b 2525
1dc90497
AG
2526 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2527 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2528 pipe_ctx->clock_source = pool->dp_clock_source;
2529 else {
2530 pipe_ctx->clock_source = NULL;
4562236b 2531
1dc90497 2532 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2533 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG
2534 &context->res_ctx,
2535 pipe_ctx);
4562236b 2536
1dc90497
AG
2537 if (pipe_ctx->clock_source == NULL)
2538 pipe_ctx->clock_source =
2539 dc_resource_find_first_free_pll(
2540 &context->res_ctx,
2541 pool);
2542 }
4562236b 2543
1dc90497
AG
2544 if (pipe_ctx->clock_source == NULL)
2545 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2546
1dc90497
AG
2547 resource_reference_clock_source(
2548 &context->res_ctx, pool,
2549 pipe_ctx->clock_source);
4562236b
HW
2550
2551 return DC_OK;
2552}
2553
2554/*
2555 * Note: We need to disable output if clock sources change,
2556 * since bios does optimization and doesn't apply if changing
2557 * PHY when not already disabled.
2558 */
2559bool pipe_need_reprogram(
2560 struct pipe_ctx *pipe_ctx_old,
2561 struct pipe_ctx *pipe_ctx)
2562{
cfe4645e
DL
2563 if (!pipe_ctx_old->stream)
2564 return false;
2565
4562236b
HW
2566 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2567 return true;
2568
2569 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2570 return true;
2571
afaacef4 2572 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW
2573 return true;
2574
2575 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2576 && pipe_ctx_old->stream != pipe_ctx->stream)
2577 return true;
2578
8e9c4c8c 2579 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW
2580 return true;
2581
2582 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2583 return true;
2584
6b622181
JP
2585 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2586 return true;
4562236b 2587
1e7e86c4
ST
2588 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2589 return true;
2590
1336926f
A
2591 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2592 return true;
2593
eed928dc
CL
2594 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2595 false == pipe_ctx_old->stream->dpms_off)
2596 return true;
2597
4562236b
HW
2598 return false;
2599}
529cad0f 2600
0971c40e 2601void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW
2602 struct bit_depth_reduction_params *fmt_bit_depth)
2603{
4fa086b9 2604 enum dc_dither_option option = stream->dither_option;
529cad0f 2605 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2606 stream->timing.pixel_encoding;
529cad0f
DW
2607
2608 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2609
603767f9
TC
2610 if (option == DITHER_OPTION_DEFAULT) {
2611 switch (stream->timing.display_color_depth) {
2612 case COLOR_DEPTH_666:
2613 option = DITHER_OPTION_SPATIAL6;
2614 break;
2615 case COLOR_DEPTH_888:
2616 option = DITHER_OPTION_SPATIAL8;
2617 break;
2618 case COLOR_DEPTH_101010:
2619 option = DITHER_OPTION_SPATIAL10;
2620 break;
2621 default:
2622 option = DITHER_OPTION_DISABLE;
2623 }
2624 }
2625
529cad0f
DW
2626 if (option == DITHER_OPTION_DISABLE)
2627 return;
2628
2629 if (option == DITHER_OPTION_TRUN6) {
2630 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2631 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2632 } else if (option == DITHER_OPTION_TRUN8 ||
2633 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2634 option == DITHER_OPTION_TRUN8_FM6) {
2635 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2636 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2637 } else if (option == DITHER_OPTION_TRUN10 ||
2638 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2639 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2640 option == DITHER_OPTION_TRUN10_FM8 ||
2641 option == DITHER_OPTION_TRUN10_FM6 ||
2642 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2643 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2644 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2645 }
2646
2647 /* special case - Formatter can only reduce by 4 bits at most.
2648 * When reducing from 12 to 6 bits,
2649 * HW recommends we use trunc with round mode
2650 * (if we did nothing, trunc to 10 bits would be used)
2651 * note that any 12->10 bit reduction is ignored prior to DCE8,
2652 * as the input was 10 bits.
2653 */
2654 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2655 option == DITHER_OPTION_SPATIAL6 ||
2656 option == DITHER_OPTION_FM6) {
2657 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2658 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2659 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2660 }
2661
2662 /* spatial dither
2663 * note that spatial modes 1-3 are never used
2664 */
2665 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2666 option == DITHER_OPTION_SPATIAL6 ||
2667 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2668 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2669 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2670 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2671 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2672 fmt_bit_depth->flags.RGB_RANDOM =
2673 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2674 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2675 option == DITHER_OPTION_SPATIAL8 ||
2676 option == DITHER_OPTION_SPATIAL8_FM6 ||
2677 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2678 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2679 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2680 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2681 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2682 fmt_bit_depth->flags.RGB_RANDOM =
2683 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2684 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2685 option == DITHER_OPTION_SPATIAL10 ||
2686 option == DITHER_OPTION_SPATIAL10_FM8 ||
2687 option == DITHER_OPTION_SPATIAL10_FM6) {
2688 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2689 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2690 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2691 fmt_bit_depth->flags.RGB_RANDOM =
2692 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2693 }
2694
2695 if (option == DITHER_OPTION_SPATIAL6 ||
2696 option == DITHER_OPTION_SPATIAL8 ||
2697 option == DITHER_OPTION_SPATIAL10) {
2698 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2699 } else {
2700 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2701 }
2702
2703 //////////////////////
2704 //// temporal dither
2705 //////////////////////
2706 if (option == DITHER_OPTION_FM6 ||
2707 option == DITHER_OPTION_SPATIAL8_FM6 ||
2708 option == DITHER_OPTION_SPATIAL10_FM6 ||
2709 option == DITHER_OPTION_TRUN10_FM6 ||
2710 option == DITHER_OPTION_TRUN8_FM6 ||
2711 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2712 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2713 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2714 } else if (option == DITHER_OPTION_FM8 ||
2715 option == DITHER_OPTION_SPATIAL10_FM8 ||
2716 option == DITHER_OPTION_TRUN10_FM8) {
2717 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2718 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2719 } else if (option == DITHER_OPTION_FM10) {
2720 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2721 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2722 }
2723
2724 fmt_bit_depth->pixel_encoding = pixel_encoding;
2725}
9345d987 2726
62c933f9 2727enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2728{
fb3466a4 2729 struct dc *core_dc = dc;
ceb3dbb4 2730 struct dc_link *link = stream->link;
9345d987
AG
2731 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2732 enum dc_status res = DC_OK;
2733
4fa086b9 2734 calculate_phy_pix_clks(stream);
9345d987 2735
4fa086b9 2736 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG
2737 res = DC_FAIL_CONTROLLER_VALIDATE;
2738
248cbed6 2739 if (res == DC_OK) {
9345d987 2740 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2741 link->link_enc, stream))
9345d987 2742 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2743 }
9345d987
AG
2744
2745 /* TODO: validate audio ASIC caps, encoder */
2746
2747 if (res == DC_OK)
4fa086b9 2748 res = dc_link_validate_mode_timing(stream,
9345d987 2749 link,
4fa086b9 2750 &stream->timing);
9345d987 2751
62c933f9 2752 return res;
9345d987 2753}
792671d7 2754
62c933f9 2755enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2756{
62c933f9
YS
2757 enum dc_status res = DC_OK;
2758
792671d7 2759 /* TODO For now validates pixel format only */
8e7095b9 2760 if (dc->res_pool->funcs->validate_plane)
62c933f9 2761 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2762
62c933f9 2763 return res;
792671d7 2764}
74eac5f3
SSC
2765
2766unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2767{
2768 switch (format) {
2769 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2770 return 8;
2771 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2772 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2773 return 12;
2774 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2775 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2776 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2777 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2778 return 16;
2779 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2780 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2781 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2782 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2783 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2784 return 32;
2785 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2786 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2787 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2788 return 64;
2789 default:
2790 ASSERT_CRITICAL(false);
2791 return -1;
2792 }
2793}