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drm/amd/display: add fixed point fractional bit truncation function
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b 37#include "virtual/virtual_stream_encoder.h"
3b94a400 38#include "dpcd_defs.h"
4562236b
HW		 39
40#include "dce80/dce80_resource.h"
41#include "dce100/dce100_resource.h"
42#include "dce110/dce110_resource.h"
43#include "dce112/dce112_resource.h"
ff5ef992
AD		 44#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
45#include "dcn10/dcn10_resource.h"
46#endif
2c8ad2d5 47#include "dce120/dce120_resource.h"
5d4b05dd
BL		 48
49#define DC_LOGGER_INIT(logger)
50
4562236b
HW		 51enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
52{
53 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
54 switch (asic_id.chip_family) {
55
56 case FAMILY_CI:
4562236b
HW		 57 dc_version = DCE_VERSION_8_0;
58 break;
ebfdf0d0
AD		 59 case FAMILY_KV:
60 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
61 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
63 dc_version = DCE_VERSION_8_3;
64 else
65 dc_version = DCE_VERSION_8_1;
66 break;
4562236b
HW		 67 case FAMILY_CZ:
68 dc_version = DCE_VERSION_11_0;
69 break;
70
71 case FAMILY_VI:
72 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
74 dc_version = DCE_VERSION_10_0;
75 break;
76 }
77 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 78 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
79 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 80 dc_version = DCE_VERSION_11_2;
81 }
0c75d5ac
JFZ		 82 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
83 dc_version = DCE_VERSION_11_22;
4562236b 84 break;
2c8ad2d5
AD		 85 case FAMILY_AI:
86 dc_version = DCE_VERSION_12_0;
87 break;
ff5ef992
AD		 88#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
89 case FAMILY_RV:
90 dc_version = DCN_VERSION_1_0;
91 break;
92#endif
4562236b
HW		 93 default:
94 dc_version = DCE_VERSION_UNKNOWN;
95 break;
96 }
97 return dc_version;
98}
99
100struct resource_pool *dc_create_resource_pool(
fb3466a4 101 struct dc *dc,
4562236b
HW		 102 int num_virtual_links,
103 enum dce_version dc_version,
104 struct hw_asic_id asic_id)
105{
5ac3d3c9 106 struct resource_pool *res_pool = NULL;
4562236b
HW		 107
108 switch (dc_version) {
109 case DCE_VERSION_8_0:
7992a629
AD		 110 res_pool = dce80_create_resource_pool(
111 num_virtual_links, dc);
112 break;
ebfdf0d0 113 case DCE_VERSION_8_1:
7992a629
AD		 114 res_pool = dce81_create_resource_pool(
115 num_virtual_links, dc);
116 break;
ebfdf0d0 117 case DCE_VERSION_8_3:
7992a629 118 res_pool = dce83_create_resource_pool(
4562236b 119 num_virtual_links, dc);
5ac3d3c9 120 break;
4562236b 121 case DCE_VERSION_10_0:
5ac3d3c9 122 res_pool = dce100_create_resource_pool(
4562236b 123 num_virtual_links, dc);
5ac3d3c9 124 break;
4562236b 125 case DCE_VERSION_11_0:
5ac3d3c9 126 res_pool = dce110_create_resource_pool(
4562236b 127 num_virtual_links, dc, asic_id);
5ac3d3c9 128 break;
4562236b 129 case DCE_VERSION_11_2:
0c75d5ac 130 case DCE_VERSION_11_22:
5ac3d3c9 131 res_pool = dce112_create_resource_pool(
4562236b 132 num_virtual_links, dc);
5ac3d3c9 133 break;
2c8ad2d5
AD		 134 case DCE_VERSION_12_0:
135 res_pool = dce120_create_resource_pool(
136 num_virtual_links, dc);
137 break;
ff5ef992
AD		 138
139#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
140 case DCN_VERSION_1_0:
141 res_pool = dcn10_create_resource_pool(
503a7c6f 142 num_virtual_links, dc);
ff5ef992
AD		 143 break;
144#endif
3639fa68
ZF		 145
146
4562236b
HW		 147 default:
148 break;
149 }
5ac3d3c9 150 if (res_pool != NULL) {
1515a47b 151 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 152
153 if (dc->ctx->dc_bios->funcs->get_firmware_info(
154 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
155 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
156 } else
157 ASSERT_CRITICAL(false);
158 }
4562236b 159
5ac3d3c9 160 return res_pool;
4562236b
HW		 161}
162
fb3466a4 163void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 164{
165 if (dc) {
166 if (dc->res_pool)
167 dc->res_pool->funcs->destroy(&dc->res_pool);
168
d029810c 169 kfree(dc->hwseq);
4562236b
HW		 170 }
171}
172
173static void update_num_audio(
174 const struct resource_straps *straps,
175 unsigned int *num_audio,
176 struct audio_support *aud_support)
177{
b8e9eb72
CL		 178 aud_support->dp_audio = true;
179 aud_support->hdmi_audio_native = false;
180 aud_support->hdmi_audio_on_dongle = false;
181
4562236b 182 if (straps->hdmi_disable == 0) {
4562236b
HW		 183 if (straps->dc_pinstraps_audio & 0x2) {
184 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 185 aud_support->hdmi_audio_native = true;
4562236b
HW		 186 }
187 }
188
189 switch (straps->audio_stream_number) {
190 case 0: /* multi streams supported */
191 break;
192 case 1: /* multi streams not supported */
193 *num_audio = 1;
194 break;
195 default:
196 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 197 }
4562236b
HW		 198}
199
200bool resource_construct(
201 unsigned int num_virtual_links,
fb3466a4 202 struct dc *dc,
4562236b
HW		 203 struct resource_pool *pool,
204 const struct resource_create_funcs *create_funcs)
205{
206 struct dc_context *ctx = dc->ctx;
207 const struct resource_caps *caps = pool->res_cap;
208 int i;
209 unsigned int num_audio = caps->num_audio;
210 struct resource_straps straps = {0};
211
212 if (create_funcs->read_dce_straps)
213 create_funcs->read_dce_straps(dc->ctx, &straps);
214
215 pool->audio_count = 0;
216 if (create_funcs->create_audio) {
217 /* find the total number of streams available via the
218 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
219 * registers (one for each pin) starting from pin 1
220 * up to the max number of audio pins.
221 * We stop on the first pin where
222 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
223 */
224 update_num_audio(&straps, &num_audio, &pool->audio_support);
225 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
226 struct audio *aud = create_funcs->create_audio(ctx, i);
227
228 if (aud == NULL) {
229 DC_ERR("DC: failed to create audio!\n");
230 return false;
231 }
232
233 if (!aud->funcs->endpoint_valid(aud)) {
234 aud->funcs->destroy(&aud);
235 break;
236 }
237
238 pool->audios[i] = aud;
239 pool->audio_count++;
240 }
241 }
242
243 pool->stream_enc_count = 0;
244 if (create_funcs->create_stream_encoder) {
245 for (i = 0; i < caps->num_stream_encoder; i++) {
246 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
247 if (pool->stream_enc[i] == NULL)
248 DC_ERR("DC: failed to create stream_encoder!\n");
249 pool->stream_enc_count++;
250 }
251 }
4176664b
CL		 252 dc->caps.dynamic_audio = false;
253 if (pool->audio_count < pool->stream_enc_count) {
254 dc->caps.dynamic_audio = true;
255 }
4562236b
HW		 256 for (i = 0; i < num_virtual_links; i++) {
257 pool->stream_enc[pool->stream_enc_count] =
258 virtual_stream_encoder_create(
259 ctx, ctx->dc_bios);
260 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
261 DC_ERR("DC: failed to create stream_encoder!\n");
262 return false;
263 }
264 pool->stream_enc_count++;
265 }
266
267 dc->hwseq = create_funcs->create_hwseq(ctx);
268
269 return true;
270}
271
272
21e67d4d 273void resource_unreference_clock_source(
4562236b 274 struct resource_context *res_ctx,
a2b8659d 275 const struct resource_pool *pool,
4a629536 276 struct clock_source *clock_source)
4562236b
HW		 277{
278 int i;
4a629536 279
a2b8659d 280 for (i = 0; i < pool->clk_src_count; i++) {
4a629536 281 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 282 continue;
283
284 res_ctx->clock_source_ref_count[i]--;
285
4562236b
HW		 286 break;
287 }
288
21e67d4d 289 if (pool->dp_clock_source == clock_source)
4562236b 290 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 291}
292
293void resource_reference_clock_source(
294 struct resource_context *res_ctx,
a2b8659d 295 const struct resource_pool *pool,
4562236b
HW		 296 struct clock_source *clock_source)
297{
298 int i;
a2b8659d
TC		 299 for (i = 0; i < pool->clk_src_count; i++) {
300 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 301 continue;
302
303 res_ctx->clock_source_ref_count[i]++;
304 break;
305 }
306
a2b8659d 307 if (pool->dp_clock_source == clock_source)
4562236b
HW		 308 res_ctx->dp_clock_source_ref_count++;
309}
310
311bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 312 struct dc_stream_state *stream1,
313 struct dc_stream_state *stream2)
4562236b 314{
4fa086b9 315 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 316 return false;
317
4fa086b9 318 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 319 return false;
320
4fa086b9
LSL		 321 if (stream1->timing.h_addressable
322 != stream2->timing.h_addressable)
4562236b
HW		 323 return false;
324
4fa086b9
LSL		 325 if (stream1->timing.v_addressable
326 != stream2->timing.v_addressable)
4562236b
HW		 327 return false;
328
4fa086b9
LSL		 329 if (stream1->timing.pix_clk_khz
330 != stream2->timing.pix_clk_khz)
4562236b
HW		 331 return false;
332
333 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 334 && (!dc_is_dp_signal(stream1->signal)
335 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 336 return false;
337
338 return true;
339}
340
341static bool is_sharable_clk_src(
342 const struct pipe_ctx *pipe_with_clk_src,
343 const struct pipe_ctx *pipe)
344{
345 if (pipe_with_clk_src->clock_source == NULL)
346 return false;
347
348 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
349 return false;
350
351 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
352 return false;
353
354 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
355 && dc_is_dvi_signal(pipe->stream->signal))
356 return false;
357
358 if (dc_is_hdmi_signal(pipe->stream->signal)
359 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
360 return false;
361
362 if (!resource_are_streams_timing_synchronizable(
363 pipe_with_clk_src->stream, pipe->stream))
364 return false;
365
366 return true;
367}
368
369struct clock_source *resource_find_used_clk_src_for_sharing(
370 struct resource_context *res_ctx,
371 struct pipe_ctx *pipe_ctx)
372{
373 int i;
374
375 for (i = 0; i < MAX_PIPES; i++) {
376 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
377 return res_ctx->pipe_ctx[i].clock_source;
378 }
379
380 return NULL;
381}
382
383static enum pixel_format convert_pixel_format_to_dalsurface(
384 enum surface_pixel_format surface_pixel_format)
385{
386 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
387
388 switch (surface_pixel_format) {
389 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
390 dal_pixel_format = PIXEL_FORMAT_INDEX8;
391 break;
392 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
393 dal_pixel_format = PIXEL_FORMAT_RGB565;
394 break;
395 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
396 dal_pixel_format = PIXEL_FORMAT_RGB565;
397 break;
398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
399 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
400 break;
8693049a 401 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 402 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
403 break;
404 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
406 break;
407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
408 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
409 break;
410 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
411 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
412 break;
413 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
414 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
415 dal_pixel_format = PIXEL_FORMAT_FP16;
416 break;
417 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 418 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 419 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 420 break;
ffbcd19a
VP		 421 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
422 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 423 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 424 break;
4562236b
HW		 425 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
426 default:
427 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
428 break;
429 }
430 return dal_pixel_format;
431}
432
433static void rect_swap_helper(struct rect *rect)
434{
99676f20
GS		 435 swap(rect->height, rect->width);
436 swap(rect->x, rect->y);
4562236b
HW		 437}
438
b2d0a103 439static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 440{
3be5262e 441 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 442 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 443 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 444 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 445 struct rect clip = { 0 };
87449a90
AK		 446 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
447 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 448 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 449 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 450 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 451 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 452
7f5c22d1
VP		 453 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
454 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 455 pri_split = false;
456 sec_split = false;
457 }
86006a7f 458
3be5262e
HW		 459 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
460 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 461 rect_swap_helper(&surf_src);
462
4562236b
HW		 463 /* The actual clip is an intersection between stream
464 * source and surface clip
465 */
3be5262e
HW		 466 clip.x = stream->src.x > plane_state->clip_rect.x ?
467 stream->src.x : plane_state->clip_rect.x;
4562236b 468
1fbd2cfc 469 clip.width = stream->src.x + stream->src.width <
3be5262e 470 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 471 stream->src.x + stream->src.width - clip.x :
3be5262e 472 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 473
3be5262e
HW		 474 clip.y = stream->src.y > plane_state->clip_rect.y ?
475 stream->src.y : plane_state->clip_rect.y;
4562236b 476
1fbd2cfc 477 clip.height = stream->src.y + stream->src.height <
3be5262e 478 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 479 stream->src.y + stream->src.height - clip.y :
3be5262e 480 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 481
86006a7f 482 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 483 * num_pixels = clip.num_pix * scl_ratio
484 */
3be5262e
HW		 485 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
486 surf_src.width / plane_state->dst_rect.width;
b2d0a103 487 data->viewport.width = clip.width *
3be5262e 488 surf_src.width / plane_state->dst_rect.width;
4562236b 489
3be5262e
HW		 490 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
491 surf_src.height / plane_state->dst_rect.height;
b2d0a103 492 data->viewport.height = clip.height *
3be5262e 493 surf_src.height / plane_state->dst_rect.height;
4562236b 494
b2d0a103
DL		 495 /* Round down, compensate in init */
496 data->viewport_c.x = data->viewport.x / vpc_div;
497 data->viewport_c.y = data->viewport.y / vpc_div;
498 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
eb0e5154 499 dc_fixpt_half : dc_fixpt_zero;
b2d0a103 500 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
eb0e5154 501 dc_fixpt_half : dc_fixpt_zero;
b2d0a103
DL		 502 /* Round up, assume original video size always even dimensions */
503 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
504 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
505
506 /* Handle hsplit */
0c31a821
YS		 507 if (sec_split) {
508 data->viewport.x += data->viewport.width / 2;
509 data->viewport_c.x += data->viewport_c.width / 2;
510 /* Ceil offset pipe */
511 data->viewport.width = (data->viewport.width + 1) / 2;
512 data->viewport_c.width = (data->viewport_c.width + 1) / 2;
513 } else if (pri_split) {
514 data->viewport.width /= 2;
515 data->viewport_c.width /= 2;
b2d0a103 516 }
1fbd2cfc 517
3be5262e
HW		 518 if (plane_state->rotation == ROTATION_ANGLE_90 ||
519 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 520 rect_swap_helper(&data->viewport_c);
521 rect_swap_helper(&data->viewport);
522 }
4562236b
HW		 523}
524
b2d0a103 525static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 526{
3be5262e 527 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 528 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW		 529 struct rect surf_src = plane_state->src_rect;
530 struct rect surf_clip = plane_state->clip_rect;
c802570e 531 int recout_full_x, recout_full_y;
0c31a821
YS		 532 bool pri_split = pipe_ctx->bottom_pipe &&
533 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
534 bool sec_split = pipe_ctx->top_pipe &&
535 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 536 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 537
3be5262e
HW		 538 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
539 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 540 rect_swap_helper(&surf_src);
541
6702a9ac 542 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 543 if (stream->src.x < surf_clip.x)
6702a9ac 544 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 545 - stream->src.x) * stream->dst.width
546 / stream->src.width;
4562236b 547
6702a9ac 548 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 549 stream->dst.width / stream->src.width;
6702a9ac 550 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 551 stream->dst.x + stream->dst.width)
6702a9ac 552 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 553 stream->dst.x + stream->dst.width
6702a9ac 554 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 555
6702a9ac 556 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 557 if (stream->src.y < surf_clip.y)
6702a9ac 558 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 559 - stream->src.y) * stream->dst.height
560 / stream->src.height;
4562236b 561
6702a9ac 562 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 563 stream->dst.height / stream->src.height;
6702a9ac 564 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 565 stream->dst.y + stream->dst.height)
6702a9ac 566 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 567 stream->dst.y + stream->dst.height
6702a9ac 568 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 569
7b779c99 570 /* Handle h & vsplit */
b0131391
DL		 571 if (sec_split && top_bottom_split) {
572 pipe_ctx->plane_res.scl_data.recout.y +=
573 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 574 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 575 pipe_ctx->plane_res.scl_data.recout.height =
576 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
577 } else if (pri_split && top_bottom_split)
0c31a821 578 pipe_ctx->plane_res.scl_data.recout.height /= 2;
b0131391 579 else if (pri_split || sec_split) {
0c31a821
YS		 580 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
581 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
582 (plane_state->rotation == ROTATION_ANGLE_180);
583
584 if (plane_state->rotation == ROTATION_ANGLE_90
585 || plane_state->rotation == ROTATION_ANGLE_270)
586 /* Secondary_pipe XOR Rotation_270 */
587 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
588
589 if (right_view) {
590 pipe_ctx->plane_res.scl_data.recout.x +=
591 pipe_ctx->plane_res.scl_data.recout.width / 2;
592 /* Ceil offset pipe */
593 pipe_ctx->plane_res.scl_data.recout.width =
594 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
595 } else {
6702a9ac 596 pipe_ctx->plane_res.scl_data.recout.width /= 2;
0c31a821 597 }
b2d0a103 598 }
86006a7f
DL		 599 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
600 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 601 * ratio)
602 */
b0131391 603 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 604 * stream->dst.width / stream->src.width -
3be5262e 605 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 606 * stream->dst.width / stream->src.width;
b0131391 607 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 608 * stream->dst.height / stream->src.height -
3be5262e 609 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 610 * stream->dst.height / stream->src.height;
c802570e 611
6702a9ac
HW		 612 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
613 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
4562236b
HW		 614}
615
b2d0a103 616static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 617{
3be5262e 618 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 619 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 620 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 621 const int in_w = stream->src.width;
622 const int in_h = stream->src.height;
623 const int out_w = stream->dst.width;
624 const int out_h = stream->dst.height;
4562236b 625
3be5262e
HW		 626 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
627 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 628 rect_swap_helper(&surf_src);
629
eb0e5154 630 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 631 surf_src.width,
3be5262e 632 plane_state->dst_rect.width);
eb0e5154 633 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 634 surf_src.height,
3be5262e 635 plane_state->dst_rect.height);
4562236b 636
4fa086b9 637 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 638 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 639 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 640 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 641
6702a9ac
HW		 642 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
643 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
644 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
645 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 646
6702a9ac
HW		 647 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
648 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 649
6702a9ac
HW		 650 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
651 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
652 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
653 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b
HW		 654 }
655}
656
b2d0a103
DL		 657static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
658{
6702a9ac 659 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 660 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK		 661 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
662 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b0131391 663 bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
b2d0a103 664
b0131391
DL		 665 /*
666 * Need to calculate the scan direction for viewport to make adjustments
667 */
668 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
669 flip_vert_scan_dir = true;
670 flip_horz_scan_dir = true;
671 } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
672 flip_vert_scan_dir = true;
673 else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
674 flip_horz_scan_dir = true;
675 if (pipe_ctx->plane_state->horizontal_mirror)
676 flip_horz_scan_dir = !flip_horz_scan_dir;
677
3be5262e
HW		 678 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
679 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 680 rect_swap_helper(&src);
1fbd2cfc
DL		 681 rect_swap_helper(&data->viewport_c);
682 rect_swap_helper(&data->viewport);
683 }
684
b2d0a103
DL		 685 /*
686 * Init calculated according to formula:
687 * init = (scaling_ratio + number_of_taps + 1) / 2
688 * init_bot = init + scaling_ratio
689 * init_c = init + truncated_vp_c_offset(from calculate viewport)
690 */
eb0e5154
DL		 691 data->inits.h = dc_fixpt_div_int(
692 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
b2d0a103 693
eb0e5154
DL		 694 data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
695 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
b2d0a103 696
eb0e5154
DL		 697 data->inits.v = dc_fixpt_div_int(
698 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
b2d0a103 699
eb0e5154
DL		 700 data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
701 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
b2d0a103
DL		 702
703
704 /* Adjust for viewport end clip-off */
4ee778dc 705 if ((data->viewport.x + data->viewport.width) < (src.x + src.width) && !flip_horz_scan_dir) {
b2d0a103 706 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
eb0e5154
DL		 707 int int_part = dc_fixpt_floor(
708 dc_fixpt_sub(data->inits.h, data->ratios.horz));
b2d0a103 709
1fbd2cfc 710 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 711 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
712 }
4ee778dc 713 if ((data->viewport.y + data->viewport.height) < (src.y + src.height) && !flip_vert_scan_dir) {
b2d0a103 714 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
eb0e5154
DL		 715 int int_part = dc_fixpt_floor(
716 dc_fixpt_sub(data->inits.v, data->ratios.vert));
b2d0a103 717
1fbd2cfc 718 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 719 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
720 }
4ee778dc 721 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div && !flip_horz_scan_dir) {
b2d0a103
DL		 722 int vp_clip = (src.x + src.width) / vpc_div -
723 data->viewport_c.width - data->viewport_c.x;
eb0e5154
DL		 724 int int_part = dc_fixpt_floor(
725 dc_fixpt_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 726
1fbd2cfc 727 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 728 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
729 }
4ee778dc 730 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div && !flip_vert_scan_dir) {
b2d0a103
DL		 731 int vp_clip = (src.y + src.height) / vpc_div -
732 data->viewport_c.height - data->viewport_c.y;
eb0e5154
DL		 733 int int_part = dc_fixpt_floor(
734 dc_fixpt_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 735
1fbd2cfc 736 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 737 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
738 }
739
740 /* Adjust for non-0 viewport offset */
737ae4ea 741 if (data->viewport.x && !flip_horz_scan_dir) {
b2d0a103
DL		 742 int int_part;
743
eb0e5154 744 data->inits.h = dc_fixpt_add(data->inits.h, dc_fixpt_mul_int(
b2d0a103 745 data->ratios.horz, recout_skip->width));
eb0e5154 746 int_part = dc_fixpt_floor(data->inits.h) - data->viewport.x;
b2d0a103
DL		 747 if (int_part < data->taps.h_taps) {
748 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
749 (data->taps.h_taps - int_part) : data->viewport.x;
750 data->viewport.x -= int_adj;
751 data->viewport.width += int_adj;
752 int_part += int_adj;
753 } else if (int_part > data->taps.h_taps) {
754 data->viewport.x += int_part - data->taps.h_taps;
755 data->viewport.width -= int_part - data->taps.h_taps;
756 int_part = data->taps.h_taps;
757 }
758 data->inits.h.value &= 0xffffffff;
eb0e5154 759 data->inits.h = dc_fixpt_add_int(data->inits.h, int_part);
b2d0a103
DL		 760 }
761
737ae4ea 762 if (data->viewport_c.x && !flip_horz_scan_dir) {
b2d0a103
DL		 763 int int_part;
764
eb0e5154 765 data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_mul_int(
b2d0a103 766 data->ratios.horz_c, recout_skip->width));
eb0e5154 767 int_part = dc_fixpt_floor(data->inits.h_c) - data->viewport_c.x;
b2d0a103
DL		 768 if (int_part < data->taps.h_taps_c) {
769 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
770 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
771 data->viewport_c.x -= int_adj;
772 data->viewport_c.width += int_adj;
773 int_part += int_adj;
774 } else if (int_part > data->taps.h_taps_c) {
775 data->viewport_c.x += int_part - data->taps.h_taps_c;
776 data->viewport_c.width -= int_part - data->taps.h_taps_c;
777 int_part = data->taps.h_taps_c;
778 }
779 data->inits.h_c.value &= 0xffffffff;
eb0e5154 780 data->inits.h_c = dc_fixpt_add_int(data->inits.h_c, int_part);
b2d0a103
DL		 781 }
782
737ae4ea 783 if (data->viewport.y && !flip_vert_scan_dir) {
b2d0a103
DL		 784 int int_part;
785
eb0e5154 786 data->inits.v = dc_fixpt_add(data->inits.v, dc_fixpt_mul_int(
b2d0a103 787 data->ratios.vert, recout_skip->height));
eb0e5154 788 int_part = dc_fixpt_floor(data->inits.v) - data->viewport.y;
b2d0a103
DL		 789 if (int_part < data->taps.v_taps) {
790 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
791 (data->taps.v_taps - int_part) : data->viewport.y;
792 data->viewport.y -= int_adj;
793 data->viewport.height += int_adj;
794 int_part += int_adj;
795 } else if (int_part > data->taps.v_taps) {
796 data->viewport.y += int_part - data->taps.v_taps;
797 data->viewport.height -= int_part - data->taps.v_taps;
798 int_part = data->taps.v_taps;
799 }
800 data->inits.v.value &= 0xffffffff;
eb0e5154 801 data->inits.v = dc_fixpt_add_int(data->inits.v, int_part);
b2d0a103
DL		 802 }
803
737ae4ea 804 if (data->viewport_c.y && !flip_vert_scan_dir) {
b2d0a103
DL		 805 int int_part;
806
eb0e5154 807 data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_mul_int(
b2d0a103 808 data->ratios.vert_c, recout_skip->height));
eb0e5154 809 int_part = dc_fixpt_floor(data->inits.v_c) - data->viewport_c.y;
b2d0a103
DL		 810 if (int_part < data->taps.v_taps_c) {
811 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
812 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
813 data->viewport_c.y -= int_adj;
814 data->viewport_c.height += int_adj;
815 int_part += int_adj;
816 } else if (int_part > data->taps.v_taps_c) {
817 data->viewport_c.y += int_part - data->taps.v_taps_c;
818 data->viewport_c.height -= int_part - data->taps.v_taps_c;
819 int_part = data->taps.v_taps_c;
820 }
821 data->inits.v_c.value &= 0xffffffff;
eb0e5154 822 data->inits.v_c = dc_fixpt_add_int(data->inits.v_c, int_part);
b2d0a103
DL		 823 }
824
825 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 826 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
827 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 828
3be5262e
HW		 829 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
830 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 831 rect_swap_helper(&data->viewport_c);
832 rect_swap_helper(&data->viewport);
833 }
b2d0a103
DL		 834}
835
836bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 837{
3be5262e 838 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 839 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103
DL		 840 struct view recout_skip = { 0 };
841 bool res = false;
5d4b05dd 842 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 843 /* Important: scaling ratio calculation requires pixel format,
844 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 845 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 846 */
6702a9ac 847 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 848 pipe_ctx->plane_state->format);
b2d0a103 849
dc002a2e
DL		 850 if (pipe_ctx->stream->timing.flags.INTERLACE)
851 pipe_ctx->stream->dst.height *= 2;
852
b2d0a103 853 calculate_scaling_ratios(pipe_ctx);
4562236b 854
b2d0a103 855 calculate_viewport(pipe_ctx);
4562236b 856
6702a9ac 857 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 858 return false;
859
b2d0a103 860 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 861
862 /**
863 * Setting line buffer pixel depth to 24bpp yields banding
864 * on certain displays, such as the Sharp 4k
865 */
6702a9ac 866 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 867
199e458a 868 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 869 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 870
58bb0e63
AJ		 871 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
872 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
dc002a2e
DL		 873 if (pipe_ctx->stream->timing.flags.INTERLACE)
874 pipe_ctx->plane_res.scl_data.v_active *= 2;
4562236b 875
1b6c8067 876
4562236b 877 /* Taps calculations */
d94585a0
YHL		 878 if (pipe_ctx->plane_res.xfm != NULL)
879 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
880 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
881
882 if (pipe_ctx->plane_res.dpp != NULL)
883 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
884 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 885 if (!res) {
886 /* Try 24 bpp linebuffer */
6702a9ac 887 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 888
1b6c8067
BL		 889 if (pipe_ctx->plane_res.xfm != NULL)
890 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
891 pipe_ctx->plane_res.xfm,
892 &pipe_ctx->plane_res.scl_data,
893 &plane_state->scaling_quality);
894
895 if (pipe_ctx->plane_res.dpp != NULL)
896 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
897 pipe_ctx->plane_res.dpp,
898 &pipe_ctx->plane_res.scl_data,
899 &plane_state->scaling_quality);
4562236b
HW		 900 }
901
b2d0a103 902 if (res)
1fbd2cfc 903 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 904 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
905
1296423b 906 DC_LOG_SCALER(
4562236b
HW		 907 "%s: Viewport:\nheight:%d width:%d x:%d "
908 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
909 "y:%d\n",
910 __func__,
6702a9ac
HW		 911 pipe_ctx->plane_res.scl_data.viewport.height,
912 pipe_ctx->plane_res.scl_data.viewport.width,
913 pipe_ctx->plane_res.scl_data.viewport.x,
914 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 915 plane_state->dst_rect.height,
916 plane_state->dst_rect.width,
917 plane_state->dst_rect.x,
918 plane_state->dst_rect.y);
4562236b 919
dc002a2e
DL		 920 if (pipe_ctx->stream->timing.flags.INTERLACE)
921 pipe_ctx->stream->dst.height /= 2;
922
4562236b
HW		 923 return res;
924}
925
926
927enum dc_status resource_build_scaling_params_for_context(
fb3466a4 928 const struct dc *dc,
608ac7bb 929 struct dc_state *context)
4562236b
HW		 930{
931 int i;
932
933 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 934 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 935 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 936 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 937 return DC_FAIL_SCALING;
4562236b
HW		 938 }
939
940 return DC_OK;
941}
942
a2b8659d
TC		 943struct pipe_ctx *find_idle_secondary_pipe(
944 struct resource_context *res_ctx,
945 const struct resource_pool *pool)
4562236b
HW		 946{
947 int i;
948 struct pipe_ctx *secondary_pipe = NULL;
949
950 /*
951 * search backwards for the second pipe to keep pipe
952 * assignment more consistent
953 */
954
a2b8659d 955 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 956 if (res_ctx->pipe_ctx[i].stream == NULL) {
957 secondary_pipe = &res_ctx->pipe_ctx[i];
958 secondary_pipe->pipe_idx = i;
959 break;
960 }
961 }
962
963
964 return secondary_pipe;
965}
966
967struct pipe_ctx *resource_get_head_pipe_for_stream(
968 struct resource_context *res_ctx,
0971c40e 969 struct dc_stream_state *stream)
4562236b
HW		 970{
971 int i;
a2b8659d 972 for (i = 0; i < MAX_PIPES; i++) {
4562236b 973 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 974 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 975 return &res_ctx->pipe_ctx[i];
976 break;
977 }
978 }
979 return NULL;
980}
981
19f89e23
AG		 982static struct pipe_ctx *resource_get_tail_pipe_for_stream(
983 struct resource_context *res_ctx,
984 struct dc_stream_state *stream)
985{
986 struct pipe_ctx *head_pipe, *tail_pipe;
987 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
988
989 if (!head_pipe)
990 return NULL;
991
992 tail_pipe = head_pipe->bottom_pipe;
993
994 while (tail_pipe) {
995 head_pipe = tail_pipe;
996 tail_pipe = tail_pipe->bottom_pipe;
997 }
998
999 return head_pipe;
1000}
1001
4562236b 1002/*
ab2541b6
AC		 1003 * A free_pipe for a stream is defined here as a pipe
1004 * that has no surface attached yet
4562236b 1005 */
ab2541b6 1006static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1007 struct dc_state *context,
a2b8659d 1008 const struct resource_pool *pool,
0971c40e 1009 struct dc_stream_state *stream)
4562236b
HW		 1010{
1011 int i;
745cc746 1012 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1013
1014 struct pipe_ctx *head_pipe = NULL;
1015
1016 /* Find head pipe, which has the back end set up*/
1017
1018 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1019
e41ab030 1020 if (!head_pipe) {
4562236b 1021 ASSERT(0);
e41ab030
HW		 1022 return NULL;
1023 }
4562236b 1024
3be5262e 1025 if (!head_pipe->plane_state)
4562236b
HW		 1026 return head_pipe;
1027
1028 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1029 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1030 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1031 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1032 return &res_ctx->pipe_ctx[i];
1033 }
1034 }
1035
1036 /*
1037 * At this point we have no re-useable pipe for this stream and we need
1038 * to acquire an idle one to satisfy the request
1039 */
1040
a2b8659d 1041 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1042 return NULL;
1043
a2b8659d 1044 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1045
1046}
1047
0f9a536f
DL		 1048#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1049static int acquire_first_split_pipe(
1050 struct resource_context *res_ctx,
1051 const struct resource_pool *pool,
0971c40e 1052 struct dc_stream_state *stream)
0f9a536f
DL		 1053{
1054 int i;
1055
1056 for (i = 0; i < pool->pipe_count; i++) {
1057 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1058
1059 if (pipe_ctx->top_pipe &&
3be5262e 1060 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1061 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1062 if (pipe_ctx->bottom_pipe)
1063 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1064
1065 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1066 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1067 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1068 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1069 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1070 pipe_ctx->stream_res.opp = pool->opps[i];
e07f541f 1071 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
0f9a536f 1072 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1073
1074 pipe_ctx->stream = stream;
1075 return i;
1076 }
1077 }
1078 return -1;
1079}
1080#endif
1081
19f89e23
AG		 1082bool dc_add_plane_to_context(
1083 const struct dc *dc,
0971c40e 1084 struct dc_stream_state *stream,
19f89e23 1085 struct dc_plane_state *plane_state,
608ac7bb 1086 struct dc_state *context)
4562236b
HW		 1087{
1088 int i;
19f89e23
AG		 1089 struct resource_pool *pool = dc->res_pool;
1090 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1091 struct dc_stream_status *stream_status = NULL;
4562236b 1092
19f89e23
AG		 1093 for (i = 0; i < context->stream_count; i++)
1094 if (context->streams[i] == stream) {
1095 stream_status = &context->stream_status[i];
1096 break;
1097 }
1098 if (stream_status == NULL) {
1099 dm_error("Existing stream not found; failed to attach surface!\n");
1100 return false;
1101 }
1102
4562236b 1103
19f89e23
AG		 1104 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1105 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1106 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1107 return false;
1108 }
1109
19f89e23
AG		 1110 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1111
1112 if (!head_pipe) {
1113 dm_error("Head pipe not found for stream_state %p !\n", stream);
1114 return false;
1115 }
1116
19f89e23
AG		 1117 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1118
1119#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1120 if (!free_pipe) {
1121 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1122 if (pipe_idx >= 0)
1123 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1124 }
1125#endif
abb4986e 1126 if (!free_pipe)
19f89e23 1127 return false;
19f89e23 1128
abb4986e
AJ		 1129 /* retain new surfaces */
1130 dc_plane_state_retain(plane_state);
19f89e23
AG		 1131 free_pipe->plane_state = plane_state;
1132
1133 if (head_pipe != free_pipe) {
1134
1135 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1136 ASSERT(tail_pipe);
1137
1138 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1139 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1140 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1141 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1142 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1143 free_pipe->clock_source = tail_pipe->clock_source;
1144 free_pipe->top_pipe = tail_pipe;
1145 tail_pipe->bottom_pipe = free_pipe;
1146 }
1147
1148 /* assign new surfaces*/
1149 stream_status->plane_states[stream_status->plane_count] = plane_state;
1150
1151 stream_status->plane_count++;
1152
1153 return true;
1154}
1155
1156bool dc_remove_plane_from_context(
1157 const struct dc *dc,
1158 struct dc_stream_state *stream,
1159 struct dc_plane_state *plane_state,
608ac7bb 1160 struct dc_state *context)
19f89e23
AG		 1161{
1162 int i;
1163 struct dc_stream_status *stream_status = NULL;
1164 struct resource_pool *pool = dc->res_pool;
1165
ab2541b6 1166 for (i = 0; i < context->stream_count; i++)
4fa086b9 1167 if (context->streams[i] == stream) {
ab2541b6 1168 stream_status = &context->stream_status[i];
4562236b
HW		 1169 break;
1170 }
19f89e23 1171
ab2541b6 1172 if (stream_status == NULL) {
19f89e23 1173 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1174 return false;
1175 }
1176
19f89e23
AG		 1177 /* release pipe for plane*/
1178 for (i = pool->pipe_count - 1; i >= 0; i--) {
1179 struct pipe_ctx *pipe_ctx;
4562236b 1180
19f89e23
AG		 1181 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1182 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1183
19f89e23
AG		 1184 if (pipe_ctx->top_pipe)
1185 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1186
19f89e23
AG		 1187 /* Second condition is to avoid setting NULL to top pipe
1188 * of tail pipe making it look like head pipe in subsequent
1189 * deletes
1190 */
1191 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1192 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1193
19f89e23
AG		 1194 /*
1195 * For head pipe detach surfaces from pipe for tail
1196 * pipe just zero it out
1197 */
1198 if (!pipe_ctx->top_pipe) {
1199 pipe_ctx->plane_state = NULL;
1200 pipe_ctx->bottom_pipe = NULL;
1201 } else {
1202 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1203 }
4562236b 1204 }
19f89e23 1205 }
4562236b 1206
4562236b 1207
19f89e23
AG		 1208 for (i = 0; i < stream_status->plane_count; i++) {
1209 if (stream_status->plane_states[i] == plane_state) {
1210
1211 dc_plane_state_release(stream_status->plane_states[i]);
1212 break;
4562236b 1213 }
19f89e23 1214 }
4562236b 1215
19f89e23
AG		 1216 if (i == stream_status->plane_count) {
1217 dm_error("Existing plane_state not found; failed to detach it!\n");
1218 return false;
4562236b
HW		 1219 }
1220
19f89e23 1221 stream_status->plane_count--;
4562236b 1222
abb4986e
AJ		 1223 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1224 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1225 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1226
1227 stream_status->plane_states[stream_status->plane_count] = NULL;
1228
1229 return true;
1230}
1231
1232bool dc_rem_all_planes_for_stream(
1233 const struct dc *dc,
1234 struct dc_stream_state *stream,
608ac7bb 1235 struct dc_state *context)
19f89e23
AG		 1236{
1237 int i, old_plane_count;
1238 struct dc_stream_status *stream_status = NULL;
1239 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1240
1241 for (i = 0; i < context->stream_count; i++)
1242 if (context->streams[i] == stream) {
1243 stream_status = &context->stream_status[i];
1244 break;
1245 }
1246
1247 if (stream_status == NULL) {
1248 dm_error("Existing stream %p not found!\n", stream);
1249 return false;
1250 }
1251
1252 old_plane_count = stream_status->plane_count;
1253
1254 for (i = 0; i < old_plane_count; i++)
1255 del_planes[i] = stream_status->plane_states[i];
1256
1257 for (i = 0; i < old_plane_count; i++)
1258 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1259 return false;
1260
1261 return true;
1262}
1263
1264static bool add_all_planes_for_stream(
1265 const struct dc *dc,
1266 struct dc_stream_state *stream,
1267 const struct dc_validation_set set[],
1268 int set_count,
608ac7bb 1269 struct dc_state *context)
19f89e23
AG		 1270{
1271 int i, j;
1272
1273 for (i = 0; i < set_count; i++)
1274 if (set[i].stream == stream)
1275 break;
1276
1277 if (i == set_count) {
1278 dm_error("Stream %p not found in set!\n", stream);
1279 return false;
1280 }
4562236b 1281
19f89e23
AG		 1282 for (j = 0; j < set[i].plane_count; j++)
1283 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1284 return false;
4562236b
HW		 1285
1286 return true;
1287}
1288
19f89e23
AG		 1289bool dc_add_all_planes_for_stream(
1290 const struct dc *dc,
1291 struct dc_stream_state *stream,
1292 struct dc_plane_state * const *plane_states,
1293 int plane_count,
608ac7bb 1294 struct dc_state *context)
19f89e23
AG		 1295{
1296 struct dc_validation_set set;
1297 int i;
1298
1299 set.stream = stream;
1300 set.plane_count = plane_count;
1301
1302 for (i = 0; i < plane_count; i++)
1303 set.plane_states[i] = plane_states[i];
1304
1305 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1306}
1307
1308
6b622181
JP		 1309static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1310 struct dc_stream_state *new_stream)
1311{
1312 if (cur_stream == NULL)
1313 return true;
1314
1315 if (memcmp(&cur_stream->hdr_static_metadata,
1316 &new_stream->hdr_static_metadata,
1317 sizeof(struct dc_info_packet)) != 0)
1318 return true;
1319
1320 return false;
1321}
4562236b 1322
0971c40e
HW		 1323static bool is_timing_changed(struct dc_stream_state *cur_stream,
1324 struct dc_stream_state *new_stream)
4562236b
HW		 1325{
1326 if (cur_stream == NULL)
1327 return true;
1328
1329 /* If sink pointer changed, it means this is a hotplug, we should do
1330 * full hw setting.
1331 */
1332 if (cur_stream->sink != new_stream->sink)
1333 return true;
1334
1335 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1336 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1337 return true;
1338
1339 return memcmp(
4fa086b9
LSL		 1340 &cur_stream->timing,
1341 &new_stream->timing,
4562236b
HW		 1342 sizeof(struct dc_crtc_timing)) != 0;
1343}
1344
1345static bool are_stream_backends_same(
0971c40e 1346 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1347{
1348 if (stream_a == stream_b)
1349 return true;
1350
1351 if (stream_a == NULL || stream_b == NULL)
1352 return false;
1353
1354 if (is_timing_changed(stream_a, stream_b))
1355 return false;
1356
6b622181
JP		 1357 if (is_hdr_static_meta_changed(stream_a, stream_b))
1358 return false;
1359
4562236b
HW		 1360 return true;
1361}
1362
d54d29db 1363bool dc_is_stream_unchanged(
0971c40e 1364 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1365{
4562236b 1366
ab2541b6
AC		 1367 if (!are_stream_backends_same(old_stream, stream))
1368 return false;
4562236b
HW		 1369
1370 return true;
1371}
1372
9a5d9c48
LSL		 1373bool dc_is_stream_scaling_unchanged(
1374 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1375{
1376 if (old_stream == stream)
1377 return true;
1378
1379 if (old_stream == NULL || stream == NULL)
1380 return false;
1381
1382 if (memcmp(&old_stream->src,
1383 &stream->src,
1384 sizeof(struct rect)) != 0)
1385 return false;
1386
1387 if (memcmp(&old_stream->dst,
1388 &stream->dst,
1389 sizeof(struct rect)) != 0)
1390 return false;
1391
1392 return true;
1393}
1394
1dc90497 1395static void update_stream_engine_usage(
4562236b 1396 struct resource_context *res_ctx,
a2b8659d 1397 const struct resource_pool *pool,
1dc90497
AG		 1398 struct stream_encoder *stream_enc,
1399 bool acquired)
4562236b
HW		 1400{
1401 int i;
1402
a2b8659d
TC		 1403 for (i = 0; i < pool->stream_enc_count; i++) {
1404 if (pool->stream_enc[i] == stream_enc)
1dc90497 1405 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1406 }
1407}
1408
1409/* TODO: release audio object */
4176664b 1410void update_audio_usage(
4562236b 1411 struct resource_context *res_ctx,
a2b8659d 1412 const struct resource_pool *pool,
1dc90497
AG		 1413 struct audio *audio,
1414 bool acquired)
4562236b
HW		 1415{
1416 int i;
a2b8659d
TC		 1417 for (i = 0; i < pool->audio_count; i++) {
1418 if (pool->audios[i] == audio)
1dc90497 1419 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1420 }
1421}
1422
1423static int acquire_first_free_pipe(
1424 struct resource_context *res_ctx,
a2b8659d 1425 const struct resource_pool *pool,
0971c40e 1426 struct dc_stream_state *stream)
4562236b
HW		 1427{
1428 int i;
1429
a2b8659d 1430 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1431 if (!res_ctx->pipe_ctx[i].stream) {
1432 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1433
6b670fa9 1434 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1435 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1436 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1437 pipe_ctx->plane_res.ipp = pool->ipps[i];
1438 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1439 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1440 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1441 if (pool->dpps[i])
1442 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1443 pipe_ctx->pipe_idx = i;
1444
ff5ef992 1445
4562236b
HW		 1446 pipe_ctx->stream = stream;
1447 return i;
1448 }
1449 }
1450 return -1;
1451}
1452
1453static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1454 struct resource_context *res_ctx,
a2b8659d 1455 const struct resource_pool *pool,
0971c40e 1456 struct dc_stream_state *stream)
4562236b
HW		 1457{
1458 int i;
1459 int j = -1;
d0778ebf 1460 struct dc_link *link = stream->sink->link;
4562236b 1461
a2b8659d 1462 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1463 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1464 pool->stream_enc[i]) {
4562236b
HW		 1465 /* Store first available for MST second display
1466 * in daisy chain use case */
1467 j = i;
a2b8659d 1468 if (pool->stream_enc[i]->id ==
4562236b 1469 link->link_enc->preferred_engine)
a2b8659d 1470 return pool->stream_enc[i];
4562236b
HW		 1471 }
1472 }
1473
1474 /*
1475 * below can happen in cases when stream encoder is acquired:
1476 * 1) for second MST display in chain, so preferred engine already
1477 * acquired;
1478 * 2) for another link, which preferred engine already acquired by any
1479 * MST configuration.
1480 *
1481 * If signal is of DP type and preferred engine not found, return last available
1482 *
1483 * TODO - This is just a patch up and a generic solution is
1484 * required for non DP connectors.
1485 */
1486
1487 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1488 return pool->stream_enc[j];
4562236b
HW		 1489
1490 return NULL;
1491}
1492
a2b8659d
TC		 1493static struct audio *find_first_free_audio(
1494 struct resource_context *res_ctx,
cfb071f7
CL		 1495 const struct resource_pool *pool,
1496 enum engine_id id)
4562236b
HW		 1497{
1498 int i;
66bfd4fd
CL		 1499 for (i = 0; i < pool->audio_count; i++) {
1500 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1501 /*we have enough audio endpoint, find the matching inst*/
1502 if (id != i)
1503 continue;
1504
66bfd4fd 1505 return pool->audios[i];
4562236b 1506 }
66bfd4fd
CL		 1507 }
1508 /*not found the matching one, first come first serve*/
1509 for (i = 0; i < pool->audio_count; i++) {
1510 if (res_ctx->is_audio_acquired[i] == false) {
1511 return pool->audios[i];
4176664b
CL		 1512 }
1513 }
4562236b
HW		 1514 return 0;
1515}
1516
4562236b 1517bool resource_is_stream_unchanged(
608ac7bb 1518 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1519{
ab2541b6 1520 int i;
4562236b 1521
ab2541b6 1522 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1523 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1524
ab2541b6 1525 if (are_stream_backends_same(old_stream, stream))
4562236b 1526 return true;
4562236b
HW		 1527 }
1528
1529 return false;
1530}
1531
13ab1b44 1532enum dc_status dc_add_stream_to_ctx(
1dc90497 1533 struct dc *dc,
608ac7bb 1534 struct dc_state *new_ctx,
1dc90497
AG		 1535 struct dc_stream_state *stream)
1536{
1537 struct dc_context *dc_ctx = dc->ctx;
1538 enum dc_status res;
1539
1540 if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
1541 DC_ERROR("Max streams reached, can add stream %p !\n", stream);
1542 return DC_ERROR_UNEXPECTED;
1543 }
1544
1545 new_ctx->streams[new_ctx->stream_count] = stream;
1546 dc_stream_retain(stream);
1547 new_ctx->stream_count++;
1548
1549 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1550 if (res != DC_OK)
1551 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1552
13ab1b44 1553 return res;
1dc90497
AG		 1554}
1555
62c933f9 1556enum dc_status dc_remove_stream_from_ctx(
1dc90497 1557 struct dc *dc,
608ac7bb 1558 struct dc_state *new_ctx,
1dc90497
AG		 1559 struct dc_stream_state *stream)
1560{
19f89e23 1561 int i;
1dc90497
AG		 1562 struct dc_context *dc_ctx = dc->ctx;
1563 struct pipe_ctx *del_pipe = NULL;
1564
19f89e23 1565 /* Release primary pipe */
1dc90497 1566 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1567 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1568 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1569 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1570
19f89e23
AG		 1571 ASSERT(del_pipe->stream_res.stream_enc);
1572 update_stream_engine_usage(
1573 &new_ctx->res_ctx,
1dc90497 1574 dc->res_pool,
19f89e23
AG		 1575 del_pipe->stream_res.stream_enc,
1576 false);
1dc90497
AG		 1577
1578 if (del_pipe->stream_res.audio)
1579 update_audio_usage(
1580 &new_ctx->res_ctx,
1581 dc->res_pool,
1582 del_pipe->stream_res.audio,
1583 false);
1584
9d0dcecd
HW		 1585 resource_unreference_clock_source(&new_ctx->res_ctx,
1586 dc->res_pool,
1587 del_pipe->clock_source);
1588
e56ae556
NC		 1589 if (dc->res_pool->funcs->remove_stream_from_ctx)
1590 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1591
1dc90497 1592 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG		 1593
1594 break;
1dc90497
AG		 1595 }
1596 }
1597
1598 if (!del_pipe) {
1599 DC_ERROR("Pipe not found for stream %p !\n", stream);
1600 return DC_ERROR_UNEXPECTED;
1601 }
1602
1603 for (i = 0; i < new_ctx->stream_count; i++)
1604 if (new_ctx->streams[i] == stream)
1605 break;
1606
1607 if (new_ctx->streams[i] != stream) {
1608 DC_ERROR("Context doesn't have stream %p !\n", stream);
1609 return DC_ERROR_UNEXPECTED;
1610 }
1611
1612 dc_stream_release(new_ctx->streams[i]);
1613 new_ctx->stream_count--;
1614
1dc90497
AG		 1615 /* Trim back arrays */
1616 for (; i < new_ctx->stream_count; i++) {
1617 new_ctx->streams[i] = new_ctx->streams[i + 1];
1618 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1619 }
1620
1621 new_ctx->streams[new_ctx->stream_count] = NULL;
1622 memset(
1623 &new_ctx->stream_status[new_ctx->stream_count],
1624 0,
1625 sizeof(new_ctx->stream_status[0]));
1626
1627 return DC_OK;
1628}
1629
0971c40e
HW		 1630static struct dc_stream_state *find_pll_sharable_stream(
1631 struct dc_stream_state *stream_needs_pll,
608ac7bb 1632 struct dc_state *context)
4562236b 1633{
ab2541b6 1634 int i;
4562236b 1635
ab2541b6 1636 for (i = 0; i < context->stream_count; i++) {
0971c40e 1637 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1638
ab2541b6
AC		 1639 /* We are looking for non dp, non virtual stream */
1640 if (resource_are_streams_timing_synchronizable(
1641 stream_needs_pll, stream_has_pll)
1642 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1643 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1644 != SIGNAL_TYPE_VIRTUAL)
1645 return stream_has_pll;
4562236b 1646
4562236b
HW		 1647 }
1648
1649 return NULL;
1650}
1651
1652static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1653{
1654 uint32_t pix_clk = timing->pix_clk_khz;
1655 uint32_t normalized_pix_clk = pix_clk;
1656
1657 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1658 pix_clk /= 2;
cc4d99b8
CL		 1659 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1660 switch (timing->display_color_depth) {
1661 case COLOR_DEPTH_888:
1662 normalized_pix_clk = pix_clk;
1663 break;
1664 case COLOR_DEPTH_101010:
1665 normalized_pix_clk = (pix_clk * 30) / 24;
1666 break;
1667 case COLOR_DEPTH_121212:
1668 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1669 break;
cc4d99b8
CL		 1670 case COLOR_DEPTH_161616:
1671 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1672 break;
cc4d99b8
CL		 1673 default:
1674 ASSERT(0);
4562236b 1675 break;
cc4d99b8 1676 }
4562236b 1677 }
4562236b
HW		 1678 return normalized_pix_clk;
1679}
1680
0971c40e 1681static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1682{
9345d987
AG		 1683 /* update actual pixel clock on all streams */
1684 if (dc_is_hdmi_signal(stream->signal))
1685 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1686 &stream->timing);
9345d987
AG		 1687 else
1688 stream->phy_pix_clk =
4fa086b9 1689 stream->timing.pix_clk_khz;
4562236b
HW		 1690}
1691
1692enum dc_status resource_map_pool_resources(
fb3466a4 1693 const struct dc *dc,
608ac7bb 1694 struct dc_state *context,
1dc90497 1695 struct dc_stream_state *stream)
4562236b 1696{
a2b8659d 1697 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1698 int i;
1699 struct dc_context *dc_ctx = dc->ctx;
1700 struct pipe_ctx *pipe_ctx = NULL;
1701 int pipe_idx = -1;
4562236b 1702
1dc90497
AG		 1703 /* TODO Check if this is needed */
1704 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1705 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1706 stream->bit_depth_params =
430ef426
DL		 1707 old_context->streams[i]->bit_depth_params;
1708 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1709 continue;
1710 }
4b679bc3 1711 }
1dc90497 1712 */
7e2fe319 1713
1dc90497
AG		 1714 /* acquire new resources */
1715 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1716
94c6d735 1717#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1718 if (pipe_idx < 0)
13ab1b44 1719 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1720#endif
13ab1b44 1721
c5b38aec 1722 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1723 return DC_NO_CONTROLLER_RESOURCE;
1724
1725 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1726
1727 pipe_ctx->stream_res.stream_enc =
1728 find_first_free_match_stream_enc_for_link(
1729 &context->res_ctx, pool, stream);
1730
1731 if (!pipe_ctx->stream_res.stream_enc)
1732 return DC_NO_STREAM_ENG_RESOURCE;
1733
1734 update_stream_engine_usage(
1735 &context->res_ctx, pool,
1736 pipe_ctx->stream_res.stream_enc,
1737 true);
1738
1739 /* TODO: Add check if ASIC support and EDID audio */
1740 if (!stream->sink->converter_disable_audio &&
1741 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1742 stream->audio_info.mode_count) {
1743 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1744 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1745
1746 /*
1747 * Audio assigned in order first come first get.
1748 * There are asics which has number of audio
1749 * resources less then number of pipes
1750 */
1751 if (pipe_ctx->stream_res.audio)
1752 update_audio_usage(&context->res_ctx, pool,
1753 pipe_ctx->stream_res.audio, true);
1754 }
268cadbd 1755
9aef1a31
S		 1756 /* Add ABM to the resource if on EDP */
1757 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1758 pipe_ctx->stream_res.abm = pool->abm;
1759
1dc90497
AG		 1760 for (i = 0; i < context->stream_count; i++)
1761 if (context->streams[i] == stream) {
1762 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1763 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1764 return DC_OK;
1765 }
4562236b 1766
1dc90497
AG		 1767 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1768 return DC_ERROR_UNEXPECTED;
1769}
4562236b 1770
f36cc577 1771void dc_resource_state_copy_construct_current(
1dc90497 1772 const struct dc *dc,
608ac7bb 1773 struct dc_state *dst_ctx)
1dc90497 1774{
f36cc577 1775 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1776}
1777
ab8db3e1
AG		 1778
1779void dc_resource_state_construct(
1780 const struct dc *dc,
1781 struct dc_state *dst_ctx)
1782{
1783 dst_ctx->dis_clk = dc->res_pool->display_clock;
1784}
1785
e750d56d 1786enum dc_status dc_validate_global_state(
1dc90497 1787 struct dc *dc,
608ac7bb 1788 struct dc_state *new_ctx)
4562236b 1789{
1dc90497 1790 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1791 int i, j;
4562236b 1792
e41ab030
HW		 1793 if (!new_ctx)
1794 return DC_ERROR_UNEXPECTED;
1795
d596e5d0 1796 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 1797 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1798 if (result != DC_OK)
1799 return result;
d596e5d0 1800 }
4562236b 1801
e41ab030 1802 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 1803 struct dc_stream_state *stream = new_ctx->streams[i];
1804
1805 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1806 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1807
1808 if (pipe_ctx->stream != stream)
1809 continue;
1810
1811 /* Switch to dp clock source only if there is
1812 * no non dp stream that shares the same timing
1813 * with the dp stream.
1814 */
1815 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1816 !find_pll_sharable_stream(stream, new_ctx)) {
1817
9d0dcecd 1818 resource_unreference_clock_source(
1dc90497
AG		 1819 &new_ctx->res_ctx,
1820 dc->res_pool,
9d0dcecd 1821 pipe_ctx->clock_source);
4a629536 1822
1dc90497
AG		 1823 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1824 resource_reference_clock_source(
1825 &new_ctx->res_ctx,
1826 dc->res_pool,
1827 pipe_ctx->clock_source);
1828 }
1829 }
1830 }
1831
1dc90497
AG		 1832 result = resource_build_scaling_params_for_context(dc, new_ctx);
1833
1834 if (result == DC_OK)
1835 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1836 result = DC_FAIL_BANDWIDTH_VALIDATE;
1837
1838 return result;
4562236b
HW		 1839}
1840
6e4d6bee 1841static void patch_gamut_packet_checksum(
e09b6473 1842 struct dc_info_packet *gamut_packet)
4562236b 1843{
4562236b 1844 /* For gamut we recalc checksum */
6e4d6bee 1845 if (gamut_packet->valid) {
4562236b
HW		 1846 uint8_t chk_sum = 0;
1847 uint8_t *ptr;
1848 uint8_t i;
1849
4562236b 1850 /*start of the Gamut data. */
6e4d6bee 1851 ptr = &gamut_packet->sb[3];
4562236b 1852
6e4d6bee 1853 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1854 chk_sum += ptr[i];
1855
6e4d6bee 1856 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1857 }
4562236b
HW		 1858}
1859
1860static void set_avi_info_frame(
e09b6473 1861 struct dc_info_packet *info_packet,
4562236b
HW		 1862 struct pipe_ctx *pipe_ctx)
1863{
0971c40e 1864 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 1865 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 1866 uint32_t pixel_encoding = 0;
1867 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1868 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1869 bool itc = false;
50e27654 1870 uint8_t itc_value = 0;
4562236b 1871 uint8_t cn0_cn1 = 0;
50e27654 1872 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1873 uint8_t *check_sum = NULL;
1874 uint8_t byte_index = 0;
754e3673 1875 union hdmi_info_packet hdmi_info;
50e27654 1876 union display_content_support support = {0};
4fa086b9 1877 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 1878 enum dc_timing_3d_format format;
4562236b 1879
754e3673
AK		 1880 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
1881
4fa086b9 1882 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 1883 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 1884 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 1885 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1886
1887 /* Initialize header */
e09b6473 1888 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1889 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1890 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 1891 hdmi_info.bits.header.version = 2;
1892 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1893
1894 /*
1895 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1896 * according to HDMI 2.0 spec (Section 10.1)
1897 */
1898
4fa086b9 1899 switch (stream->timing.pixel_encoding) {
4562236b
HW		 1900 case PIXEL_ENCODING_YCBCR422:
1901 pixel_encoding = 1;
1902 break;
1903
1904 case PIXEL_ENCODING_YCBCR444:
1905 pixel_encoding = 2;
1906 break;
1907 case PIXEL_ENCODING_YCBCR420:
1908 pixel_encoding = 3;
1909 break;
1910
1911 case PIXEL_ENCODING_RGB:
1912 default:
1913 pixel_encoding = 0;
1914 }
1915
1916 /* Y0_Y1_Y2 : The pixel encoding */
1917 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 1918 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1919
1920 /* A0 = 1 Active Format Information valid */
e09b6473 1921 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1922
1923 /* B0, B1 = 3; Bar info data is valid */
e09b6473 1924 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1925
e09b6473 1926 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1927
1928 /* S0, S1 : Underscan / Overscan */
1929 /* TODO: un-hardcode scan type */
1930 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 1931 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 1932
1933 /* C0, C1 : Colorimetry */
8fde5884 1934 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1935 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 1936 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1937 else if (color_space == COLOR_SPACE_YCBCR601 ||
1938 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 1939 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 1940 else {
e09b6473 1941 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1942 }
534db198 1943 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1944 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1945 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 1946 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1947 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1948 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 1949 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1950 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1951 }
1952
4562236b 1953 /* TODO: un-hardcode aspect ratio */
4fa086b9 1954 aspect = stream->timing.aspect_ratio;
4562236b
HW		 1955
1956 switch (aspect) {
1957 case ASPECT_RATIO_4_3:
1958 case ASPECT_RATIO_16_9:
e09b6473 1959 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 1960 break;
1961
1962 case ASPECT_RATIO_NO_DATA:
1963 case ASPECT_RATIO_64_27:
1964 case ASPECT_RATIO_256_135:
1965 default:
e09b6473 1966 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 1967 }
1968
1969 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 1970 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1971
1972 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1973
4562236b 1974 cn0_cn1 = 0;
50e27654
ZF		 1975 cn0_cn1_value = 0;
1976
1977 itc = true;
1978 itc_value = 1;
1979
4fa086b9 1980 support = stream->sink->edid_caps.content_support;
4562236b
HW		 1981
1982 if (itc) {
50e27654
ZF		 1983 if (!support.bits.valid_content_type) {
1984 cn0_cn1_value = 0;
1985 } else {
1986 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1987 if (support.bits.graphics_content == 1) {
1988 cn0_cn1_value = 0;
1989 }
1990 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1991 if (support.bits.photo_content == 1) {
1992 cn0_cn1_value = 1;
1993 } else {
1994 cn0_cn1_value = 0;
1995 itc_value = 0;
1996 }
1997 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1998 if (support.bits.cinema_content == 1) {
1999 cn0_cn1_value = 2;
2000 } else {
2001 cn0_cn1_value = 0;
2002 itc_value = 0;
2003 }
2004 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2005 if (support.bits.game_content == 1) {
2006 cn0_cn1_value = 3;
2007 } else {
2008 cn0_cn1_value = 0;
2009 itc_value = 0;
2010 }
2011 }
2012 }
e09b6473
AK		 2013 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2014 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2015 }
2016
2017 /* TODO : We should handle YCC quantization */
2018 /* but we do not have matrix calculation */
4fa086b9
LSL		 2019 if (stream->sink->edid_caps.qs_bit == 1 &&
2020 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 2021 if (color_space == COLOR_SPACE_SRGB ||
2022 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2023 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2024 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2025 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2026 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2027 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2028 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2029 } else {
e09b6473
AK		 2030 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2031 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2032 }
4562236b 2033 } else {
e09b6473
AK		 2034 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2035 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2036 }
50e27654 2037
15e17335 2038 ///VIC
4fa086b9 2039 format = stream->timing.timing_3d_format;
15e17335
CL		 2040 /*todo, add 3DStereo support*/
2041 if (format != TIMING_3D_FORMAT_NONE) {
2042 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2043 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2044 case 1:
2045 vic = 95;
2046 break;
2047 case 2:
2048 vic = 94;
2049 break;
2050 case 3:
2051 vic = 93;
2052 break;
2053 case 4:
2054 vic = 98;
2055 break;
2056 default:
2057 break;
2058 }
2059 }
e09b6473 2060 hdmi_info.bits.VIC0_VIC7 = vic;
4562236b
HW		 2061
2062 /* pixel repetition
2063 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2064 * repetition start from 1 */
e09b6473 2065 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2066
2067 /* Bar Info
2068 * barTop: Line Number of End of Top Bar.
2069 * barBottom: Line Number of Start of Bottom Bar.
2070 * barLeft: Pixel Number of End of Left Bar.
2071 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2072 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2073 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2074 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2075 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2076 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2077 - stream->timing.h_border_right + 1);
4562236b
HW		 2078
2079 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2080 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2081
3e183c5f 2082 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2083
3e183c5f 2084 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e09b6473 2085 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2086
2087 /* one byte complement */
2088 *check_sum = (uint8_t) (0x100 - *check_sum);
2089
2090 /* Store in hw_path_mode */
e09b6473
AK		 2091 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2092 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2093 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2094
e09b6473
AK		 2095 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2096 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2097
2098 info_packet->valid = true;
2099}
2100
6e4d6bee 2101static void set_vendor_info_packet(
e09b6473 2102 struct dc_info_packet *info_packet,
0971c40e 2103 struct dc_stream_state *stream)
4562236b
HW		 2104{
2105 uint32_t length = 0;
2106 bool hdmi_vic_mode = false;
2107 uint8_t checksum = 0;
2108 uint32_t i = 0;
2109 enum dc_timing_3d_format format;
15e17335
CL		 2110 // Can be different depending on packet content /*todo*/
2111 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2112
2113 info_packet->valid = false;
4562236b 2114
4fa086b9
LSL		 2115 format = stream->timing.timing_3d_format;
2116 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2117 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2118
2119 /* Can be different depending on packet content */
2120 length = 5;
2121
4fa086b9
LSL		 2122 if (stream->timing.hdmi_vic != 0
2123 && stream->timing.h_total >= 3840
2124 && stream->timing.v_total >= 2160)
4562236b
HW		 2125 hdmi_vic_mode = true;
2126
2127 /* According to HDMI 1.4a CTS, VSIF should be sent
2128 * for both 3D stereo and HDMI VIC modes.
2129 * For all other modes, there is no VSIF sent. */
2130
2131 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2132 return;
2133
2134 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2135 info_packet->sb[1] = 0x03;
2136 info_packet->sb[2] = 0x0C;
2137 info_packet->sb[3] = 0x00;
2138
2139 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2140 * The value for HDMI_Video_Format are:
2141 * 0x0 (0b000) - No additional HDMI video format is presented in this
2142 * packet
2143 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2144 * parameter follows
2145 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2146 * potentially 3D_Ext_Data follows
2147 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2148 if (format != TIMING_3D_FORMAT_NONE)
2149 info_packet->sb[4] = (2 << 5);
2150 else if (hdmi_vic_mode)
2151 info_packet->sb[4] = (1 << 5);
2152
2153 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2154 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2155 * The value for 3D_Structure are:
2156 * 0x0 - Frame Packing
2157 * 0x1 - Field Alternative
2158 * 0x2 - Line Alternative
2159 * 0x3 - Side-by-Side (full)
2160 * 0x4 - L + depth
2161 * 0x5 - L + depth + graphics + graphics-depth
2162 * 0x6 - Top-and-Bottom
2163 * 0x7 - Reserved for future use
2164 * 0x8 - Side-by-Side (Half)
2165 * 0x9..0xE - Reserved for future use
2166 * 0xF - Not used */
2167 switch (format) {
2168 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2169 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2170 info_packet->sb[5] = (0x0 << 4);
2171 break;
2172
2173 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2174 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2175 info_packet->sb[5] = (0x8 << 4);
2176 length = 6;
2177 break;
2178
2179 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2180 case TIMING_3D_FORMAT_TB_SW_PACKED:
2181 info_packet->sb[5] = (0x6 << 4);
2182 break;
2183
2184 default:
2185 break;
2186 }
2187
2188 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2189 * fill PB5 with the correct HDMI VIC code */
2190 if (hdmi_vic_mode)
4fa086b9 2191 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2192
2193 /* Header */
3e183c5f 2194 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2195 info_packet->hb1 = 0x01; /* Version */
2196
2197 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2198 info_packet->hb2 = (uint8_t) (length);
2199
2200 /* Calculate checksum */
2201 checksum = 0;
2202 checksum += info_packet->hb0;
2203 checksum += info_packet->hb1;
2204 checksum += info_packet->hb2;
2205
2206 for (i = 1; i <= length; i++)
2207 checksum += info_packet->sb[i];
2208
2209 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2210
2211 info_packet->valid = true;
2212}
2213
6e4d6bee 2214static void set_spd_info_packet(
e09b6473 2215 struct dc_info_packet *info_packet,
0971c40e 2216 struct dc_stream_state *stream)
4562236b
HW		 2217{
2218 /* SPD info packet for FreeSync */
2219
2220 unsigned char checksum = 0;
2221 unsigned int idx, payload_size = 0;
2222
2223 /* Check if Freesync is supported. Return if false. If true,
2224 * set the corresponding bit in the info packet
2225 */
4fa086b9 2226 if (stream->freesync_ctx.supported == false)
4562236b
HW		 2227 return;
2228
2229 if (dc_is_hdmi_signal(stream->signal)) {
2230
2231 /* HEADER */
2232
2233 /* HB0 = Packet Type = 0x83 (Source Product
2234 * Descriptor InfoFrame)
2235 */
3e183c5f 2236 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2237
2238 /* HB1 = Version = 0x01 */
2239 info_packet->hb1 = 0x01;
2240
2241 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2242 info_packet->hb2 = 0x08;
2243
2244 payload_size = 0x08;
2245
2246 } else if (dc_is_dp_signal(stream->signal)) {
2247
2248 /* HEADER */
2249
2250 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2251 * when used to associate audio related info packets
2252 */
2253 info_packet->hb0 = 0x00;
2254
2255 /* HB1 = Packet Type = 0x83 (Source Product
2256 * Descriptor InfoFrame)
2257 */
3e183c5f 2258 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2259
2260 /* HB2 = [Bits 7:0 = Least significant eight bits -
2261 * For INFOFRAME, the value must be 1Bh]
2262 */
2263 info_packet->hb2 = 0x1B;
2264
2265 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2266 * [Bits 1:0 = Most significant two bits = 0x00]
2267 */
2268 info_packet->hb3 = 0x04;
2269
2270 payload_size = 0x1B;
2271 }
2272
2273 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2274 info_packet->sb[1] = 0x1A;
2275
2276 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2277 info_packet->sb[2] = 0x00;
2278
2279 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2280 info_packet->sb[3] = 0x00;
2281
2282 /* PB4 = Reserved */
2283 info_packet->sb[4] = 0x00;
2284
2285 /* PB5 = Reserved */
2286 info_packet->sb[5] = 0x00;
2287
2288 /* PB6 = [Bits 7:3 = Reserved] */
2289 info_packet->sb[6] = 0x00;
2290
4fa086b9 2291 if (stream->freesync_ctx.supported == true)
4562236b
HW		 2292 /* PB6 = [Bit 0 = FreeSync Supported] */
2293 info_packet->sb[6] |= 0x01;
2294
4fa086b9 2295 if (stream->freesync_ctx.enabled == true)
4562236b
HW		 2296 /* PB6 = [Bit 1 = FreeSync Enabled] */
2297 info_packet->sb[6] |= 0x02;
2298
4fa086b9 2299 if (stream->freesync_ctx.active == true)
4562236b
HW		 2300 /* PB6 = [Bit 2 = FreeSync Active] */
2301 info_packet->sb[6] |= 0x04;
2302
2303 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2304 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2305 min_refresh_in_micro_hz / 1000000);
2306
2307 /* PB8 = FreeSync Maximum refresh rate (Hz)
2308 *
2309 * Note: We do not use the maximum capable refresh rate
2310 * of the panel, because we should never go above the field
2311 * rate of the mode timing set.
2312 */
4fa086b9 2313 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2314 nominal_refresh_in_micro_hz / 1000000);
2315
2316 /* PB9 - PB27 = Reserved */
2317 for (idx = 9; idx <= 27; idx++)
2318 info_packet->sb[idx] = 0x00;
2319
2320 /* Calculate checksum */
2321 checksum += info_packet->hb0;
2322 checksum += info_packet->hb1;
2323 checksum += info_packet->hb2;
2324 checksum += info_packet->hb3;
2325
2326 for (idx = 1; idx <= payload_size; idx++)
2327 checksum += info_packet->sb[idx];
2328
2329 /* PB0 = Checksum (one byte complement) */
2330 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2331
2332 info_packet->valid = true;
2333}
2334
1646a6fe 2335static void set_hdr_static_info_packet(
e09b6473 2336 struct dc_info_packet *info_packet,
0971c40e 2337 struct dc_stream_state *stream)
1646a6fe 2338{
0eeef690 2339 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2340
0eeef690 2341 if (!stream->hdr_static_metadata.valid)
10bff005
YS		 2342 return;
2343
0eeef690 2344 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2345}
2346
6e4d6bee 2347static void set_vsc_info_packet(
e09b6473 2348 struct dc_info_packet *info_packet,
0971c40e 2349 struct dc_stream_state *stream)
4562236b
HW		 2350{
2351 unsigned int vscPacketRevision = 0;
2352 unsigned int i;
2353
3b94a400 2354 /*VSC packet set to 2 when DP revision >= 1.2*/
85075fa0 2355 if (stream->psr_version != 0) {
4562236b
HW		 2356 vscPacketRevision = 2;
2357 }
2358
2359 /* VSC packet not needed based on the features
2360 * supported by this DP display
2361 */
2362 if (vscPacketRevision == 0)
2363 return;
2364
2365 if (vscPacketRevision == 0x2) {
2366 /* Secondary-data Packet ID = 0*/
2367 info_packet->hb0 = 0x00;
2368 /* 07h - Packet Type Value indicating Video
2369 * Stream Configuration packet
2370 */
2371 info_packet->hb1 = 0x07;
2372 /* 02h = VSC SDP supporting 3D stereo and PSR
2373 * (applies to eDP v1.3 or higher).
2374 */
2375 info_packet->hb2 = 0x02;
2376 /* 08h = VSC packet supporting 3D stereo + PSR
2377 * (HB2 = 02h).
2378 */
2379 info_packet->hb3 = 0x08;
2380
2381 for (i = 0; i < 28; i++)
2382 info_packet->sb[i] = 0;
2383
2384 info_packet->valid = true;
2385 }
2386
2387 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2388}
2389
f36cc577 2390void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2391{
2392 int i, j;
2393
ab2541b6 2394 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2395 for (j = 0; j < context->stream_status[i].plane_count; j++)
2396 dc_plane_state_release(
2397 context->stream_status[i].plane_states[j]);
4562236b 2398
3be5262e 2399 context->stream_status[i].plane_count = 0;
4fa086b9 2400 dc_stream_release(context->streams[i]);
ab2541b6 2401 context->streams[i] = NULL;
4562236b
HW		 2402 }
2403}
2404
2405/*
ab2541b6 2406 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2407 * by the src_ctx
2408 */
f36cc577 2409void dc_resource_state_copy_construct(
608ac7bb
JZ		 2410 const struct dc_state *src_ctx,
2411 struct dc_state *dst_ctx)
4562236b
HW		 2412{
2413 int i, j;
8ee5702a 2414 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2415
2416 *dst_ctx = *src_ctx;
2417
a2b8659d 2418 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2419 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2420
2421 if (cur_pipe->top_pipe)
2422 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2423
2424 if (cur_pipe->bottom_pipe)
2425 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2426
2427 }
2428
ab2541b6 2429 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2430 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2431 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2432 dc_plane_state_retain(
2433 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2434 }
9a3afbb3
AG		 2435
2436 /* context refcount should not be overridden */
8ee5702a 2437 dst_ctx->refcount = refcount;
9a3afbb3 2438
4562236b
HW		 2439}
2440
2441struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2442 struct resource_context *res_ctx,
2443 const struct resource_pool *pool)
4562236b
HW		 2444{
2445 int i;
2446
a2b8659d 2447 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2448 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2449 return pool->clock_sources[i];
4562236b
HW		 2450 }
2451
2452 return NULL;
2453}
2454
2455void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2456{
2457 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2458 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2459
2460 /* default all packets to invalid */
6e4d6bee
TC		 2461 info->avi.valid = false;
2462 info->gamut.valid = false;
2463 info->vendor.valid = false;
630e3573 2464 info->spd.valid = false;
6e4d6bee
TC		 2465 info->hdrsmd.valid = false;
2466 info->vsc.valid = false;
4562236b
HW		 2467
2468 signal = pipe_ctx->stream->signal;
2469
2470 /* HDMi and DP have different info packets*/
2471 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2472 set_avi_info_frame(&info->avi, pipe_ctx);
2473
2474 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2475
2476 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2477
56ef6ed9 2478 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2479
a33fa99d 2480 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2481 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2482
2483 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2484
56ef6ed9 2485 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2486 }
4562236b 2487
6e4d6bee 2488 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2489}
2490
2491enum dc_status resource_map_clock_resources(
fb3466a4 2492 const struct dc *dc,
608ac7bb 2493 struct dc_state *context,
1dc90497 2494 struct dc_stream_state *stream)
4562236b 2495{
4562236b 2496 /* acquire new resources */
1dc90497
AG		 2497 const struct resource_pool *pool = dc->res_pool;
2498 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2499 &context->res_ctx, stream);
ab2541b6 2500
1dc90497
AG		 2501 if (!pipe_ctx)
2502 return DC_ERROR_UNEXPECTED;
4562236b 2503
1dc90497
AG		 2504 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2505 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2506 pipe_ctx->clock_source = pool->dp_clock_source;
2507 else {
2508 pipe_ctx->clock_source = NULL;
4562236b 2509
1dc90497 2510 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2511 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2512 &context->res_ctx,
2513 pipe_ctx);
4562236b 2514
1dc90497
AG		 2515 if (pipe_ctx->clock_source == NULL)
2516 pipe_ctx->clock_source =
2517 dc_resource_find_first_free_pll(
2518 &context->res_ctx,
2519 pool);
2520 }
4562236b 2521
1dc90497
AG		 2522 if (pipe_ctx->clock_source == NULL)
2523 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2524
1dc90497
AG		 2525 resource_reference_clock_source(
2526 &context->res_ctx, pool,
2527 pipe_ctx->clock_source);
4562236b
HW		 2528
2529 return DC_OK;
2530}
2531
2532/*
2533 * Note: We need to disable output if clock sources change,
2534 * since bios does optimization and doesn't apply if changing
2535 * PHY when not already disabled.
2536 */
2537bool pipe_need_reprogram(
2538 struct pipe_ctx *pipe_ctx_old,
2539 struct pipe_ctx *pipe_ctx)
2540{
cfe4645e
DL		 2541 if (!pipe_ctx_old->stream)
2542 return false;
2543
4562236b
HW		 2544 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2545 return true;
2546
2547 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2548 return true;
2549
afaacef4 2550 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2551 return true;
2552
2553 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2554 && pipe_ctx_old->stream != pipe_ctx->stream)
2555 return true;
2556
8e9c4c8c 2557 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2558 return true;
2559
2560 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2561 return true;
2562
6b622181
JP		 2563 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2564 return true;
4562236b
HW		 2565
2566 return false;
2567}
529cad0f 2568
0971c40e 2569void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2570 struct bit_depth_reduction_params *fmt_bit_depth)
2571{
4fa086b9 2572 enum dc_dither_option option = stream->dither_option;
529cad0f 2573 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2574 stream->timing.pixel_encoding;
529cad0f
DW		 2575
2576 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2577
603767f9
TC		 2578 if (option == DITHER_OPTION_DEFAULT) {
2579 switch (stream->timing.display_color_depth) {
2580 case COLOR_DEPTH_666:
2581 option = DITHER_OPTION_SPATIAL6;
2582 break;
2583 case COLOR_DEPTH_888:
2584 option = DITHER_OPTION_SPATIAL8;
2585 break;
2586 case COLOR_DEPTH_101010:
2587 option = DITHER_OPTION_SPATIAL10;
2588 break;
2589 default:
2590 option = DITHER_OPTION_DISABLE;
2591 }
2592 }
2593
529cad0f
DW		 2594 if (option == DITHER_OPTION_DISABLE)
2595 return;
2596
2597 if (option == DITHER_OPTION_TRUN6) {
2598 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2599 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2600 } else if (option == DITHER_OPTION_TRUN8 ||
2601 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2602 option == DITHER_OPTION_TRUN8_FM6) {
2603 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2604 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2605 } else if (option == DITHER_OPTION_TRUN10 ||
2606 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2607 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2608 option == DITHER_OPTION_TRUN10_FM8 ||
2609 option == DITHER_OPTION_TRUN10_FM6 ||
2610 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2611 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2612 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2613 }
2614
2615 /* special case - Formatter can only reduce by 4 bits at most.
2616 * When reducing from 12 to 6 bits,
2617 * HW recommends we use trunc with round mode
2618 * (if we did nothing, trunc to 10 bits would be used)
2619 * note that any 12->10 bit reduction is ignored prior to DCE8,
2620 * as the input was 10 bits.
2621 */
2622 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2623 option == DITHER_OPTION_SPATIAL6 ||
2624 option == DITHER_OPTION_FM6) {
2625 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2626 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2627 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2628 }
2629
2630 /* spatial dither
2631 * note that spatial modes 1-3 are never used
2632 */
2633 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2634 option == DITHER_OPTION_SPATIAL6 ||
2635 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2636 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2637 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2638 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2639 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2640 fmt_bit_depth->flags.RGB_RANDOM =
2641 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2642 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2643 option == DITHER_OPTION_SPATIAL8 ||
2644 option == DITHER_OPTION_SPATIAL8_FM6 ||
2645 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2646 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2647 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2648 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2649 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2650 fmt_bit_depth->flags.RGB_RANDOM =
2651 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2652 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2653 option == DITHER_OPTION_SPATIAL10 ||
2654 option == DITHER_OPTION_SPATIAL10_FM8 ||
2655 option == DITHER_OPTION_SPATIAL10_FM6) {
2656 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2657 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2658 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2659 fmt_bit_depth->flags.RGB_RANDOM =
2660 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2661 }
2662
2663 if (option == DITHER_OPTION_SPATIAL6 ||
2664 option == DITHER_OPTION_SPATIAL8 ||
2665 option == DITHER_OPTION_SPATIAL10) {
2666 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2667 } else {
2668 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2669 }
2670
2671 //////////////////////
2672 //// temporal dither
2673 //////////////////////
2674 if (option == DITHER_OPTION_FM6 ||
2675 option == DITHER_OPTION_SPATIAL8_FM6 ||
2676 option == DITHER_OPTION_SPATIAL10_FM6 ||
2677 option == DITHER_OPTION_TRUN10_FM6 ||
2678 option == DITHER_OPTION_TRUN8_FM6 ||
2679 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2680 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2681 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2682 } else if (option == DITHER_OPTION_FM8 ||
2683 option == DITHER_OPTION_SPATIAL10_FM8 ||
2684 option == DITHER_OPTION_TRUN10_FM8) {
2685 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2686 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2687 } else if (option == DITHER_OPTION_FM10) {
2688 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2689 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2690 }
2691
2692 fmt_bit_depth->pixel_encoding = pixel_encoding;
2693}
9345d987 2694
62c933f9 2695enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2696{
fb3466a4 2697 struct dc *core_dc = dc;
4fa086b9 2698 struct dc_link *link = stream->sink->link;
9345d987
AG		 2699 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2700 enum dc_status res = DC_OK;
2701
4fa086b9 2702 calculate_phy_pix_clks(stream);
9345d987 2703
4fa086b9 2704 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2705 res = DC_FAIL_CONTROLLER_VALIDATE;
2706
2707 if (res == DC_OK)
2708 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2709 link->link_enc, stream))
9345d987
AG		 2710 res = DC_FAIL_ENC_VALIDATE;
2711
2712 /* TODO: validate audio ASIC caps, encoder */
2713
2714 if (res == DC_OK)
4fa086b9 2715 res = dc_link_validate_mode_timing(stream,
9345d987 2716 link,
4fa086b9 2717 &stream->timing);
9345d987 2718
62c933f9 2719 return res;
9345d987 2720}
792671d7 2721
62c933f9 2722enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2723{
62c933f9
YS		 2724 enum dc_status res = DC_OK;
2725
792671d7 2726 /* TODO For now validates pixel format only */
8e7095b9 2727 if (dc->res_pool->funcs->validate_plane)
62c933f9 2728 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2729
62c933f9 2730 return res;
792671d7 2731}
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