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drm/amd/display: remove get_position() of underlay
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
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4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
5ac3d3c9 34#include "core_types.h"
4562236b 35#include "set_mode_types.h"
4562236b
HW		 36#include "virtual/virtual_stream_encoder.h"
37
38#include "dce80/dce80_resource.h"
39#include "dce100/dce100_resource.h"
40#include "dce110/dce110_resource.h"
41#include "dce112/dce112_resource.h"
ff5ef992
AD		 42#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
43#include "dcn10/dcn10_resource.h"
44#endif
2c8ad2d5 45#include "dce120/dce120_resource.h"
4562236b
HW		 46
47enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
48{
49 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
50 switch (asic_id.chip_family) {
51
52 case FAMILY_CI:
53 case FAMILY_KV:
54 dc_version = DCE_VERSION_8_0;
55 break;
56 case FAMILY_CZ:
57 dc_version = DCE_VERSION_11_0;
58 break;
59
60 case FAMILY_VI:
61 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
63 dc_version = DCE_VERSION_10_0;
64 break;
65 }
66 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 67 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 69 dc_version = DCE_VERSION_11_2;
70 }
71 break;
2c8ad2d5
AD		 72 case FAMILY_AI:
73 dc_version = DCE_VERSION_12_0;
74 break;
ff5ef992
AD		 75#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
76 case FAMILY_RV:
77 dc_version = DCN_VERSION_1_0;
78 break;
79#endif
4562236b
HW		 80 default:
81 dc_version = DCE_VERSION_UNKNOWN;
82 break;
83 }
84 return dc_version;
85}
86
87struct resource_pool *dc_create_resource_pool(
88 struct core_dc *dc,
89 int num_virtual_links,
90 enum dce_version dc_version,
91 struct hw_asic_id asic_id)
92{
5ac3d3c9 93 struct resource_pool *res_pool = NULL;
4562236b
HW		 94
95 switch (dc_version) {
96 case DCE_VERSION_8_0:
5ac3d3c9 97 res_pool = dce80_create_resource_pool(
4562236b 98 num_virtual_links, dc);
5ac3d3c9 99 break;
4562236b 100 case DCE_VERSION_10_0:
5ac3d3c9 101 res_pool = dce100_create_resource_pool(
4562236b 102 num_virtual_links, dc);
5ac3d3c9 103 break;
4562236b 104 case DCE_VERSION_11_0:
5ac3d3c9 105 res_pool = dce110_create_resource_pool(
4562236b 106 num_virtual_links, dc, asic_id);
5ac3d3c9 107 break;
4562236b 108 case DCE_VERSION_11_2:
5ac3d3c9 109 res_pool = dce112_create_resource_pool(
4562236b 110 num_virtual_links, dc);
5ac3d3c9 111 break;
2c8ad2d5
AD		 112 case DCE_VERSION_12_0:
113 res_pool = dce120_create_resource_pool(
114 num_virtual_links, dc);
115 break;
ff5ef992
AD		 116
117#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
118 case DCN_VERSION_1_0:
119 res_pool = dcn10_create_resource_pool(
120 num_virtual_links, dc);
121 break;
122#endif
4562236b
HW		 123 default:
124 break;
125 }
5ac3d3c9
CL		 126 if (res_pool != NULL) {
127 struct firmware_info fw_info = { { 0 } };
128
129 if (dc->ctx->dc_bios->funcs->get_firmware_info(
130 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
131 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
132 } else
133 ASSERT_CRITICAL(false);
134 }
4562236b 135
5ac3d3c9 136 return res_pool;
4562236b
HW		 137}
138
139void dc_destroy_resource_pool(struct core_dc *dc)
140{
141 if (dc) {
142 if (dc->res_pool)
143 dc->res_pool->funcs->destroy(&dc->res_pool);
144
145 if (dc->hwseq)
146 dm_free(dc->hwseq);
147 }
148}
149
150static void update_num_audio(
151 const struct resource_straps *straps,
152 unsigned int *num_audio,
153 struct audio_support *aud_support)
154{
155 if (straps->hdmi_disable == 0) {
156 aud_support->hdmi_audio_native = true;
157 aud_support->hdmi_audio_on_dongle = true;
158 aud_support->dp_audio = true;
159 } else {
160 if (straps->dc_pinstraps_audio & 0x2) {
161 aud_support->hdmi_audio_on_dongle = true;
162 aud_support->dp_audio = true;
163 } else {
164 aud_support->dp_audio = true;
165 }
166 }
167
168 switch (straps->audio_stream_number) {
169 case 0: /* multi streams supported */
170 break;
171 case 1: /* multi streams not supported */
172 *num_audio = 1;
173 break;
174 default:
175 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 176 }
4562236b
HW		 177}
178
179bool resource_construct(
180 unsigned int num_virtual_links,
181 struct core_dc *dc,
182 struct resource_pool *pool,
183 const struct resource_create_funcs *create_funcs)
184{
185 struct dc_context *ctx = dc->ctx;
186 const struct resource_caps *caps = pool->res_cap;
187 int i;
188 unsigned int num_audio = caps->num_audio;
189 struct resource_straps straps = {0};
190
191 if (create_funcs->read_dce_straps)
192 create_funcs->read_dce_straps(dc->ctx, &straps);
193
194 pool->audio_count = 0;
195 if (create_funcs->create_audio) {
196 /* find the total number of streams available via the
197 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
198 * registers (one for each pin) starting from pin 1
199 * up to the max number of audio pins.
200 * We stop on the first pin where
201 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
202 */
203 update_num_audio(&straps, &num_audio, &pool->audio_support);
204 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
205 struct audio *aud = create_funcs->create_audio(ctx, i);
206
207 if (aud == NULL) {
208 DC_ERR("DC: failed to create audio!\n");
209 return false;
210 }
211
212 if (!aud->funcs->endpoint_valid(aud)) {
213 aud->funcs->destroy(&aud);
214 break;
215 }
216
217 pool->audios[i] = aud;
218 pool->audio_count++;
219 }
220 }
221
222 pool->stream_enc_count = 0;
223 if (create_funcs->create_stream_encoder) {
224 for (i = 0; i < caps->num_stream_encoder; i++) {
225 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
226 if (pool->stream_enc[i] == NULL)
227 DC_ERR("DC: failed to create stream_encoder!\n");
228 pool->stream_enc_count++;
229 }
230 }
231
232 for (i = 0; i < num_virtual_links; i++) {
233 pool->stream_enc[pool->stream_enc_count] =
234 virtual_stream_encoder_create(
235 ctx, ctx->dc_bios);
236 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
237 DC_ERR("DC: failed to create stream_encoder!\n");
238 return false;
239 }
240 pool->stream_enc_count++;
241 }
242
243 dc->hwseq = create_funcs->create_hwseq(ctx);
244
245 return true;
246}
247
248
249void resource_unreference_clock_source(
250 struct resource_context *res_ctx,
a2b8659d 251 const struct resource_pool *pool,
8c737fcc 252 struct clock_source **clock_source)
4562236b
HW		 253{
254 int i;
a2b8659d
TC		 255 for (i = 0; i < pool->clk_src_count; i++) {
256 if (pool->clock_sources[i] != *clock_source)
4562236b
HW		 257 continue;
258
259 res_ctx->clock_source_ref_count[i]--;
260
261 if (res_ctx->clock_source_ref_count[i] == 0)
8c737fcc 262 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b
HW		 263
264 break;
265 }
266
a2b8659d 267 if (pool->dp_clock_source == *clock_source) {
4562236b
HW		 268 res_ctx->dp_clock_source_ref_count--;
269
270 if (res_ctx->dp_clock_source_ref_count == 0)
8c737fcc 271 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b 272 }
8c737fcc 273 *clock_source = NULL;
4562236b
HW		 274}
275
276void resource_reference_clock_source(
277 struct resource_context *res_ctx,
a2b8659d 278 const struct resource_pool *pool,
4562236b
HW		 279 struct clock_source *clock_source)
280{
281 int i;
a2b8659d
TC		 282 for (i = 0; i < pool->clk_src_count; i++) {
283 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 284 continue;
285
286 res_ctx->clock_source_ref_count[i]++;
287 break;
288 }
289
a2b8659d 290 if (pool->dp_clock_source == clock_source)
4562236b
HW		 291 res_ctx->dp_clock_source_ref_count++;
292}
293
294bool resource_are_streams_timing_synchronizable(
295 const struct core_stream *stream1,
296 const struct core_stream *stream2)
297{
298 if (stream1->public.timing.h_total != stream2->public.timing.h_total)
299 return false;
300
301 if (stream1->public.timing.v_total != stream2->public.timing.v_total)
302 return false;
303
304 if (stream1->public.timing.h_addressable
305 != stream2->public.timing.h_addressable)
306 return false;
307
308 if (stream1->public.timing.v_addressable
309 != stream2->public.timing.v_addressable)
310 return false;
311
312 if (stream1->public.timing.pix_clk_khz
313 != stream2->public.timing.pix_clk_khz)
314 return false;
315
316 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 317 && (!dc_is_dp_signal(stream1->signal)
318 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 319 return false;
320
321 return true;
322}
323
324static bool is_sharable_clk_src(
325 const struct pipe_ctx *pipe_with_clk_src,
326 const struct pipe_ctx *pipe)
327{
328 if (pipe_with_clk_src->clock_source == NULL)
329 return false;
330
331 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
332 return false;
333
334 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
335 return false;
336
337 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
338 && dc_is_dvi_signal(pipe->stream->signal))
339 return false;
340
341 if (dc_is_hdmi_signal(pipe->stream->signal)
342 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
343 return false;
344
345 if (!resource_are_streams_timing_synchronizable(
346 pipe_with_clk_src->stream, pipe->stream))
347 return false;
348
349 return true;
350}
351
352struct clock_source *resource_find_used_clk_src_for_sharing(
353 struct resource_context *res_ctx,
354 struct pipe_ctx *pipe_ctx)
355{
356 int i;
357
358 for (i = 0; i < MAX_PIPES; i++) {
359 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
360 return res_ctx->pipe_ctx[i].clock_source;
361 }
362
363 return NULL;
364}
365
366static enum pixel_format convert_pixel_format_to_dalsurface(
367 enum surface_pixel_format surface_pixel_format)
368{
369 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
370
371 switch (surface_pixel_format) {
372 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
373 dal_pixel_format = PIXEL_FORMAT_INDEX8;
374 break;
375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
376 dal_pixel_format = PIXEL_FORMAT_RGB565;
377 break;
378 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
379 dal_pixel_format = PIXEL_FORMAT_RGB565;
380 break;
381 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
382 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
383 break;
8693049a 384 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 385 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
386 break;
387 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
388 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
389 break;
390 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
391 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
392 break;
393 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
394 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
395 break;
396 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
397 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
398 dal_pixel_format = PIXEL_FORMAT_FP16;
399 break;
400 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b
HW		 401 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
402 dal_pixel_format = PIXEL_FORMAT_420BPP12;
403 break;
ffbcd19a
VP		 404 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
405 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
406 dal_pixel_format = PIXEL_FORMAT_420BPP15;
407 break;
4562236b
HW		 408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
409 default:
410 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
411 break;
412 }
413 return dal_pixel_format;
414}
415
416static void rect_swap_helper(struct rect *rect)
417{
418 uint32_t temp = 0;
419
420 temp = rect->height;
421 rect->height = rect->width;
422 rect->width = temp;
423
424 temp = rect->x;
425 rect->x = rect->y;
426 rect->y = temp;
427}
428
b2d0a103 429static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 430{
b2d0a103 431 const struct dc_surface *surface = &pipe_ctx->surface->public;
1fbd2cfc 432 const struct dc_stream *stream = &pipe_ctx->stream->public;
b2d0a103 433 struct scaler_data *data = &pipe_ctx->scl_data;
86006a7f 434 struct rect surf_src = surface->src_rect;
1fbd2cfc 435 struct rect clip = { 0 };
b2d0a103
DL		 436 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
437 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
1fbd2cfc
DL		 438 bool pri_split = pipe_ctx->bottom_pipe &&
439 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
440 bool sec_split = pipe_ctx->top_pipe &&
441 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
4562236b 442
7b779c99
VP		 443 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
444 stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
445 pri_split = false;
446 sec_split = false;
447 }
86006a7f
DL		 448
449 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
450 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270)
451 rect_swap_helper(&surf_src);
452
4562236b
HW		 453 /* The actual clip is an intersection between stream
454 * source and surface clip
455 */
1fbd2cfc
DL		 456 clip.x = stream->src.x > surface->clip_rect.x ?
457 stream->src.x : surface->clip_rect.x;
4562236b 458
1fbd2cfc
DL		 459 clip.width = stream->src.x + stream->src.width <
460 surface->clip_rect.x + surface->clip_rect.width ?
461 stream->src.x + stream->src.width - clip.x :
462 surface->clip_rect.x + surface->clip_rect.width - clip.x ;
4562236b 463
1fbd2cfc
DL		 464 clip.y = stream->src.y > surface->clip_rect.y ?
465 stream->src.y : surface->clip_rect.y;
4562236b 466
1fbd2cfc
DL		 467 clip.height = stream->src.y + stream->src.height <
468 surface->clip_rect.y + surface->clip_rect.height ?
469 stream->src.y + stream->src.height - clip.y :
470 surface->clip_rect.y + surface->clip_rect.height - clip.y ;
4562236b 471
86006a7f 472 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 473 * num_pixels = clip.num_pix * scl_ratio
474 */
86006a7f
DL		 475 data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) *
476 surf_src.width / surface->dst_rect.width;
b2d0a103 477 data->viewport.width = clip.width *
86006a7f 478 surf_src.width / surface->dst_rect.width;
4562236b 479
86006a7f
DL		 480 data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) *
481 surf_src.height / surface->dst_rect.height;
b2d0a103 482 data->viewport.height = clip.height *
86006a7f 483 surf_src.height / surface->dst_rect.height;
4562236b 484
b2d0a103
DL		 485 /* Round down, compensate in init */
486 data->viewport_c.x = data->viewport.x / vpc_div;
487 data->viewport_c.y = data->viewport.y / vpc_div;
488 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
489 dal_fixed31_32_half : dal_fixed31_32_zero;
490 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
491 dal_fixed31_32_half : dal_fixed31_32_zero;
492 /* Round up, assume original video size always even dimensions */
493 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
494 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
495
496 /* Handle hsplit */
1fbd2cfc
DL		 497 if (pri_split || sec_split) {
498 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
499 bool right_view = (sec_split != surface->horizontal_mirror) !=
500 (surface->rotation == ROTATION_ANGLE_180);
501
502 if (surface->rotation == ROTATION_ANGLE_90
503 || surface->rotation == ROTATION_ANGLE_270)
504 /* Secondary_pipe XOR Rotation_270 */
505 right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 506
507 if (right_view) {
508 data->viewport.width /= 2;
509 data->viewport_c.width /= 2;
510 data->viewport.x += data->viewport.width;
511 data->viewport_c.x += data->viewport_c.width;
512 /* Ceil offset pipe */
513 data->viewport.width += data->viewport.width % 2;
514 data->viewport_c.width += data->viewport_c.width % 2;
515 } else {
516 data->viewport.width /= 2;
517 data->viewport_c.width /= 2;
518 }
b2d0a103 519 }
1fbd2cfc
DL		 520
521 if (surface->rotation == ROTATION_ANGLE_90 ||
522 surface->rotation == ROTATION_ANGLE_270) {
523 rect_swap_helper(&data->viewport_c);
524 rect_swap_helper(&data->viewport);
525 }
4562236b
HW		 526}
527
b2d0a103 528static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 529{
b2d0a103 530 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 531 struct core_stream *stream = pipe_ctx->stream;
86006a7f
DL		 532 struct rect surf_src = surface->src_rect;
533 struct rect surf_clip = surface->clip_rect;
c802570e 534 int recout_full_x, recout_full_y;
4562236b 535
86006a7f
DL		 536 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
537 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270)
538 rect_swap_helper(&surf_src);
539
4562236b 540 pipe_ctx->scl_data.recout.x = stream->public.dst.x;
86006a7f
DL		 541 if (stream->public.src.x < surf_clip.x)
542 pipe_ctx->scl_data.recout.x += (surf_clip.x
4562236b
HW		 543 - stream->public.src.x) * stream->public.dst.width
544 / stream->public.src.width;
545
86006a7f 546 pipe_ctx->scl_data.recout.width = surf_clip.width *
4562236b
HW		 547 stream->public.dst.width / stream->public.src.width;
548 if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x >
549 stream->public.dst.x + stream->public.dst.width)
550 pipe_ctx->scl_data.recout.width =
551 stream->public.dst.x + stream->public.dst.width
552 - pipe_ctx->scl_data.recout.x;
553
554 pipe_ctx->scl_data.recout.y = stream->public.dst.y;
86006a7f
DL		 555 if (stream->public.src.y < surf_clip.y)
556 pipe_ctx->scl_data.recout.y += (surf_clip.y
4562236b
HW		 557 - stream->public.src.y) * stream->public.dst.height
558 / stream->public.src.height;
559
86006a7f 560 pipe_ctx->scl_data.recout.height = surf_clip.height *
4562236b
HW		 561 stream->public.dst.height / stream->public.src.height;
562 if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y >
563 stream->public.dst.y + stream->public.dst.height)
564 pipe_ctx->scl_data.recout.height =
565 stream->public.dst.y + stream->public.dst.height
566 - pipe_ctx->scl_data.recout.y;
b2d0a103 567
7b779c99
VP		 568 /* Handle h & vsplit */
569 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface ==
570 pipe_ctx->surface) {
571 if (stream->public.timing.timing_3d_format ==
572 TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
573 pipe_ctx->scl_data.recout.height /= 2;
574 pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height;
575 /* Floor primary pipe, ceil 2ndary pipe */
576 pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2;
577 } else {
578 pipe_ctx->scl_data.recout.width /= 2;
579 pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
580 pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
581 }
582 } else if (pipe_ctx->bottom_pipe &&
86006a7f 583 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
7b779c99
VP		 584 if (stream->public.timing.timing_3d_format ==
585 TIMING_3D_FORMAT_TOP_AND_BOTTOM)
586 pipe_ctx->scl_data.recout.height /= 2;
587 else
588 pipe_ctx->scl_data.recout.width /= 2;
b2d0a103
DL		 589 }
590
86006a7f
DL		 591 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
592 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 593 * ratio)
594 */
595 recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x)
596 * stream->public.dst.width / stream->public.src.width -
86006a7f 597 surf_src.x * surface->dst_rect.width / surf_src.width
c802570e
DL		 598 * stream->public.dst.width / stream->public.src.width;
599 recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y)
600 * stream->public.dst.height / stream->public.src.height -
86006a7f 601 surf_src.y * surface->dst_rect.height / surf_src.height
c802570e
DL		 602 * stream->public.dst.height / stream->public.src.height;
603
604 recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
605 recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
4562236b
HW		 606}
607
b2d0a103 608static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 609{
b2d0a103 610 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 611 struct core_stream *stream = pipe_ctx->stream;
86006a7f 612 struct rect surf_src = surface->src_rect;
1fbd2cfc
DL		 613 const int in_w = stream->public.src.width;
614 const int in_h = stream->public.src.height;
615 const int out_w = stream->public.dst.width;
616 const int out_h = stream->public.dst.height;
4562236b 617
86006a7f
DL		 618 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
619 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270)
620 rect_swap_helper(&surf_src);
621
4562236b 622 pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 623 surf_src.width,
4562236b
HW		 624 surface->dst_rect.width);
625 pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 626 surf_src.height,
4562236b
HW		 627 surface->dst_rect.height);
628
629 if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
630 pipe_ctx->scl_data.ratios.horz.value *= 2;
631 else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
632 pipe_ctx->scl_data.ratios.vert.value *= 2;
633
634 pipe_ctx->scl_data.ratios.vert.value = div64_s64(
635 pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
636 pipe_ctx->scl_data.ratios.horz.value = div64_s64(
637 pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
638
639 pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
640 pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
641
b2d0a103
DL		 642 if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
643 || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
4562236b
HW		 644 pipe_ctx->scl_data.ratios.horz_c.value /= 2;
645 pipe_ctx->scl_data.ratios.vert_c.value /= 2;
646 }
647}
648
b2d0a103
DL		 649static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
650{
651 struct scaler_data *data = &pipe_ctx->scl_data;
652 struct rect src = pipe_ctx->surface->public.src_rect;
653 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
654 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
655
86006a7f 656
1fbd2cfc
DL		 657 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
658 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
86006a7f 659 rect_swap_helper(&src);
1fbd2cfc
DL		 660 rect_swap_helper(&data->viewport_c);
661 rect_swap_helper(&data->viewport);
662 }
663
b2d0a103
DL		 664 /*
665 * Init calculated according to formula:
666 * init = (scaling_ratio + number_of_taps + 1) / 2
667 * init_bot = init + scaling_ratio
668 * init_c = init + truncated_vp_c_offset(from calculate viewport)
669 */
670 data->inits.h = dal_fixed31_32_div_int(
671 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
672
673 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
674 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
675
676 data->inits.v = dal_fixed31_32_div_int(
677 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
678
679 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
680 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
681
682
683 /* Adjust for viewport end clip-off */
684 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
685 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 686 int int_part = dal_fixed31_32_floor(
687 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 688
1fbd2cfc 689 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 690 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
691 }
692 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
693 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 694 int int_part = dal_fixed31_32_floor(
695 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 696
1fbd2cfc 697 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 698 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
699 }
700 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
701 int vp_clip = (src.x + src.width) / vpc_div -
702 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 703 int int_part = dal_fixed31_32_floor(
704 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 705
1fbd2cfc 706 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 707 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
708 }
709 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
710 int vp_clip = (src.y + src.height) / vpc_div -
711 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 712 int int_part = dal_fixed31_32_floor(
713 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 714
1fbd2cfc 715 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 716 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
717 }
718
719 /* Adjust for non-0 viewport offset */
720 if (data->viewport.x) {
721 int int_part;
722
723 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
724 data->ratios.horz, recout_skip->width));
725 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
726 if (int_part < data->taps.h_taps) {
727 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
728 (data->taps.h_taps - int_part) : data->viewport.x;
729 data->viewport.x -= int_adj;
730 data->viewport.width += int_adj;
731 int_part += int_adj;
732 } else if (int_part > data->taps.h_taps) {
733 data->viewport.x += int_part - data->taps.h_taps;
734 data->viewport.width -= int_part - data->taps.h_taps;
735 int_part = data->taps.h_taps;
736 }
737 data->inits.h.value &= 0xffffffff;
738 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
739 }
740
741 if (data->viewport_c.x) {
742 int int_part;
743
744 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
745 data->ratios.horz_c, recout_skip->width));
746 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
747 if (int_part < data->taps.h_taps_c) {
748 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
749 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
750 data->viewport_c.x -= int_adj;
751 data->viewport_c.width += int_adj;
752 int_part += int_adj;
753 } else if (int_part > data->taps.h_taps_c) {
754 data->viewport_c.x += int_part - data->taps.h_taps_c;
755 data->viewport_c.width -= int_part - data->taps.h_taps_c;
756 int_part = data->taps.h_taps_c;
757 }
758 data->inits.h_c.value &= 0xffffffff;
759 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
760 }
761
762 if (data->viewport.y) {
763 int int_part;
764
765 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
766 data->ratios.vert, recout_skip->height));
767 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
768 if (int_part < data->taps.v_taps) {
769 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
770 (data->taps.v_taps - int_part) : data->viewport.y;
771 data->viewport.y -= int_adj;
772 data->viewport.height += int_adj;
773 int_part += int_adj;
774 } else if (int_part > data->taps.v_taps) {
775 data->viewport.y += int_part - data->taps.v_taps;
776 data->viewport.height -= int_part - data->taps.v_taps;
777 int_part = data->taps.v_taps;
778 }
779 data->inits.v.value &= 0xffffffff;
780 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
781 }
782
783 if (data->viewport_c.y) {
784 int int_part;
785
786 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
787 data->ratios.vert_c, recout_skip->height));
788 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
789 if (int_part < data->taps.v_taps_c) {
790 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
791 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
792 data->viewport_c.y -= int_adj;
793 data->viewport_c.height += int_adj;
794 int_part += int_adj;
795 } else if (int_part > data->taps.v_taps_c) {
796 data->viewport_c.y += int_part - data->taps.v_taps_c;
797 data->viewport_c.height -= int_part - data->taps.v_taps_c;
798 int_part = data->taps.v_taps_c;
799 }
800 data->inits.v_c.value &= 0xffffffff;
801 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
802 }
803
804 /* Interlaced inits based on final vert inits */
805 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
806 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc
DL		 807
808 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
809 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
810 rect_swap_helper(&data->viewport_c);
811 rect_swap_helper(&data->viewport);
812 }
b2d0a103
DL		 813}
814
815bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 816{
b2d0a103 817 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 818 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
b2d0a103
DL		 819 struct view recout_skip = { 0 };
820 bool res = false;
821
4562236b
HW		 822 /* Important: scaling ratio calculation requires pixel format,
823 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 824 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 825 */
b2d0a103
DL		 826 pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
827 pipe_ctx->surface->public.format);
828
829 calculate_scaling_ratios(pipe_ctx);
4562236b 830
b2d0a103 831 calculate_viewport(pipe_ctx);
4562236b
HW		 832
833 if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
834 return false;
835
b2d0a103 836 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 837
838 /**
839 * Setting line buffer pixel depth to 24bpp yields banding
840 * on certain displays, such as the Sharp 4k
841 */
842 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
843
844 pipe_ctx->scl_data.h_active = timing->h_addressable;
845 pipe_ctx->scl_data.v_active = timing->v_addressable;
846
847 /* Taps calculations */
848 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
849 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
850
851 if (!res) {
852 /* Try 24 bpp linebuffer */
853 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
854
855 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
856 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
857 }
858
b2d0a103 859 if (res)
1fbd2cfc 860 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 861 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
862
4562236b
HW		 863 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
864 "%s: Viewport:\nheight:%d width:%d x:%d "
865 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
866 "y:%d\n",
867 __func__,
868 pipe_ctx->scl_data.viewport.height,
869 pipe_ctx->scl_data.viewport.width,
870 pipe_ctx->scl_data.viewport.x,
871 pipe_ctx->scl_data.viewport.y,
872 surface->dst_rect.height,
873 surface->dst_rect.width,
874 surface->dst_rect.x,
875 surface->dst_rect.y);
876
877 return res;
878}
879
880
881enum dc_status resource_build_scaling_params_for_context(
882 const struct core_dc *dc,
883 struct validate_context *context)
884{
885 int i;
886
887 for (i = 0; i < MAX_PIPES; i++) {
888 if (context->res_ctx.pipe_ctx[i].surface != NULL &&
889 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 890 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 891 return DC_FAIL_SCALING;
4562236b
HW		 892 }
893
894 return DC_OK;
895}
896
a2b8659d
TC		 897struct pipe_ctx *find_idle_secondary_pipe(
898 struct resource_context *res_ctx,
899 const struct resource_pool *pool)
4562236b
HW		 900{
901 int i;
902 struct pipe_ctx *secondary_pipe = NULL;
903
904 /*
905 * search backwards for the second pipe to keep pipe
906 * assignment more consistent
907 */
908
a2b8659d 909 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 910 if (res_ctx->pipe_ctx[i].stream == NULL) {
911 secondary_pipe = &res_ctx->pipe_ctx[i];
912 secondary_pipe->pipe_idx = i;
913 break;
914 }
915 }
916
917
918 return secondary_pipe;
919}
920
921struct pipe_ctx *resource_get_head_pipe_for_stream(
922 struct resource_context *res_ctx,
923 const struct core_stream *stream)
924{
925 int i;
a2b8659d 926 for (i = 0; i < MAX_PIPES; i++) {
4562236b 927 if (res_ctx->pipe_ctx[i].stream == stream &&
e73c1efc 928 res_ctx->pipe_ctx[i].stream_enc) {
4562236b
HW		 929 return &res_ctx->pipe_ctx[i];
930 break;
931 }
932 }
933 return NULL;
934}
935
936/*
ab2541b6
AC		 937 * A free_pipe for a stream is defined here as a pipe
938 * that has no surface attached yet
4562236b 939 */
ab2541b6 940static struct pipe_ctx *acquire_free_pipe_for_stream(
745cc746 941 struct validate_context *context,
a2b8659d 942 const struct resource_pool *pool,
ab2541b6 943 const struct dc_stream *dc_stream)
4562236b
HW		 944{
945 int i;
745cc746 946 struct resource_context *res_ctx = &context->res_ctx;
ab2541b6 947 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 948
949 struct pipe_ctx *head_pipe = NULL;
950
951 /* Find head pipe, which has the back end set up*/
952
953 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
954
955 if (!head_pipe)
956 ASSERT(0);
957
958 if (!head_pipe->surface)
959 return head_pipe;
960
961 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 962 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 963 if (res_ctx->pipe_ctx[i].stream == stream &&
964 !res_ctx->pipe_ctx[i].surface) {
965 return &res_ctx->pipe_ctx[i];
966 }
967 }
968
969 /*
970 * At this point we have no re-useable pipe for this stream and we need
971 * to acquire an idle one to satisfy the request
972 */
973
a2b8659d 974 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 975 return NULL;
976
a2b8659d 977 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 978
979}
980
ab2541b6 981static void release_free_pipes_for_stream(
4562236b 982 struct resource_context *res_ctx,
ab2541b6 983 const struct dc_stream *dc_stream)
4562236b
HW		 984{
985 int i;
ab2541b6 986 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b 987
a2b8659d 988 for (i = MAX_PIPES - 1; i >= 0; i--) {
05a19c39 989 /* never release the topmost pipe*/
4562236b 990 if (res_ctx->pipe_ctx[i].stream == stream &&
05a19c39 991 res_ctx->pipe_ctx[i].top_pipe &&
4562236b 992 !res_ctx->pipe_ctx[i].surface) {
05a19c39 993 memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx));
4562236b
HW		 994 }
995 }
996}
997
0f9a536f
DL		 998#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
999static int acquire_first_split_pipe(
1000 struct resource_context *res_ctx,
1001 const struct resource_pool *pool,
1002 struct core_stream *stream)
1003{
1004 int i;
1005
1006 for (i = 0; i < pool->pipe_count; i++) {
1007 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1008
1009 if (pipe_ctx->top_pipe &&
1010 pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
0f9a536f
DL		 1011 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1012 if (pipe_ctx->bottom_pipe)
1013 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1014
1015 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1016 pipe_ctx->tg = pool->timing_generators[i];
1017 pipe_ctx->mi = pool->mis[i];
1018 pipe_ctx->ipp = pool->ipps[i];
1019 pipe_ctx->xfm = pool->transforms[i];
1020 pipe_ctx->opp = pool->opps[i];
1021 pipe_ctx->dis_clk = pool->display_clock;
f0558542 1022 pipe_ctx->mpcc = pool->mpcc[i];
0f9a536f 1023 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1024
1025 pipe_ctx->stream = stream;
1026 return i;
1027 }
1028 }
1029 return -1;
1030}
1031#endif
1032
4562236b
HW		 1033bool resource_attach_surfaces_to_context(
1034 const struct dc_surface * const *surfaces,
1035 int surface_count,
ab2541b6 1036 const struct dc_stream *dc_stream,
a2b8659d
TC		 1037 struct validate_context *context,
1038 const struct resource_pool *pool)
4562236b
HW		 1039{
1040 int i;
1041 struct pipe_ctx *tail_pipe;
ab2541b6 1042 struct dc_stream_status *stream_status = NULL;
05a19c39 1043 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 1044
1045
1046 if (surface_count > MAX_SURFACE_NUM) {
1047 dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
1048 surface_count, MAX_SURFACE_NUM);
1049 return false;
1050 }
1051
ab2541b6
AC		 1052 for (i = 0; i < context->stream_count; i++)
1053 if (&context->streams[i]->public == dc_stream) {
1054 stream_status = &context->stream_status[i];
4562236b
HW		 1055 break;
1056 }
ab2541b6
AC		 1057 if (stream_status == NULL) {
1058 dm_error("Existing stream not found; failed to attach surfaces\n");
4562236b
HW		 1059 return false;
1060 }
1061
1062 /* retain new surfaces */
1063 for (i = 0; i < surface_count; i++)
1064 dc_surface_retain(surfaces[i]);
1065
05a19c39
DL		 1066 /* detach surfaces from pipes */
1067 for (i = 0; i < pool->pipe_count; i++)
1068 if (context->res_ctx.pipe_ctx[i].stream == stream) {
1069 context->res_ctx.pipe_ctx[i].surface = NULL;
1070 context->res_ctx.pipe_ctx[i].bottom_pipe = NULL;
1071 }
4562236b
HW		 1072
1073 /* release existing surfaces*/
ab2541b6
AC		 1074 for (i = 0; i < stream_status->surface_count; i++)
1075 dc_surface_release(stream_status->surfaces[i]);
4562236b 1076
ab2541b6
AC		 1077 for (i = surface_count; i < stream_status->surface_count; i++)
1078 stream_status->surfaces[i] = NULL;
4562236b 1079
4562236b
HW		 1080 tail_pipe = NULL;
1081 for (i = 0; i < surface_count; i++) {
1082 struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
a2b8659d
TC		 1083 struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(
1084 context, pool, dc_stream);
4562236b 1085
0f9a536f
DL		 1086#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1087 if (!free_pipe) {
1088 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1089 if (pipe_idx >= 0)
1090 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1091 }
1092#endif
4562236b 1093 if (!free_pipe) {
ab2541b6 1094 stream_status->surfaces[i] = NULL;
4562236b
HW		 1095 return false;
1096 }
1097
1098 free_pipe->surface = surface;
1099
1100 if (tail_pipe) {
1101 free_pipe->top_pipe = tail_pipe;
1102 tail_pipe->bottom_pipe = free_pipe;
1103 }
1104
1105 tail_pipe = free_pipe;
1106 }
1107
ab2541b6 1108 release_free_pipes_for_stream(&context->res_ctx, dc_stream);
4562236b
HW		 1109
1110 /* assign new surfaces*/
1111 for (i = 0; i < surface_count; i++)
ab2541b6 1112 stream_status->surfaces[i] = surfaces[i];
4562236b 1113
ab2541b6 1114 stream_status->surface_count = surface_count;
4562236b
HW		 1115
1116 return true;
1117}
1118
1119
1120static bool is_timing_changed(const struct core_stream *cur_stream,
1121 const struct core_stream *new_stream)
1122{
1123 if (cur_stream == NULL)
1124 return true;
1125
1126 /* If sink pointer changed, it means this is a hotplug, we should do
1127 * full hw setting.
1128 */
1129 if (cur_stream->sink != new_stream->sink)
1130 return true;
1131
1132 /* If output color space is changed, need to reprogram info frames */
1133 if (cur_stream->public.output_color_space !=
1134 new_stream->public.output_color_space)
1135 return true;
1136
1137 return memcmp(
1138 &cur_stream->public.timing,
1139 &new_stream->public.timing,
1140 sizeof(struct dc_crtc_timing)) != 0;
1141}
1142
1143static bool are_stream_backends_same(
1144 const struct core_stream *stream_a, const struct core_stream *stream_b)
1145{
1146 if (stream_a == stream_b)
1147 return true;
1148
1149 if (stream_a == NULL || stream_b == NULL)
1150 return false;
1151
1152 if (is_timing_changed(stream_a, stream_b))
1153 return false;
1154
1155 return true;
1156}
1157
ab2541b6
AC		 1158bool is_stream_unchanged(
1159 const struct core_stream *old_stream, const struct core_stream *stream)
4562236b 1160{
4562236b 1161
ab2541b6
AC		 1162 if (!are_stream_backends_same(old_stream, stream))
1163 return false;
4562236b
HW		 1164
1165 return true;
1166}
1167
1168bool resource_validate_attach_surfaces(
1169 const struct dc_validation_set set[],
1170 int set_count,
1171 const struct validate_context *old_context,
a2b8659d
TC		 1172 struct validate_context *context,
1173 const struct resource_pool *pool)
4562236b
HW		 1174{
1175 int i, j;
1176
1177 for (i = 0; i < set_count; i++) {
430ef426 1178 for (j = 0; old_context && j < old_context->stream_count; j++)
ab2541b6
AC		 1179 if (is_stream_unchanged(
1180 old_context->streams[j],
1181 context->streams[i])) {
4562236b 1182 if (!resource_attach_surfaces_to_context(
ab2541b6
AC		 1183 old_context->stream_status[j].surfaces,
1184 old_context->stream_status[j].surface_count,
1185 &context->streams[i]->public,
a2b8659d 1186 context, pool))
4562236b 1187 return false;
ab2541b6 1188 context->stream_status[i] = old_context->stream_status[j];
4562236b
HW		 1189 }
1190 if (set[i].surface_count != 0)
1191 if (!resource_attach_surfaces_to_context(
1192 set[i].surfaces,
1193 set[i].surface_count,
ab2541b6 1194 &context->streams[i]->public,
a2b8659d 1195 context, pool))
4562236b
HW		 1196 return false;
1197
1198 }
1199
1200 return true;
1201}
1202
1203/* Maximum TMDS single link pixel clock 165MHz */
1204#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
909e8c9e 1205#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
4562236b
HW		 1206
1207static void set_stream_engine_in_use(
1208 struct resource_context *res_ctx,
a2b8659d 1209 const struct resource_pool *pool,
4562236b
HW		 1210 struct stream_encoder *stream_enc)
1211{
1212 int i;
1213
a2b8659d
TC		 1214 for (i = 0; i < pool->stream_enc_count; i++) {
1215 if (pool->stream_enc[i] == stream_enc)
4562236b
HW		 1216 res_ctx->is_stream_enc_acquired[i] = true;
1217 }
1218}
1219
1220/* TODO: release audio object */
1221static void set_audio_in_use(
1222 struct resource_context *res_ctx,
a2b8659d 1223 const struct resource_pool *pool,
4562236b
HW		 1224 struct audio *audio)
1225{
1226 int i;
a2b8659d
TC		 1227 for (i = 0; i < pool->audio_count; i++) {
1228 if (pool->audios[i] == audio)
4562236b 1229 res_ctx->is_audio_acquired[i] = true;
4562236b
HW		 1230 }
1231}
1232
1233static int acquire_first_free_pipe(
1234 struct resource_context *res_ctx,
a2b8659d 1235 const struct resource_pool *pool,
4562236b
HW		 1236 struct core_stream *stream)
1237{
1238 int i;
1239
a2b8659d 1240 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1241 if (!res_ctx->pipe_ctx[i].stream) {
1242 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1243
f0558542
DL		 1244#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1245 pipe_ctx->mpcc = pool->mpcc[i];
1246#endif
a2b8659d
TC		 1247 pipe_ctx->tg = pool->timing_generators[i];
1248 pipe_ctx->mi = pool->mis[i];
1249 pipe_ctx->ipp = pool->ipps[i];
1250 pipe_ctx->xfm = pool->transforms[i];
1251 pipe_ctx->opp = pool->opps[i];
1252 pipe_ctx->dis_clk = pool->display_clock;
4562236b
HW		 1253 pipe_ctx->pipe_idx = i;
1254
ff5ef992 1255
4562236b
HW		 1256 pipe_ctx->stream = stream;
1257 return i;
1258 }
1259 }
1260 return -1;
1261}
1262
1263static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1264 struct resource_context *res_ctx,
a2b8659d 1265 const struct resource_pool *pool,
4562236b
HW		 1266 struct core_stream *stream)
1267{
1268 int i;
1269 int j = -1;
1270 struct core_link *link = stream->sink->link;
1271
a2b8659d 1272 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1273 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1274 pool->stream_enc[i]) {
4562236b
HW		 1275 /* Store first available for MST second display
1276 * in daisy chain use case */
1277 j = i;
a2b8659d 1278 if (pool->stream_enc[i]->id ==
4562236b 1279 link->link_enc->preferred_engine)
a2b8659d 1280 return pool->stream_enc[i];
4562236b
HW		 1281 }
1282 }
1283
1284 /*
1285 * below can happen in cases when stream encoder is acquired:
1286 * 1) for second MST display in chain, so preferred engine already
1287 * acquired;
1288 * 2) for another link, which preferred engine already acquired by any
1289 * MST configuration.
1290 *
1291 * If signal is of DP type and preferred engine not found, return last available
1292 *
1293 * TODO - This is just a patch up and a generic solution is
1294 * required for non DP connectors.
1295 */
1296
1297 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1298 return pool->stream_enc[j];
4562236b
HW		 1299
1300 return NULL;
1301}
1302
a2b8659d
TC		 1303static struct audio *find_first_free_audio(
1304 struct resource_context *res_ctx,
1305 const struct resource_pool *pool)
4562236b
HW		 1306{
1307 int i;
a2b8659d 1308 for (i = 0; i < pool->audio_count; i++) {
4562236b 1309 if (res_ctx->is_audio_acquired[i] == false) {
a2b8659d 1310 return pool->audios[i];
4562236b
HW		 1311 }
1312 }
1313
1314 return 0;
1315}
1316
1317static void update_stream_signal(struct core_stream *stream)
1318{
8b32076c
ST		 1319 if (stream->public.output_signal == SIGNAL_TYPE_NONE) {
1320 const struct dc_sink *dc_sink = stream->public.sink;
1321
1322 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
1323 stream->signal =
1324 stream->sink->link->
1325 public.connector_signal;
4562236b 1326 else
8b32076c
ST		 1327 stream->signal = dc_sink->sink_signal;
1328 } else {
1329 stream->signal = stream->public.output_signal;
1330 }
1331
56dcade3 1332 if (dc_is_dvi_signal(stream->signal)) {
909e8c9e
CL		 1333 if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
1334 stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
56dcade3
HW		 1335 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1336 else
1337 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1338 }
4562236b
HW		 1339}
1340
1341bool resource_is_stream_unchanged(
ab2541b6 1342 const struct validate_context *old_context, const struct core_stream *stream)
4562236b 1343{
ab2541b6 1344 int i;
4562236b 1345
ab2541b6
AC		 1346 for (i = 0; i < old_context->stream_count; i++) {
1347 const struct core_stream *old_stream = old_context->streams[i];
4562236b 1348
ab2541b6 1349 if (are_stream_backends_same(old_stream, stream))
4562236b 1350 return true;
4562236b
HW		 1351 }
1352
1353 return false;
1354}
1355
1356static void copy_pipe_ctx(
1357 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1358{
1359 struct core_surface *surface = to_pipe_ctx->surface;
1360 struct core_stream *stream = to_pipe_ctx->stream;
1361
1362 *to_pipe_ctx = *from_pipe_ctx;
1363 to_pipe_ctx->stream = stream;
1364 if (surface != NULL)
1365 to_pipe_ctx->surface = surface;
1366}
1367
1368static struct core_stream *find_pll_sharable_stream(
1369 const struct core_stream *stream_needs_pll,
1370 struct validate_context *context)
1371{
ab2541b6 1372 int i;
4562236b 1373
ab2541b6
AC		 1374 for (i = 0; i < context->stream_count; i++) {
1375 struct core_stream *stream_has_pll = context->streams[i];
4562236b 1376
ab2541b6
AC		 1377 /* We are looking for non dp, non virtual stream */
1378 if (resource_are_streams_timing_synchronizable(
1379 stream_needs_pll, stream_has_pll)
1380 && !dc_is_dp_signal(stream_has_pll->signal)
1381 && stream_has_pll->sink->link->public.connector_signal
1382 != SIGNAL_TYPE_VIRTUAL)
1383 return stream_has_pll;
4562236b 1384
4562236b
HW		 1385 }
1386
1387 return NULL;
1388}
1389
1390static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1391{
1392 uint32_t pix_clk = timing->pix_clk_khz;
1393 uint32_t normalized_pix_clk = pix_clk;
1394
1395 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1396 pix_clk /= 2;
cc4d99b8
CL		 1397 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1398 switch (timing->display_color_depth) {
1399 case COLOR_DEPTH_888:
1400 normalized_pix_clk = pix_clk;
1401 break;
1402 case COLOR_DEPTH_101010:
1403 normalized_pix_clk = (pix_clk * 30) / 24;
1404 break;
1405 case COLOR_DEPTH_121212:
1406 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1407 break;
cc4d99b8
CL		 1408 case COLOR_DEPTH_161616:
1409 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1410 break;
cc4d99b8
CL		 1411 default:
1412 ASSERT(0);
4562236b 1413 break;
cc4d99b8 1414 }
4562236b 1415 }
4562236b
HW		 1416 return normalized_pix_clk;
1417}
1418
430ef426 1419static void calculate_phy_pix_clks(struct validate_context *context)
4562236b 1420{
ab2541b6 1421 int i;
4562236b 1422
ab2541b6
AC		 1423 for (i = 0; i < context->stream_count; i++) {
1424 struct core_stream *stream = context->streams[i];
4562236b 1425
ab2541b6 1426 update_stream_signal(stream);
4562236b 1427
ab2541b6
AC		 1428 /* update actual pixel clock on all streams */
1429 if (dc_is_hdmi_signal(stream->signal))
1430 stream->phy_pix_clk = get_norm_pix_clk(
1431 &stream->public.timing);
1432 else
1433 stream->phy_pix_clk =
1434 stream->public.timing.pix_clk_khz;
4562236b
HW		 1435 }
1436}
1437
1438enum dc_status resource_map_pool_resources(
1439 const struct core_dc *dc,
430ef426
DL		 1440 struct validate_context *context,
1441 struct validate_context *old_context)
4562236b 1442{
a2b8659d 1443 const struct resource_pool *pool = dc->res_pool;
ab2541b6 1444 int i, j;
4562236b 1445
430ef426 1446 calculate_phy_pix_clks(context);
4562236b 1447
430ef426 1448 for (i = 0; old_context && i < context->stream_count; i++) {
ab2541b6 1449 struct core_stream *stream = context->streams[i];
4562236b 1450
430ef426
DL		 1451 if (!resource_is_stream_unchanged(old_context, stream)) {
1452 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1453 stream->bit_depth_params =
430ef426
DL		 1454 old_context->streams[i]->bit_depth_params;
1455 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1456 continue;
1457 }
4b679bc3 1458 }
7e2fe319 1459
ab2541b6 1460 /* mark resources used for stream that is already active */
a2b8659d 1461 for (j = 0; j < pool->pipe_count; j++) {
ab2541b6
AC		 1462 struct pipe_ctx *pipe_ctx =
1463 &context->res_ctx.pipe_ctx[j];
1464 const struct pipe_ctx *old_pipe_ctx =
430ef426 1465 &old_context->res_ctx.pipe_ctx[j];
4562236b 1466
ab2541b6
AC		 1467 if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
1468 continue;
8c737fcc 1469
268cadbd
YS		 1470 if (old_pipe_ctx->top_pipe)
1471 continue;
1472
ab2541b6
AC		 1473 pipe_ctx->stream = stream;
1474 copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
4562236b 1475
ab2541b6
AC		 1476 /* Split pipe resource, do not acquire back end */
1477 if (!pipe_ctx->stream_enc)
1478 continue;
4562236b 1479
ab2541b6 1480 set_stream_engine_in_use(
a2b8659d 1481 &context->res_ctx, pool,
ab2541b6
AC		 1482 pipe_ctx->stream_enc);
1483
1484 /* Switch to dp clock source only if there is
1485 * no non dp stream that shares the same timing
1486 * with the dp stream.
1487 */
1488 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1489 !find_pll_sharable_stream(stream, context))
a2b8659d 1490 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 1491
1492 resource_reference_clock_source(
a2b8659d 1493 &context->res_ctx, pool,
ab2541b6
AC		 1494 pipe_ctx->clock_source);
1495
a2b8659d
TC		 1496 set_audio_in_use(&context->res_ctx, pool,
1497 pipe_ctx->audio);
4562236b
HW		 1498 }
1499 }
1500
ab2541b6
AC		 1501 for (i = 0; i < context->stream_count; i++) {
1502 struct core_stream *stream = context->streams[i];
1503 struct pipe_ctx *pipe_ctx = NULL;
1504 int pipe_idx = -1;
4562236b 1505
430ef426 1506 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 1507 continue;
1508 /* acquire new resources */
5d11e9fc
DL		 1509 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
1510#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1511 if (pipe_idx < 0)
1512 acquire_first_split_pipe(&context->res_ctx, pool, stream);
1513#endif
ab2541b6
AC		 1514 if (pipe_idx < 0)
1515 return DC_NO_CONTROLLER_RESOURCE;
1516
ab2541b6
AC		 1517 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1518
1519 pipe_ctx->stream_enc =
1520 find_first_free_match_stream_enc_for_link(
a2b8659d 1521 &context->res_ctx, pool, stream);
ab2541b6
AC		 1522
1523 if (!pipe_ctx->stream_enc)
1524 return DC_NO_STREAM_ENG_RESOURCE;
1525
1526 set_stream_engine_in_use(
a2b8659d 1527 &context->res_ctx, pool,
ab2541b6
AC		 1528 pipe_ctx->stream_enc);
1529
1530 /* TODO: Add check if ASIC support and EDID audio */
4a9a5d62 1531 if (!stream->sink->public.converter_disable_audio &&
ab2541b6
AC		 1532 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1533 stream->public.audio_info.mode_count) {
1534 pipe_ctx->audio = find_first_free_audio(
a2b8659d 1535 &context->res_ctx, pool);
ab2541b6
AC		 1536
1537 /*
1538 * Audio assigned in order first come first get.
1539 * There are asics which has number of audio
1540 * resources less then number of pipes
1541 */
1542 if (pipe_ctx->audio)
1543 set_audio_in_use(
a2b8659d 1544 &context->res_ctx, pool,
ab2541b6 1545 pipe_ctx->audio);
4562236b 1546 }
ab2541b6
AC		 1547
1548 context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
4562236b
HW		 1549 }
1550
1551 return DC_OK;
1552}
1553
ab2541b6
AC		 1554/* first stream in the context is used to populate the rest */
1555void validate_guaranteed_copy_streams(
4562236b 1556 struct validate_context *context,
ab2541b6 1557 int max_streams)
4562236b
HW		 1558{
1559 int i;
1560
ab2541b6
AC		 1561 for (i = 1; i < max_streams; i++) {
1562 context->streams[i] = context->streams[0];
4562236b
HW		 1563
1564 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1565 &context->res_ctx.pipe_ctx[i]);
1566 context->res_ctx.pipe_ctx[i].stream =
1567 context->res_ctx.pipe_ctx[0].stream;
1568
ab2541b6
AC		 1569 dc_stream_retain(&context->streams[i]->public);
1570 context->stream_count++;
4562236b
HW		 1571 }
1572}
1573
6e4d6bee
TC		 1574static void patch_gamut_packet_checksum(
1575 struct encoder_info_packet *gamut_packet)
4562236b 1576{
4562236b 1577 /* For gamut we recalc checksum */
6e4d6bee 1578 if (gamut_packet->valid) {
4562236b
HW		 1579 uint8_t chk_sum = 0;
1580 uint8_t *ptr;
1581 uint8_t i;
1582
4562236b 1583 /*start of the Gamut data. */
6e4d6bee 1584 ptr = &gamut_packet->sb[3];
4562236b 1585
6e4d6bee 1586 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1587 chk_sum += ptr[i];
1588
6e4d6bee 1589 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1590 }
4562236b
HW		 1591}
1592
1593static void set_avi_info_frame(
6e4d6bee 1594 struct encoder_info_packet *info_packet,
4562236b
HW		 1595 struct pipe_ctx *pipe_ctx)
1596{
1597 struct core_stream *stream = pipe_ctx->stream;
1598 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1599 struct info_frame info_frame = { {0} };
1600 uint32_t pixel_encoding = 0;
1601 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1602 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1603 bool itc = false;
1604 uint8_t cn0_cn1 = 0;
1605 uint8_t *check_sum = NULL;
1606 uint8_t byte_index = 0;
e8d726b7 1607 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
4562236b 1608
4562236b
HW		 1609 color_space = pipe_ctx->stream->public.output_color_space;
1610
1611 /* Initialize header */
e8d726b7 1612 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1613 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1614 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1615 hdmi_info->bits.header.version = 2;
1616 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1617
1618 /*
1619 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1620 * according to HDMI 2.0 spec (Section 10.1)
1621 */
1622
1623 switch (stream->public.timing.pixel_encoding) {
1624 case PIXEL_ENCODING_YCBCR422:
1625 pixel_encoding = 1;
1626 break;
1627
1628 case PIXEL_ENCODING_YCBCR444:
1629 pixel_encoding = 2;
1630 break;
1631 case PIXEL_ENCODING_YCBCR420:
1632 pixel_encoding = 3;
1633 break;
1634
1635 case PIXEL_ENCODING_RGB:
1636 default:
1637 pixel_encoding = 0;
1638 }
1639
1640 /* Y0_Y1_Y2 : The pixel encoding */
1641 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1642 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1643
1644 /* A0 = 1 Active Format Information valid */
e8d726b7 1645 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1646
1647 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1648 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1649
e8d726b7 1650 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1651
1652 /* S0, S1 : Underscan / Overscan */
1653 /* TODO: un-hardcode scan type */
1654 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1655 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1656
1657 /* C0, C1 : Colorimetry */
8fde5884
CL		 1658 if (color_space == COLOR_SPACE_YCBCR709 ||
1659 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1660 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1661 else if (color_space == COLOR_SPACE_YCBCR601 ||
1662 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1663 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884
CL		 1664 else {
1665 if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
1666 BREAK_TO_DEBUGGER();
e8d726b7 1667 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1668 }
534db198 1669 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1670 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1671 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1672 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1673 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1674 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1675 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1676 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1677 }
1678
4562236b
HW		 1679 /* TODO: un-hardcode aspect ratio */
1680 aspect = stream->public.timing.aspect_ratio;
1681
1682 switch (aspect) {
1683 case ASPECT_RATIO_4_3:
1684 case ASPECT_RATIO_16_9:
e8d726b7 1685 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1686 break;
1687
1688 case ASPECT_RATIO_NO_DATA:
1689 case ASPECT_RATIO_64_27:
1690 case ASPECT_RATIO_256_135:
1691 default:
e8d726b7 1692 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1693 }
1694
1695 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 1696 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1697
1698 /* TODO: un-hardcode cn0_cn1 and itc */
1699 cn0_cn1 = 0;
1700 itc = false;
1701
1702 if (itc) {
e8d726b7
RA		 1703 hdmi_info->bits.ITC = 1;
1704 hdmi_info->bits.CN0_CN1 = cn0_cn1;
4562236b
HW		 1705 }
1706
1707 /* TODO : We should handle YCC quantization */
1708 /* but we do not have matrix calculation */
1709 if (color_space == COLOR_SPACE_SRGB) {
e8d726b7
RA		 1710 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
1711 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
4562236b 1712 } else if (color_space == COLOR_SPACE_SRGB_LIMITED) {
e8d726b7
RA		 1713 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
1714 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 1715 } else {
e8d726b7
RA		 1716 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
1717 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b
HW		 1718 }
1719
e8d726b7 1720 hdmi_info->bits.VIC0_VIC7 =
4562236b
HW		 1721 stream->public.timing.vic;
1722
1723 /* pixel repetition
1724 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
1725 * repetition start from 1 */
e8d726b7 1726 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 1727
1728 /* Bar Info
1729 * barTop: Line Number of End of Top Bar.
1730 * barBottom: Line Number of Start of Bottom Bar.
1731 * barLeft: Pixel Number of End of Left Bar.
1732 * barRight: Pixel Number of Start of Right Bar. */
e8d726b7
RA		 1733 hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
1734 hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top
4562236b 1735 - stream->public.timing.v_border_bottom + 1);
e8d726b7
RA		 1736 hdmi_info->bits.bar_left = stream->public.timing.h_border_left;
1737 hdmi_info->bits.bar_right = (stream->public.timing.h_total
4562236b
HW		 1738 - stream->public.timing.h_border_right + 1);
1739
1740 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 1741 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
1742
3e183c5f 1743 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 1744
3e183c5f 1745 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 1746 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 1747
1748 /* one byte complement */
1749 *check_sum = (uint8_t) (0x100 - *check_sum);
1750
1751 /* Store in hw_path_mode */
e8d726b7
RA		 1752 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
1753 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
1754 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 1755
e66e4d64
HW		 1756 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
1757 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 1758 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 1759 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 1760
1761 info_packet->valid = true;
1762}
1763
6e4d6bee
TC		 1764static void set_vendor_info_packet(
1765 struct encoder_info_packet *info_packet,
1766 struct core_stream *stream)
4562236b
HW		 1767{
1768 uint32_t length = 0;
1769 bool hdmi_vic_mode = false;
1770 uint8_t checksum = 0;
1771 uint32_t i = 0;
1772 enum dc_timing_3d_format format;
1773
4562236b
HW		 1774 format = stream->public.timing.timing_3d_format;
1775
1776 /* Can be different depending on packet content */
1777 length = 5;
1778
1779 if (stream->public.timing.hdmi_vic != 0
1780 && stream->public.timing.h_total >= 3840
1781 && stream->public.timing.v_total >= 2160)
1782 hdmi_vic_mode = true;
1783
1784 /* According to HDMI 1.4a CTS, VSIF should be sent
1785 * for both 3D stereo and HDMI VIC modes.
1786 * For all other modes, there is no VSIF sent. */
1787
1788 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
1789 return;
1790
1791 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
1792 info_packet->sb[1] = 0x03;
1793 info_packet->sb[2] = 0x0C;
1794 info_packet->sb[3] = 0x00;
1795
1796 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
1797 * The value for HDMI_Video_Format are:
1798 * 0x0 (0b000) - No additional HDMI video format is presented in this
1799 * packet
1800 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
1801 * parameter follows
1802 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
1803 * potentially 3D_Ext_Data follows
1804 * 0x3..0x7 (0b011..0b111) - reserved for future use */
1805 if (format != TIMING_3D_FORMAT_NONE)
1806 info_packet->sb[4] = (2 << 5);
1807 else if (hdmi_vic_mode)
1808 info_packet->sb[4] = (1 << 5);
1809
1810 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
1811 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
1812 * The value for 3D_Structure are:
1813 * 0x0 - Frame Packing
1814 * 0x1 - Field Alternative
1815 * 0x2 - Line Alternative
1816 * 0x3 - Side-by-Side (full)
1817 * 0x4 - L + depth
1818 * 0x5 - L + depth + graphics + graphics-depth
1819 * 0x6 - Top-and-Bottom
1820 * 0x7 - Reserved for future use
1821 * 0x8 - Side-by-Side (Half)
1822 * 0x9..0xE - Reserved for future use
1823 * 0xF - Not used */
1824 switch (format) {
1825 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
1826 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
1827 info_packet->sb[5] = (0x0 << 4);
1828 break;
1829
1830 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
1831 case TIMING_3D_FORMAT_SBS_SW_PACKED:
1832 info_packet->sb[5] = (0x8 << 4);
1833 length = 6;
1834 break;
1835
1836 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
1837 case TIMING_3D_FORMAT_TB_SW_PACKED:
1838 info_packet->sb[5] = (0x6 << 4);
1839 break;
1840
1841 default:
1842 break;
1843 }
1844
1845 /*PB5: If PB4 is set to 0x1 (extended resolution format)
1846 * fill PB5 with the correct HDMI VIC code */
1847 if (hdmi_vic_mode)
1848 info_packet->sb[5] = stream->public.timing.hdmi_vic;
1849
1850 /* Header */
3e183c5f 1851 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 1852 info_packet->hb1 = 0x01; /* Version */
1853
1854 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
1855 info_packet->hb2 = (uint8_t) (length);
1856
1857 /* Calculate checksum */
1858 checksum = 0;
1859 checksum += info_packet->hb0;
1860 checksum += info_packet->hb1;
1861 checksum += info_packet->hb2;
1862
1863 for (i = 1; i <= length; i++)
1864 checksum += info_packet->sb[i];
1865
1866 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
1867
1868 info_packet->valid = true;
1869}
1870
6e4d6bee
TC		 1871static void set_spd_info_packet(
1872 struct encoder_info_packet *info_packet,
1873 struct core_stream *stream)
4562236b
HW		 1874{
1875 /* SPD info packet for FreeSync */
1876
1877 unsigned char checksum = 0;
1878 unsigned int idx, payload_size = 0;
1879
1880 /* Check if Freesync is supported. Return if false. If true,
1881 * set the corresponding bit in the info packet
1882 */
1883 if (stream->public.freesync_ctx.supported == false)
1884 return;
1885
1886 if (dc_is_hdmi_signal(stream->signal)) {
1887
1888 /* HEADER */
1889
1890 /* HB0 = Packet Type = 0x83 (Source Product
1891 * Descriptor InfoFrame)
1892 */
3e183c5f 1893 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1894
1895 /* HB1 = Version = 0x01 */
1896 info_packet->hb1 = 0x01;
1897
1898 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1899 info_packet->hb2 = 0x08;
1900
1901 payload_size = 0x08;
1902
1903 } else if (dc_is_dp_signal(stream->signal)) {
1904
1905 /* HEADER */
1906
1907 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1908 * when used to associate audio related info packets
1909 */
1910 info_packet->hb0 = 0x00;
1911
1912 /* HB1 = Packet Type = 0x83 (Source Product
1913 * Descriptor InfoFrame)
1914 */
3e183c5f 1915 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1916
1917 /* HB2 = [Bits 7:0 = Least significant eight bits -
1918 * For INFOFRAME, the value must be 1Bh]
1919 */
1920 info_packet->hb2 = 0x1B;
1921
1922 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
1923 * [Bits 1:0 = Most significant two bits = 0x00]
1924 */
1925 info_packet->hb3 = 0x04;
1926
1927 payload_size = 0x1B;
1928 }
1929
1930 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
1931 info_packet->sb[1] = 0x1A;
1932
1933 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
1934 info_packet->sb[2] = 0x00;
1935
1936 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
1937 info_packet->sb[3] = 0x00;
1938
1939 /* PB4 = Reserved */
1940 info_packet->sb[4] = 0x00;
1941
1942 /* PB5 = Reserved */
1943 info_packet->sb[5] = 0x00;
1944
1945 /* PB6 = [Bits 7:3 = Reserved] */
1946 info_packet->sb[6] = 0x00;
1947
1948 if (stream->public.freesync_ctx.supported == true)
1949 /* PB6 = [Bit 0 = FreeSync Supported] */
1950 info_packet->sb[6] |= 0x01;
1951
1952 if (stream->public.freesync_ctx.enabled == true)
1953 /* PB6 = [Bit 1 = FreeSync Enabled] */
1954 info_packet->sb[6] |= 0x02;
1955
1956 if (stream->public.freesync_ctx.active == true)
1957 /* PB6 = [Bit 2 = FreeSync Active] */
1958 info_packet->sb[6] |= 0x04;
1959
1960 /* PB7 = FreeSync Minimum refresh rate (Hz) */
1961 info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx.
1962 min_refresh_in_micro_hz / 1000000);
1963
1964 /* PB8 = FreeSync Maximum refresh rate (Hz)
1965 *
1966 * Note: We do not use the maximum capable refresh rate
1967 * of the panel, because we should never go above the field
1968 * rate of the mode timing set.
1969 */
1970 info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx.
1971 nominal_refresh_in_micro_hz / 1000000);
1972
1973 /* PB9 - PB27 = Reserved */
1974 for (idx = 9; idx <= 27; idx++)
1975 info_packet->sb[idx] = 0x00;
1976
1977 /* Calculate checksum */
1978 checksum += info_packet->hb0;
1979 checksum += info_packet->hb1;
1980 checksum += info_packet->hb2;
1981 checksum += info_packet->hb3;
1982
1983 for (idx = 1; idx <= payload_size; idx++)
1984 checksum += info_packet->sb[idx];
1985
1986 /* PB0 = Checksum (one byte complement) */
1987 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
1988
1989 info_packet->valid = true;
1990}
1991
1646a6fe 1992static void set_hdr_static_info_packet(
6e4d6bee 1993 struct encoder_info_packet *info_packet,
1646a6fe 1994 struct core_surface *surface,
6e4d6bee 1995 struct core_stream *stream)
1646a6fe 1996{
e5cf325b 1997 uint16_t i = 0;
1646a6fe 1998 enum signal_type signal = stream->signal;
e5cf325b
HW		 1999 struct dc_hdr_static_metadata hdr_metadata;
2000 uint32_t data;
1646a6fe
AW		 2001
2002 if (!surface)
2003 return;
2004
e5cf325b 2005 hdr_metadata = surface->public.hdr_static_ctx;
1646a6fe 2006
70063a59 2007 if (!hdr_metadata.hdr_supported)
10bff005
YS		 2008 return;
2009
1646a6fe
AW		 2010 if (dc_is_hdmi_signal(signal)) {
2011 info_packet->valid = true;
2012
2013 info_packet->hb0 = 0x87;
2014 info_packet->hb1 = 0x01;
2015 info_packet->hb2 = 0x1A;
2016 i = 1;
2017 } else if (dc_is_dp_signal(signal)) {
2018 info_packet->valid = true;
2019
2020 info_packet->hb0 = 0x00;
2021 info_packet->hb1 = 0x87;
2022 info_packet->hb2 = 0x1D;
2023 info_packet->hb3 = (0x13 << 2);
2024 i = 2;
2025 }
2026
1646a6fe
AW		 2027 data = hdr_metadata.is_hdr;
2028 info_packet->sb[i++] = data ? 0x02 : 0x00;
2029 info_packet->sb[i++] = 0x00;
2030
2031 data = hdr_metadata.chromaticity_green_x / 2;
2032 info_packet->sb[i++] = data & 0xFF;
2033 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2034
2035 data = hdr_metadata.chromaticity_green_y / 2;
2036 info_packet->sb[i++] = data & 0xFF;
2037 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2038
2039 data = hdr_metadata.chromaticity_blue_x / 2;
2040 info_packet->sb[i++] = data & 0xFF;
2041 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2042
2043 data = hdr_metadata.chromaticity_blue_y / 2;
2044 info_packet->sb[i++] = data & 0xFF;
2045 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2046
2047 data = hdr_metadata.chromaticity_red_x / 2;
2048 info_packet->sb[i++] = data & 0xFF;
2049 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2050
2051 data = hdr_metadata.chromaticity_red_y / 2;
2052 info_packet->sb[i++] = data & 0xFF;
2053 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2054
2055 data = hdr_metadata.chromaticity_white_point_x / 2;
2056 info_packet->sb[i++] = data & 0xFF;
2057 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2058
2059 data = hdr_metadata.chromaticity_white_point_y / 2;
2060 info_packet->sb[i++] = data & 0xFF;
2061 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2062
2063 data = hdr_metadata.max_luminance;
2064 info_packet->sb[i++] = data & 0xFF;
2065 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2066
2067 data = hdr_metadata.min_luminance;
2068 info_packet->sb[i++] = data & 0xFF;
2069 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2070
2071 data = hdr_metadata.maximum_content_light_level;
2072 info_packet->sb[i++] = data & 0xFF;
2073 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2074
2075 data = hdr_metadata.maximum_frame_average_light_level;
2076 info_packet->sb[i++] = data & 0xFF;
2077 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2078
2079 if (dc_is_hdmi_signal(signal)) {
2080 uint32_t checksum = 0;
2081
2082 checksum += info_packet->hb0;
2083 checksum += info_packet->hb1;
2084 checksum += info_packet->hb2;
2085
2086 for (i = 1; i <= info_packet->hb2; i++)
2087 checksum += info_packet->sb[i];
2088
2089 info_packet->sb[0] = 0x100 - checksum;
2090 } else if (dc_is_dp_signal(signal)) {
2091 info_packet->sb[0] = 0x01;
2092 info_packet->sb[1] = 0x1A;
2093 }
2094}
2095
6e4d6bee
TC		 2096static void set_vsc_info_packet(
2097 struct encoder_info_packet *info_packet,
2098 struct core_stream *stream)
4562236b
HW		 2099{
2100 unsigned int vscPacketRevision = 0;
2101 unsigned int i;
2102
94267b3d 2103 if (stream->sink->link->psr_enabled) {
4562236b
HW		 2104 vscPacketRevision = 2;
2105 }
2106
2107 /* VSC packet not needed based on the features
2108 * supported by this DP display
2109 */
2110 if (vscPacketRevision == 0)
2111 return;
2112
2113 if (vscPacketRevision == 0x2) {
2114 /* Secondary-data Packet ID = 0*/
2115 info_packet->hb0 = 0x00;
2116 /* 07h - Packet Type Value indicating Video
2117 * Stream Configuration packet
2118 */
2119 info_packet->hb1 = 0x07;
2120 /* 02h = VSC SDP supporting 3D stereo and PSR
2121 * (applies to eDP v1.3 or higher).
2122 */
2123 info_packet->hb2 = 0x02;
2124 /* 08h = VSC packet supporting 3D stereo + PSR
2125 * (HB2 = 02h).
2126 */
2127 info_packet->hb3 = 0x08;
2128
2129 for (i = 0; i < 28; i++)
2130 info_packet->sb[i] = 0;
2131
2132 info_packet->valid = true;
2133 }
2134
2135 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2136}
2137
8122a253 2138void dc_resource_validate_ctx_destruct(struct validate_context *context)
4562236b
HW		 2139{
2140 int i, j;
2141
ab2541b6
AC		 2142 for (i = 0; i < context->stream_count; i++) {
2143 for (j = 0; j < context->stream_status[i].surface_count; j++)
4562236b 2144 dc_surface_release(
ab2541b6 2145 context->stream_status[i].surfaces[j]);
4562236b 2146
ab2541b6
AC		 2147 context->stream_status[i].surface_count = 0;
2148 dc_stream_release(&context->streams[i]->public);
2149 context->streams[i] = NULL;
4562236b
HW		 2150 }
2151}
2152
2153/*
ab2541b6 2154 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2155 * by the src_ctx
2156 */
8122a253 2157void dc_resource_validate_ctx_copy_construct(
4562236b
HW		 2158 const struct validate_context *src_ctx,
2159 struct validate_context *dst_ctx)
2160{
2161 int i, j;
2162
2163 *dst_ctx = *src_ctx;
2164
a2b8659d 2165 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2166 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2167
2168 if (cur_pipe->top_pipe)
2169 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2170
2171 if (cur_pipe->bottom_pipe)
2172 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2173
2174 }
2175
ab2541b6
AC		 2176 for (i = 0; i < dst_ctx->stream_count; i++) {
2177 dc_stream_retain(&dst_ctx->streams[i]->public);
2178 for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++)
4562236b 2179 dc_surface_retain(
ab2541b6 2180 dst_ctx->stream_status[i].surfaces[j]);
4562236b
HW		 2181 }
2182}
2183
2184struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2185 struct resource_context *res_ctx,
2186 const struct resource_pool *pool)
4562236b
HW		 2187{
2188 int i;
2189
a2b8659d 2190 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2191 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2192 return pool->clock_sources[i];
4562236b
HW		 2193 }
2194
2195 return NULL;
2196}
2197
2198void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2199{
2200 enum signal_type signal = SIGNAL_TYPE_NONE;
6e4d6bee 2201 struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
4562236b
HW		 2202
2203 /* default all packets to invalid */
6e4d6bee
TC		 2204 info->avi.valid = false;
2205 info->gamut.valid = false;
2206 info->vendor.valid = false;
630e3573 2207 info->spd.valid = false;
6e4d6bee
TC		 2208 info->hdrsmd.valid = false;
2209 info->vsc.valid = false;
4562236b
HW		 2210
2211 signal = pipe_ctx->stream->signal;
2212
2213 /* HDMi and DP have different info packets*/
2214 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2215 set_avi_info_frame(&info->avi, pipe_ctx);
2216
2217 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2218
2219 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2220
2221 set_hdr_static_info_packet(&info->hdrsmd,
2222 pipe_ctx->surface, pipe_ctx->stream);
2223
a33fa99d 2224 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2225 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2226
2227 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2228
2229 set_hdr_static_info_packet(&info->hdrsmd,
2230 pipe_ctx->surface, pipe_ctx->stream);
a33fa99d 2231 }
4562236b 2232
6e4d6bee 2233 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2234}
2235
2236enum dc_status resource_map_clock_resources(
2237 const struct core_dc *dc,
430ef426
DL		 2238 struct validate_context *context,
2239 struct validate_context *old_context)
4562236b 2240{
ab2541b6 2241 int i, j;
a2b8659d 2242 const struct resource_pool *pool = dc->res_pool;
4562236b
HW		 2243
2244 /* acquire new resources */
ab2541b6
AC		 2245 for (i = 0; i < context->stream_count; i++) {
2246 const struct core_stream *stream = context->streams[i];
4562236b 2247
430ef426 2248 if (old_context && resource_is_stream_unchanged(old_context, stream))
ab2541b6
AC		 2249 continue;
2250
2251 for (j = 0; j < MAX_PIPES; j++) {
2252 struct pipe_ctx *pipe_ctx =
2253 &context->res_ctx.pipe_ctx[j];
4562236b 2254
ab2541b6 2255 if (context->res_ctx.pipe_ctx[j].stream != stream)
4562236b
HW		 2256 continue;
2257
ab2541b6
AC		 2258 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2259 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
a2b8659d 2260 pipe_ctx->clock_source = pool->dp_clock_source;
ab2541b6
AC		 2261 else {
2262 pipe_ctx->clock_source = NULL;
4562236b 2263
ab2541b6
AC		 2264 if (!dc->public.config.disable_disp_pll_sharing)
2265 resource_find_used_clk_src_for_sharing(
2266 &context->res_ctx,
2267 pipe_ctx);
4562236b 2268
ab2541b6 2269 if (pipe_ctx->clock_source == NULL)
4562236b 2270 pipe_ctx->clock_source =
a2b8659d
TC		 2271 dc_resource_find_first_free_pll(
2272 &context->res_ctx,
2273 pool);
ab2541b6 2274 }
4562236b 2275
ab2541b6
AC		 2276 if (pipe_ctx->clock_source == NULL)
2277 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2278
ab2541b6 2279 resource_reference_clock_source(
a2b8659d 2280 &context->res_ctx, pool,
ab2541b6 2281 pipe_ctx->clock_source);
4562236b 2282
ab2541b6
AC		 2283 /* only one cs per stream regardless of mpo */
2284 break;
4562236b
HW		 2285 }
2286 }
2287
2288 return DC_OK;
2289}
2290
2291/*
2292 * Note: We need to disable output if clock sources change,
2293 * since bios does optimization and doesn't apply if changing
2294 * PHY when not already disabled.
2295 */
2296bool pipe_need_reprogram(
2297 struct pipe_ctx *pipe_ctx_old,
2298 struct pipe_ctx *pipe_ctx)
2299{
2300 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2301 return true;
2302
2303 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2304 return true;
2305
2306 if (pipe_ctx_old->audio != pipe_ctx->audio)
2307 return true;
2308
2309 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2310 && pipe_ctx_old->stream != pipe_ctx->stream)
2311 return true;
2312
2313 if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
2314 return true;
2315
2316 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2317 return true;
2318
2319
2320 return false;
2321}
529cad0f
DW		 2322
2323void resource_build_bit_depth_reduction_params(const struct core_stream *stream,
2324 struct bit_depth_reduction_params *fmt_bit_depth)
2325{
2326 enum dc_dither_option option = stream->public.dither_option;
2327 enum dc_pixel_encoding pixel_encoding =
2328 stream->public.timing.pixel_encoding;
2329
2330 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2331
2332 if (option == DITHER_OPTION_DISABLE)
2333 return;
2334
2335 if (option == DITHER_OPTION_TRUN6) {
2336 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2337 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2338 } else if (option == DITHER_OPTION_TRUN8 ||
2339 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2340 option == DITHER_OPTION_TRUN8_FM6) {
2341 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2342 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2343 } else if (option == DITHER_OPTION_TRUN10 ||
2344 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2345 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2346 option == DITHER_OPTION_TRUN10_FM8 ||
2347 option == DITHER_OPTION_TRUN10_FM6 ||
2348 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2349 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2350 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2351 }
2352
2353 /* special case - Formatter can only reduce by 4 bits at most.
2354 * When reducing from 12 to 6 bits,
2355 * HW recommends we use trunc with round mode
2356 * (if we did nothing, trunc to 10 bits would be used)
2357 * note that any 12->10 bit reduction is ignored prior to DCE8,
2358 * as the input was 10 bits.
2359 */
2360 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2361 option == DITHER_OPTION_SPATIAL6 ||
2362 option == DITHER_OPTION_FM6) {
2363 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2364 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2365 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2366 }
2367
2368 /* spatial dither
2369 * note that spatial modes 1-3 are never used
2370 */
2371 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2372 option == DITHER_OPTION_SPATIAL6 ||
2373 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2374 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2375 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2376 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2377 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2378 fmt_bit_depth->flags.RGB_RANDOM =
2379 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2380 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2381 option == DITHER_OPTION_SPATIAL8 ||
2382 option == DITHER_OPTION_SPATIAL8_FM6 ||
2383 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2384 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2385 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2386 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2387 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2388 fmt_bit_depth->flags.RGB_RANDOM =
2389 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2390 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2391 option == DITHER_OPTION_SPATIAL10 ||
2392 option == DITHER_OPTION_SPATIAL10_FM8 ||
2393 option == DITHER_OPTION_SPATIAL10_FM6) {
2394 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2395 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2396 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2397 fmt_bit_depth->flags.RGB_RANDOM =
2398 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2399 }
2400
2401 if (option == DITHER_OPTION_SPATIAL6 ||
2402 option == DITHER_OPTION_SPATIAL8 ||
2403 option == DITHER_OPTION_SPATIAL10) {
2404 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2405 } else {
2406 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2407 }
2408
2409 //////////////////////
2410 //// temporal dither
2411 //////////////////////
2412 if (option == DITHER_OPTION_FM6 ||
2413 option == DITHER_OPTION_SPATIAL8_FM6 ||
2414 option == DITHER_OPTION_SPATIAL10_FM6 ||
2415 option == DITHER_OPTION_TRUN10_FM6 ||
2416 option == DITHER_OPTION_TRUN8_FM6 ||
2417 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2418 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2419 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2420 } else if (option == DITHER_OPTION_FM8 ||
2421 option == DITHER_OPTION_SPATIAL10_FM8 ||
2422 option == DITHER_OPTION_TRUN10_FM8) {
2423 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2424 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2425 } else if (option == DITHER_OPTION_FM10) {
2426 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2427 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2428 }
2429
2430 fmt_bit_depth->pixel_encoding = pixel_encoding;
2431}
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