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drm/amdgpu: set adev->num_vmhubs for gmc6,7,8
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW		 44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
dc37a9a0 49#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 50#include "dcn10/dcn10_resource.h"
51#endif
7ed4e635
HW		 52#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
53#include "dcn20/dcn20_resource.h"
54#endif
2c8ad2d5 55#include "dce120/dce120_resource.h"
5d4b05dd
BL		 56
57#define DC_LOGGER_INIT(logger)
58
4562236b
HW		 59enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
60{
61 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
62 switch (asic_id.chip_family) {
63
64 case FAMILY_CI:
4562236b
HW		 65 dc_version = DCE_VERSION_8_0;
66 break;
ebfdf0d0
AD		 67 case FAMILY_KV:
68 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
70 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
71 dc_version = DCE_VERSION_8_3;
72 else
73 dc_version = DCE_VERSION_8_1;
74 break;
4562236b
HW		 75 case FAMILY_CZ:
76 dc_version = DCE_VERSION_11_0;
77 break;
78
79 case FAMILY_VI:
80 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
82 dc_version = DCE_VERSION_10_0;
83 break;
84 }
85 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 86 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 88 dc_version = DCE_VERSION_11_2;
89 }
0c75d5ac
JFZ		 90 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
91 dc_version = DCE_VERSION_11_22;
4562236b 92 break;
2c8ad2d5 93 case FAMILY_AI:
b8b6ce89
LL		 94 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
95 dc_version = DCE_VERSION_12_1;
96 else
97 dc_version = DCE_VERSION_12_0;
2c8ad2d5 98 break;
dc37a9a0 99#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 100 case FAMILY_RV:
101 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 102 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
103 dc_version = DCN_VERSION_1_01;
ff5ef992
AD		 104 break;
105#endif
7ed4e635
HW		 106
107#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
111#endif
4562236b
HW		 112 default:
113 dc_version = DCE_VERSION_UNKNOWN;
114 break;
115 }
116 return dc_version;
117}
118
d9673c92
HW		 119struct resource_pool *dc_create_resource_pool(struct dc *dc,
120 const struct dc_init_data *init_data,
121 enum dce_version dc_version)
4562236b 122{
5ac3d3c9 123 struct resource_pool *res_pool = NULL;
4562236b
HW		 124
125 switch (dc_version) {
126 case DCE_VERSION_8_0:
7992a629 127 res_pool = dce80_create_resource_pool(
d9673c92 128 init_data->num_virtual_links, dc);
7992a629 129 break;
ebfdf0d0 130 case DCE_VERSION_8_1:
7992a629 131 res_pool = dce81_create_resource_pool(
d9673c92 132 init_data->num_virtual_links, dc);
7992a629 133 break;
ebfdf0d0 134 case DCE_VERSION_8_3:
7992a629 135 res_pool = dce83_create_resource_pool(
d9673c92 136 init_data->num_virtual_links, dc);
5ac3d3c9 137 break;
4562236b 138 case DCE_VERSION_10_0:
5ac3d3c9 139 res_pool = dce100_create_resource_pool(
d9673c92 140 init_data->num_virtual_links, dc);
5ac3d3c9 141 break;
4562236b 142 case DCE_VERSION_11_0:
5ac3d3c9 143 res_pool = dce110_create_resource_pool(
d9673c92
HW		 144 init_data->num_virtual_links, dc,
145 init_data->asic_id);
5ac3d3c9 146 break;
4562236b 147 case DCE_VERSION_11_2:
0c75d5ac 148 case DCE_VERSION_11_22:
5ac3d3c9 149 res_pool = dce112_create_resource_pool(
d9673c92 150 init_data->num_virtual_links, dc);
5ac3d3c9 151 break;
2c8ad2d5 152 case DCE_VERSION_12_0:
b8b6ce89 153 case DCE_VERSION_12_1:
2c8ad2d5 154 res_pool = dce120_create_resource_pool(
d9673c92 155 init_data->num_virtual_links, dc);
2c8ad2d5 156 break;
ff5ef992 157
dc37a9a0 158#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 159 case DCN_VERSION_1_0:
0e3d73f1 160 case DCN_VERSION_1_01:
d9673c92 161 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992
AD		 162 break;
163#endif
3639fa68
ZF		 164
165
7ed4e635
HW		 166#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
167 case DCN_VERSION_2_0:
168 res_pool = dcn20_create_resource_pool(init_data, dc);
169 break;
170#endif
171
4562236b
HW		 172 default:
173 break;
174 }
5ac3d3c9 175 if (res_pool != NULL) {
9adc8050 176 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 177 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 178 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 179 /* initialize with firmware data first, no all
180 * ASIC have DCCG SW component. FPGA or
181 * simulation need initialization of
182 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
183 * with xtalin_clock_inKhz
184 */
185 res_pool->ref_clocks.dccg_ref_clock_inKhz =
186 res_pool->ref_clocks.xtalin_clock_inKhz;
187 res_pool->ref_clocks.dchub_ref_clock_inKhz =
188 res_pool->ref_clocks.xtalin_clock_inKhz;
189 } else
190 ASSERT_CRITICAL(false);
5ac3d3c9 191 }
4562236b 192
5ac3d3c9 193 return res_pool;
4562236b
HW		 194}
195
fb3466a4 196void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 197{
198 if (dc) {
199 if (dc->res_pool)
200 dc->res_pool->funcs->destroy(&dc->res_pool);
201
d029810c 202 kfree(dc->hwseq);
4562236b
HW		 203 }
204}
205
206static void update_num_audio(
207 const struct resource_straps *straps,
208 unsigned int *num_audio,
209 struct audio_support *aud_support)
210{
b8e9eb72
CL		 211 aud_support->dp_audio = true;
212 aud_support->hdmi_audio_native = false;
213 aud_support->hdmi_audio_on_dongle = false;
214
4562236b 215 if (straps->hdmi_disable == 0) {
4562236b
HW		 216 if (straps->dc_pinstraps_audio & 0x2) {
217 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 218 aud_support->hdmi_audio_native = true;
4562236b
HW		 219 }
220 }
221
222 switch (straps->audio_stream_number) {
223 case 0: /* multi streams supported */
224 break;
225 case 1: /* multi streams not supported */
226 *num_audio = 1;
227 break;
228 default:
229 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 230 }
4562236b
HW		 231}
232
233bool resource_construct(
234 unsigned int num_virtual_links,
fb3466a4 235 struct dc *dc,
4562236b
HW		 236 struct resource_pool *pool,
237 const struct resource_create_funcs *create_funcs)
238{
239 struct dc_context *ctx = dc->ctx;
240 const struct resource_caps *caps = pool->res_cap;
241 int i;
242 unsigned int num_audio = caps->num_audio;
243 struct resource_straps straps = {0};
244
245 if (create_funcs->read_dce_straps)
246 create_funcs->read_dce_straps(dc->ctx, &straps);
247
248 pool->audio_count = 0;
249 if (create_funcs->create_audio) {
250 /* find the total number of streams available via the
251 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
252 * registers (one for each pin) starting from pin 1
253 * up to the max number of audio pins.
254 * We stop on the first pin where
255 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
256 */
257 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 258 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 259 struct audio *aud = create_funcs->create_audio(ctx, i);
260
261 if (aud == NULL) {
262 DC_ERR("DC: failed to create audio!\n");
263 return false;
264 }
265
266 if (!aud->funcs->endpoint_valid(aud)) {
267 aud->funcs->destroy(&aud);
268 break;
269 }
270
271 pool->audios[i] = aud;
272 pool->audio_count++;
273 }
274 }
275
276 pool->stream_enc_count = 0;
277 if (create_funcs->create_stream_encoder) {
278 for (i = 0; i < caps->num_stream_encoder; i++) {
279 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
280 if (pool->stream_enc[i] == NULL)
281 DC_ERR("DC: failed to create stream_encoder!\n");
282 pool->stream_enc_count++;
283 }
284 }
929c3aaa 285
4176664b
CL		 286 dc->caps.dynamic_audio = false;
287 if (pool->audio_count < pool->stream_enc_count) {
288 dc->caps.dynamic_audio = true;
289 }
4562236b
HW		 290 for (i = 0; i < num_virtual_links; i++) {
291 pool->stream_enc[pool->stream_enc_count] =
292 virtual_stream_encoder_create(
293 ctx, ctx->dc_bios);
294 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
295 DC_ERR("DC: failed to create stream_encoder!\n");
296 return false;
297 }
298 pool->stream_enc_count++;
299 }
300
301 dc->hwseq = create_funcs->create_hwseq(ctx);
302
303 return true;
304}
ad8960a6
ML		 305static int find_matching_clock_source(
306 const struct resource_pool *pool,
307 struct clock_source *clock_source)
308{
4562236b 309
ad8960a6
ML		 310 int i;
311
312 for (i = 0; i < pool->clk_src_count; i++) {
313 if (pool->clock_sources[i] == clock_source)
314 return i;
315 }
316 return -1;
317}
4562236b 318
21e67d4d 319void resource_unreference_clock_source(
4562236b 320 struct resource_context *res_ctx,
a2b8659d 321 const struct resource_pool *pool,
4a629536 322 struct clock_source *clock_source)
4562236b 323{
ad8960a6 324 int i = find_matching_clock_source(pool, clock_source);
4562236b 325
ad8960a6 326 if (i > -1)
4562236b
HW		 327 res_ctx->clock_source_ref_count[i]--;
328
21e67d4d 329 if (pool->dp_clock_source == clock_source)
4562236b 330 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 331}
332
333void resource_reference_clock_source(
334 struct resource_context *res_ctx,
a2b8659d 335 const struct resource_pool *pool,
4562236b
HW		 336 struct clock_source *clock_source)
337{
ad8960a6 338 int i = find_matching_clock_source(pool, clock_source);
4562236b 339
ad8960a6 340 if (i > -1)
4562236b 341 res_ctx->clock_source_ref_count[i]++;
4562236b 342
a2b8659d 343 if (pool->dp_clock_source == clock_source)
4562236b
HW		 344 res_ctx->dp_clock_source_ref_count++;
345}
346
ad8960a6
ML		 347int resource_get_clock_source_reference(
348 struct resource_context *res_ctx,
349 const struct resource_pool *pool,
350 struct clock_source *clock_source)
351{
352 int i = find_matching_clock_source(pool, clock_source);
353
354 if (i > -1)
355 return res_ctx->clock_source_ref_count[i];
356
357 if (pool->dp_clock_source == clock_source)
358 return res_ctx->dp_clock_source_ref_count;
359
360 return -1;
361}
362
4562236b 363bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 364 struct dc_stream_state *stream1,
365 struct dc_stream_state *stream2)
4562236b 366{
4fa086b9 367 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 368 return false;
369
4fa086b9 370 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 371 return false;
372
4fa086b9
LSL		 373 if (stream1->timing.h_addressable
374 != stream2->timing.h_addressable)
4562236b
HW		 375 return false;
376
4fa086b9
LSL		 377 if (stream1->timing.v_addressable
378 != stream2->timing.v_addressable)
4562236b
HW		 379 return false;
380
380604e2
KC		 381 if (stream1->timing.pix_clk_100hz
382 != stream2->timing.pix_clk_100hz)
4562236b
HW		 383 return false;
384
3e27e10e
ML		 385 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
386 return false;
387
4562236b 388 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 389 && (!dc_is_dp_signal(stream1->signal)
390 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 391 return false;
392
d77f778e
CL		 393 if (stream1->view_format != stream2->view_format)
394 return false;
395
4562236b
HW		 396 return true;
397}
3e27e10e
ML		 398static bool is_dp_and_hdmi_sharable(
399 struct dc_stream_state *stream1,
400 struct dc_stream_state *stream2)
401{
402 if (stream1->ctx->dc->caps.disable_dp_clk_share)
403 return false;
404
405 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 406 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 407 return false;
3e27e10e
ML		 408
409 return true;
410
411}
4562236b
HW		 412
413static bool is_sharable_clk_src(
414 const struct pipe_ctx *pipe_with_clk_src,
415 const struct pipe_ctx *pipe)
416{
417 if (pipe_with_clk_src->clock_source == NULL)
418 return false;
419
420 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
421 return false;
422
3e27e10e
ML		 423 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
424 (dc_is_dp_signal(pipe->stream->signal) &&
425 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
426 pipe->stream)))
4562236b
HW		 427 return false;
428
429 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 430 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 431 return false;
432
433 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 434 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 435 return false;
436
437 if (!resource_are_streams_timing_synchronizable(
438 pipe_with_clk_src->stream, pipe->stream))
439 return false;
440
441 return true;
442}
443
444struct clock_source *resource_find_used_clk_src_for_sharing(
445 struct resource_context *res_ctx,
446 struct pipe_ctx *pipe_ctx)
447{
448 int i;
449
450 for (i = 0; i < MAX_PIPES; i++) {
451 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
452 return res_ctx->pipe_ctx[i].clock_source;
453 }
454
455 return NULL;
456}
457
458static enum pixel_format convert_pixel_format_to_dalsurface(
459 enum surface_pixel_format surface_pixel_format)
460{
461 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
462
463 switch (surface_pixel_format) {
464 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
465 dal_pixel_format = PIXEL_FORMAT_INDEX8;
466 break;
467 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
468 dal_pixel_format = PIXEL_FORMAT_RGB565;
469 break;
470 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
471 dal_pixel_format = PIXEL_FORMAT_RGB565;
472 break;
473 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
474 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
475 break;
8693049a 476 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 477 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
478 break;
479 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
480 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
481 break;
482 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
483 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
484 break;
485 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
486 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
487 break;
488 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
489 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
490 dal_pixel_format = PIXEL_FORMAT_FP16;
491 break;
492 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 493 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 494 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 495 break;
ffbcd19a
VP		 496 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
497 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 498 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 499 break;
4562236b
HW		 500 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
501 default:
502 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
503 break;
504 }
505 return dal_pixel_format;
506}
507
9b6067c0
DL		 508static inline void get_vp_scan_direction(
509 enum dc_rotation_angle rotation,
510 bool horizontal_mirror,
511 bool *orthogonal_rotation,
512 bool *flip_vert_scan_dir,
513 bool *flip_horz_scan_dir)
4562236b 514{
9b6067c0
DL		 515 *orthogonal_rotation = false;
516 *flip_vert_scan_dir = false;
517 *flip_horz_scan_dir = false;
518 if (rotation == ROTATION_ANGLE_180) {
519 *flip_vert_scan_dir = true;
520 *flip_horz_scan_dir = true;
521 } else if (rotation == ROTATION_ANGLE_90) {
522 *orthogonal_rotation = true;
523 *flip_horz_scan_dir = true;
524 } else if (rotation == ROTATION_ANGLE_270) {
525 *orthogonal_rotation = true;
526 *flip_vert_scan_dir = true;
527 }
528
529 if (horizontal_mirror)
530 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 531}
532
b2d0a103 533static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 534{
3be5262e 535 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 536 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 537 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 538 struct rect surf_src = plane_state->src_rect;
9b6067c0 539 struct rect clip, dest;
87449a90
AK		 540 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
541 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 542 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 543 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 544 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 545 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
9b6067c0 546 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 547
7f5c22d1
VP		 548 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
549 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 550 pri_split = false;
551 sec_split = false;
552 }
86006a7f 553
4562236b
HW		 554 /* The actual clip is an intersection between stream
555 * source and surface clip
556 */
9b6067c0 557 dest = plane_state->dst_rect;
3be5262e
HW		 558 clip.x = stream->src.x > plane_state->clip_rect.x ?
559 stream->src.x : plane_state->clip_rect.x;
4562236b 560
1fbd2cfc 561 clip.width = stream->src.x + stream->src.width <
3be5262e 562 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 563 stream->src.x + stream->src.width - clip.x :
3be5262e 564 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 565
3be5262e
HW		 566 clip.y = stream->src.y > plane_state->clip_rect.y ?
567 stream->src.y : plane_state->clip_rect.y;
4562236b 568
1fbd2cfc 569 clip.height = stream->src.y + stream->src.height <
3be5262e 570 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 571 stream->src.y + stream->src.height - clip.y :
3be5262e 572 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 573
9b6067c0
DL		 574 /*
575 * Need to calculate how scan origin is shifted in vp space
576 * to correctly rotate clip and dst
577 */
578 get_vp_scan_direction(
579 plane_state->rotation,
580 plane_state->horizontal_mirror,
581 &orthogonal_rotation,
582 &flip_y_start,
583 &flip_x_start);
584
585 if (orthogonal_rotation) {
586 swap(clip.x, clip.y);
587 swap(clip.width, clip.height);
588 swap(dest.x, dest.y);
589 swap(dest.width, dest.height);
590 }
591 if (flip_x_start) {
592 clip.x = dest.x + dest.width - clip.x - clip.width;
593 dest.x = 0;
594 }
595 if (flip_y_start) {
596 clip.y = dest.y + dest.height - clip.y - clip.height;
597 dest.y = 0;
598 }
599
86006a7f 600 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 601 * num_pixels = clip.num_pix * scl_ratio
602 */
9b6067c0
DL		 603 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
604 data->viewport.width = clip.width * surf_src.width / dest.width;
605
606 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
607 data->viewport.height = clip.height * surf_src.height / dest.height;
608
609 /* Handle split */
610 if (pri_split || sec_split) {
611 if (orthogonal_rotation) {
612 if (flip_y_start != pri_split)
613 data->viewport.height /= 2;
614 else {
615 data->viewport.y += data->viewport.height / 2;
616 /* Ceil offset pipe */
617 data->viewport.height = (data->viewport.height + 1) / 2;
618 }
619 } else {
620 if (flip_x_start != pri_split)
621 data->viewport.width /= 2;
622 else {
623 data->viewport.x += data->viewport.width / 2;
624 /* Ceil offset pipe */
625 data->viewport.width = (data->viewport.width + 1) / 2;
626 }
627 }
628 }
9b5349f7 629
b2d0a103
DL		 630 /* Round down, compensate in init */
631 data->viewport_c.x = data->viewport.x / vpc_div;
632 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 633 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
634 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
635
b2d0a103
DL		 636 /* Round up, assume original video size always even dimensions */
637 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
638 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 639}
640
9b6067c0 641static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 642{
3be5262e 643 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 644 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 645 struct rect surf_clip = plane_state->clip_rect;
0c31a821
YS		 646 bool pri_split = pipe_ctx->bottom_pipe &&
647 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
648 bool sec_split = pipe_ctx->top_pipe &&
649 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 650 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 651
6702a9ac 652 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 653 if (stream->src.x < surf_clip.x)
6702a9ac 654 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 655 - stream->src.x) * stream->dst.width
656 / stream->src.width;
4562236b 657
6702a9ac 658 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 659 stream->dst.width / stream->src.width;
6702a9ac 660 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 661 stream->dst.x + stream->dst.width)
6702a9ac 662 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 663 stream->dst.x + stream->dst.width
6702a9ac 664 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 665
6702a9ac 666 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 667 if (stream->src.y < surf_clip.y)
6702a9ac 668 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 669 - stream->src.y) * stream->dst.height
670 / stream->src.height;
4562236b 671
6702a9ac 672 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 673 stream->dst.height / stream->src.height;
6702a9ac 674 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 675 stream->dst.y + stream->dst.height)
6702a9ac 676 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 677 stream->dst.y + stream->dst.height
6702a9ac 678 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 679
9b6067c0 680 /* Handle h & v split, handle rotation using viewport */
b0131391
DL		 681 if (sec_split && top_bottom_split) {
682 pipe_ctx->plane_res.scl_data.recout.y +=
683 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 684 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 685 pipe_ctx->plane_res.scl_data.recout.height =
686 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
687 } else if (pri_split && top_bottom_split)
0c31a821 688 pipe_ctx->plane_res.scl_data.recout.height /= 2;
9b6067c0
DL		 689 else if (sec_split) {
690 pipe_ctx->plane_res.scl_data.recout.x +=
691 pipe_ctx->plane_res.scl_data.recout.width / 2;
692 /* Ceil offset pipe */
693 pipe_ctx->plane_res.scl_data.recout.width =
694 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
695 } else if (pri_split)
696 pipe_ctx->plane_res.scl_data.recout.width /= 2;
4562236b
HW		 697}
698
b2d0a103 699static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 700{
3be5262e 701 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 702 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 703 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 704 const int in_w = stream->src.width;
705 const int in_h = stream->src.height;
706 const int out_w = stream->dst.width;
707 const int out_h = stream->dst.height;
4562236b 708
9b6067c0 709 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 710 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
711 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 712 swap(surf_src.height, surf_src.width);
86006a7f 713
eb0e5154 714 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 715 surf_src.width,
3be5262e 716 plane_state->dst_rect.width);
eb0e5154 717 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 718 surf_src.height,
3be5262e 719 plane_state->dst_rect.height);
4562236b 720
4fa086b9 721 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 722 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 723 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 724 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 725
6702a9ac
HW		 726 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
727 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
728 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
729 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 730
6702a9ac
HW		 731 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
732 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 733
6702a9ac
HW		 734 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
735 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
736 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
737 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 738 }
0002d3ac
DL		 739 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
740 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
741 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
742 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
743 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
744 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
745 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
746 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 747}
748
9b6067c0
DL		 749static inline void adjust_vp_and_init_for_seamless_clip(
750 bool flip_scan_dir,
751 int recout_skip,
752 int src_size,
753 int taps,
754 struct fixed31_32 ratio,
755 struct fixed31_32 *init,
756 int *vp_offset,
757 int *vp_size)
b2d0a103 758{
9b6067c0 759 if (!flip_scan_dir) {
9a08f51f 760 /* Adjust for viewport end clip-off */
9b6067c0
DL		 761 if ((*vp_offset + *vp_size) < src_size) {
762 int vp_clip = src_size - *vp_size - *vp_offset;
763 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 764
765 int_part = int_part > 0 ? int_part : 0;
9b6067c0 766 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 767 }
b2d0a103 768
9a08f51f 769 /* Adjust for non-0 viewport offset */
9b6067c0 770 if (*vp_offset) {
9a08f51f
DL		 771 int int_part;
772
9b6067c0
DL		 773 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
774 int_part = dc_fixpt_floor(*init) - *vp_offset;
775 if (int_part < taps) {
776 int int_adj = *vp_offset >= (taps - int_part) ?
777 (taps - int_part) : *vp_offset;
778 *vp_offset -= int_adj;
779 *vp_size += int_adj;
9a08f51f 780 int_part += int_adj;
9b6067c0
DL		 781 } else if (int_part > taps) {
782 *vp_offset += int_part - taps;
783 *vp_size -= int_part - taps;
784 int_part = taps;
9a08f51f 785 }
9b6067c0
DL		 786 init->value &= 0xffffffff;
787 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 788 }
789 } else {
790 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 791 if (*vp_offset) {
792 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 793
9a08f51f 794 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 795 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
796 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 797 }
b2d0a103 798
9a08f51f 799 /* Adjust for viewport end clip-off */
9b6067c0 800 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 801 int int_part;
9b6067c0 802 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 803
804 /*
805 * this is init if vp had no offset, keep in mind this is from the
806 * right side of vp due to scan direction
807 */
9b6067c0 808 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 809 /*
810 * this is the difference between first pixel of viewport available to read
811 * and init position, takning into account scan direction
812 */
9b6067c0
DL		 813 int_part = dc_fixpt_floor(*init) - end_offset;
814 if (int_part < taps) {
815 int int_adj = end_offset >= (taps - int_part) ?
816 (taps - int_part) : end_offset;
817 *vp_size += int_adj;
9a08f51f 818 int_part += int_adj;
9b6067c0
DL		 819 } else if (int_part > taps) {
820 *vp_size += int_part - taps;
821 int_part = taps;
9a08f51f 822 }
9b6067c0
DL		 823 init->value &= 0xffffffff;
824 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 825 }
b2d0a103 826 }
9b6067c0 827}
9a08f51f 828
9b6067c0
DL		 829static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
830{
831 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
832 const struct dc_stream_state *stream = pipe_ctx->stream;
833 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
834 struct rect src = pipe_ctx->plane_state->src_rect;
835 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
836 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
837 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
838 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 839
9b6067c0
DL		 840 /*
841 * Need to calculate the scan direction for viewport to make adjustments
842 */
843 get_vp_scan_direction(
844 plane_state->rotation,
845 plane_state->horizontal_mirror,
846 &orthogonal_rotation,
847 &flip_vert_scan_dir,
848 &flip_horz_scan_dir);
849
850 /* Calculate src rect rotation adjusted to recout space */
851 surf_size_h = src.x + src.width;
852 surf_size_v = src.y + src.height;
853 if (flip_horz_scan_dir)
854 src.x = 0;
855 if (flip_vert_scan_dir)
856 src.y = 0;
857 if (orthogonal_rotation) {
858 swap(src.x, src.y);
859 swap(src.width, src.height);
860 }
9a08f51f 861
9b6067c0
DL		 862 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
863 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
864 * - (surf surf_src offset * 1/ full scl ratio))
865 */
866 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
867 * stream->dst.width / stream->src.width -
868 src.x * plane_state->dst_rect.width / src.width
869 * stream->dst.width / stream->src.width);
870 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
871 * stream->dst.height / stream->src.height -
872 src.y * plane_state->dst_rect.height / src.height
873 * stream->dst.height / stream->src.height);
874 if (orthogonal_rotation)
875 swap(recout_skip_h, recout_skip_v);
876 /*
877 * Init calculated according to formula:
878 * init = (scaling_ratio + number_of_taps + 1) / 2
879 * init_bot = init + scaling_ratio
880 * init_c = init + truncated_vp_c_offset(from calculate viewport)
881 */
882 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
883 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 884
9b6067c0
DL		 885 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
886 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 887
9b6067c0
DL		 888 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
889 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 890
9b6067c0
DL		 891 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
892 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 893
9b6067c0
DL		 894 /*
895 * Taps, inits and scaling ratios are in recout space need to rotate
896 * to viewport rotation before adjustment
897 */
898 adjust_vp_and_init_for_seamless_clip(
899 flip_horz_scan_dir,
900 recout_skip_h,
901 surf_size_h,
902 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
903 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
904 orthogonal_rotation ? &data->inits.v : &data->inits.h,
905 &data->viewport.x,
906 &data->viewport.width);
907 adjust_vp_and_init_for_seamless_clip(
908 flip_horz_scan_dir,
909 recout_skip_h,
910 surf_size_h / vpc_div,
911 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
912 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
913 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
914 &data->viewport_c.x,
915 &data->viewport_c.width);
916 adjust_vp_and_init_for_seamless_clip(
917 flip_vert_scan_dir,
918 recout_skip_v,
919 surf_size_v,
920 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
921 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
922 orthogonal_rotation ? &data->inits.h : &data->inits.v,
923 &data->viewport.y,
924 &data->viewport.height);
925 adjust_vp_and_init_for_seamless_clip(
926 flip_vert_scan_dir,
927 recout_skip_v,
928 surf_size_v / vpc_div,
929 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
930 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
931 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
932 &data->viewport_c.y,
933 &data->viewport_c.height);
b2d0a103
DL		 934
935 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 936 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
937 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 938
b2d0a103 939}
f7938bc0
RA		 940static bool are_rect_integer_multiples(struct rect src, struct rect dest)
941{
942 if (dest.width >= src.width && dest.width % src.width == 0 &&
943 dest.height >= src.height && dest.height % src.height == 0)
944 return true;
b2d0a103 945
f7938bc0
RA		 946 return false;
947}
b2d0a103 948bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 949{
3be5262e 950 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 951 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 952 bool res = false;
5d4b05dd 953 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 954 /* Important: scaling ratio calculation requires pixel format,
955 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 956 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 957 */
6702a9ac 958 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 959 pipe_ctx->plane_state->format);
b2d0a103
DL		 960
961 calculate_scaling_ratios(pipe_ctx);
4562236b 962
b2d0a103 963 calculate_viewport(pipe_ctx);
4562236b 964
6702a9ac 965 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 966 return false;
967
9b6067c0 968 calculate_recout(pipe_ctx);
4562236b
HW		 969
970 /**
971 * Setting line buffer pixel depth to 24bpp yields banding
972 * on certain displays, such as the Sharp 4k
973 */
6702a9ac 974 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 975
199e458a 976 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 977 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 978
58bb0e63
AJ		 979 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
980 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1b6c8067 981
4562236b 982 /* Taps calculations */
d94585a0
YHL		 983 if (pipe_ctx->plane_res.xfm != NULL)
984 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
985 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
986
987 if (pipe_ctx->plane_res.dpp != NULL)
988 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
989 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0
RA		 990
991 if (res &&
992 plane_state->scaling_quality.integer_scaling &&
993 are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
994 pipe_ctx->plane_res.scl_data.recout)) {
995 pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
996 pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
997 }
998
4562236b
HW		 999 if (!res) {
1000 /* Try 24 bpp linebuffer */
6702a9ac 1001 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1002
1b6c8067
BL		 1003 if (pipe_ctx->plane_res.xfm != NULL)
1004 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1005 pipe_ctx->plane_res.xfm,
1006 &pipe_ctx->plane_res.scl_data,
1007 &plane_state->scaling_quality);
1008
1009 if (pipe_ctx->plane_res.dpp != NULL)
1010 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1011 pipe_ctx->plane_res.dpp,
1012 &pipe_ctx->plane_res.scl_data,
1013 &plane_state->scaling_quality);
4562236b
HW		 1014 }
1015
b2d0a103 1016 if (res)
1fbd2cfc 1017 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1018 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1019
1296423b 1020 DC_LOG_SCALER(
4562236b
HW		 1021 "%s: Viewport:\nheight:%d width:%d x:%d "
1022 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1023 "y:%d\n",
1024 __func__,
6702a9ac
HW		 1025 pipe_ctx->plane_res.scl_data.viewport.height,
1026 pipe_ctx->plane_res.scl_data.viewport.width,
1027 pipe_ctx->plane_res.scl_data.viewport.x,
1028 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 1029 plane_state->dst_rect.height,
1030 plane_state->dst_rect.width,
1031 plane_state->dst_rect.x,
1032 plane_state->dst_rect.y);
4562236b
HW		 1033
1034 return res;
1035}
1036
1037
1038enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1039 const struct dc *dc,
608ac7bb 1040 struct dc_state *context)
4562236b
HW		 1041{
1042 int i;
1043
1044 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1045 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1046 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1047 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1048 return DC_FAIL_SCALING;
4562236b
HW		 1049 }
1050
1051 return DC_OK;
1052}
1053
a2b8659d
TC		 1054struct pipe_ctx *find_idle_secondary_pipe(
1055 struct resource_context *res_ctx,
5581192d
JL		 1056 const struct resource_pool *pool,
1057 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1058{
1059 int i;
1060 struct pipe_ctx *secondary_pipe = NULL;
1061
1062 /*
5581192d
JL		 1063 * We add a preferred pipe mapping to avoid the chance that
1064 * MPCCs already in use will need to be reassigned to other trees.
1065 * For example, if we went with the strict, assign backwards logic:
1066 *
1067 * (State 1)
1068 * Display A on, no surface, top pipe = 0
1069 * Display B on, no surface, top pipe = 1
1070 *
1071 * (State 2)
1072 * Display A on, no surface, top pipe = 0
1073 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1074 *
1075 * (State 3)
1076 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1077 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1078 *
1079 * The state 2->3 transition requires remapping MPCC 5 from display B
1080 * to display A.
1081 *
1082 * However, with the preferred pipe logic, state 2 would look like:
1083 *
1084 * (State 2)
1085 * Display A on, no surface, top pipe = 0
1086 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1087 *
1088 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1089 */
5581192d
JL		 1090 if (primary_pipe) {
1091 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1092 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1093 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1094 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1095 }
1096 }
1097
5581192d
JL		 1098 /*
1099 * search backwards for the second pipe to keep pipe
1100 * assignment more consistent
1101 */
1102 if (!secondary_pipe)
1103 for (i = pool->pipe_count - 1; i >= 0; i--) {
1104 if (res_ctx->pipe_ctx[i].stream == NULL) {
1105 secondary_pipe = &res_ctx->pipe_ctx[i];
1106 secondary_pipe->pipe_idx = i;
1107 break;
1108 }
1109 }
4562236b
HW		 1110
1111 return secondary_pipe;
1112}
1113
1114struct pipe_ctx *resource_get_head_pipe_for_stream(
1115 struct resource_context *res_ctx,
0971c40e 1116 struct dc_stream_state *stream)
4562236b
HW		 1117{
1118 int i;
a2b8659d 1119 for (i = 0; i < MAX_PIPES; i++) {
4562236b 1120 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 1121 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 1122 return &res_ctx->pipe_ctx[i];
1123 break;
1124 }
1125 }
1126 return NULL;
1127}
1128
19f89e23
AG		 1129static struct pipe_ctx *resource_get_tail_pipe_for_stream(
1130 struct resource_context *res_ctx,
1131 struct dc_stream_state *stream)
1132{
1133 struct pipe_ctx *head_pipe, *tail_pipe;
1134 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1135
1136 if (!head_pipe)
1137 return NULL;
1138
1139 tail_pipe = head_pipe->bottom_pipe;
1140
1141 while (tail_pipe) {
1142 head_pipe = tail_pipe;
1143 tail_pipe = tail_pipe->bottom_pipe;
1144 }
1145
1146 return head_pipe;
1147}
1148
4562236b 1149/*
ab2541b6
AC		 1150 * A free_pipe for a stream is defined here as a pipe
1151 * that has no surface attached yet
4562236b 1152 */
ab2541b6 1153static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1154 struct dc_state *context,
a2b8659d 1155 const struct resource_pool *pool,
0971c40e 1156 struct dc_stream_state *stream)
4562236b
HW		 1157{
1158 int i;
745cc746 1159 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1160
1161 struct pipe_ctx *head_pipe = NULL;
1162
1163 /* Find head pipe, which has the back end set up*/
1164
1165 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1166
e41ab030 1167 if (!head_pipe) {
4562236b 1168 ASSERT(0);
e41ab030
HW		 1169 return NULL;
1170 }
4562236b 1171
3be5262e 1172 if (!head_pipe->plane_state)
4562236b
HW		 1173 return head_pipe;
1174
1175 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1176 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1177 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1178 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1179 return &res_ctx->pipe_ctx[i];
1180 }
1181 }
1182
1183 /*
1184 * At this point we have no re-useable pipe for this stream and we need
1185 * to acquire an idle one to satisfy the request
1186 */
1187
a2b8659d 1188 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1189 return NULL;
1190
a2b8659d 1191 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1192
1193}
1194
dc37a9a0 1195#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
0f9a536f
DL		 1196static int acquire_first_split_pipe(
1197 struct resource_context *res_ctx,
1198 const struct resource_pool *pool,
0971c40e 1199 struct dc_stream_state *stream)
0f9a536f
DL		 1200{
1201 int i;
1202
1203 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1204 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1205
1206 if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
1207 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1208 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1209 if (split_pipe->bottom_pipe)
1210 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1211
1212 if (split_pipe->top_pipe->plane_state)
1213 resource_build_scaling_params(split_pipe->top_pipe);
1214
1215 memset(split_pipe, 0, sizeof(*split_pipe));
1216 split_pipe->stream_res.tg = pool->timing_generators[i];
1217 split_pipe->plane_res.hubp = pool->hubps[i];
1218 split_pipe->plane_res.ipp = pool->ipps[i];
1219 split_pipe->plane_res.dpp = pool->dpps[i];
1220 split_pipe->stream_res.opp = pool->opps[i];
1221 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1222 split_pipe->pipe_idx = i;
1223
1224 split_pipe->stream = stream;
0f9a536f
DL		 1225 return i;
1226 }
1227 }
1228 return -1;
1229}
1230#endif
1231
19f89e23
AG		 1232bool dc_add_plane_to_context(
1233 const struct dc *dc,
0971c40e 1234 struct dc_stream_state *stream,
19f89e23 1235 struct dc_plane_state *plane_state,
608ac7bb 1236 struct dc_state *context)
4562236b
HW		 1237{
1238 int i;
19f89e23
AG		 1239 struct resource_pool *pool = dc->res_pool;
1240 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1241 struct dc_stream_status *stream_status = NULL;
4562236b 1242
19f89e23
AG		 1243 for (i = 0; i < context->stream_count; i++)
1244 if (context->streams[i] == stream) {
1245 stream_status = &context->stream_status[i];
1246 break;
1247 }
1248 if (stream_status == NULL) {
1249 dm_error("Existing stream not found; failed to attach surface!\n");
1250 return false;
1251 }
1252
4562236b 1253
19f89e23
AG		 1254 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1255 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1256 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1257 return false;
1258 }
1259
19f89e23
AG		 1260 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1261
1262 if (!head_pipe) {
1263 dm_error("Head pipe not found for stream_state %p !\n", stream);
1264 return false;
1265 }
1266
00737c59
EB		 1267 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1268 ASSERT(tail_pipe);
1269
19f89e23
AG		 1270 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1271
dc37a9a0 1272#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
19f89e23
AG		 1273 if (!free_pipe) {
1274 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1275 if (pipe_idx >= 0)
1276 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1277 }
1278#endif
abb4986e 1279 if (!free_pipe)
19f89e23 1280 return false;
19f89e23 1281
abb4986e
AJ		 1282 /* retain new surfaces */
1283 dc_plane_state_retain(plane_state);
19f89e23
AG		 1284 free_pipe->plane_state = plane_state;
1285
1286 if (head_pipe != free_pipe) {
19f89e23 1287 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1288 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1289 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1290 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1291 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1292 free_pipe->clock_source = tail_pipe->clock_source;
1293 free_pipe->top_pipe = tail_pipe;
1294 tail_pipe->bottom_pipe = free_pipe;
4a797d24
DL		 1295 } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
1296 ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
1297 free_pipe->bottom_pipe->plane_state = plane_state;
19f89e23
AG		 1298 }
1299
1300 /* assign new surfaces*/
1301 stream_status->plane_states[stream_status->plane_count] = plane_state;
1302
1303 stream_status->plane_count++;
1304
1305 return true;
1306}
1307
6ffaa6fc
DL		 1308struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
1309{
1310 struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
1311
1312 /* ODM should only be updated once per otg */
1313 if (pipe_ctx->top_pipe)
1314 return NULL;
1315
1316 while (bottom_pipe) {
1317 if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
1318 break;
1319 bottom_pipe = bottom_pipe->bottom_pipe;
1320 }
1321
1322 return bottom_pipe;
1323}
1324
c0415c87 1325bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
6ffaa6fc
DL		 1326{
1327 struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
6ffaa6fc 1328
fe6382cd
DL		 1329 if (!top_pipe)
1330 return false;
6ffaa6fc
DL		 1331 if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
1332 return false;
1333
fe6382cd 1334 return true;
6ffaa6fc
DL		 1335}
1336
19f89e23
AG		 1337bool dc_remove_plane_from_context(
1338 const struct dc *dc,
1339 struct dc_stream_state *stream,
1340 struct dc_plane_state *plane_state,
608ac7bb 1341 struct dc_state *context)
19f89e23
AG		 1342{
1343 int i;
1344 struct dc_stream_status *stream_status = NULL;
1345 struct resource_pool *pool = dc->res_pool;
1346
ab2541b6 1347 for (i = 0; i < context->stream_count; i++)
4fa086b9 1348 if (context->streams[i] == stream) {
ab2541b6 1349 stream_status = &context->stream_status[i];
4562236b
HW		 1350 break;
1351 }
19f89e23 1352
ab2541b6 1353 if (stream_status == NULL) {
19f89e23 1354 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1355 return false;
1356 }
1357
19f89e23
AG		 1358 /* release pipe for plane*/
1359 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1360 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1361
6ffaa6fc 1362 if (pipe_ctx->plane_state == plane_state) {
c0415c87 1363 if (dc_res_is_odm_head_pipe(pipe_ctx)) {
6ffaa6fc
DL		 1364 pipe_ctx->plane_state = NULL;
1365 pipe_ctx->bottom_pipe = NULL;
1366 continue;
1367 }
4562236b 1368
19f89e23
AG		 1369 if (pipe_ctx->top_pipe)
1370 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1371
19f89e23
AG		 1372 /* Second condition is to avoid setting NULL to top pipe
1373 * of tail pipe making it look like head pipe in subsequent
1374 * deletes
1375 */
1376 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1377 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1378
19f89e23
AG		 1379 /*
1380 * For head pipe detach surfaces from pipe for tail
1381 * pipe just zero it out
1382 */
6ffaa6fc 1383 if (!pipe_ctx->top_pipe) {
19f89e23 1384 pipe_ctx->plane_state = NULL;
6ffaa6fc
DL		 1385 if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
1386 pipe_ctx->bottom_pipe = NULL;
bc219399 1387 } else {
19f89e23
AG		 1388 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1389 }
4562236b 1390 }
19f89e23 1391 }
4562236b 1392
4562236b 1393
19f89e23
AG		 1394 for (i = 0; i < stream_status->plane_count; i++) {
1395 if (stream_status->plane_states[i] == plane_state) {
1396
1397 dc_plane_state_release(stream_status->plane_states[i]);
1398 break;
4562236b 1399 }
19f89e23 1400 }
4562236b 1401
19f89e23
AG		 1402 if (i == stream_status->plane_count) {
1403 dm_error("Existing plane_state not found; failed to detach it!\n");
1404 return false;
4562236b
HW		 1405 }
1406
19f89e23 1407 stream_status->plane_count--;
4562236b 1408
abb4986e
AJ		 1409 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1410 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1411 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1412
1413 stream_status->plane_states[stream_status->plane_count] = NULL;
1414
1415 return true;
1416}
1417
1418bool dc_rem_all_planes_for_stream(
1419 const struct dc *dc,
1420 struct dc_stream_state *stream,
608ac7bb 1421 struct dc_state *context)
19f89e23
AG		 1422{
1423 int i, old_plane_count;
1424 struct dc_stream_status *stream_status = NULL;
1425 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1426
1427 for (i = 0; i < context->stream_count; i++)
1428 if (context->streams[i] == stream) {
1429 stream_status = &context->stream_status[i];
1430 break;
1431 }
1432
1433 if (stream_status == NULL) {
1434 dm_error("Existing stream %p not found!\n", stream);
1435 return false;
1436 }
1437
1438 old_plane_count = stream_status->plane_count;
1439
1440 for (i = 0; i < old_plane_count; i++)
1441 del_planes[i] = stream_status->plane_states[i];
1442
1443 for (i = 0; i < old_plane_count; i++)
1444 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1445 return false;
1446
1447 return true;
1448}
1449
1450static bool add_all_planes_for_stream(
1451 const struct dc *dc,
1452 struct dc_stream_state *stream,
1453 const struct dc_validation_set set[],
1454 int set_count,
608ac7bb 1455 struct dc_state *context)
19f89e23
AG		 1456{
1457 int i, j;
1458
1459 for (i = 0; i < set_count; i++)
1460 if (set[i].stream == stream)
1461 break;
1462
1463 if (i == set_count) {
1464 dm_error("Stream %p not found in set!\n", stream);
1465 return false;
1466 }
4562236b 1467
19f89e23
AG		 1468 for (j = 0; j < set[i].plane_count; j++)
1469 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1470 return false;
4562236b
HW		 1471
1472 return true;
1473}
1474
19f89e23
AG		 1475bool dc_add_all_planes_for_stream(
1476 const struct dc *dc,
1477 struct dc_stream_state *stream,
1478 struct dc_plane_state * const *plane_states,
1479 int plane_count,
608ac7bb 1480 struct dc_state *context)
19f89e23
AG		 1481{
1482 struct dc_validation_set set;
1483 int i;
1484
1485 set.stream = stream;
1486 set.plane_count = plane_count;
1487
1488 for (i = 0; i < plane_count; i++)
1489 set.plane_states[i] = plane_states[i];
1490
1491 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1492}
1493
1494
6b622181
JP		 1495static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1496 struct dc_stream_state *new_stream)
1497{
1498 if (cur_stream == NULL)
1499 return true;
1500
1501 if (memcmp(&cur_stream->hdr_static_metadata,
1502 &new_stream->hdr_static_metadata,
1503 sizeof(struct dc_info_packet)) != 0)
1504 return true;
1505
1506 return false;
1507}
4562236b 1508
1336926f
A		 1509static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1510 struct dc_stream_state *new_stream)
1511{
1512 if (cur_stream == NULL)
1513 return true;
1514
1515 if (memcmp(&cur_stream->vsc_infopacket,
1516 &new_stream->vsc_infopacket,
1517 sizeof(struct dc_info_packet)) != 0)
1518 return true;
1519
1520 return false;
1521}
1522
0971c40e
HW		 1523static bool is_timing_changed(struct dc_stream_state *cur_stream,
1524 struct dc_stream_state *new_stream)
4562236b
HW		 1525{
1526 if (cur_stream == NULL)
1527 return true;
1528
1529 /* If sink pointer changed, it means this is a hotplug, we should do
1530 * full hw setting.
1531 */
1532 if (cur_stream->sink != new_stream->sink)
1533 return true;
1534
1535 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1536 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1537 return true;
1538
1539 return memcmp(
4fa086b9
LSL		 1540 &cur_stream->timing,
1541 &new_stream->timing,
4562236b
HW		 1542 sizeof(struct dc_crtc_timing)) != 0;
1543}
1544
1545static bool are_stream_backends_same(
0971c40e 1546 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1547{
1548 if (stream_a == stream_b)
1549 return true;
1550
1551 if (stream_a == NULL || stream_b == NULL)
1552 return false;
1553
1554 if (is_timing_changed(stream_a, stream_b))
1555 return false;
1556
6b622181
JP		 1557 if (is_hdr_static_meta_changed(stream_a, stream_b))
1558 return false;
1559
1e7e86c4
ST		 1560 if (stream_a->dpms_off != stream_b->dpms_off)
1561 return false;
1562
1336926f
A		 1563 if (is_vsc_info_packet_changed(stream_a, stream_b))
1564 return false;
1565
4562236b
HW		 1566 return true;
1567}
1568
2119aa17
DF		 1569/**
1570 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1571 *
1572 * Checks if there a difference between the two states
1573 * that would require a mode change.
1574 *
1575 * Does not compare cursor position or attributes.
1576 */
d54d29db 1577bool dc_is_stream_unchanged(
0971c40e 1578 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1579{
4562236b 1580
ab2541b6
AC		 1581 if (!are_stream_backends_same(old_stream, stream))
1582 return false;
4562236b
HW		 1583
1584 return true;
1585}
1586
2119aa17
DF		 1587/**
1588 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1589 */
9a5d9c48
LSL		 1590bool dc_is_stream_scaling_unchanged(
1591 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1592{
1593 if (old_stream == stream)
1594 return true;
1595
1596 if (old_stream == NULL || stream == NULL)
1597 return false;
1598
1599 if (memcmp(&old_stream->src,
1600 &stream->src,
1601 sizeof(struct rect)) != 0)
1602 return false;
1603
1604 if (memcmp(&old_stream->dst,
1605 &stream->dst,
1606 sizeof(struct rect)) != 0)
1607 return false;
1608
1609 return true;
1610}
1611
1dc90497 1612static void update_stream_engine_usage(
4562236b 1613 struct resource_context *res_ctx,
a2b8659d 1614 const struct resource_pool *pool,
1dc90497
AG		 1615 struct stream_encoder *stream_enc,
1616 bool acquired)
4562236b
HW		 1617{
1618 int i;
1619
a2b8659d
TC		 1620 for (i = 0; i < pool->stream_enc_count; i++) {
1621 if (pool->stream_enc[i] == stream_enc)
1dc90497 1622 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1623 }
1624}
1625
1626/* TODO: release audio object */
4176664b 1627void update_audio_usage(
4562236b 1628 struct resource_context *res_ctx,
a2b8659d 1629 const struct resource_pool *pool,
1dc90497
AG		 1630 struct audio *audio,
1631 bool acquired)
4562236b
HW		 1632{
1633 int i;
a2b8659d
TC		 1634 for (i = 0; i < pool->audio_count; i++) {
1635 if (pool->audios[i] == audio)
1dc90497 1636 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1637 }
1638}
1639
1640static int acquire_first_free_pipe(
1641 struct resource_context *res_ctx,
a2b8659d 1642 const struct resource_pool *pool,
0971c40e 1643 struct dc_stream_state *stream)
4562236b
HW		 1644{
1645 int i;
1646
a2b8659d 1647 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1648 if (!res_ctx->pipe_ctx[i].stream) {
1649 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1650
6b670fa9 1651 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1652 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1653 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1654 pipe_ctx->plane_res.ipp = pool->ipps[i];
1655 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1656 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1657 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1658 if (pool->dpps[i])
1659 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1660 pipe_ctx->pipe_idx = i;
1661
ff5ef992 1662
4562236b
HW		 1663 pipe_ctx->stream = stream;
1664 return i;
1665 }
1666 }
1667 return -1;
1668}
1669
a2b8659d
TC		 1670static struct audio *find_first_free_audio(
1671 struct resource_context *res_ctx,
cfb071f7
CL		 1672 const struct resource_pool *pool,
1673 enum engine_id id)
4562236b
HW		 1674{
1675 int i;
66bfd4fd
CL		 1676 for (i = 0; i < pool->audio_count; i++) {
1677 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1678 /*we have enough audio endpoint, find the matching inst*/
1679 if (id != i)
1680 continue;
1681
66bfd4fd 1682 return pool->audios[i];
4562236b 1683 }
66bfd4fd 1684 }
5feb9f07
TM		 1685
1686 /* use engine id to find free audio */
1687 if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1688 return pool->audios[id];
1689 }
1690
66bfd4fd
CL		 1691 /*not found the matching one, first come first serve*/
1692 for (i = 0; i < pool->audio_count; i++) {
1693 if (res_ctx->is_audio_acquired[i] == false) {
1694 return pool->audios[i];
4176664b
CL		 1695 }
1696 }
4562236b
HW		 1697 return 0;
1698}
1699
4562236b 1700bool resource_is_stream_unchanged(
608ac7bb 1701 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1702{
ab2541b6 1703 int i;
4562236b 1704
ab2541b6 1705 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1706 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1707
ab2541b6 1708 if (are_stream_backends_same(old_stream, stream))
4562236b 1709 return true;
4562236b
HW		 1710 }
1711
1712 return false;
1713}
1714
2119aa17
DF		 1715/**
1716 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1717 */
13ab1b44 1718enum dc_status dc_add_stream_to_ctx(
1dc90497 1719 struct dc *dc,
608ac7bb 1720 struct dc_state *new_ctx,
1dc90497
AG		 1721 struct dc_stream_state *stream)
1722{
1dc90497 1723 enum dc_status res;
eb9714a2 1724 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1725
ece4147f 1726 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1727 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1728 return DC_ERROR_UNEXPECTED;
1729 }
1730
1731 new_ctx->streams[new_ctx->stream_count] = stream;
1732 dc_stream_retain(stream);
1733 new_ctx->stream_count++;
1734
1735 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1736 if (res != DC_OK)
eb9714a2 1737 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1738
13ab1b44 1739 return res;
1dc90497
AG		 1740}
1741
2119aa17
DF		 1742/**
1743 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1744 */
62c933f9 1745enum dc_status dc_remove_stream_from_ctx(
1dc90497 1746 struct dc *dc,
608ac7bb 1747 struct dc_state *new_ctx,
1dc90497
AG		 1748 struct dc_stream_state *stream)
1749{
19f89e23 1750 int i;
1dc90497
AG		 1751 struct dc_context *dc_ctx = dc->ctx;
1752 struct pipe_ctx *del_pipe = NULL;
1753
19f89e23 1754 /* Release primary pipe */
1dc90497 1755 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1756 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1757 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
6ffaa6fc
DL		 1758 struct pipe_ctx *odm_pipe =
1759 dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
1760
1dc90497
AG		 1761 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1762
19f89e23
AG		 1763 ASSERT(del_pipe->stream_res.stream_enc);
1764 update_stream_engine_usage(
1765 &new_ctx->res_ctx,
1dc90497 1766 dc->res_pool,
19f89e23
AG		 1767 del_pipe->stream_res.stream_enc,
1768 false);
1dc90497
AG		 1769
1770 if (del_pipe->stream_res.audio)
1771 update_audio_usage(
1772 &new_ctx->res_ctx,
1773 dc->res_pool,
1774 del_pipe->stream_res.audio,
1775 false);
1776
9d0dcecd
HW		 1777 resource_unreference_clock_source(&new_ctx->res_ctx,
1778 dc->res_pool,
1779 del_pipe->clock_source);
1780
e56ae556
NC		 1781 if (dc->res_pool->funcs->remove_stream_from_ctx)
1782 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1783
1dc90497 1784 memset(del_pipe, 0, sizeof(*del_pipe));
6ffaa6fc
DL		 1785 if (odm_pipe)
1786 memset(odm_pipe, 0, sizeof(*odm_pipe));
1787
1788 break;
1dc90497
AG		 1789 }
1790 }
1791
1792 if (!del_pipe) {
1793 DC_ERROR("Pipe not found for stream %p !\n", stream);
1794 return DC_ERROR_UNEXPECTED;
1795 }
1796
1797 for (i = 0; i < new_ctx->stream_count; i++)
1798 if (new_ctx->streams[i] == stream)
1799 break;
1800
1801 if (new_ctx->streams[i] != stream) {
1802 DC_ERROR("Context doesn't have stream %p !\n", stream);
1803 return DC_ERROR_UNEXPECTED;
1804 }
1805
1806 dc_stream_release(new_ctx->streams[i]);
1807 new_ctx->stream_count--;
1808
1dc90497
AG		 1809 /* Trim back arrays */
1810 for (; i < new_ctx->stream_count; i++) {
1811 new_ctx->streams[i] = new_ctx->streams[i + 1];
1812 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1813 }
1814
1815 new_ctx->streams[new_ctx->stream_count] = NULL;
1816 memset(
1817 &new_ctx->stream_status[new_ctx->stream_count],
1818 0,
1819 sizeof(new_ctx->stream_status[0]));
1820
1821 return DC_OK;
1822}
1823
0971c40e
HW		 1824static struct dc_stream_state *find_pll_sharable_stream(
1825 struct dc_stream_state *stream_needs_pll,
608ac7bb 1826 struct dc_state *context)
4562236b 1827{
ab2541b6 1828 int i;
4562236b 1829
ab2541b6 1830 for (i = 0; i < context->stream_count; i++) {
0971c40e 1831 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1832
ab2541b6
AC		 1833 /* We are looking for non dp, non virtual stream */
1834 if (resource_are_streams_timing_synchronizable(
1835 stream_needs_pll, stream_has_pll)
1836 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1837 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1838 != SIGNAL_TYPE_VIRTUAL)
1839 return stream_has_pll;
4562236b 1840
4562236b
HW		 1841 }
1842
1843 return NULL;
1844}
1845
1846static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1847{
380604e2 1848 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1849 uint32_t normalized_pix_clk = pix_clk;
1850
1851 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1852 pix_clk /= 2;
cc4d99b8
CL		 1853 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1854 switch (timing->display_color_depth) {
8897810a 1855 case COLOR_DEPTH_666:
cc4d99b8
CL		 1856 case COLOR_DEPTH_888:
1857 normalized_pix_clk = pix_clk;
1858 break;
1859 case COLOR_DEPTH_101010:
1860 normalized_pix_clk = (pix_clk * 30) / 24;
1861 break;
1862 case COLOR_DEPTH_121212:
1863 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1864 break;
cc4d99b8
CL		 1865 case COLOR_DEPTH_161616:
1866 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1867 break;
cc4d99b8
CL		 1868 default:
1869 ASSERT(0);
4562236b 1870 break;
cc4d99b8 1871 }
4562236b 1872 }
4562236b
HW		 1873 return normalized_pix_clk;
1874}
1875
0971c40e 1876static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1877{
9345d987
AG		 1878 /* update actual pixel clock on all streams */
1879 if (dc_is_hdmi_signal(stream->signal))
1880 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1881 &stream->timing) / 10;
9345d987
AG		 1882 else
1883 stream->phy_pix_clk =
380604e2 1884 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1885
1886 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1887 stream->phy_pix_clk *= 2;
4562236b
HW		 1888}
1889
d2d7885f
AK		 1890static int acquire_resource_from_hw_enabled_state(
1891 struct resource_context *res_ctx,
1892 const struct resource_pool *pool,
1893 struct dc_stream_state *stream)
1894{
1895 struct dc_link *link = stream->link;
5ec43eda 1896 unsigned int inst, tg_inst;
d2d7885f
AK		 1897
1898 /* Check for enabled DIG to identify enabled display */
1899 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1900 return -1;
1901
1902 /* Check for which front end is used by this encoder.
1903 * Note the inst is 1 indexed, where 0 is undefined.
1904 * Note that DIG_FE can source from different OTG but our
1905 * current implementation always map 1-to-1, so this code makes
1906 * the same assumption and doesn't check OTG source.
1907 */
5ec43eda 1908 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f
AK		 1909
1910 /* Instance should be within the range of the pool */
1911 if (inst >= pool->pipe_count)
1912 return -1;
1913
5ec43eda
ML		 1914 if (inst >= pool->stream_enc_count)
1915 return -1;
1916
1917 tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
1918
1919 if (tg_inst >= pool->timing_generator_count)
1920 return false;
1921
1922 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1923 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1924
1925 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1926 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1927 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1928 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1929 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1930 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1931 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1932
5ec43eda
ML		 1933 if (pool->dpps[tg_inst])
1934 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
1935 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK		 1936
1937 pipe_ctx->stream = stream;
5ec43eda 1938 return tg_inst;
d2d7885f
AK		 1939 }
1940
1941 return -1;
1942}
1943
4562236b 1944enum dc_status resource_map_pool_resources(
fb3466a4 1945 const struct dc *dc,
608ac7bb 1946 struct dc_state *context,
1dc90497 1947 struct dc_stream_state *stream)
4562236b 1948{
a2b8659d 1949 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1950 int i;
1951 struct dc_context *dc_ctx = dc->ctx;
1952 struct pipe_ctx *pipe_ctx = NULL;
1953 int pipe_idx = -1;
46570f09 1954 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 1955
1dc90497
AG		 1956 /* TODO Check if this is needed */
1957 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1958 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1959 stream->bit_depth_params =
430ef426
DL		 1960 old_context->streams[i]->bit_depth_params;
1961 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1962 continue;
1963 }
4b679bc3 1964 }
1dc90497 1965 */
7e2fe319 1966
08e1c28d
YMM		 1967 calculate_phy_pix_clks(stream);
1968
46570f09
AK		 1969 /* TODO: Check Linux */
1970 if (dc->config.allow_seamless_boot_optimization &&
1971 !dcb->funcs->is_accelerated_mode(dcb)) {
1972 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1973 stream->apply_seamless_boot_optimization = true;
1974 }
1975
d2d7885f
AK		 1976 if (stream->apply_seamless_boot_optimization)
1977 pipe_idx = acquire_resource_from_hw_enabled_state(
1978 &context->res_ctx,
1979 pool,
1980 stream);
1981
1982 if (pipe_idx < 0)
1983 /* acquire new resources */
1984 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1985
dc37a9a0 1986#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1987 if (pipe_idx < 0)
13ab1b44 1988 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1989#endif
13ab1b44 1990
c5b38aec 1991 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1992 return DC_NO_CONTROLLER_RESOURCE;
1993
1994 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1995
1996 pipe_ctx->stream_res.stream_enc =
78cc70b1 1997 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 1998 &context->res_ctx, pool, stream);
1999
2000 if (!pipe_ctx->stream_res.stream_enc)
38684e46 2001 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 2002
2003 update_stream_engine_usage(
2004 &context->res_ctx, pool,
2005 pipe_ctx->stream_res.stream_enc,
2006 true);
2007
2008 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2009 if (!stream->converter_disable_audio &&
1dc90497 2010 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2011 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2012 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 2013 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 2014
2015 /*
2016 * Audio assigned in order first come first get.
2017 * There are asics which has number of audio
2018 * resources less then number of pipes
2019 */
2020 if (pipe_ctx->stream_res.audio)
2021 update_audio_usage(&context->res_ctx, pool,
2022 pipe_ctx->stream_res.audio, true);
2023 }
268cadbd 2024
9aef1a31
S		 2025 /* Add ABM to the resource if on EDP */
2026 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2027 pipe_ctx->stream_res.abm = pool->abm;
2028
1dc90497
AG		 2029 for (i = 0; i < context->stream_count; i++)
2030 if (context->streams[i] == stream) {
2031 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 2032 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
5fdb7c4c
NK		 2033 context->stream_status[i].audio_inst =
2034 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2035
1dc90497
AG		 2036 return DC_OK;
2037 }
4562236b 2038
1dc90497
AG		 2039 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2040 return DC_ERROR_UNEXPECTED;
2041}
4562236b 2042
2119aa17
DF		 2043/**
2044 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2045 * Is a shallow copy. Increments refcounts on existing streams and planes.
2046 * @dc: copy out of dc->current_state
2047 * @dst_ctx: copy into this
2048 */
f36cc577 2049void dc_resource_state_copy_construct_current(
1dc90497 2050 const struct dc *dc,
608ac7bb 2051 struct dc_state *dst_ctx)
1dc90497 2052{
f36cc577 2053 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2054}
2055
ab8db3e1
AG		 2056
2057void dc_resource_state_construct(
2058 const struct dc *dc,
2059 struct dc_state *dst_ctx)
2060{
dc88b4a6 2061 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2062}
2063
2119aa17
DF		 2064/**
2065 * dc_validate_global_state() - Determine if HW can support a given state
2066 * Checks HW resource availability and bandwidth requirement.
2067 * @dc: dc struct for this driver
2068 * @new_ctx: state to be validated
afcd526b 2069 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2070 *
2071 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2072 */
e750d56d 2073enum dc_status dc_validate_global_state(
1dc90497 2074 struct dc *dc,
afcd526b
JA		 2075 struct dc_state *new_ctx,
2076 bool fast_validate)
4562236b 2077{
1dc90497 2078 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2079 int i, j;
4562236b 2080
e41ab030
HW		 2081 if (!new_ctx)
2082 return DC_ERROR_UNEXPECTED;
2083
d596e5d0 2084 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2085 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2086 if (result != DC_OK)
2087 return result;
d596e5d0 2088 }
4562236b 2089
e41ab030 2090 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2091 struct dc_stream_state *stream = new_ctx->streams[i];
2092
2093 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2094 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2095
2096 if (pipe_ctx->stream != stream)
2097 continue;
2098
74eac5f3
SSC		 2099 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2100 pipe_ctx->plane_state &&
2101 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2102 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2103 if (result != DC_OK)
2104 return result;
2105 }
2106
1dc90497
AG		 2107 /* Switch to dp clock source only if there is
2108 * no non dp stream that shares the same timing
2109 * with the dp stream.
2110 */
2111 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2112 !find_pll_sharable_stream(stream, new_ctx)) {
2113
9d0dcecd 2114 resource_unreference_clock_source(
1dc90497
AG		 2115 &new_ctx->res_ctx,
2116 dc->res_pool,
9d0dcecd 2117 pipe_ctx->clock_source);
4a629536 2118
1dc90497
AG		 2119 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2120 resource_reference_clock_source(
2121 &new_ctx->res_ctx,
2122 dc->res_pool,
2123 pipe_ctx->clock_source);
2124 }
2125 }
2126 }
2127
1dc90497
AG		 2128 result = resource_build_scaling_params_for_context(dc, new_ctx);
2129
2130 if (result == DC_OK)
afcd526b 2131 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2132 result = DC_FAIL_BANDWIDTH_VALIDATE;
2133
2134 return result;
4562236b
HW		 2135}
2136
6e4d6bee 2137static void patch_gamut_packet_checksum(
e09b6473 2138 struct dc_info_packet *gamut_packet)
4562236b 2139{
4562236b 2140 /* For gamut we recalc checksum */
6e4d6bee 2141 if (gamut_packet->valid) {
4562236b
HW		 2142 uint8_t chk_sum = 0;
2143 uint8_t *ptr;
2144 uint8_t i;
2145
4562236b 2146 /*start of the Gamut data. */
6e4d6bee 2147 ptr = &gamut_packet->sb[3];
4562236b 2148
6e4d6bee 2149 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2150 chk_sum += ptr[i];
2151
6e4d6bee 2152 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2153 }
4562236b
HW		 2154}
2155
2156static void set_avi_info_frame(
e09b6473 2157 struct dc_info_packet *info_packet,
4562236b
HW		 2158 struct pipe_ctx *pipe_ctx)
2159{
0971c40e 2160 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2161 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2162 uint32_t pixel_encoding = 0;
2163 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2164 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2165 bool itc = false;
50e27654 2166 uint8_t itc_value = 0;
4562236b 2167 uint8_t cn0_cn1 = 0;
50e27654 2168 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2169 uint8_t *check_sum = NULL;
2170 uint8_t byte_index = 0;
754e3673 2171 union hdmi_info_packet hdmi_info;
50e27654 2172 union display_content_support support = {0};
4fa086b9 2173 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2174 enum dc_timing_3d_format format;
4562236b 2175
754e3673
AK		 2176 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2177
4fa086b9 2178 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2179 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2180 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2181 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2182
2183 /* Initialize header */
e09b6473 2184 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2185 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2186 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2187 hdmi_info.bits.header.version = 2;
2188 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2189
2190 /*
2191 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2192 * according to HDMI 2.0 spec (Section 10.1)
2193 */
2194
4fa086b9 2195 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2196 case PIXEL_ENCODING_YCBCR422:
2197 pixel_encoding = 1;
2198 break;
2199
2200 case PIXEL_ENCODING_YCBCR444:
2201 pixel_encoding = 2;
2202 break;
2203 case PIXEL_ENCODING_YCBCR420:
2204 pixel_encoding = 3;
2205 break;
2206
2207 case PIXEL_ENCODING_RGB:
2208 default:
2209 pixel_encoding = 0;
2210 }
2211
2212 /* Y0_Y1_Y2 : The pixel encoding */
2213 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2214 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2215
2216 /* A0 = 1 Active Format Information valid */
e09b6473 2217 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2218
2219 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2220 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2221
e09b6473 2222 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2223
2224 /* S0, S1 : Underscan / Overscan */
2225 /* TODO: un-hardcode scan type */
2226 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2227 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2228
2229 /* C0, C1 : Colorimetry */
8fde5884 2230 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2231 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2232 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2233 else if (color_space == COLOR_SPACE_YCBCR601 ||
2234 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2235 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2236 else {
e09b6473 2237 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2238 }
534db198 2239 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2240 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2241 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2242 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2243 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2244 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2245 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2246 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2247 }
2248
4562236b 2249 /* TODO: un-hardcode aspect ratio */
4fa086b9 2250 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2251
2252 switch (aspect) {
2253 case ASPECT_RATIO_4_3:
2254 case ASPECT_RATIO_16_9:
e09b6473 2255 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2256 break;
2257
2258 case ASPECT_RATIO_NO_DATA:
2259 case ASPECT_RATIO_64_27:
2260 case ASPECT_RATIO_256_135:
2261 default:
e09b6473 2262 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2263 }
2264
2265 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2266 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2267
2268 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2269
4562236b 2270 cn0_cn1 = 0;
50e27654
ZF		 2271 cn0_cn1_value = 0;
2272
2273 itc = true;
2274 itc_value = 1;
2275
ceb3dbb4 2276 support = stream->content_support;
4562236b
HW		 2277
2278 if (itc) {
50e27654
ZF		 2279 if (!support.bits.valid_content_type) {
2280 cn0_cn1_value = 0;
2281 } else {
2282 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2283 if (support.bits.graphics_content == 1) {
2284 cn0_cn1_value = 0;
2285 }
2286 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2287 if (support.bits.photo_content == 1) {
2288 cn0_cn1_value = 1;
2289 } else {
2290 cn0_cn1_value = 0;
2291 itc_value = 0;
2292 }
2293 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2294 if (support.bits.cinema_content == 1) {
2295 cn0_cn1_value = 2;
2296 } else {
2297 cn0_cn1_value = 0;
2298 itc_value = 0;
2299 }
2300 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2301 if (support.bits.game_content == 1) {
2302 cn0_cn1_value = 3;
2303 } else {
2304 cn0_cn1_value = 0;
2305 itc_value = 0;
2306 }
2307 }
2308 }
e09b6473
AK		 2309 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2310 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2311 }
2312
2313 /* TODO : We should handle YCC quantization */
2314 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2315 if (stream->qs_bit == 1 &&
2316 stream->qy_bit == 1) {
50e27654
ZF		 2317 if (color_space == COLOR_SPACE_SRGB ||
2318 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2319 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2320 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2321 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2322 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2323 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2324 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2325 } else {
e09b6473
AK		 2326 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2327 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2328 }
4562236b 2329 } else {
e09b6473
AK		 2330 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2331 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2332 }
50e27654 2333
15e17335 2334 ///VIC
4fa086b9 2335 format = stream->timing.timing_3d_format;
15e17335
CL		 2336 /*todo, add 3DStereo support*/
2337 if (format != TIMING_3D_FORMAT_NONE) {
2338 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2339 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2340 case 1:
2341 vic = 95;
2342 break;
2343 case 2:
2344 vic = 94;
2345 break;
2346 case 3:
2347 vic = 93;
2348 break;
2349 case 4:
2350 vic = 98;
2351 break;
2352 default:
2353 break;
2354 }
2355 }
efa02336 2356 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2357 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2358 if (vic >= 128)
2359 hdmi_info.bits.header.version = 3;
2360 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2361 * the Source shall use 20 AVI InfoFrame Version 4
2362 */
2363 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2364 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2365 hdmi_info.bits.header.version = 4;
2366 hdmi_info.bits.header.length = 14;
2367 }
4562236b
HW		 2368
2369 /* pixel repetition
2370 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2371 * repetition start from 1 */
e09b6473 2372 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2373
2374 /* Bar Info
2375 * barTop: Line Number of End of Top Bar.
2376 * barBottom: Line Number of Start of Bottom Bar.
2377 * barLeft: Pixel Number of End of Left Bar.
2378 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2379 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2380 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2381 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2382 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2383 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2384 - stream->timing.h_border_right + 1);
4562236b 2385
2f482c4f
CP		 2386 /* Additional Colorimetry Extension
2387 * Used in conduction with C0-C1 and EC0-EC2
2388 * 0 = DCI-P3 RGB (D65)
2389 * 1 = DCI-P3 RGB (theater)
2390 */
2391 hdmi_info.bits.ACE0_ACE3 = 0;
2392
4562236b 2393 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2394 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2395
efa02336 2396 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2397
efa02336 2398 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2399 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2400
2401 /* one byte complement */
2402 *check_sum = (uint8_t) (0x100 - *check_sum);
2403
2404 /* Store in hw_path_mode */
e09b6473
AK		 2405 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2406 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2407 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2408
e09b6473
AK		 2409 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2410 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2411
2412 info_packet->valid = true;
2413}
2414
6e4d6bee 2415static void set_vendor_info_packet(
e09b6473 2416 struct dc_info_packet *info_packet,
0971c40e 2417 struct dc_stream_state *stream)
4562236b 2418{
ecd0136b 2419 /* SPD info packet for FreeSync */
4562236b 2420
ecd0136b
HT		 2421 /* Check if Freesync is supported. Return if false. If true,
2422 * set the corresponding bit in the info packet
2423 */
2424 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2425 return;
2426
ecd0136b 2427 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2428}
2429
6e4d6bee 2430static void set_spd_info_packet(
e09b6473 2431 struct dc_info_packet *info_packet,
0971c40e 2432 struct dc_stream_state *stream)
4562236b
HW		 2433{
2434 /* SPD info packet for FreeSync */
2435
4562236b
HW		 2436 /* Check if Freesync is supported. Return if false. If true,
2437 * set the corresponding bit in the info packet
2438 */
98e6436d 2439 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2440 return;
2441
98e6436d 2442 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2443}
2444
1646a6fe 2445static void set_hdr_static_info_packet(
e09b6473 2446 struct dc_info_packet *info_packet,
0971c40e 2447 struct dc_stream_state *stream)
1646a6fe 2448{
0eeef690 2449 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2450
a10dc97a
KK		 2451 if (!stream->hdr_static_metadata.valid ||
2452 stream->use_dynamic_meta)
10bff005
YS		 2453 return;
2454
0eeef690 2455 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2456}
2457
6e4d6bee 2458static void set_vsc_info_packet(
e09b6473 2459 struct dc_info_packet *info_packet,
0971c40e 2460 struct dc_stream_state *stream)
4562236b 2461{
1336926f 2462 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2463 return;
2464
1336926f 2465 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2466}
2467
f36cc577 2468void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2469{
2470 int i, j;
2471
ab2541b6 2472 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2473 for (j = 0; j < context->stream_status[i].plane_count; j++)
2474 dc_plane_state_release(
2475 context->stream_status[i].plane_states[j]);
4562236b 2476
3be5262e 2477 context->stream_status[i].plane_count = 0;
4fa086b9 2478 dc_stream_release(context->streams[i]);
ab2541b6 2479 context->streams[i] = NULL;
4562236b
HW		 2480 }
2481}
2482
f36cc577 2483void dc_resource_state_copy_construct(
608ac7bb
JZ		 2484 const struct dc_state *src_ctx,
2485 struct dc_state *dst_ctx)
4562236b
HW		 2486{
2487 int i, j;
8ee5702a 2488 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2489
2490 *dst_ctx = *src_ctx;
2491
a2b8659d 2492 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2493 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2494
2495 if (cur_pipe->top_pipe)
2496 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2497
2498 if (cur_pipe->bottom_pipe)
2499 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
4562236b
HW		 2500 }
2501
ab2541b6 2502 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2503 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2504 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2505 dc_plane_state_retain(
2506 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2507 }
9a3afbb3
AG		 2508
2509 /* context refcount should not be overridden */
8ee5702a 2510 dst_ctx->refcount = refcount;
9a3afbb3 2511
4562236b
HW		 2512}
2513
2514struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2515 struct resource_context *res_ctx,
2516 const struct resource_pool *pool)
4562236b
HW		 2517{
2518 int i;
2519
a2b8659d 2520 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2521 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2522 return pool->clock_sources[i];
4562236b
HW		 2523 }
2524
2525 return NULL;
2526}
2527
2528void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2529{
2530 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2531 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2532
2533 /* default all packets to invalid */
6e4d6bee
TC		 2534 info->avi.valid = false;
2535 info->gamut.valid = false;
2536 info->vendor.valid = false;
630e3573 2537 info->spd.valid = false;
6e4d6bee
TC		 2538 info->hdrsmd.valid = false;
2539 info->vsc.valid = false;
4562236b
HW		 2540
2541 signal = pipe_ctx->stream->signal;
2542
2543 /* HDMi and DP have different info packets*/
2544 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2545 set_avi_info_frame(&info->avi, pipe_ctx);
2546
2547 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2548
2549 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2550
56ef6ed9 2551 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2552
a33fa99d 2553 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2554 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2555
2556 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2557
56ef6ed9 2558 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2559 }
4562236b 2560
6e4d6bee 2561 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2562}
2563
2564enum dc_status resource_map_clock_resources(
fb3466a4 2565 const struct dc *dc,
608ac7bb 2566 struct dc_state *context,
1dc90497 2567 struct dc_stream_state *stream)
4562236b 2568{
4562236b 2569 /* acquire new resources */
1dc90497
AG		 2570 const struct resource_pool *pool = dc->res_pool;
2571 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2572 &context->res_ctx, stream);
ab2541b6 2573
1dc90497
AG		 2574 if (!pipe_ctx)
2575 return DC_ERROR_UNEXPECTED;
4562236b 2576
1dc90497
AG		 2577 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2578 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2579 pipe_ctx->clock_source = pool->dp_clock_source;
2580 else {
2581 pipe_ctx->clock_source = NULL;
4562236b 2582
1dc90497 2583 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2584 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2585 &context->res_ctx,
2586 pipe_ctx);
4562236b 2587
1dc90497
AG		 2588 if (pipe_ctx->clock_source == NULL)
2589 pipe_ctx->clock_source =
2590 dc_resource_find_first_free_pll(
2591 &context->res_ctx,
2592 pool);
2593 }
4562236b 2594
1dc90497
AG		 2595 if (pipe_ctx->clock_source == NULL)
2596 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2597
1dc90497
AG		 2598 resource_reference_clock_source(
2599 &context->res_ctx, pool,
2600 pipe_ctx->clock_source);
4562236b
HW		 2601
2602 return DC_OK;
2603}
2604
2605/*
2606 * Note: We need to disable output if clock sources change,
2607 * since bios does optimization and doesn't apply if changing
2608 * PHY when not already disabled.
2609 */
2610bool pipe_need_reprogram(
2611 struct pipe_ctx *pipe_ctx_old,
2612 struct pipe_ctx *pipe_ctx)
2613{
cfe4645e
DL		 2614 if (!pipe_ctx_old->stream)
2615 return false;
2616
4562236b
HW		 2617 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2618 return true;
2619
2620 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2621 return true;
2622
afaacef4 2623 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2624 return true;
2625
2626 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2627 && pipe_ctx_old->stream != pipe_ctx->stream)
2628 return true;
2629
8e9c4c8c 2630 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2631 return true;
2632
2633 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2634 return true;
2635
6b622181
JP		 2636 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2637 return true;
4562236b 2638
1e7e86c4
ST		 2639 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2640 return true;
2641
1336926f
A		 2642 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2643 return true;
2644
eed928dc
CL		 2645 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2646 false == pipe_ctx_old->stream->dpms_off)
2647 return true;
2648
4562236b
HW		 2649 return false;
2650}
529cad0f 2651
0971c40e 2652void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2653 struct bit_depth_reduction_params *fmt_bit_depth)
2654{
4fa086b9 2655 enum dc_dither_option option = stream->dither_option;
529cad0f 2656 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2657 stream->timing.pixel_encoding;
529cad0f
DW		 2658
2659 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2660
603767f9
TC		 2661 if (option == DITHER_OPTION_DEFAULT) {
2662 switch (stream->timing.display_color_depth) {
2663 case COLOR_DEPTH_666:
2664 option = DITHER_OPTION_SPATIAL6;
2665 break;
2666 case COLOR_DEPTH_888:
2667 option = DITHER_OPTION_SPATIAL8;
2668 break;
2669 case COLOR_DEPTH_101010:
2670 option = DITHER_OPTION_SPATIAL10;
2671 break;
2672 default:
2673 option = DITHER_OPTION_DISABLE;
2674 }
2675 }
2676
529cad0f
DW		 2677 if (option == DITHER_OPTION_DISABLE)
2678 return;
2679
2680 if (option == DITHER_OPTION_TRUN6) {
2681 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2682 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2683 } else if (option == DITHER_OPTION_TRUN8 ||
2684 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2685 option == DITHER_OPTION_TRUN8_FM6) {
2686 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2687 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2688 } else if (option == DITHER_OPTION_TRUN10 ||
2689 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2690 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2691 option == DITHER_OPTION_TRUN10_FM8 ||
2692 option == DITHER_OPTION_TRUN10_FM6 ||
2693 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2694 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2695 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2696 }
2697
2698 /* special case - Formatter can only reduce by 4 bits at most.
2699 * When reducing from 12 to 6 bits,
2700 * HW recommends we use trunc with round mode
2701 * (if we did nothing, trunc to 10 bits would be used)
2702 * note that any 12->10 bit reduction is ignored prior to DCE8,
2703 * as the input was 10 bits.
2704 */
2705 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2706 option == DITHER_OPTION_SPATIAL6 ||
2707 option == DITHER_OPTION_FM6) {
2708 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2709 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2710 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2711 }
2712
2713 /* spatial dither
2714 * note that spatial modes 1-3 are never used
2715 */
2716 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2717 option == DITHER_OPTION_SPATIAL6 ||
2718 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2719 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2720 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2721 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2722 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2723 fmt_bit_depth->flags.RGB_RANDOM =
2724 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2725 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2726 option == DITHER_OPTION_SPATIAL8 ||
2727 option == DITHER_OPTION_SPATIAL8_FM6 ||
2728 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2729 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2730 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2731 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2732 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2733 fmt_bit_depth->flags.RGB_RANDOM =
2734 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2735 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2736 option == DITHER_OPTION_SPATIAL10 ||
2737 option == DITHER_OPTION_SPATIAL10_FM8 ||
2738 option == DITHER_OPTION_SPATIAL10_FM6) {
2739 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2740 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2741 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2742 fmt_bit_depth->flags.RGB_RANDOM =
2743 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2744 }
2745
2746 if (option == DITHER_OPTION_SPATIAL6 ||
2747 option == DITHER_OPTION_SPATIAL8 ||
2748 option == DITHER_OPTION_SPATIAL10) {
2749 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2750 } else {
2751 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2752 }
2753
2754 //////////////////////
2755 //// temporal dither
2756 //////////////////////
2757 if (option == DITHER_OPTION_FM6 ||
2758 option == DITHER_OPTION_SPATIAL8_FM6 ||
2759 option == DITHER_OPTION_SPATIAL10_FM6 ||
2760 option == DITHER_OPTION_TRUN10_FM6 ||
2761 option == DITHER_OPTION_TRUN8_FM6 ||
2762 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2763 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2764 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2765 } else if (option == DITHER_OPTION_FM8 ||
2766 option == DITHER_OPTION_SPATIAL10_FM8 ||
2767 option == DITHER_OPTION_TRUN10_FM8) {
2768 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2769 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2770 } else if (option == DITHER_OPTION_FM10) {
2771 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2772 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2773 }
2774
2775 fmt_bit_depth->pixel_encoding = pixel_encoding;
2776}
9345d987 2777
62c933f9 2778enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2779{
fb3466a4 2780 struct dc *core_dc = dc;
ceb3dbb4 2781 struct dc_link *link = stream->link;
9345d987
AG		 2782 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2783 enum dc_status res = DC_OK;
2784
4fa086b9 2785 calculate_phy_pix_clks(stream);
9345d987 2786
4fa086b9 2787 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2788 res = DC_FAIL_CONTROLLER_VALIDATE;
2789
248cbed6 2790 if (res == DC_OK) {
9345d987 2791 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2792 link->link_enc, stream))
9345d987 2793 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2794 }
9345d987
AG		 2795
2796 /* TODO: validate audio ASIC caps, encoder */
2797
2798 if (res == DC_OK)
4fa086b9 2799 res = dc_link_validate_mode_timing(stream,
9345d987 2800 link,
4fa086b9 2801 &stream->timing);
9345d987 2802
62c933f9 2803 return res;
9345d987 2804}
792671d7 2805
62c933f9 2806enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2807{
62c933f9
YS		 2808 enum dc_status res = DC_OK;
2809
792671d7 2810 /* TODO For now validates pixel format only */
8e7095b9 2811 if (dc->res_pool->funcs->validate_plane)
62c933f9 2812 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2813
62c933f9 2814 return res;
792671d7 2815}
74eac5f3
SSC		 2816
2817unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2818{
2819 switch (format) {
2820 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2821 return 8;
2822 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2823 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2824 return 12;
2825 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2826 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2827 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2828 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2829 return 16;
2830 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2831 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2832 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2833 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2834 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2835 return 32;
2836 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2837 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2838 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2839 return 64;
2840 default:
2841 ASSERT_CRITICAL(false);
2842 return -1;
2843 }
2844}
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