]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/amd/display/dc/core/dc_resource.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/display: only include FEC overhead if both asic and display support FEC
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b
HW		 44
45#include "dce80/dce80_resource.h"
46#include "dce100/dce100_resource.h"
47#include "dce110/dce110_resource.h"
48#include "dce112/dce112_resource.h"
cf2156e2 49#include "dce120/dce120_resource.h"
b86a1aa3 50#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 51#include "dcn10/dcn10_resource.h"
7ed4e635 52#include "dcn20/dcn20_resource.h"
e22ece54 53#include "dcn21/dcn21_resource.h"
cf2156e2 54#endif
5d4b05dd
BL		 55
56#define DC_LOGGER_INIT(logger)
57
4562236b
HW		 58enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
59{
60 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
61 switch (asic_id.chip_family) {
62
63 case FAMILY_CI:
4562236b
HW		 64 dc_version = DCE_VERSION_8_0;
65 break;
ebfdf0d0
AD		 66 case FAMILY_KV:
67 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
68 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
69 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
70 dc_version = DCE_VERSION_8_3;
71 else
72 dc_version = DCE_VERSION_8_1;
73 break;
4562236b
HW		 74 case FAMILY_CZ:
75 dc_version = DCE_VERSION_11_0;
76 break;
77
78 case FAMILY_VI:
79 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
80 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
81 dc_version = DCE_VERSION_10_0;
82 break;
83 }
84 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 85 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 87 dc_version = DCE_VERSION_11_2;
88 }
0c75d5ac
JFZ		 89 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
90 dc_version = DCE_VERSION_11_22;
4562236b 91 break;
2c8ad2d5 92 case FAMILY_AI:
b8b6ce89
LL		 93 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
94 dc_version = DCE_VERSION_12_1;
95 else
96 dc_version = DCE_VERSION_12_0;
2c8ad2d5 97 break;
b86a1aa3 98#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 99 case FAMILY_RV:
100 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 101 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
102 dc_version = DCN_VERSION_1_01;
e22ece54
BL		 103 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
104 dc_version = DCN_VERSION_2_1;
ff5ef992
AD		 105 break;
106#endif
7ed4e635 107
7ed4e635
HW		 108 case FAMILY_NV:
109 dc_version = DCN_VERSION_2_0;
110 break;
4562236b
HW		 111 default:
112 dc_version = DCE_VERSION_UNKNOWN;
113 break;
114 }
115 return dc_version;
116}
117
d9673c92
HW		 118struct resource_pool *dc_create_resource_pool(struct dc *dc,
119 const struct dc_init_data *init_data,
120 enum dce_version dc_version)
4562236b 121{
5ac3d3c9 122 struct resource_pool *res_pool = NULL;
4562236b
HW		 123
124 switch (dc_version) {
125 case DCE_VERSION_8_0:
7992a629 126 res_pool = dce80_create_resource_pool(
d9673c92 127 init_data->num_virtual_links, dc);
7992a629 128 break;
ebfdf0d0 129 case DCE_VERSION_8_1:
7992a629 130 res_pool = dce81_create_resource_pool(
d9673c92 131 init_data->num_virtual_links, dc);
7992a629 132 break;
ebfdf0d0 133 case DCE_VERSION_8_3:
7992a629 134 res_pool = dce83_create_resource_pool(
d9673c92 135 init_data->num_virtual_links, dc);
5ac3d3c9 136 break;
4562236b 137 case DCE_VERSION_10_0:
5ac3d3c9 138 res_pool = dce100_create_resource_pool(
d9673c92 139 init_data->num_virtual_links, dc);
5ac3d3c9 140 break;
4562236b 141 case DCE_VERSION_11_0:
5ac3d3c9 142 res_pool = dce110_create_resource_pool(
d9673c92
HW		 143 init_data->num_virtual_links, dc,
144 init_data->asic_id);
5ac3d3c9 145 break;
4562236b 146 case DCE_VERSION_11_2:
0c75d5ac 147 case DCE_VERSION_11_22:
5ac3d3c9 148 res_pool = dce112_create_resource_pool(
d9673c92 149 init_data->num_virtual_links, dc);
5ac3d3c9 150 break;
2c8ad2d5 151 case DCE_VERSION_12_0:
b8b6ce89 152 case DCE_VERSION_12_1:
2c8ad2d5 153 res_pool = dce120_create_resource_pool(
d9673c92 154 init_data->num_virtual_links, dc);
2c8ad2d5 155 break;
ff5ef992 156
b86a1aa3 157#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 158 case DCN_VERSION_1_0:
0e3d73f1 159 case DCN_VERSION_1_01:
d9673c92 160 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 161 break;
3639fa68
ZF		 162
163
7ed4e635
HW		 164 case DCN_VERSION_2_0:
165 res_pool = dcn20_create_resource_pool(init_data, dc);
166 break;
e22ece54
BL		 167 case DCN_VERSION_2_1:
168 res_pool = dcn21_create_resource_pool(init_data, dc);
169 break;
170#endif
7ed4e635 171
4562236b
HW		 172 default:
173 break;
174 }
f49cfa27 175
5ac3d3c9 176 if (res_pool != NULL) {
9adc8050 177 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 178 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 179 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 180 /* initialize with firmware data first, no all
181 * ASIC have DCCG SW component. FPGA or
182 * simulation need initialization of
183 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
184 * with xtalin_clock_inKhz
185 */
186 res_pool->ref_clocks.dccg_ref_clock_inKhz =
187 res_pool->ref_clocks.xtalin_clock_inKhz;
188 res_pool->ref_clocks.dchub_ref_clock_inKhz =
189 res_pool->ref_clocks.xtalin_clock_inKhz;
190 } else
191 ASSERT_CRITICAL(false);
5ac3d3c9 192 }
4562236b 193
5ac3d3c9 194 return res_pool;
4562236b
HW		 195}
196
fb3466a4 197void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 198{
199 if (dc) {
200 if (dc->res_pool)
201 dc->res_pool->funcs->destroy(&dc->res_pool);
202
d029810c 203 kfree(dc->hwseq);
4562236b
HW		 204 }
205}
206
207static void update_num_audio(
208 const struct resource_straps *straps,
209 unsigned int *num_audio,
210 struct audio_support *aud_support)
211{
b8e9eb72
CL		 212 aud_support->dp_audio = true;
213 aud_support->hdmi_audio_native = false;
214 aud_support->hdmi_audio_on_dongle = false;
215
4562236b 216 if (straps->hdmi_disable == 0) {
4562236b
HW		 217 if (straps->dc_pinstraps_audio & 0x2) {
218 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 219 aud_support->hdmi_audio_native = true;
4562236b
HW		 220 }
221 }
222
223 switch (straps->audio_stream_number) {
224 case 0: /* multi streams supported */
225 break;
226 case 1: /* multi streams not supported */
227 *num_audio = 1;
228 break;
229 default:
230 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 231 }
4562236b
HW		 232}
233
234bool resource_construct(
235 unsigned int num_virtual_links,
fb3466a4 236 struct dc *dc,
4562236b
HW		 237 struct resource_pool *pool,
238 const struct resource_create_funcs *create_funcs)
239{
240 struct dc_context *ctx = dc->ctx;
241 const struct resource_caps *caps = pool->res_cap;
242 int i;
243 unsigned int num_audio = caps->num_audio;
244 struct resource_straps straps = {0};
245
246 if (create_funcs->read_dce_straps)
247 create_funcs->read_dce_straps(dc->ctx, &straps);
248
249 pool->audio_count = 0;
250 if (create_funcs->create_audio) {
251 /* find the total number of streams available via the
252 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
253 * registers (one for each pin) starting from pin 1
254 * up to the max number of audio pins.
255 * We stop on the first pin where
256 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
257 */
258 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 259 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 260 struct audio *aud = create_funcs->create_audio(ctx, i);
261
262 if (aud == NULL) {
263 DC_ERR("DC: failed to create audio!\n");
264 return false;
265 }
4562236b
HW		 266 if (!aud->funcs->endpoint_valid(aud)) {
267 aud->funcs->destroy(&aud);
268 break;
269 }
4562236b
HW		 270 pool->audios[i] = aud;
271 pool->audio_count++;
272 }
273 }
274
275 pool->stream_enc_count = 0;
276 if (create_funcs->create_stream_encoder) {
277 for (i = 0; i < caps->num_stream_encoder; i++) {
278 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
279 if (pool->stream_enc[i] == NULL)
280 DC_ERR("DC: failed to create stream_encoder!\n");
281 pool->stream_enc_count++;
282 }
283 }
929c3aaa 284
4176664b
CL		 285 dc->caps.dynamic_audio = false;
286 if (pool->audio_count < pool->stream_enc_count) {
287 dc->caps.dynamic_audio = true;
288 }
4562236b
HW		 289 for (i = 0; i < num_virtual_links; i++) {
290 pool->stream_enc[pool->stream_enc_count] =
291 virtual_stream_encoder_create(
292 ctx, ctx->dc_bios);
293 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
294 DC_ERR("DC: failed to create stream_encoder!\n");
295 return false;
296 }
297 pool->stream_enc_count++;
298 }
299
300 dc->hwseq = create_funcs->create_hwseq(ctx);
301
302 return true;
303}
ad8960a6
ML		 304static int find_matching_clock_source(
305 const struct resource_pool *pool,
306 struct clock_source *clock_source)
307{
4562236b 308
ad8960a6
ML		 309 int i;
310
311 for (i = 0; i < pool->clk_src_count; i++) {
312 if (pool->clock_sources[i] == clock_source)
313 return i;
314 }
315 return -1;
316}
4562236b 317
21e67d4d 318void resource_unreference_clock_source(
4562236b 319 struct resource_context *res_ctx,
a2b8659d 320 const struct resource_pool *pool,
4a629536 321 struct clock_source *clock_source)
4562236b 322{
ad8960a6 323 int i = find_matching_clock_source(pool, clock_source);
4562236b 324
ad8960a6 325 if (i > -1)
4562236b
HW		 326 res_ctx->clock_source_ref_count[i]--;
327
21e67d4d 328 if (pool->dp_clock_source == clock_source)
4562236b 329 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 330}
331
332void resource_reference_clock_source(
333 struct resource_context *res_ctx,
a2b8659d 334 const struct resource_pool *pool,
4562236b
HW		 335 struct clock_source *clock_source)
336{
ad8960a6 337 int i = find_matching_clock_source(pool, clock_source);
4562236b 338
ad8960a6 339 if (i > -1)
4562236b 340 res_ctx->clock_source_ref_count[i]++;
4562236b 341
a2b8659d 342 if (pool->dp_clock_source == clock_source)
4562236b
HW		 343 res_ctx->dp_clock_source_ref_count++;
344}
345
ad8960a6
ML		 346int resource_get_clock_source_reference(
347 struct resource_context *res_ctx,
348 const struct resource_pool *pool,
349 struct clock_source *clock_source)
350{
351 int i = find_matching_clock_source(pool, clock_source);
352
353 if (i > -1)
354 return res_ctx->clock_source_ref_count[i];
355
356 if (pool->dp_clock_source == clock_source)
357 return res_ctx->dp_clock_source_ref_count;
358
359 return -1;
360}
361
4562236b 362bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 363 struct dc_stream_state *stream1,
364 struct dc_stream_state *stream2)
4562236b 365{
4fa086b9 366 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 367 return false;
368
4fa086b9 369 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 370 return false;
371
4fa086b9
LSL		 372 if (stream1->timing.h_addressable
373 != stream2->timing.h_addressable)
4562236b
HW		 374 return false;
375
4fa086b9
LSL		 376 if (stream1->timing.v_addressable
377 != stream2->timing.v_addressable)
4562236b
HW		 378 return false;
379
380604e2
KC		 380 if (stream1->timing.pix_clk_100hz
381 != stream2->timing.pix_clk_100hz)
4562236b
HW		 382 return false;
383
3e27e10e
ML		 384 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
385 return false;
386
4562236b 387 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 388 && (!dc_is_dp_signal(stream1->signal)
389 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 390 return false;
391
d77f778e
CL		 392 if (stream1->view_format != stream2->view_format)
393 return false;
394
0460f9ab
JL		 395 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
396 return false;
397
4562236b
HW		 398 return true;
399}
3e27e10e
ML		 400static bool is_dp_and_hdmi_sharable(
401 struct dc_stream_state *stream1,
402 struct dc_stream_state *stream2)
403{
404 if (stream1->ctx->dc->caps.disable_dp_clk_share)
405 return false;
406
407 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 408 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 409 return false;
3e27e10e
ML		 410
411 return true;
412
413}
4562236b
HW		 414
415static bool is_sharable_clk_src(
416 const struct pipe_ctx *pipe_with_clk_src,
417 const struct pipe_ctx *pipe)
418{
419 if (pipe_with_clk_src->clock_source == NULL)
420 return false;
421
422 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
423 return false;
424
3e27e10e
ML		 425 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
426 (dc_is_dp_signal(pipe->stream->signal) &&
427 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
428 pipe->stream)))
4562236b
HW		 429 return false;
430
431 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 432 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 433 return false;
434
435 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 436 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 437 return false;
438
439 if (!resource_are_streams_timing_synchronizable(
440 pipe_with_clk_src->stream, pipe->stream))
441 return false;
442
443 return true;
444}
445
446struct clock_source *resource_find_used_clk_src_for_sharing(
447 struct resource_context *res_ctx,
448 struct pipe_ctx *pipe_ctx)
449{
450 int i;
451
452 for (i = 0; i < MAX_PIPES; i++) {
453 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
454 return res_ctx->pipe_ctx[i].clock_source;
455 }
456
457 return NULL;
458}
459
460static enum pixel_format convert_pixel_format_to_dalsurface(
461 enum surface_pixel_format surface_pixel_format)
462{
463 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
464
465 switch (surface_pixel_format) {
466 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
467 dal_pixel_format = PIXEL_FORMAT_INDEX8;
468 break;
469 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
470 dal_pixel_format = PIXEL_FORMAT_RGB565;
471 break;
472 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
473 dal_pixel_format = PIXEL_FORMAT_RGB565;
474 break;
475 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
476 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
477 break;
8693049a 478 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 479 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
480 break;
481 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
482 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
483 break;
484 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
485 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
486 break;
487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
488 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
489 break;
490 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
491 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
492 dal_pixel_format = PIXEL_FORMAT_FP16;
493 break;
494 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 495 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 496 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 497 break;
ffbcd19a
VP		 498 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
499 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 500 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 501 break;
4562236b
HW		 502 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
503 default:
504 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
505 break;
506 }
507 return dal_pixel_format;
508}
509
9b6067c0
DL		 510static inline void get_vp_scan_direction(
511 enum dc_rotation_angle rotation,
512 bool horizontal_mirror,
513 bool *orthogonal_rotation,
514 bool *flip_vert_scan_dir,
515 bool *flip_horz_scan_dir)
4562236b 516{
9b6067c0
DL		 517 *orthogonal_rotation = false;
518 *flip_vert_scan_dir = false;
519 *flip_horz_scan_dir = false;
520 if (rotation == ROTATION_ANGLE_180) {
521 *flip_vert_scan_dir = true;
522 *flip_horz_scan_dir = true;
523 } else if (rotation == ROTATION_ANGLE_90) {
524 *orthogonal_rotation = true;
525 *flip_horz_scan_dir = true;
526 } else if (rotation == ROTATION_ANGLE_270) {
527 *orthogonal_rotation = true;
528 *flip_vert_scan_dir = true;
529 }
530
531 if (horizontal_mirror)
532 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 533}
534
228a10d4
AD		 535int get_num_odm_splits(struct pipe_ctx *pipe)
536{
537 int odm_split_count = 0;
538 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
539 while (next_pipe) {
540 odm_split_count++;
541 next_pipe = next_pipe->next_odm_pipe;
542 }
543 pipe = pipe->prev_odm_pipe;
544 while (pipe) {
545 odm_split_count++;
546 pipe = pipe->prev_odm_pipe;
547 }
548 return odm_split_count;
549}
550
5bf24270
DL		 551static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
552{
553 *split_count = get_num_odm_splits(pipe_ctx);
554 *split_idx = 0;
555 if (*split_count == 0) {
556 /*Check for mpc split*/
557 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
558
559 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
560 (*split_idx)++;
561 (*split_count)++;
562 split_pipe = split_pipe->top_pipe;
563 }
564 split_pipe = pipe_ctx->bottom_pipe;
565 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
566 (*split_count)++;
567 split_pipe = split_pipe->bottom_pipe;
568 }
569 } else {
570 /*Get odm split index*/
571 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
572
573 while (split_pipe) {
574 (*split_idx)++;
575 split_pipe = split_pipe->prev_odm_pipe;
576 }
577 }
578}
579
b2d0a103 580static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 581{
3be5262e 582 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 583 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 584 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 585 struct rect surf_src = plane_state->src_rect;
9b6067c0 586 struct rect clip, dest;
87449a90
AK		 587 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
588 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
5bf24270
DL		 589 int split_count = 0;
590 int split_idx = 0;
9b6067c0 591 bool orthogonal_rotation, flip_y_start, flip_x_start;
83d40659 592
5bf24270
DL		 593 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
594
7f5c22d1
VP		 595 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
596 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
5bf24270
DL		 597 split_count = 0;
598 split_idx = 0;
7b779c99 599 }
86006a7f 600
4562236b
HW		 601 /* The actual clip is an intersection between stream
602 * source and surface clip
603 */
9b6067c0 604 dest = plane_state->dst_rect;
3be5262e
HW		 605 clip.x = stream->src.x > plane_state->clip_rect.x ?
606 stream->src.x : plane_state->clip_rect.x;
4562236b 607
1fbd2cfc 608 clip.width = stream->src.x + stream->src.width <
3be5262e 609 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 610 stream->src.x + stream->src.width - clip.x :
3be5262e 611 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 612
3be5262e
HW		 613 clip.y = stream->src.y > plane_state->clip_rect.y ?
614 stream->src.y : plane_state->clip_rect.y;
4562236b 615
1fbd2cfc 616 clip.height = stream->src.y + stream->src.height <
3be5262e 617 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 618 stream->src.y + stream->src.height - clip.y :
3be5262e 619 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 620
9b6067c0
DL		 621 /*
622 * Need to calculate how scan origin is shifted in vp space
623 * to correctly rotate clip and dst
624 */
625 get_vp_scan_direction(
626 plane_state->rotation,
627 plane_state->horizontal_mirror,
628 &orthogonal_rotation,
629 &flip_y_start,
630 &flip_x_start);
631
632 if (orthogonal_rotation) {
633 swap(clip.x, clip.y);
634 swap(clip.width, clip.height);
635 swap(dest.x, dest.y);
636 swap(dest.width, dest.height);
637 }
638 if (flip_x_start) {
639 clip.x = dest.x + dest.width - clip.x - clip.width;
640 dest.x = 0;
641 }
642 if (flip_y_start) {
643 clip.y = dest.y + dest.height - clip.y - clip.height;
644 dest.y = 0;
645 }
646
86006a7f 647 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 648 * num_pixels = clip.num_pix * scl_ratio
649 */
9b6067c0
DL		 650 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
651 data->viewport.width = clip.width * surf_src.width / dest.width;
652
653 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
654 data->viewport.height = clip.height * surf_src.height / dest.height;
655
656 /* Handle split */
5bf24270
DL		 657 if (split_count) {
658 /* extra pixels in the division remainder need to go to pipes after
659 * the extra pixel index minus one(epimo) defined here as:
660 */
661 int epimo = 0;
662
9b6067c0 663 if (orthogonal_rotation) {
5bf24270
DL		 664 if (flip_y_start)
665 split_idx = split_count - split_idx;
666
667 epimo = split_count - data->viewport.height % (split_count + 1);
668
669 data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
670 if (split_idx > epimo)
671 data->viewport.y += split_idx - epimo - 1;
672 data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0 673 } else {
5bf24270
DL		 674 if (flip_x_start)
675 split_idx = split_count - split_idx;
676
677 epimo = split_count - data->viewport.width % (split_count + 1);
678
679 data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
680 if (split_idx > epimo)
681 data->viewport.x += split_idx - epimo - 1;
682 data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
9b6067c0
DL		 683 }
684 }
9b5349f7 685
b2d0a103
DL		 686 /* Round down, compensate in init */
687 data->viewport_c.x = data->viewport.x / vpc_div;
688 data->viewport_c.y = data->viewport.y / vpc_div;
9b6067c0
DL		 689 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
690 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
691
b2d0a103
DL		 692 /* Round up, assume original video size always even dimensions */
693 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
694 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
4562236b
HW		 695}
696
9b6067c0 697static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 698{
3be5262e 699 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 700 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 701 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 702 struct rect surf_clip = plane_state->clip_rect;
5bf24270
DL		 703 bool pri_split_tb = pipe_ctx->bottom_pipe &&
704 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
705 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
706 bool sec_split_tb = pipe_ctx->top_pipe &&
707 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
708 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
709 int split_count = 0;
710 int split_idx = 0;
711
712 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
713
714 data->recout.x = stream->dst.x;
4fa086b9 715 if (stream->src.x < surf_clip.x)
5bf24270 716 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
4fa086b9 717 / stream->src.width;
4562236b 718
5bf24270
DL		 719 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
720 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
721 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
4562236b 722
5bf24270 723 data->recout.y = stream->dst.y;
4fa086b9 724 if (stream->src.y < surf_clip.y)
5bf24270 725 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
4fa086b9 726 / stream->src.height;
4562236b 727
5bf24270
DL		 728 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
729 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
730 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
b2d0a103 731
9b6067c0 732 /* Handle h & v split, handle rotation using viewport */
5bf24270
DL		 733 if (sec_split_tb) {
734 data->recout.y += data->recout.height / 2;
0c31a821 735 /* Floor primary pipe, ceil 2ndary pipe */
5bf24270
DL		 736 data->recout.height = (data->recout.height + 1) / 2;
737 } else if (pri_split_tb)
738 data->recout.height /= 2;
739 else if (split_count) {
740 /* extra pixels in the division remainder need to go to pipes after
741 * the extra pixel index minus one(epimo) defined here as:
742 */
743 int epimo = split_count - data->recout.width % (split_count + 1);
744
745 /*no recout offset due to odm */
746 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
747 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
748 if (split_idx > epimo)
749 data->recout.x += split_idx - epimo - 1;
750 }
751 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
752 }
4562236b
HW		 753}
754
b2d0a103 755static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 756{
3be5262e 757 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 758 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 759 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 760 const int in_w = stream->src.width;
761 const int in_h = stream->src.height;
762 const int out_w = stream->dst.width;
763 const int out_h = stream->dst.height;
4562236b 764
9b6067c0 765 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 766 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
767 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 768 swap(surf_src.height, surf_src.width);
86006a7f 769
eb0e5154 770 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 771 surf_src.width,
3be5262e 772 plane_state->dst_rect.width);
eb0e5154 773 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 774 surf_src.height,
3be5262e 775 plane_state->dst_rect.height);
4562236b 776
4fa086b9 777 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 778 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 779 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 780 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 781
6702a9ac
HW		 782 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
783 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
784 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
785 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 786
6702a9ac
HW		 787 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
788 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 789
6702a9ac
HW		 790 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
791 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
792 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
793 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 794 }
0002d3ac
DL		 795 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
796 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
797 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
798 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
799 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
800 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
801 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
802 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 803}
804
9b6067c0
DL		 805static inline void adjust_vp_and_init_for_seamless_clip(
806 bool flip_scan_dir,
807 int recout_skip,
808 int src_size,
809 int taps,
810 struct fixed31_32 ratio,
811 struct fixed31_32 *init,
812 int *vp_offset,
813 int *vp_size)
b2d0a103 814{
9b6067c0 815 if (!flip_scan_dir) {
9a08f51f 816 /* Adjust for viewport end clip-off */
9b6067c0
DL		 817 if ((*vp_offset + *vp_size) < src_size) {
818 int vp_clip = src_size - *vp_size - *vp_offset;
819 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
9a08f51f
DL		 820
821 int_part = int_part > 0 ? int_part : 0;
9b6067c0 822 *vp_size += int_part < vp_clip ? int_part : vp_clip;
9a08f51f 823 }
b2d0a103 824
9a08f51f 825 /* Adjust for non-0 viewport offset */
9b6067c0 826 if (*vp_offset) {
9a08f51f
DL		 827 int int_part;
828
9b6067c0
DL		 829 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
830 int_part = dc_fixpt_floor(*init) - *vp_offset;
831 if (int_part < taps) {
832 int int_adj = *vp_offset >= (taps - int_part) ?
833 (taps - int_part) : *vp_offset;
834 *vp_offset -= int_adj;
835 *vp_size += int_adj;
9a08f51f 836 int_part += int_adj;
9b6067c0
DL		 837 } else if (int_part > taps) {
838 *vp_offset += int_part - taps;
839 *vp_size -= int_part - taps;
840 int_part = taps;
9a08f51f 841 }
9b6067c0
DL		 842 init->value &= 0xffffffff;
843 *init = dc_fixpt_add_int(*init, int_part);
9a08f51f
DL		 844 }
845 } else {
846 /* Adjust for non-0 viewport offset */
9b6067c0
DL		 847 if (*vp_offset) {
848 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
b2d0a103 849
9a08f51f 850 int_part = int_part > 0 ? int_part : 0;
9b6067c0
DL		 851 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
852 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
9a08f51f 853 }
b2d0a103 854
9a08f51f 855 /* Adjust for viewport end clip-off */
9b6067c0 856 if ((*vp_offset + *vp_size) < src_size) {
9a08f51f 857 int int_part;
9b6067c0 858 int end_offset = src_size - *vp_offset - *vp_size;
9a08f51f
DL		 859
860 /*
861 * this is init if vp had no offset, keep in mind this is from the
862 * right side of vp due to scan direction
863 */
9b6067c0 864 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
9a08f51f
DL		 865 /*
866 * this is the difference between first pixel of viewport available to read
867 * and init position, takning into account scan direction
868 */
9b6067c0
DL		 869 int_part = dc_fixpt_floor(*init) - end_offset;
870 if (int_part < taps) {
871 int int_adj = end_offset >= (taps - int_part) ?
872 (taps - int_part) : end_offset;
873 *vp_size += int_adj;
9a08f51f 874 int_part += int_adj;
9b6067c0
DL		 875 } else if (int_part > taps) {
876 *vp_size += int_part - taps;
877 int_part = taps;
9a08f51f 878 }
9b6067c0
DL		 879 init->value &= 0xffffffff;
880 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 881 }
b2d0a103 882 }
9b6067c0 883}
9a08f51f 884
9b6067c0
DL		 885static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
886{
887 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
888 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 889 struct pipe_ctx *odm_pipe = pipe_ctx->prev_odm_pipe;
9b6067c0
DL		 890 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
891 struct rect src = pipe_ctx->plane_state->src_rect;
892 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
893 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
894 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
895 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
9a08f51f 896
9b6067c0
DL		 897 /*
898 * Need to calculate the scan direction for viewport to make adjustments
899 */
900 get_vp_scan_direction(
901 plane_state->rotation,
902 plane_state->horizontal_mirror,
903 &orthogonal_rotation,
904 &flip_vert_scan_dir,
905 &flip_horz_scan_dir);
906
907 /* Calculate src rect rotation adjusted to recout space */
908 surf_size_h = src.x + src.width;
909 surf_size_v = src.y + src.height;
910 if (flip_horz_scan_dir)
911 src.x = 0;
912 if (flip_vert_scan_dir)
913 src.y = 0;
914 if (orthogonal_rotation) {
915 swap(src.x, src.y);
916 swap(src.width, src.height);
917 }
9a08f51f 918
9b6067c0
DL		 919 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
920 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
921 * - (surf surf_src offset * 1/ full scl ratio))
922 */
923 recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
924 * stream->dst.width / stream->src.width -
925 src.x * plane_state->dst_rect.width / src.width
926 * stream->dst.width / stream->src.width);
5bf24270
DL		 927 /*modified recout_skip_h calculation due to odm having no recout offset caused by split*/
928 while (odm_pipe) {
929 recout_skip_h += odm_pipe->plane_res.scl_data.recout.width + odm_pipe->plane_res.scl_data.recout.x;
930 odm_pipe = odm_pipe->prev_odm_pipe;
931 }
932
9b6067c0
DL		 933 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
934 * stream->dst.height / stream->src.height -
935 src.y * plane_state->dst_rect.height / src.height
936 * stream->dst.height / stream->src.height);
937 if (orthogonal_rotation)
938 swap(recout_skip_h, recout_skip_v);
939 /*
940 * Init calculated according to formula:
941 * init = (scaling_ratio + number_of_taps + 1) / 2
942 * init_bot = init + scaling_ratio
943 * init_c = init + truncated_vp_c_offset(from calculate viewport)
944 */
945 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
946 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
b2d0a103 947
9b6067c0
DL		 948 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
949 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
9a08f51f 950
9b6067c0
DL		 951 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
952 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
9a08f51f 953
9b6067c0
DL		 954 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
955 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
9a08f51f 956
9b6067c0
DL		 957 /*
958 * Taps, inits and scaling ratios are in recout space need to rotate
959 * to viewport rotation before adjustment
960 */
961 adjust_vp_and_init_for_seamless_clip(
962 flip_horz_scan_dir,
963 recout_skip_h,
964 surf_size_h,
965 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
966 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
967 orthogonal_rotation ? &data->inits.v : &data->inits.h,
968 &data->viewport.x,
969 &data->viewport.width);
970 adjust_vp_and_init_for_seamless_clip(
971 flip_horz_scan_dir,
972 recout_skip_h,
973 surf_size_h / vpc_div,
974 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
975 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
976 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
977 &data->viewport_c.x,
978 &data->viewport_c.width);
979 adjust_vp_and_init_for_seamless_clip(
980 flip_vert_scan_dir,
981 recout_skip_v,
982 surf_size_v,
983 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
984 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
985 orthogonal_rotation ? &data->inits.h : &data->inits.v,
986 &data->viewport.y,
987 &data->viewport.height);
988 adjust_vp_and_init_for_seamless_clip(
989 flip_vert_scan_dir,
990 recout_skip_v,
991 surf_size_v / vpc_div,
992 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
993 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
994 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
995 &data->viewport_c.y,
996 &data->viewport_c.height);
b2d0a103
DL		 997
998 /* Interlaced inits based on final vert inits */
eb0e5154
DL		 999 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
1000 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 1001
b2d0a103 1002}
3b733278 1003
89d07b66
ST		 1004/*
1005 * When handling 270 rotation in mixed SLS mode, we have
1006 * stream->timing.h_border_left that is non zero. If we are doing
1007 * pipe-splitting, this h_border_left value gets added to recout.x and when it
1008 * calls calculate_inits_and_adj_vp() and
1009 * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
1010 * pipe to be incorrect.
1011 *
1012 * To fix this, instead of using stream->timing.h_border_left, we can use
1013 * stream->dst.x to represent the border instead. So we will set h_border_left
1014 * to 0 and shift the appropriate amount in stream->dst.x. We will then
1015 * perform all calculations in resource_build_scaling_params() based on this
1016 * and then restore the h_border_left and stream->dst.x to their original
1017 * values.
1018 *
1019 * shift_border_left_to_dst() will shift the amount of h_border_left to
1020 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst()
1021 * will restore h_border_left and stream->dst.x back to their original values
1022 * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
1023 * original h_border_left value in its calculation.
1024 */
1025int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
1026{
1027 int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
1028
1029 if (store_h_border_left) {
1030 pipe_ctx->stream->timing.h_border_left = 0;
1031 pipe_ctx->stream->dst.x += store_h_border_left;
1032 }
1033 return store_h_border_left;
1034}
1035
1036void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
1037 int store_h_border_left)
1038{
1039 pipe_ctx->stream->dst.x -= store_h_border_left;
1040 pipe_ctx->stream->timing.h_border_left = store_h_border_left;
1041}
1042
b2d0a103 1043bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 1044{
3be5262e 1045 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 1046 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 1047 bool res = false;
89d07b66 1048 int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
5d4b05dd 1049 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 1050 /* Important: scaling ratio calculation requires pixel format,
1051 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 1052 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 1053 */
6702a9ac 1054 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 1055 pipe_ctx->plane_state->format);
b2d0a103
DL		 1056
1057 calculate_scaling_ratios(pipe_ctx);
4562236b 1058
b2d0a103 1059 calculate_viewport(pipe_ctx);
4562236b 1060
89d07b66
ST		 1061 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 ||
1062 pipe_ctx->plane_res.scl_data.viewport.width < 16) {
1063 if (store_h_border_left) {
1064 restore_border_left_from_dst(pipe_ctx,
1065 store_h_border_left);
1066 }
4562236b 1067 return false;
89d07b66 1068 }
4562236b 1069
9b6067c0 1070 calculate_recout(pipe_ctx);
4562236b
HW		 1071
1072 /**
1073 * Setting line buffer pixel depth to 24bpp yields banding
1074 * on certain displays, such as the Sharp 4k
1075 */
6702a9ac 1076 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 1077
199e458a 1078 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 1079 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 1080
89d07b66
ST		 1081 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1082 store_h_border_left + timing->h_border_right;
1083 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1084 timing->v_border_top + timing->v_border_bottom;
5bf24270
DL		 1085 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1086 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1b6c8067 1087
4562236b 1088 /* Taps calculations */
d94585a0
YHL		 1089 if (pipe_ctx->plane_res.xfm != NULL)
1090 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1091 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1092
1093 if (pipe_ctx->plane_res.dpp != NULL)
1094 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1095 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1096
f7938bc0 1097
4562236b
HW		 1098 if (!res) {
1099 /* Try 24 bpp linebuffer */
6702a9ac 1100 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1101
1b6c8067
BL		 1102 if (pipe_ctx->plane_res.xfm != NULL)
1103 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1104 pipe_ctx->plane_res.xfm,
1105 &pipe_ctx->plane_res.scl_data,
1106 &plane_state->scaling_quality);
1107
1108 if (pipe_ctx->plane_res.dpp != NULL)
1109 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1110 pipe_ctx->plane_res.dpp,
1111 &pipe_ctx->plane_res.scl_data,
1112 &plane_state->scaling_quality);
4562236b
HW		 1113 }
1114
b2d0a103 1115 if (res)
1fbd2cfc 1116 /* May need to re-check lb size after this in some obscure scenario */
9b6067c0 1117 calculate_inits_and_adj_vp(pipe_ctx);
b2d0a103 1118
1296423b 1119 DC_LOG_SCALER(
4562236b
HW		 1120 "%s: Viewport:\nheight:%d width:%d x:%d "
1121 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1122 "y:%d\n",
1123 __func__,
6702a9ac
HW		 1124 pipe_ctx->plane_res.scl_data.viewport.height,
1125 pipe_ctx->plane_res.scl_data.viewport.width,
1126 pipe_ctx->plane_res.scl_data.viewport.x,
1127 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 1128 plane_state->dst_rect.height,
1129 plane_state->dst_rect.width,
1130 plane_state->dst_rect.x,
1131 plane_state->dst_rect.y);
4562236b 1132
89d07b66
ST		 1133 if (store_h_border_left)
1134 restore_border_left_from_dst(pipe_ctx, store_h_border_left);
1135
4562236b
HW		 1136 return res;
1137}
1138
1139
1140enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1141 const struct dc *dc,
608ac7bb 1142 struct dc_state *context)
4562236b
HW		 1143{
1144 int i;
1145
1146 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1147 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1148 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1149 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1150 return DC_FAIL_SCALING;
4562236b
HW		 1151 }
1152
1153 return DC_OK;
1154}
1155
a2b8659d
TC		 1156struct pipe_ctx *find_idle_secondary_pipe(
1157 struct resource_context *res_ctx,
5581192d
JL		 1158 const struct resource_pool *pool,
1159 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1160{
1161 int i;
1162 struct pipe_ctx *secondary_pipe = NULL;
1163
1164 /*
5581192d
JL		 1165 * We add a preferred pipe mapping to avoid the chance that
1166 * MPCCs already in use will need to be reassigned to other trees.
1167 * For example, if we went with the strict, assign backwards logic:
1168 *
1169 * (State 1)
1170 * Display A on, no surface, top pipe = 0
1171 * Display B on, no surface, top pipe = 1
1172 *
1173 * (State 2)
1174 * Display A on, no surface, top pipe = 0
1175 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1176 *
1177 * (State 3)
1178 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1179 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1180 *
1181 * The state 2->3 transition requires remapping MPCC 5 from display B
1182 * to display A.
1183 *
1184 * However, with the preferred pipe logic, state 2 would look like:
1185 *
1186 * (State 2)
1187 * Display A on, no surface, top pipe = 0
1188 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1189 *
1190 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1191 */
5581192d
JL		 1192 if (primary_pipe) {
1193 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1194 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1195 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1196 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1197 }
1198 }
1199
5581192d
JL		 1200 /*
1201 * search backwards for the second pipe to keep pipe
1202 * assignment more consistent
1203 */
1204 if (!secondary_pipe)
1205 for (i = pool->pipe_count - 1; i >= 0; i--) {
1206 if (res_ctx->pipe_ctx[i].stream == NULL) {
1207 secondary_pipe = &res_ctx->pipe_ctx[i];
1208 secondary_pipe->pipe_idx = i;
1209 break;
1210 }
1211 }
4562236b
HW		 1212
1213 return secondary_pipe;
1214}
1215
1216struct pipe_ctx *resource_get_head_pipe_for_stream(
1217 struct resource_context *res_ctx,
0971c40e 1218 struct dc_stream_state *stream)
4562236b
HW		 1219{
1220 int i;
22498036 1221
a2b8659d 1222 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL		 1223 if (res_ctx->pipe_ctx[i].stream == stream
1224 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1225 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1226 return &res_ctx->pipe_ctx[i];
4562236b
HW		 1227 }
1228 return NULL;
1229}
1230
b1f6d01c 1231static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1232 struct resource_context *res_ctx,
b1f6d01c 1233 struct pipe_ctx *head_pipe)
19f89e23 1234{
b1f6d01c 1235 struct pipe_ctx *tail_pipe;
19f89e23
AG		 1236
1237 tail_pipe = head_pipe->bottom_pipe;
1238
1239 while (tail_pipe) {
1240 head_pipe = tail_pipe;
1241 tail_pipe = tail_pipe->bottom_pipe;
1242 }
1243
1244 return head_pipe;
1245}
1246
4562236b 1247/*
ab2541b6
AC		 1248 * A free_pipe for a stream is defined here as a pipe
1249 * that has no surface attached yet
4562236b 1250 */
b1f6d01c 1251static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1252 struct dc_state *context,
a2b8659d 1253 const struct resource_pool *pool,
b1f6d01c 1254 struct pipe_ctx *head_pipe)
4562236b
HW		 1255{
1256 int i;
745cc746 1257 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1258
3be5262e 1259 if (!head_pipe->plane_state)
4562236b
HW		 1260 return head_pipe;
1261
1262 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1263 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1264 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1265 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1266 return &res_ctx->pipe_ctx[i];
1267 }
1268 }
1269
1270 /*
1271 * At this point we have no re-useable pipe for this stream and we need
1272 * to acquire an idle one to satisfy the request
1273 */
1274
a2b8659d 1275 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1276 return NULL;
1277
b1f6d01c 1278 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW		 1279}
1280
b86a1aa3 1281#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL		 1282static int acquire_first_split_pipe(
1283 struct resource_context *res_ctx,
1284 const struct resource_pool *pool,
0971c40e 1285 struct dc_stream_state *stream)
0f9a536f
DL		 1286{
1287 int i;
1288
1289 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1290 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1291
b1f6d01c 1292 if (split_pipe->top_pipe &&
79592db3
DL		 1293 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1294 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1295 if (split_pipe->bottom_pipe)
1296 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1297
1298 if (split_pipe->top_pipe->plane_state)
1299 resource_build_scaling_params(split_pipe->top_pipe);
1300
1301 memset(split_pipe, 0, sizeof(*split_pipe));
1302 split_pipe->stream_res.tg = pool->timing_generators[i];
1303 split_pipe->plane_res.hubp = pool->hubps[i];
1304 split_pipe->plane_res.ipp = pool->ipps[i];
1305 split_pipe->plane_res.dpp = pool->dpps[i];
1306 split_pipe->stream_res.opp = pool->opps[i];
1307 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1308 split_pipe->pipe_idx = i;
1309
1310 split_pipe->stream = stream;
0f9a536f
DL		 1311 return i;
1312 }
1313 }
1314 return -1;
1315}
1316#endif
1317
19f89e23
AG		 1318bool dc_add_plane_to_context(
1319 const struct dc *dc,
0971c40e 1320 struct dc_stream_state *stream,
19f89e23 1321 struct dc_plane_state *plane_state,
608ac7bb 1322 struct dc_state *context)
4562236b
HW		 1323{
1324 int i;
19f89e23
AG		 1325 struct resource_pool *pool = dc->res_pool;
1326 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1327 struct dc_stream_status *stream_status = NULL;
4562236b 1328
19f89e23
AG		 1329 for (i = 0; i < context->stream_count; i++)
1330 if (context->streams[i] == stream) {
1331 stream_status = &context->stream_status[i];
1332 break;
1333 }
1334 if (stream_status == NULL) {
1335 dm_error("Existing stream not found; failed to attach surface!\n");
1336 return false;
1337 }
1338
4562236b 1339
19f89e23
AG		 1340 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1341 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1342 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1343 return false;
1344 }
1345
19f89e23
AG		 1346 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1347
1348 if (!head_pipe) {
1349 dm_error("Head pipe not found for stream_state %p !\n", stream);
1350 return false;
1351 }
1352
b1f6d01c
DL		 1353 /* retain new surface, but only once per stream */
1354 dc_plane_state_retain(plane_state);
00737c59 1355
b1f6d01c
DL		 1356 while (head_pipe) {
1357 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1358 ASSERT(tail_pipe);
19f89e23 1359
b1f6d01c 1360 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1361
b86a1aa3 1362 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL		 1363 if (!free_pipe) {
1364 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1365 if (pipe_idx >= 0)
1366 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1367 }
1368 #endif
1369 if (!free_pipe) {
1370 dc_plane_state_release(plane_state);
1371 return false;
1372 }
19f89e23 1373
b1f6d01c
DL		 1374 free_pipe->plane_state = plane_state;
1375
1376 if (head_pipe != free_pipe) {
1377 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1378 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1379 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1380 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1381 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1382 free_pipe->clock_source = tail_pipe->clock_source;
1383 free_pipe->top_pipe = tail_pipe;
1384 tail_pipe->bottom_pipe = free_pipe;
1385 }
1386 head_pipe = head_pipe->next_odm_pipe;
1387 }
19f89e23
AG		 1388 /* assign new surfaces*/
1389 stream_status->plane_states[stream_status->plane_count] = plane_state;
1390
1391 stream_status->plane_count++;
1392
1393 return true;
1394}
1395
1396bool dc_remove_plane_from_context(
1397 const struct dc *dc,
1398 struct dc_stream_state *stream,
1399 struct dc_plane_state *plane_state,
608ac7bb 1400 struct dc_state *context)
19f89e23
AG		 1401{
1402 int i;
1403 struct dc_stream_status *stream_status = NULL;
1404 struct resource_pool *pool = dc->res_pool;
1405
ab2541b6 1406 for (i = 0; i < context->stream_count; i++)
4fa086b9 1407 if (context->streams[i] == stream) {
ab2541b6 1408 stream_status = &context->stream_status[i];
4562236b
HW		 1409 break;
1410 }
19f89e23 1411
ab2541b6 1412 if (stream_status == NULL) {
19f89e23 1413 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1414 return false;
1415 }
1416
19f89e23
AG		 1417 /* release pipe for plane*/
1418 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1419 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1420
6ffaa6fc 1421 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG		 1422 if (pipe_ctx->top_pipe)
1423 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1424
19f89e23
AG		 1425 /* Second condition is to avoid setting NULL to top pipe
1426 * of tail pipe making it look like head pipe in subsequent
1427 * deletes
1428 */
1429 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1430 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1431
19f89e23
AG		 1432 /*
1433 * For head pipe detach surfaces from pipe for tail
1434 * pipe just zero it out
1435 */
b1f6d01c 1436 if (!pipe_ctx->top_pipe)
19f89e23 1437 pipe_ctx->plane_state = NULL;
b1f6d01c 1438 else
19f89e23 1439 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1440 }
19f89e23 1441 }
4562236b 1442
4562236b 1443
19f89e23
AG		 1444 for (i = 0; i < stream_status->plane_count; i++) {
1445 if (stream_status->plane_states[i] == plane_state) {
1446
1447 dc_plane_state_release(stream_status->plane_states[i]);
1448 break;
4562236b 1449 }
19f89e23 1450 }
4562236b 1451
19f89e23
AG		 1452 if (i == stream_status->plane_count) {
1453 dm_error("Existing plane_state not found; failed to detach it!\n");
1454 return false;
4562236b
HW		 1455 }
1456
19f89e23 1457 stream_status->plane_count--;
4562236b 1458
abb4986e
AJ		 1459 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1460 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1461 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1462
1463 stream_status->plane_states[stream_status->plane_count] = NULL;
1464
1465 return true;
1466}
1467
1468bool dc_rem_all_planes_for_stream(
1469 const struct dc *dc,
1470 struct dc_stream_state *stream,
608ac7bb 1471 struct dc_state *context)
19f89e23
AG		 1472{
1473 int i, old_plane_count;
1474 struct dc_stream_status *stream_status = NULL;
1475 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1476
1477 for (i = 0; i < context->stream_count; i++)
1478 if (context->streams[i] == stream) {
1479 stream_status = &context->stream_status[i];
1480 break;
1481 }
1482
1483 if (stream_status == NULL) {
1484 dm_error("Existing stream %p not found!\n", stream);
1485 return false;
1486 }
1487
1488 old_plane_count = stream_status->plane_count;
1489
1490 for (i = 0; i < old_plane_count; i++)
1491 del_planes[i] = stream_status->plane_states[i];
1492
1493 for (i = 0; i < old_plane_count; i++)
1494 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1495 return false;
1496
1497 return true;
1498}
1499
1500static bool add_all_planes_for_stream(
1501 const struct dc *dc,
1502 struct dc_stream_state *stream,
1503 const struct dc_validation_set set[],
1504 int set_count,
608ac7bb 1505 struct dc_state *context)
19f89e23
AG		 1506{
1507 int i, j;
1508
1509 for (i = 0; i < set_count; i++)
1510 if (set[i].stream == stream)
1511 break;
1512
1513 if (i == set_count) {
1514 dm_error("Stream %p not found in set!\n", stream);
1515 return false;
1516 }
4562236b 1517
19f89e23
AG		 1518 for (j = 0; j < set[i].plane_count; j++)
1519 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1520 return false;
4562236b
HW		 1521
1522 return true;
1523}
1524
19f89e23
AG		 1525bool dc_add_all_planes_for_stream(
1526 const struct dc *dc,
1527 struct dc_stream_state *stream,
1528 struct dc_plane_state * const *plane_states,
1529 int plane_count,
608ac7bb 1530 struct dc_state *context)
19f89e23
AG		 1531{
1532 struct dc_validation_set set;
1533 int i;
1534
1535 set.stream = stream;
1536 set.plane_count = plane_count;
1537
1538 for (i = 0; i < plane_count; i++)
1539 set.plane_states[i] = plane_states[i];
1540
1541 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1542}
1543
1544
6b622181
JP		 1545static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1546 struct dc_stream_state *new_stream)
1547{
1548 if (cur_stream == NULL)
1549 return true;
1550
1551 if (memcmp(&cur_stream->hdr_static_metadata,
1552 &new_stream->hdr_static_metadata,
1553 sizeof(struct dc_info_packet)) != 0)
1554 return true;
1555
1556 return false;
1557}
4562236b 1558
1336926f
A		 1559static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1560 struct dc_stream_state *new_stream)
1561{
1562 if (cur_stream == NULL)
1563 return true;
1564
1565 if (memcmp(&cur_stream->vsc_infopacket,
1566 &new_stream->vsc_infopacket,
1567 sizeof(struct dc_info_packet)) != 0)
1568 return true;
1569
1570 return false;
1571}
1572
0971c40e
HW		 1573static bool is_timing_changed(struct dc_stream_state *cur_stream,
1574 struct dc_stream_state *new_stream)
4562236b
HW		 1575{
1576 if (cur_stream == NULL)
1577 return true;
1578
1579 /* If sink pointer changed, it means this is a hotplug, we should do
1580 * full hw setting.
1581 */
1582 if (cur_stream->sink != new_stream->sink)
1583 return true;
1584
1585 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1586 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1587 return true;
1588
1589 return memcmp(
4fa086b9
LSL		 1590 &cur_stream->timing,
1591 &new_stream->timing,
4562236b
HW		 1592 sizeof(struct dc_crtc_timing)) != 0;
1593}
1594
1595static bool are_stream_backends_same(
0971c40e 1596 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1597{
1598 if (stream_a == stream_b)
1599 return true;
1600
1601 if (stream_a == NULL || stream_b == NULL)
1602 return false;
1603
1604 if (is_timing_changed(stream_a, stream_b))
1605 return false;
1606
6b622181
JP		 1607 if (is_hdr_static_meta_changed(stream_a, stream_b))
1608 return false;
1609
1e7e86c4
ST		 1610 if (stream_a->dpms_off != stream_b->dpms_off)
1611 return false;
1612
1336926f
A		 1613 if (is_vsc_info_packet_changed(stream_a, stream_b))
1614 return false;
1615
4562236b
HW		 1616 return true;
1617}
1618
2119aa17
DF		 1619/**
1620 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1621 *
1622 * Checks if there a difference between the two states
1623 * that would require a mode change.
1624 *
1625 * Does not compare cursor position or attributes.
1626 */
d54d29db 1627bool dc_is_stream_unchanged(
0971c40e 1628 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1629{
4562236b 1630
ab2541b6
AC		 1631 if (!are_stream_backends_same(old_stream, stream))
1632 return false;
4562236b 1633
0460f9ab
JL		 1634 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1635 return false;
1636
4562236b
HW		 1637 return true;
1638}
1639
2119aa17
DF		 1640/**
1641 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1642 */
9a5d9c48
LSL		 1643bool dc_is_stream_scaling_unchanged(
1644 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1645{
1646 if (old_stream == stream)
1647 return true;
1648
1649 if (old_stream == NULL || stream == NULL)
1650 return false;
1651
1652 if (memcmp(&old_stream->src,
1653 &stream->src,
1654 sizeof(struct rect)) != 0)
1655 return false;
1656
1657 if (memcmp(&old_stream->dst,
1658 &stream->dst,
1659 sizeof(struct rect)) != 0)
1660 return false;
1661
1662 return true;
1663}
1664
1dc90497 1665static void update_stream_engine_usage(
4562236b 1666 struct resource_context *res_ctx,
a2b8659d 1667 const struct resource_pool *pool,
1dc90497
AG		 1668 struct stream_encoder *stream_enc,
1669 bool acquired)
4562236b
HW		 1670{
1671 int i;
1672
a2b8659d
TC		 1673 for (i = 0; i < pool->stream_enc_count; i++) {
1674 if (pool->stream_enc[i] == stream_enc)
1dc90497 1675 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1676 }
1677}
1678
1679/* TODO: release audio object */
4176664b 1680void update_audio_usage(
4562236b 1681 struct resource_context *res_ctx,
a2b8659d 1682 const struct resource_pool *pool,
1dc90497
AG		 1683 struct audio *audio,
1684 bool acquired)
4562236b
HW		 1685{
1686 int i;
a2b8659d
TC		 1687 for (i = 0; i < pool->audio_count; i++) {
1688 if (pool->audios[i] == audio)
1dc90497 1689 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1690 }
1691}
1692
1693static int acquire_first_free_pipe(
1694 struct resource_context *res_ctx,
a2b8659d 1695 const struct resource_pool *pool,
0971c40e 1696 struct dc_stream_state *stream)
4562236b
HW		 1697{
1698 int i;
1699
a2b8659d 1700 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1701 if (!res_ctx->pipe_ctx[i].stream) {
1702 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1703
6b670fa9 1704 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1705 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1706 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1707 pipe_ctx->plane_res.ipp = pool->ipps[i];
1708 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1709 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1710 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1711 if (pool->dpps[i])
1712 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1713 pipe_ctx->pipe_idx = i;
1714
ff5ef992 1715
4562236b
HW		 1716 pipe_ctx->stream = stream;
1717 return i;
1718 }
1719 }
1720 return -1;
1721}
1722
a2b8659d
TC		 1723static struct audio *find_first_free_audio(
1724 struct resource_context *res_ctx,
cfb071f7 1725 const struct resource_pool *pool,
f24b0522
PH		 1726 enum engine_id id,
1727 enum dce_version dc_version)
4562236b 1728{
b5a41620
CL		 1729 int i, available_audio_count;
1730
1731 available_audio_count = pool->audio_count;
1732
1733 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1734 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1735 /*we have enough audio endpoint, find the matching inst*/
1736 if (id != i)
1737 continue;
66bfd4fd 1738 return pool->audios[i];
4562236b 1739 }
66bfd4fd 1740 }
5feb9f07 1741
b5a41620
CL		 1742 /* use engine id to find free audio */
1743 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM		 1744 return pool->audios[id];
1745 }
66bfd4fd 1746 /*not found the matching one, first come first serve*/
b5a41620 1747 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL		 1748 if (res_ctx->is_audio_acquired[i] == false) {
1749 return pool->audios[i];
4176664b
CL		 1750 }
1751 }
4562236b
HW		 1752 return 0;
1753}
1754
4562236b 1755bool resource_is_stream_unchanged(
608ac7bb 1756 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1757{
ab2541b6 1758 int i;
4562236b 1759
ab2541b6 1760 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1761 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1762
ab2541b6 1763 if (are_stream_backends_same(old_stream, stream))
4562236b 1764 return true;
4562236b
HW		 1765 }
1766
1767 return false;
1768}
1769
2119aa17
DF		 1770/**
1771 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1772 */
13ab1b44 1773enum dc_status dc_add_stream_to_ctx(
1dc90497 1774 struct dc *dc,
608ac7bb 1775 struct dc_state *new_ctx,
1dc90497
AG		 1776 struct dc_stream_state *stream)
1777{
1dc90497 1778 enum dc_status res;
eb9714a2 1779 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1780
ece4147f 1781 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1782 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1783 return DC_ERROR_UNEXPECTED;
1784 }
1785
1786 new_ctx->streams[new_ctx->stream_count] = stream;
1787 dc_stream_retain(stream);
1788 new_ctx->stream_count++;
1789
1790 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1791 if (res != DC_OK)
eb9714a2 1792 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1793
13ab1b44 1794 return res;
1dc90497
AG		 1795}
1796
2119aa17
DF		 1797/**
1798 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1799 */
62c933f9 1800enum dc_status dc_remove_stream_from_ctx(
1dc90497 1801 struct dc *dc,
608ac7bb 1802 struct dc_state *new_ctx,
1dc90497
AG		 1803 struct dc_stream_state *stream)
1804{
19f89e23 1805 int i;
1dc90497 1806 struct dc_context *dc_ctx = dc->ctx;
22498036
DL		 1807 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1808 struct pipe_ctx *odm_pipe;
1dc90497
AG		 1809
1810 if (!del_pipe) {
1811 DC_ERROR("Pipe not found for stream %p !\n", stream);
1812 return DC_ERROR_UNEXPECTED;
1813 }
1814
22498036
DL		 1815 odm_pipe = del_pipe->next_odm_pipe;
1816
1817 /* Release primary pipe */
1818 ASSERT(del_pipe->stream_res.stream_enc);
1819 update_stream_engine_usage(
1820 &new_ctx->res_ctx,
1821 dc->res_pool,
1822 del_pipe->stream_res.stream_enc,
1823 false);
1824
1825 if (del_pipe->stream_res.audio)
1826 update_audio_usage(
1827 &new_ctx->res_ctx,
1828 dc->res_pool,
1829 del_pipe->stream_res.audio,
1830 false);
1831
1832 resource_unreference_clock_source(&new_ctx->res_ctx,
1833 dc->res_pool,
1834 del_pipe->clock_source);
1835
1836 if (dc->res_pool->funcs->remove_stream_from_ctx)
1837 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1838
1839 while (odm_pipe) {
1840 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1841
1842 memset(odm_pipe, 0, sizeof(*odm_pipe));
1843 odm_pipe = next_odm_pipe;
1844 }
1845 memset(del_pipe, 0, sizeof(*del_pipe));
1846
1dc90497
AG		 1847 for (i = 0; i < new_ctx->stream_count; i++)
1848 if (new_ctx->streams[i] == stream)
1849 break;
1850
1851 if (new_ctx->streams[i] != stream) {
1852 DC_ERROR("Context doesn't have stream %p !\n", stream);
1853 return DC_ERROR_UNEXPECTED;
1854 }
1855
1856 dc_stream_release(new_ctx->streams[i]);
1857 new_ctx->stream_count--;
1858
1dc90497
AG		 1859 /* Trim back arrays */
1860 for (; i < new_ctx->stream_count; i++) {
1861 new_ctx->streams[i] = new_ctx->streams[i + 1];
1862 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1863 }
1864
1865 new_ctx->streams[new_ctx->stream_count] = NULL;
1866 memset(
1867 &new_ctx->stream_status[new_ctx->stream_count],
1868 0,
1869 sizeof(new_ctx->stream_status[0]));
1870
1871 return DC_OK;
1872}
1873
0971c40e
HW		 1874static struct dc_stream_state *find_pll_sharable_stream(
1875 struct dc_stream_state *stream_needs_pll,
608ac7bb 1876 struct dc_state *context)
4562236b 1877{
ab2541b6 1878 int i;
4562236b 1879
ab2541b6 1880 for (i = 0; i < context->stream_count; i++) {
0971c40e 1881 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1882
ab2541b6
AC		 1883 /* We are looking for non dp, non virtual stream */
1884 if (resource_are_streams_timing_synchronizable(
1885 stream_needs_pll, stream_has_pll)
1886 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1887 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1888 != SIGNAL_TYPE_VIRTUAL)
1889 return stream_has_pll;
4562236b 1890
4562236b
HW		 1891 }
1892
1893 return NULL;
1894}
1895
1896static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1897{
380604e2 1898 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1899 uint32_t normalized_pix_clk = pix_clk;
1900
1901 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1902 pix_clk /= 2;
cc4d99b8
CL		 1903 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1904 switch (timing->display_color_depth) {
8897810a 1905 case COLOR_DEPTH_666:
cc4d99b8
CL		 1906 case COLOR_DEPTH_888:
1907 normalized_pix_clk = pix_clk;
1908 break;
1909 case COLOR_DEPTH_101010:
1910 normalized_pix_clk = (pix_clk * 30) / 24;
1911 break;
1912 case COLOR_DEPTH_121212:
1913 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1914 break;
cc4d99b8
CL		 1915 case COLOR_DEPTH_161616:
1916 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1917 break;
cc4d99b8
CL		 1918 default:
1919 ASSERT(0);
4562236b 1920 break;
cc4d99b8 1921 }
4562236b 1922 }
4562236b
HW		 1923 return normalized_pix_clk;
1924}
1925
0971c40e 1926static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1927{
9345d987
AG		 1928 /* update actual pixel clock on all streams */
1929 if (dc_is_hdmi_signal(stream->signal))
1930 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1931 &stream->timing) / 10;
9345d987
AG		 1932 else
1933 stream->phy_pix_clk =
380604e2 1934 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1935
1936 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1937 stream->phy_pix_clk *= 2;
4562236b
HW		 1938}
1939
d2d7885f
AK		 1940static int acquire_resource_from_hw_enabled_state(
1941 struct resource_context *res_ctx,
1942 const struct resource_pool *pool,
1943 struct dc_stream_state *stream)
1944{
1945 struct dc_link *link = stream->link;
08b66279 1946 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK		 1947
1948 /* Check for enabled DIG to identify enabled display */
1949 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1950 return -1;
1951
5ec43eda 1952 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 1953
7f7652ee 1954 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 1955 return -1;
d2d7885f 1956
7f7652ee
ML		 1957 for (i = 0; i < pool->stream_enc_count; i++) {
1958 if (pool->stream_enc[i]->id == inst) {
1959 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
1960 pool->stream_enc[i]);
1961 break;
1962 }
1963 }
5ec43eda 1964
7f7652ee
ML		 1965 // tg_inst not found
1966 if (i == pool->stream_enc_count)
75441d9d 1967 return -1;
5ec43eda
ML		 1968
1969 if (tg_inst >= pool->timing_generator_count)
75441d9d 1970 return -1;
5ec43eda
ML		 1971
1972 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1973 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1974
1975 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1976 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1977 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1978 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1979 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1980 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1981 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1982
ccce745c 1983 if (pool->dpps[tg_inst]) {
5ec43eda 1984 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
ccce745c
ML		 1985
1986 // Read DPP->MPCC->OPP Pipe from HW State
1987 if (pool->mpc->funcs->read_mpcc_state) {
1988 struct mpcc_state s = {0};
1989
1990 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
1991
1992 if (s.dpp_id < MAX_MPCC)
1993 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
1994
1995 if (s.bot_mpcc_id < MAX_MPCC)
1996 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
1997 &pool->mpc->mpcc_array[s.bot_mpcc_id];
1998
1999 if (s.opp_id < MAX_OPP)
2000 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2001 }
2002 }
5ec43eda 2003 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK		 2004
2005 pipe_ctx->stream = stream;
5ec43eda 2006 return tg_inst;
d2d7885f
AK		 2007 }
2008
2009 return -1;
2010}
2011
4562236b 2012enum dc_status resource_map_pool_resources(
fb3466a4 2013 const struct dc *dc,
608ac7bb 2014 struct dc_state *context,
1dc90497 2015 struct dc_stream_state *stream)
4562236b 2016{
a2b8659d 2017 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 2018 int i;
2019 struct dc_context *dc_ctx = dc->ctx;
2020 struct pipe_ctx *pipe_ctx = NULL;
2021 int pipe_idx = -1;
46570f09 2022 struct dc_bios *dcb = dc->ctx->dc_bios;
4562236b 2023
1dc90497
AG		 2024 /* TODO Check if this is needed */
2025 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 2026 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 2027 stream->bit_depth_params =
430ef426
DL		 2028 old_context->streams[i]->bit_depth_params;
2029 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 2030 continue;
2031 }
4b679bc3 2032 }
1dc90497 2033 */
7e2fe319 2034
08e1c28d
YMM		 2035 calculate_phy_pix_clks(stream);
2036
46570f09
AK		 2037 /* TODO: Check Linux */
2038 if (dc->config.allow_seamless_boot_optimization &&
2039 !dcb->funcs->is_accelerated_mode(dcb)) {
2040 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2041 stream->apply_seamless_boot_optimization = true;
2042 }
2043
d2d7885f
AK		 2044 if (stream->apply_seamless_boot_optimization)
2045 pipe_idx = acquire_resource_from_hw_enabled_state(
2046 &context->res_ctx,
2047 pool,
2048 stream);
2049
2050 if (pipe_idx < 0)
2051 /* acquire new resources */
2052 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 2053
b86a1aa3 2054#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 2055 if (pipe_idx < 0)
13ab1b44 2056 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 2057#endif
13ab1b44 2058
c5b38aec 2059 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 2060 return DC_NO_CONTROLLER_RESOURCE;
2061
2062 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2063
2064 pipe_ctx->stream_res.stream_enc =
78cc70b1 2065 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 2066 &context->res_ctx, pool, stream);
2067
2068 if (!pipe_ctx->stream_res.stream_enc)
38684e46 2069 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 2070
2071 update_stream_engine_usage(
2072 &context->res_ctx, pool,
2073 pipe_ctx->stream_res.stream_enc,
2074 true);
2075
2076 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2077 if (!stream->converter_disable_audio &&
1dc90497 2078 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2079 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2080 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 2081 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG		 2082
2083 /*
2084 * Audio assigned in order first come first get.
2085 * There are asics which has number of audio
2086 * resources less then number of pipes
2087 */
2088 if (pipe_ctx->stream_res.audio)
2089 update_audio_usage(&context->res_ctx, pool,
2090 pipe_ctx->stream_res.audio, true);
2091 }
268cadbd 2092
9aef1a31
S		 2093 /* Add ABM to the resource if on EDP */
2094 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
2095 pipe_ctx->stream_res.abm = pool->abm;
2096
1dc90497
AG		 2097 for (i = 0; i < context->stream_count; i++)
2098 if (context->streams[i] == stream) {
2099 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3f0940f8 2100 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
5fdb7c4c
NK		 2101 context->stream_status[i].audio_inst =
2102 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2103
1dc90497
AG		 2104 return DC_OK;
2105 }
4562236b 2106
1dc90497
AG		 2107 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2108 return DC_ERROR_UNEXPECTED;
2109}
4562236b 2110
2119aa17
DF		 2111/**
2112 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2113 * Is a shallow copy. Increments refcounts on existing streams and planes.
2114 * @dc: copy out of dc->current_state
2115 * @dst_ctx: copy into this
2116 */
f36cc577 2117void dc_resource_state_copy_construct_current(
1dc90497 2118 const struct dc *dc,
608ac7bb 2119 struct dc_state *dst_ctx)
1dc90497 2120{
f36cc577 2121 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2122}
2123
ab8db3e1
AG		 2124
2125void dc_resource_state_construct(
2126 const struct dc *dc,
2127 struct dc_state *dst_ctx)
2128{
dc88b4a6 2129 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2130}
2131
6d822156
NC		 2132
2133bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2134{
2135 return dc->res_pool->res_cap->num_dsc > 0;
2136}
2137
2138
2119aa17
DF		 2139/**
2140 * dc_validate_global_state() - Determine if HW can support a given state
2141 * Checks HW resource availability and bandwidth requirement.
2142 * @dc: dc struct for this driver
2143 * @new_ctx: state to be validated
afcd526b 2144 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2145 *
2146 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2147 */
e750d56d 2148enum dc_status dc_validate_global_state(
1dc90497 2149 struct dc *dc,
afcd526b
JA		 2150 struct dc_state *new_ctx,
2151 bool fast_validate)
4562236b 2152{
1dc90497 2153 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2154 int i, j;
4562236b 2155
e41ab030
HW		 2156 if (!new_ctx)
2157 return DC_ERROR_UNEXPECTED;
2158
d596e5d0 2159 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2160 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2161 if (result != DC_OK)
2162 return result;
d596e5d0 2163 }
4562236b 2164
e41ab030 2165 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2166 struct dc_stream_state *stream = new_ctx->streams[i];
2167
2168 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2169 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2170
2171 if (pipe_ctx->stream != stream)
2172 continue;
2173
74eac5f3
SSC		 2174 if (dc->res_pool->funcs->get_default_swizzle_mode &&
2175 pipe_ctx->plane_state &&
2176 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2177 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2178 if (result != DC_OK)
2179 return result;
2180 }
2181
1dc90497
AG		 2182 /* Switch to dp clock source only if there is
2183 * no non dp stream that shares the same timing
2184 * with the dp stream.
2185 */
2186 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2187 !find_pll_sharable_stream(stream, new_ctx)) {
2188
9d0dcecd 2189 resource_unreference_clock_source(
1dc90497
AG		 2190 &new_ctx->res_ctx,
2191 dc->res_pool,
9d0dcecd 2192 pipe_ctx->clock_source);
4a629536 2193
1dc90497
AG		 2194 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2195 resource_reference_clock_source(
2196 &new_ctx->res_ctx,
2197 dc->res_pool,
2198 pipe_ctx->clock_source);
2199 }
2200 }
2201 }
2202
1dc90497
AG		 2203 result = resource_build_scaling_params_for_context(dc, new_ctx);
2204
2205 if (result == DC_OK)
afcd526b 2206 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2207 result = DC_FAIL_BANDWIDTH_VALIDATE;
2208
2209 return result;
4562236b
HW		 2210}
2211
6e4d6bee 2212static void patch_gamut_packet_checksum(
e09b6473 2213 struct dc_info_packet *gamut_packet)
4562236b 2214{
4562236b 2215 /* For gamut we recalc checksum */
6e4d6bee 2216 if (gamut_packet->valid) {
4562236b
HW		 2217 uint8_t chk_sum = 0;
2218 uint8_t *ptr;
2219 uint8_t i;
2220
4562236b 2221 /*start of the Gamut data. */
6e4d6bee 2222 ptr = &gamut_packet->sb[3];
4562236b 2223
6e4d6bee 2224 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2225 chk_sum += ptr[i];
2226
6e4d6bee 2227 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2228 }
4562236b
HW		 2229}
2230
2231static void set_avi_info_frame(
e09b6473 2232 struct dc_info_packet *info_packet,
4562236b
HW		 2233 struct pipe_ctx *pipe_ctx)
2234{
0971c40e 2235 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2236 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2237 uint32_t pixel_encoding = 0;
2238 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2239 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2240 bool itc = false;
50e27654 2241 uint8_t itc_value = 0;
4562236b 2242 uint8_t cn0_cn1 = 0;
50e27654 2243 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2244 uint8_t *check_sum = NULL;
2245 uint8_t byte_index = 0;
754e3673 2246 union hdmi_info_packet hdmi_info;
50e27654 2247 union display_content_support support = {0};
4fa086b9 2248 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2249 enum dc_timing_3d_format format;
4562236b 2250
754e3673
AK		 2251 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2252
4fa086b9 2253 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2254 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2255 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2256 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2257
2258 /* Initialize header */
e09b6473 2259 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2260 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2261 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2262 hdmi_info.bits.header.version = 2;
2263 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2264
2265 /*
2266 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2267 * according to HDMI 2.0 spec (Section 10.1)
2268 */
2269
4fa086b9 2270 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2271 case PIXEL_ENCODING_YCBCR422:
2272 pixel_encoding = 1;
2273 break;
2274
2275 case PIXEL_ENCODING_YCBCR444:
2276 pixel_encoding = 2;
2277 break;
2278 case PIXEL_ENCODING_YCBCR420:
2279 pixel_encoding = 3;
2280 break;
2281
2282 case PIXEL_ENCODING_RGB:
2283 default:
2284 pixel_encoding = 0;
2285 }
2286
2287 /* Y0_Y1_Y2 : The pixel encoding */
2288 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2289 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2290
2291 /* A0 = 1 Active Format Information valid */
e09b6473 2292 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2293
2294 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2295 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2296
e09b6473 2297 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2298
2299 /* S0, S1 : Underscan / Overscan */
2300 /* TODO: un-hardcode scan type */
2301 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2302 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2303
2304 /* C0, C1 : Colorimetry */
8fde5884 2305 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2306 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2307 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2308 else if (color_space == COLOR_SPACE_YCBCR601 ||
2309 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2310 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2311 else {
e09b6473 2312 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2313 }
534db198 2314 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2315 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2316 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2317 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2318 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2319 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2320 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2321 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2322 }
2323
4562236b 2324 /* TODO: un-hardcode aspect ratio */
4fa086b9 2325 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2326
2327 switch (aspect) {
2328 case ASPECT_RATIO_4_3:
2329 case ASPECT_RATIO_16_9:
e09b6473 2330 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2331 break;
2332
2333 case ASPECT_RATIO_NO_DATA:
2334 case ASPECT_RATIO_64_27:
2335 case ASPECT_RATIO_256_135:
2336 default:
e09b6473 2337 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2338 }
2339
2340 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2341 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2342
2343 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2344
4562236b 2345 cn0_cn1 = 0;
50e27654
ZF		 2346 cn0_cn1_value = 0;
2347
2348 itc = true;
2349 itc_value = 1;
2350
ceb3dbb4 2351 support = stream->content_support;
4562236b
HW		 2352
2353 if (itc) {
50e27654
ZF		 2354 if (!support.bits.valid_content_type) {
2355 cn0_cn1_value = 0;
2356 } else {
2357 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2358 if (support.bits.graphics_content == 1) {
2359 cn0_cn1_value = 0;
2360 }
2361 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2362 if (support.bits.photo_content == 1) {
2363 cn0_cn1_value = 1;
2364 } else {
2365 cn0_cn1_value = 0;
2366 itc_value = 0;
2367 }
2368 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2369 if (support.bits.cinema_content == 1) {
2370 cn0_cn1_value = 2;
2371 } else {
2372 cn0_cn1_value = 0;
2373 itc_value = 0;
2374 }
2375 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2376 if (support.bits.game_content == 1) {
2377 cn0_cn1_value = 3;
2378 } else {
2379 cn0_cn1_value = 0;
2380 itc_value = 0;
2381 }
2382 }
2383 }
e09b6473
AK		 2384 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2385 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2386 }
2387
2388 /* TODO : We should handle YCC quantization */
2389 /* but we do not have matrix calculation */
ceb3dbb4
JL		 2390 if (stream->qs_bit == 1 &&
2391 stream->qy_bit == 1) {
50e27654
ZF		 2392 if (color_space == COLOR_SPACE_SRGB ||
2393 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473 2394 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
993dca3e 2395 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654
ZF		 2396 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2397 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2398 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2399 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2400 } else {
e09b6473
AK		 2401 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2402 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2403 }
4562236b 2404 } else {
e09b6473
AK		 2405 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2406 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2407 }
50e27654 2408
15e17335 2409 ///VIC
4fa086b9 2410 format = stream->timing.timing_3d_format;
15e17335
CL		 2411 /*todo, add 3DStereo support*/
2412 if (format != TIMING_3D_FORMAT_NONE) {
2413 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2414 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2415 case 1:
2416 vic = 95;
2417 break;
2418 case 2:
2419 vic = 94;
2420 break;
2421 case 3:
2422 vic = 93;
2423 break;
2424 case 4:
2425 vic = 98;
2426 break;
2427 default:
2428 break;
2429 }
2430 }
efa02336 2431 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2432 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2433 if (vic >= 128)
2434 hdmi_info.bits.header.version = 3;
2435 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2436 * the Source shall use 20 AVI InfoFrame Version 4
2437 */
2438 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2439 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2440 hdmi_info.bits.header.version = 4;
2441 hdmi_info.bits.header.length = 14;
2442 }
4562236b
HW		 2443
2444 /* pixel repetition
2445 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2446 * repetition start from 1 */
e09b6473 2447 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2448
2449 /* Bar Info
2450 * barTop: Line Number of End of Top Bar.
2451 * barBottom: Line Number of Start of Bottom Bar.
2452 * barLeft: Pixel Number of End of Left Bar.
2453 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2454 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2455 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2456 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2457 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2458 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2459 - stream->timing.h_border_right + 1);
4562236b 2460
2f482c4f
CP		 2461 /* Additional Colorimetry Extension
2462 * Used in conduction with C0-C1 and EC0-EC2
2463 * 0 = DCI-P3 RGB (D65)
2464 * 1 = DCI-P3 RGB (theater)
2465 */
2466 hdmi_info.bits.ACE0_ACE3 = 0;
2467
4562236b 2468 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2469 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2470
efa02336 2471 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2472
efa02336 2473 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2474 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2475
2476 /* one byte complement */
2477 *check_sum = (uint8_t) (0x100 - *check_sum);
2478
2479 /* Store in hw_path_mode */
e09b6473
AK		 2480 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2481 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2482 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2483
e09b6473
AK		 2484 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2485 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2486
2487 info_packet->valid = true;
2488}
2489
6e4d6bee 2490static void set_vendor_info_packet(
e09b6473 2491 struct dc_info_packet *info_packet,
0971c40e 2492 struct dc_stream_state *stream)
4562236b 2493{
ecd0136b 2494 /* SPD info packet for FreeSync */
4562236b 2495
ecd0136b
HT		 2496 /* Check if Freesync is supported. Return if false. If true,
2497 * set the corresponding bit in the info packet
2498 */
2499 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2500 return;
2501
ecd0136b 2502 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2503}
2504
6e4d6bee 2505static void set_spd_info_packet(
e09b6473 2506 struct dc_info_packet *info_packet,
0971c40e 2507 struct dc_stream_state *stream)
4562236b
HW		 2508{
2509 /* SPD info packet for FreeSync */
2510
4562236b
HW		 2511 /* Check if Freesync is supported. Return if false. If true,
2512 * set the corresponding bit in the info packet
2513 */
98e6436d 2514 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2515 return;
2516
98e6436d 2517 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2518}
2519
1646a6fe 2520static void set_hdr_static_info_packet(
e09b6473 2521 struct dc_info_packet *info_packet,
0971c40e 2522 struct dc_stream_state *stream)
1646a6fe 2523{
0eeef690 2524 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2525
a10dc97a
KK		 2526 if (!stream->hdr_static_metadata.valid ||
2527 stream->use_dynamic_meta)
10bff005
YS		 2528 return;
2529
0eeef690 2530 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2531}
2532
6e4d6bee 2533static void set_vsc_info_packet(
e09b6473 2534 struct dc_info_packet *info_packet,
0971c40e 2535 struct dc_stream_state *stream)
4562236b 2536{
1336926f 2537 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2538 return;
2539
1336926f 2540 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2541}
2542
f36cc577 2543void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2544{
2545 int i, j;
2546
ab2541b6 2547 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2548 for (j = 0; j < context->stream_status[i].plane_count; j++)
2549 dc_plane_state_release(
2550 context->stream_status[i].plane_states[j]);
4562236b 2551
3be5262e 2552 context->stream_status[i].plane_count = 0;
4fa086b9 2553 dc_stream_release(context->streams[i]);
ab2541b6 2554 context->streams[i] = NULL;
4562236b
HW		 2555 }
2556}
2557
f36cc577 2558void dc_resource_state_copy_construct(
608ac7bb
JZ		 2559 const struct dc_state *src_ctx,
2560 struct dc_state *dst_ctx)
4562236b
HW		 2561{
2562 int i, j;
8ee5702a 2563 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2564
2565 *dst_ctx = *src_ctx;
2566
a2b8659d 2567 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2568 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2569
2570 if (cur_pipe->top_pipe)
2571 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2572
2573 if (cur_pipe->bottom_pipe)
2574 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL		 2575
2576 if (cur_pipe->next_odm_pipe)
2577 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2578
2579 if (cur_pipe->prev_odm_pipe)
2580 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW		 2581 }
2582
ab2541b6 2583 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2584 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2585 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2586 dc_plane_state_retain(
2587 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2588 }
9a3afbb3
AG		 2589
2590 /* context refcount should not be overridden */
8ee5702a 2591 dst_ctx->refcount = refcount;
9a3afbb3 2592
4562236b
HW		 2593}
2594
2595struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2596 struct resource_context *res_ctx,
2597 const struct resource_pool *pool)
4562236b
HW		 2598{
2599 int i;
2600
a2b8659d 2601 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2602 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2603 return pool->clock_sources[i];
4562236b
HW		 2604 }
2605
2606 return NULL;
2607}
2608
2609void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2610{
2611 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2612 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2613
2614 /* default all packets to invalid */
6e4d6bee
TC		 2615 info->avi.valid = false;
2616 info->gamut.valid = false;
2617 info->vendor.valid = false;
630e3573 2618 info->spd.valid = false;
6e4d6bee
TC		 2619 info->hdrsmd.valid = false;
2620 info->vsc.valid = false;
4562236b
HW		 2621
2622 signal = pipe_ctx->stream->signal;
2623
2624 /* HDMi and DP have different info packets*/
2625 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2626 set_avi_info_frame(&info->avi, pipe_ctx);
2627
2628 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2629
2630 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2631
56ef6ed9 2632 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2633
a33fa99d 2634 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2635 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2636
2637 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2638
56ef6ed9 2639 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2640 }
4562236b 2641
6e4d6bee 2642 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2643}
2644
2645enum dc_status resource_map_clock_resources(
fb3466a4 2646 const struct dc *dc,
608ac7bb 2647 struct dc_state *context,
1dc90497 2648 struct dc_stream_state *stream)
4562236b 2649{
4562236b 2650 /* acquire new resources */
1dc90497
AG		 2651 const struct resource_pool *pool = dc->res_pool;
2652 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2653 &context->res_ctx, stream);
ab2541b6 2654
1dc90497
AG		 2655 if (!pipe_ctx)
2656 return DC_ERROR_UNEXPECTED;
4562236b 2657
1dc90497
AG		 2658 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2659 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2660 pipe_ctx->clock_source = pool->dp_clock_source;
2661 else {
2662 pipe_ctx->clock_source = NULL;
4562236b 2663
1dc90497 2664 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2665 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2666 &context->res_ctx,
2667 pipe_ctx);
4562236b 2668
1dc90497
AG		 2669 if (pipe_ctx->clock_source == NULL)
2670 pipe_ctx->clock_source =
2671 dc_resource_find_first_free_pll(
2672 &context->res_ctx,
2673 pool);
2674 }
4562236b 2675
1dc90497
AG		 2676 if (pipe_ctx->clock_source == NULL)
2677 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2678
1dc90497
AG		 2679 resource_reference_clock_source(
2680 &context->res_ctx, pool,
2681 pipe_ctx->clock_source);
4562236b
HW		 2682
2683 return DC_OK;
2684}
2685
2686/*
2687 * Note: We need to disable output if clock sources change,
2688 * since bios does optimization and doesn't apply if changing
2689 * PHY when not already disabled.
2690 */
2691bool pipe_need_reprogram(
2692 struct pipe_ctx *pipe_ctx_old,
2693 struct pipe_ctx *pipe_ctx)
2694{
cfe4645e
DL		 2695 if (!pipe_ctx_old->stream)
2696 return false;
2697
4562236b
HW		 2698 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2699 return true;
2700
2701 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2702 return true;
2703
afaacef4 2704 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2705 return true;
2706
2707 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2708 && pipe_ctx_old->stream != pipe_ctx->stream)
2709 return true;
2710
8e9c4c8c 2711 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2712 return true;
2713
2714 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2715 return true;
2716
6b622181
JP		 2717 if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2718 return true;
4562236b 2719
1e7e86c4
ST		 2720 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2721 return true;
2722
1336926f
A		 2723 if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2724 return true;
2725
eed928dc
CL		 2726 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2727 false == pipe_ctx_old->stream->dpms_off)
2728 return true;
2729
4562236b
HW		 2730 return false;
2731}
529cad0f 2732
0971c40e 2733void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2734 struct bit_depth_reduction_params *fmt_bit_depth)
2735{
4fa086b9 2736 enum dc_dither_option option = stream->dither_option;
529cad0f 2737 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2738 stream->timing.pixel_encoding;
529cad0f
DW		 2739
2740 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2741
603767f9
TC		 2742 if (option == DITHER_OPTION_DEFAULT) {
2743 switch (stream->timing.display_color_depth) {
2744 case COLOR_DEPTH_666:
2745 option = DITHER_OPTION_SPATIAL6;
2746 break;
2747 case COLOR_DEPTH_888:
2748 option = DITHER_OPTION_SPATIAL8;
2749 break;
2750 case COLOR_DEPTH_101010:
2751 option = DITHER_OPTION_SPATIAL10;
2752 break;
2753 default:
2754 option = DITHER_OPTION_DISABLE;
2755 }
2756 }
2757
529cad0f
DW		 2758 if (option == DITHER_OPTION_DISABLE)
2759 return;
2760
2761 if (option == DITHER_OPTION_TRUN6) {
2762 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2763 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2764 } else if (option == DITHER_OPTION_TRUN8 ||
2765 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2766 option == DITHER_OPTION_TRUN8_FM6) {
2767 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2768 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2769 } else if (option == DITHER_OPTION_TRUN10 ||
2770 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2771 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2772 option == DITHER_OPTION_TRUN10_FM8 ||
2773 option == DITHER_OPTION_TRUN10_FM6 ||
2774 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2775 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2776 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2777 }
2778
2779 /* special case - Formatter can only reduce by 4 bits at most.
2780 * When reducing from 12 to 6 bits,
2781 * HW recommends we use trunc with round mode
2782 * (if we did nothing, trunc to 10 bits would be used)
2783 * note that any 12->10 bit reduction is ignored prior to DCE8,
2784 * as the input was 10 bits.
2785 */
2786 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2787 option == DITHER_OPTION_SPATIAL6 ||
2788 option == DITHER_OPTION_FM6) {
2789 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2790 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2791 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2792 }
2793
2794 /* spatial dither
2795 * note that spatial modes 1-3 are never used
2796 */
2797 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2798 option == DITHER_OPTION_SPATIAL6 ||
2799 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2800 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2801 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2802 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2803 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2804 fmt_bit_depth->flags.RGB_RANDOM =
2805 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2806 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2807 option == DITHER_OPTION_SPATIAL8 ||
2808 option == DITHER_OPTION_SPATIAL8_FM6 ||
2809 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2810 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2811 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2812 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2813 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2814 fmt_bit_depth->flags.RGB_RANDOM =
2815 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2816 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2817 option == DITHER_OPTION_SPATIAL10 ||
2818 option == DITHER_OPTION_SPATIAL10_FM8 ||
2819 option == DITHER_OPTION_SPATIAL10_FM6) {
2820 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2821 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2822 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2823 fmt_bit_depth->flags.RGB_RANDOM =
2824 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2825 }
2826
2827 if (option == DITHER_OPTION_SPATIAL6 ||
2828 option == DITHER_OPTION_SPATIAL8 ||
2829 option == DITHER_OPTION_SPATIAL10) {
2830 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2831 } else {
2832 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2833 }
2834
2835 //////////////////////
2836 //// temporal dither
2837 //////////////////////
2838 if (option == DITHER_OPTION_FM6 ||
2839 option == DITHER_OPTION_SPATIAL8_FM6 ||
2840 option == DITHER_OPTION_SPATIAL10_FM6 ||
2841 option == DITHER_OPTION_TRUN10_FM6 ||
2842 option == DITHER_OPTION_TRUN8_FM6 ||
2843 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2844 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2845 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2846 } else if (option == DITHER_OPTION_FM8 ||
2847 option == DITHER_OPTION_SPATIAL10_FM8 ||
2848 option == DITHER_OPTION_TRUN10_FM8) {
2849 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2850 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2851 } else if (option == DITHER_OPTION_FM10) {
2852 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2853 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2854 }
2855
2856 fmt_bit_depth->pixel_encoding = pixel_encoding;
2857}
9345d987 2858
62c933f9 2859enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2860{
ceb3dbb4 2861 struct dc_link *link = stream->link;
2b77dcc5 2862 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG		 2863 enum dc_status res = DC_OK;
2864
4fa086b9 2865 calculate_phy_pix_clks(stream);
9345d987 2866
4fa086b9 2867 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2868 res = DC_FAIL_CONTROLLER_VALIDATE;
2869
248cbed6 2870 if (res == DC_OK) {
9345d987 2871 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2872 link->link_enc, stream))
9345d987 2873 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2874 }
9345d987
AG		 2875
2876 /* TODO: validate audio ASIC caps, encoder */
2877
2878 if (res == DC_OK)
4fa086b9 2879 res = dc_link_validate_mode_timing(stream,
9345d987 2880 link,
4fa086b9 2881 &stream->timing);
9345d987 2882
62c933f9 2883 return res;
9345d987 2884}
792671d7 2885
62c933f9 2886enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2887{
62c933f9
YS		 2888 enum dc_status res = DC_OK;
2889
792671d7 2890 /* TODO For now validates pixel format only */
8e7095b9 2891 if (dc->res_pool->funcs->validate_plane)
62c933f9 2892 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2893
62c933f9 2894 return res;
792671d7 2895}
74eac5f3
SSC		 2896
2897unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2898{
2899 switch (format) {
2900 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2901 return 8;
2902 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2903 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2904 return 12;
2905 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2906 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2907 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2908 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2909 return 16;
2910 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2911 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2912 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2913 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2914 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2915 return 32;
2916 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2917 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2918 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2919 return 64;
2920 default:
2921 ASSERT_CRITICAL(false);
2922 return -1;
2923 }
2924}
3ab4cc65
CL		 2925static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
2926{
2927 if (modes) {
2928 if (modes->sample_rates.rate.RATE_192)
2929 return 192000;
2930 if (modes->sample_rates.rate.RATE_176_4)
2931 return 176400;
2932 if (modes->sample_rates.rate.RATE_96)
2933 return 96000;
2934 if (modes->sample_rates.rate.RATE_88_2)
2935 return 88200;
2936 if (modes->sample_rates.rate.RATE_48)
2937 return 48000;
2938 if (modes->sample_rates.rate.RATE_44_1)
2939 return 44100;
2940 if (modes->sample_rates.rate.RATE_32)
2941 return 32000;
2942 }
2943 /*original logic when no audio info*/
2944 return 441000;
2945}
2946
2947void get_audio_check(struct audio_info *aud_modes,
2948 struct audio_check *audio_chk)
2949{
2950 unsigned int i;
2951 unsigned int max_sample_rate = 0;
2952
2953 if (aud_modes) {
2954 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
2955
2956 audio_chk->max_audiosample_rate = 0;
2957 for (i = 0; i < aud_modes->mode_count; i++) {
2958 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
2959 if (audio_chk->max_audiosample_rate < max_sample_rate)
2960 audio_chk->max_audiosample_rate = max_sample_rate;
2961 /*dts takes the same as type 2: AP = 0.25*/
2962 }
2963 /*check which one take more bandwidth*/
2964 if (audio_chk->max_audiosample_rate > 192000)
2965 audio_chk->audio_packet_type = 0x9;/*AP =1*/
2966 audio_chk->acat = 0;/*not support*/
2967 }
2968}
2969
Ubuntu Jammy Linux kernel mirror