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drm: fix doc warnings in drm_atomic.h
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
4fc4dca8
SR		 25
26#include <linux/slab.h>
27
4562236b
HW		 28#include "dm_services.h"
29
30#include "resource.h"
31#include "include/irq_service_interface.h"
32#include "link_encoder.h"
33#include "stream_encoder.h"
34#include "opp.h"
35#include "timing_generator.h"
36#include "transform.h"
33d7598d
JL		 37#include "dccg.h"
38#include "dchubbub.h"
d94585a0 39#include "dpp.h"
5ac3d3c9 40#include "core_types.h"
4562236b 41#include "set_mode_types.h"
4562236b 42#include "virtual/virtual_stream_encoder.h"
3b94a400 43#include "dpcd_defs.h"
4562236b 44
683b5950
MR		 45#if defined(CONFIG_DRM_AMD_DC_SI)
46#include "dce60/dce60_resource.h"
47#endif
4562236b
HW		 48#include "dce80/dce80_resource.h"
49#include "dce100/dce100_resource.h"
50#include "dce110/dce110_resource.h"
51#include "dce112/dce112_resource.h"
cf2156e2 52#include "dce120/dce120_resource.h"
b86a1aa3 53#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 54#include "dcn10/dcn10_resource.h"
7ed4e635 55#include "dcn20/dcn20_resource.h"
e22ece54 56#include "dcn21/dcn21_resource.h"
20f2ffe5
AD		 57#include "dcn30/dcn30_resource.h"
58#include "dcn301/dcn301_resource.h"
59#include "dcn302/dcn302_resource.h"
cd6d421e 60#include "dcn303/dcn303_resource.h"
36d26912 61#endif
5d4b05dd
BL		 62
63#define DC_LOGGER_INIT(logger)
64
4562236b
HW		 65enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
66{
67 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
68 switch (asic_id.chip_family) {
69
683b5950
MR		 70#if defined(CONFIG_DRM_AMD_DC_SI)
71 case FAMILY_SI:
72 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
74 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
34b0c779 75 dc_version = DCE_VERSION_6_0;
683b5950
MR		 76 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
77 dc_version = DCE_VERSION_6_4;
78 else
79 dc_version = DCE_VERSION_6_1;
80 break;
81#endif
4562236b 82 case FAMILY_CI:
4562236b
HW		 83 dc_version = DCE_VERSION_8_0;
84 break;
ebfdf0d0
AD		 85 case FAMILY_KV:
86 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
88 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
89 dc_version = DCE_VERSION_8_3;
90 else
91 dc_version = DCE_VERSION_8_1;
92 break;
4562236b
HW		 93 case FAMILY_CZ:
94 dc_version = DCE_VERSION_11_0;
95 break;
96
97 case FAMILY_VI:
98 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
99 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
100 dc_version = DCE_VERSION_10_0;
101 break;
102 }
103 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 104 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
105 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 106 dc_version = DCE_VERSION_11_2;
107 }
0c75d5ac
JFZ		 108 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
109 dc_version = DCE_VERSION_11_22;
4562236b 110 break;
2c8ad2d5 111 case FAMILY_AI:
b8b6ce89
LL		 112 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
113 dc_version = DCE_VERSION_12_1;
114 else
115 dc_version = DCE_VERSION_12_0;
2c8ad2d5 116 break;
b86a1aa3 117#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 118 case FAMILY_RV:
119 dc_version = DCN_VERSION_1_0;
0e3d73f1
BL		 120 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
121 dc_version = DCN_VERSION_1_01;
e22ece54
BL		 122 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
123 dc_version = DCN_VERSION_2_1;
9ba93114
RL		 124 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
125 dc_version = DCN_VERSION_2_1;
ff5ef992 126 break;
7ed4e635 127
7ed4e635
HW		 128 case FAMILY_NV:
129 dc_version = DCN_VERSION_2_0;
5dba4991
BL		 130 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
131 dc_version = DCN_VERSION_3_0;
36d26912
BL		 132 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
133 dc_version = DCN_VERSION_3_02;
cd6d421e
AP		 134 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
135 dc_version = DCN_VERSION_3_03;
7ed4e635 136 break;
3a83e4e6 137
3a83e4e6
RL		 138 case FAMILY_VGH:
139 dc_version = DCN_VERSION_3_01;
140 break;
141#endif
4562236b
HW		 142 default:
143 dc_version = DCE_VERSION_UNKNOWN;
144 break;
145 }
146 return dc_version;
147}
148
d9673c92
HW		 149struct resource_pool *dc_create_resource_pool(struct dc *dc,
150 const struct dc_init_data *init_data,
151 enum dce_version dc_version)
4562236b 152{
5ac3d3c9 153 struct resource_pool *res_pool = NULL;
4562236b
HW		 154
155 switch (dc_version) {
683b5950
MR		 156#if defined(CONFIG_DRM_AMD_DC_SI)
157 case DCE_VERSION_6_0:
158 res_pool = dce60_create_resource_pool(
159 init_data->num_virtual_links, dc);
160 break;
161 case DCE_VERSION_6_1:
162 res_pool = dce61_create_resource_pool(
163 init_data->num_virtual_links, dc);
164 break;
165 case DCE_VERSION_6_4:
166 res_pool = dce64_create_resource_pool(
167 init_data->num_virtual_links, dc);
168 break;
169#endif
4562236b 170 case DCE_VERSION_8_0:
7992a629 171 res_pool = dce80_create_resource_pool(
d9673c92 172 init_data->num_virtual_links, dc);
7992a629 173 break;
ebfdf0d0 174 case DCE_VERSION_8_1:
7992a629 175 res_pool = dce81_create_resource_pool(
d9673c92 176 init_data->num_virtual_links, dc);
7992a629 177 break;
ebfdf0d0 178 case DCE_VERSION_8_3:
7992a629 179 res_pool = dce83_create_resource_pool(
d9673c92 180 init_data->num_virtual_links, dc);
5ac3d3c9 181 break;
4562236b 182 case DCE_VERSION_10_0:
5ac3d3c9 183 res_pool = dce100_create_resource_pool(
d9673c92 184 init_data->num_virtual_links, dc);
5ac3d3c9 185 break;
4562236b 186 case DCE_VERSION_11_0:
5ac3d3c9 187 res_pool = dce110_create_resource_pool(
d9673c92
HW		 188 init_data->num_virtual_links, dc,
189 init_data->asic_id);
5ac3d3c9 190 break;
4562236b 191 case DCE_VERSION_11_2:
0c75d5ac 192 case DCE_VERSION_11_22:
5ac3d3c9 193 res_pool = dce112_create_resource_pool(
d9673c92 194 init_data->num_virtual_links, dc);
5ac3d3c9 195 break;
2c8ad2d5 196 case DCE_VERSION_12_0:
b8b6ce89 197 case DCE_VERSION_12_1:
2c8ad2d5 198 res_pool = dce120_create_resource_pool(
d9673c92 199 init_data->num_virtual_links, dc);
2c8ad2d5 200 break;
ff5ef992 201
b86a1aa3 202#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 203 case DCN_VERSION_1_0:
0e3d73f1 204 case DCN_VERSION_1_01:
d9673c92 205 res_pool = dcn10_create_resource_pool(init_data, dc);
ff5ef992 206 break;
7ed4e635
HW		 207 case DCN_VERSION_2_0:
208 res_pool = dcn20_create_resource_pool(init_data, dc);
209 break;
e22ece54
BL		 210 case DCN_VERSION_2_1:
211 res_pool = dcn21_create_resource_pool(init_data, dc);
212 break;
5dba4991
BL		 213 case DCN_VERSION_3_0:
214 res_pool = dcn30_create_resource_pool(init_data, dc);
215 break;
3a83e4e6
RL		 216 case DCN_VERSION_3_01:
217 res_pool = dcn301_create_resource_pool(init_data, dc);
218 break;
36d26912
BL		 219 case DCN_VERSION_3_02:
220 res_pool = dcn302_create_resource_pool(init_data, dc);
221 break;
cd6d421e
AP		 222 case DCN_VERSION_3_03:
223 res_pool = dcn303_create_resource_pool(init_data, dc);
224 break;
3a83e4e6 225#endif
4562236b
HW		 226 default:
227 break;
228 }
f49cfa27 229
5ac3d3c9 230 if (res_pool != NULL) {
9adc8050 231 if (dc->ctx->dc_bios->fw_info_valid) {
41a5a2a8 232 res_pool->ref_clocks.xtalin_clock_inKhz =
9adc8050 233 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
41a5a2a8 234 /* initialize with firmware data first, no all
235 * ASIC have DCCG SW component. FPGA or
236 * simulation need initialization of
237 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
238 * with xtalin_clock_inKhz
239 */
240 res_pool->ref_clocks.dccg_ref_clock_inKhz =
241 res_pool->ref_clocks.xtalin_clock_inKhz;
242 res_pool->ref_clocks.dchub_ref_clock_inKhz =
243 res_pool->ref_clocks.xtalin_clock_inKhz;
244 } else
245 ASSERT_CRITICAL(false);
5ac3d3c9 246 }
4562236b 247
5ac3d3c9 248 return res_pool;
4562236b
HW		 249}
250
fb3466a4 251void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 252{
253 if (dc) {
254 if (dc->res_pool)
255 dc->res_pool->funcs->destroy(&dc->res_pool);
256
d029810c 257 kfree(dc->hwseq);
4562236b
HW		 258 }
259}
260
261static void update_num_audio(
262 const struct resource_straps *straps,
263 unsigned int *num_audio,
264 struct audio_support *aud_support)
265{
b8e9eb72
CL		 266 aud_support->dp_audio = true;
267 aud_support->hdmi_audio_native = false;
268 aud_support->hdmi_audio_on_dongle = false;
269
4562236b 270 if (straps->hdmi_disable == 0) {
4562236b
HW		 271 if (straps->dc_pinstraps_audio & 0x2) {
272 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 273 aud_support->hdmi_audio_native = true;
4562236b
HW		 274 }
275 }
276
277 switch (straps->audio_stream_number) {
278 case 0: /* multi streams supported */
279 break;
280 case 1: /* multi streams not supported */
281 *num_audio = 1;
282 break;
283 default:
284 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 285 }
4562236b
HW		 286}
287
288bool resource_construct(
289 unsigned int num_virtual_links,
fb3466a4 290 struct dc *dc,
4562236b
HW		 291 struct resource_pool *pool,
292 const struct resource_create_funcs *create_funcs)
293{
294 struct dc_context *ctx = dc->ctx;
295 const struct resource_caps *caps = pool->res_cap;
296 int i;
297 unsigned int num_audio = caps->num_audio;
298 struct resource_straps straps = {0};
299
300 if (create_funcs->read_dce_straps)
301 create_funcs->read_dce_straps(dc->ctx, &straps);
302
303 pool->audio_count = 0;
304 if (create_funcs->create_audio) {
305 /* find the total number of streams available via the
306 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
307 * registers (one for each pin) starting from pin 1
308 * up to the max number of audio pins.
309 * We stop on the first pin where
310 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
311 */
312 update_num_audio(&straps, &num_audio, &pool->audio_support);
5feb9f07 313 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 314 struct audio *aud = create_funcs->create_audio(ctx, i);
315
316 if (aud == NULL) {
317 DC_ERR("DC: failed to create audio!\n");
318 return false;
319 }
4562236b
HW		 320 if (!aud->funcs->endpoint_valid(aud)) {
321 aud->funcs->destroy(&aud);
322 break;
323 }
4562236b
HW		 324 pool->audios[i] = aud;
325 pool->audio_count++;
326 }
327 }
328
329 pool->stream_enc_count = 0;
330 if (create_funcs->create_stream_encoder) {
331 for (i = 0; i < caps->num_stream_encoder; i++) {
332 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
333 if (pool->stream_enc[i] == NULL)
334 DC_ERR("DC: failed to create stream_encoder!\n");
335 pool->stream_enc_count++;
336 }
337 }
929c3aaa 338
20f2ffe5 339#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 340 for (i = 0; i < caps->num_mpc_3dlut; i++) {
341 pool->mpc_lut[i] = dc_create_3dlut_func();
342 if (pool->mpc_lut[i] == NULL)
343 DC_ERR("DC: failed to create MPC 3dlut!\n");
344 pool->mpc_shaper[i] = dc_create_transfer_func();
345 if (pool->mpc_shaper[i] == NULL)
346 DC_ERR("DC: failed to create MPC shaper!\n");
347 }
348#endif
4176664b
CL		 349 dc->caps.dynamic_audio = false;
350 if (pool->audio_count < pool->stream_enc_count) {
351 dc->caps.dynamic_audio = true;
352 }
4562236b
HW		 353 for (i = 0; i < num_virtual_links; i++) {
354 pool->stream_enc[pool->stream_enc_count] =
355 virtual_stream_encoder_create(
356 ctx, ctx->dc_bios);
357 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
358 DC_ERR("DC: failed to create stream_encoder!\n");
359 return false;
360 }
361 pool->stream_enc_count++;
362 }
363
364 dc->hwseq = create_funcs->create_hwseq(ctx);
365
366 return true;
367}
ad8960a6
ML		 368static int find_matching_clock_source(
369 const struct resource_pool *pool,
370 struct clock_source *clock_source)
371{
4562236b 372
ad8960a6
ML		 373 int i;
374
375 for (i = 0; i < pool->clk_src_count; i++) {
376 if (pool->clock_sources[i] == clock_source)
377 return i;
378 }
379 return -1;
380}
4562236b 381
21e67d4d 382void resource_unreference_clock_source(
4562236b 383 struct resource_context *res_ctx,
a2b8659d 384 const struct resource_pool *pool,
4a629536 385 struct clock_source *clock_source)
4562236b 386{
ad8960a6 387 int i = find_matching_clock_source(pool, clock_source);
4562236b 388
ad8960a6 389 if (i > -1)
4562236b
HW		 390 res_ctx->clock_source_ref_count[i]--;
391
21e67d4d 392 if (pool->dp_clock_source == clock_source)
4562236b 393 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 394}
395
396void resource_reference_clock_source(
397 struct resource_context *res_ctx,
a2b8659d 398 const struct resource_pool *pool,
4562236b
HW		 399 struct clock_source *clock_source)
400{
ad8960a6 401 int i = find_matching_clock_source(pool, clock_source);
4562236b 402
ad8960a6 403 if (i > -1)
4562236b 404 res_ctx->clock_source_ref_count[i]++;
4562236b 405
a2b8659d 406 if (pool->dp_clock_source == clock_source)
4562236b
HW		 407 res_ctx->dp_clock_source_ref_count++;
408}
409
ad8960a6
ML		 410int resource_get_clock_source_reference(
411 struct resource_context *res_ctx,
412 const struct resource_pool *pool,
413 struct clock_source *clock_source)
414{
415 int i = find_matching_clock_source(pool, clock_source);
416
417 if (i > -1)
418 return res_ctx->clock_source_ref_count[i];
419
420 if (pool->dp_clock_source == clock_source)
421 return res_ctx->dp_clock_source_ref_count;
422
423 return -1;
424}
425
77a2b726
VS		 426bool resource_are_vblanks_synchronizable(
427 struct dc_stream_state *stream1,
428 struct dc_stream_state *stream2)
429{
430 uint32_t base60_refresh_rates[] = {10, 20, 5};
431 uint8_t i;
432 uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]);
783bf403 433 uint64_t frame_time_diff;
77a2b726
VS		 434
435 if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
436 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
437 dc_is_dp_signal(stream1->signal) &&
438 dc_is_dp_signal(stream2->signal) &&
439 false == stream1->has_non_synchronizable_pclk &&
440 false == stream2->has_non_synchronizable_pclk &&
441 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
442 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
443 /* disable refresh rates higher than 60Hz for now */
444 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
445 stream1->timing.v_total > 60)
446 return false;
447 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
448 stream2->timing.v_total > 60)
449 return false;
783bf403 450 frame_time_diff = (uint64_t)10000 *
77a2b726
VS		 451 stream1->timing.h_total *
452 stream1->timing.v_total *
783bf403
VS		 453 stream2->timing.pix_clk_100hz;
454 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
455 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
456 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
77a2b726 457 for (i = 0; i < rr_count; i++) {
783bf403 458 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
77a2b726
VS		 459
460 if (diff < 0)
461 diff = -diff;
462 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
463 return true;
464 }
465 }
466 return false;
467}
468
4562236b 469bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 470 struct dc_stream_state *stream1,
471 struct dc_stream_state *stream2)
4562236b 472{
4fa086b9 473 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 474 return false;
475
4fa086b9 476 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 477 return false;
478
4fa086b9
LSL		 479 if (stream1->timing.h_addressable
480 != stream2->timing.h_addressable)
4562236b
HW		 481 return false;
482
4fa086b9
LSL		 483 if (stream1->timing.v_addressable
484 != stream2->timing.v_addressable)
4562236b
HW		 485 return false;
486
8582aea2
DG		 487 if (stream1->timing.v_front_porch
488 != stream2->timing.v_front_porch)
489 return false;
490
380604e2
KC		 491 if (stream1->timing.pix_clk_100hz
492 != stream2->timing.pix_clk_100hz)
4562236b
HW		 493 return false;
494
3e27e10e
ML		 495 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
496 return false;
497
4562236b 498 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 499 && (!dc_is_dp_signal(stream1->signal)
500 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 501 return false;
502
d77f778e
CL		 503 if (stream1->view_format != stream2->view_format)
504 return false;
505
0460f9ab
JL		 506 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
507 return false;
508
4562236b
HW		 509 return true;
510}
3e27e10e
ML		 511static bool is_dp_and_hdmi_sharable(
512 struct dc_stream_state *stream1,
513 struct dc_stream_state *stream2)
514{
515 if (stream1->ctx->dc->caps.disable_dp_clk_share)
516 return false;
517
518 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
d77f778e 519 stream2->clamping.c_depth != COLOR_DEPTH_888)
43fbbe89 520 return false;
3e27e10e
ML		 521
522 return true;
523
524}
4562236b
HW		 525
526static bool is_sharable_clk_src(
527 const struct pipe_ctx *pipe_with_clk_src,
528 const struct pipe_ctx *pipe)
529{
530 if (pipe_with_clk_src->clock_source == NULL)
531 return false;
532
533 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
534 return false;
535
3e27e10e
ML		 536 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
537 (dc_is_dp_signal(pipe->stream->signal) &&
538 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
539 pipe->stream)))
4562236b
HW		 540 return false;
541
542 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
fc69009e 543 && dc_is_dual_link_signal(pipe->stream->signal))
4562236b
HW		 544 return false;
545
546 if (dc_is_hdmi_signal(pipe->stream->signal)
fc69009e 547 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
4562236b
HW		 548 return false;
549
550 if (!resource_are_streams_timing_synchronizable(
551 pipe_with_clk_src->stream, pipe->stream))
552 return false;
553
554 return true;
555}
556
557struct clock_source *resource_find_used_clk_src_for_sharing(
558 struct resource_context *res_ctx,
559 struct pipe_ctx *pipe_ctx)
560{
561 int i;
562
563 for (i = 0; i < MAX_PIPES; i++) {
564 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
565 return res_ctx->pipe_ctx[i].clock_source;
566 }
567
568 return NULL;
569}
570
571static enum pixel_format convert_pixel_format_to_dalsurface(
572 enum surface_pixel_format surface_pixel_format)
573{
574 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
575
576 switch (surface_pixel_format) {
577 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
578 dal_pixel_format = PIXEL_FORMAT_INDEX8;
579 break;
580 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
581 dal_pixel_format = PIXEL_FORMAT_RGB565;
582 break;
583 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
584 dal_pixel_format = PIXEL_FORMAT_RGB565;
585 break;
586 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
587 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
588 break;
8693049a 589 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 590 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
591 break;
592 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
593 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
594 break;
595 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
596 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
597 break;
598 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
599 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
600 break;
601 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
602 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
603 dal_pixel_format = PIXEL_FORMAT_FP16;
604 break;
605 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 606 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 607 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 608 break;
ffbcd19a
VP		 609 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
610 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 611 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 612 break;
4562236b 613 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
050cd3d6 614 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
4562236b
HW		 615 default:
616 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
617 break;
618 }
619 return dal_pixel_format;
620}
621
9b6067c0
DL		 622static inline void get_vp_scan_direction(
623 enum dc_rotation_angle rotation,
624 bool horizontal_mirror,
625 bool *orthogonal_rotation,
626 bool *flip_vert_scan_dir,
627 bool *flip_horz_scan_dir)
4562236b 628{
9b6067c0
DL		 629 *orthogonal_rotation = false;
630 *flip_vert_scan_dir = false;
631 *flip_horz_scan_dir = false;
632 if (rotation == ROTATION_ANGLE_180) {
633 *flip_vert_scan_dir = true;
634 *flip_horz_scan_dir = true;
635 } else if (rotation == ROTATION_ANGLE_90) {
636 *orthogonal_rotation = true;
637 *flip_horz_scan_dir = true;
638 } else if (rotation == ROTATION_ANGLE_270) {
639 *orthogonal_rotation = true;
640 *flip_vert_scan_dir = true;
641 }
642
643 if (horizontal_mirror)
644 *flip_horz_scan_dir = !*flip_horz_scan_dir;
4562236b
HW		 645}
646
570bc18c
DL		 647int get_num_mpc_splits(struct pipe_ctx *pipe)
648{
649 int mpc_split_count = 0;
650 struct pipe_ctx *other_pipe = pipe->bottom_pipe;
651
652 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
653 mpc_split_count++;
654 other_pipe = other_pipe->bottom_pipe;
655 }
656 other_pipe = pipe->top_pipe;
657 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
658 mpc_split_count++;
659 other_pipe = other_pipe->top_pipe;
660 }
661
662 return mpc_split_count;
663}
664
228a10d4
AD		 665int get_num_odm_splits(struct pipe_ctx *pipe)
666{
667 int odm_split_count = 0;
668 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
669 while (next_pipe) {
670 odm_split_count++;
671 next_pipe = next_pipe->next_odm_pipe;
672 }
673 pipe = pipe->prev_odm_pipe;
674 while (pipe) {
675 odm_split_count++;
676 pipe = pipe->prev_odm_pipe;
677 }
678 return odm_split_count;
679}
680
5bf24270
DL		 681static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
682{
683 *split_count = get_num_odm_splits(pipe_ctx);
684 *split_idx = 0;
685 if (*split_count == 0) {
686 /*Check for mpc split*/
687 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
688
570bc18c 689 *split_count = get_num_mpc_splits(pipe_ctx);
5bf24270
DL		 690 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
691 (*split_idx)++;
5bf24270
DL		 692 split_pipe = split_pipe->top_pipe;
693 }
5bf24270
DL		 694 } else {
695 /*Get odm split index*/
696 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
697
698 while (split_pipe) {
699 (*split_idx)++;
700 split_pipe = split_pipe->prev_odm_pipe;
701 }
702 }
703}
704
6566cae7
DL		 705/*
706 * This is a preliminary vp size calculation to allow us to check taps support.
707 * The result is completely overridden afterwards.
708 */
709static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
4562236b 710{
6702a9ac 711 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
9b6067c0 712
6566cae7
DL		 713 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width));
714 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height));
715 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width));
716 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height));
717 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
718 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
719 swap(data->viewport.width, data->viewport.height);
720 swap(data->viewport_c.width, data->viewport_c.height);
9b6067c0 721 }
4562236b
HW		 722}
723
9b6067c0 724static void calculate_recout(struct pipe_ctx *pipe_ctx)
4562236b 725{
3be5262e 726 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 727 const struct dc_stream_state *stream = pipe_ctx->stream;
5bf24270 728 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 729 struct rect surf_clip = plane_state->clip_rect;
6566cae7
DL		 730 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
731 int split_count, split_idx;
5bf24270
DL		 732
733 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
6566cae7
DL		 734 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
735 split_idx = 0;
5bf24270 736
05e3d830
WC		 737 /*
738 * Only the leftmost ODM pipe should be offset by a nonzero distance
739 */
6566cae7 740 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
05e3d830 741 data->recout.x = stream->dst.x;
25b31581
WC		 742 if (stream->src.x < surf_clip.x)
743 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
4fa086b9 744 / stream->src.width;
25b31581
WC		 745 } else
746 data->recout.x = 0;
747
84aef2ab
DL		 748 if (stream->src.x > surf_clip.x)
749 surf_clip.width -= stream->src.x - surf_clip.x;
5bf24270
DL		 750 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
751 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
752 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
4562236b 753
5bf24270 754 data->recout.y = stream->dst.y;
4fa086b9 755 if (stream->src.y < surf_clip.y)
5bf24270 756 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
4fa086b9 757 / stream->src.height;
84aef2ab
DL		 758 else if (stream->src.y > surf_clip.y)
759 surf_clip.height -= stream->src.y - surf_clip.y;
4562236b 760
5bf24270
DL		 761 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
762 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
763 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
b2d0a103 764
6566cae7
DL		 765 /* Handle h & v split */
766 if (split_tb) {
767 ASSERT(data->recout.height % 2 == 0);
5bf24270 768 data->recout.height /= 2;
6566cae7 769 } else if (split_count) {
5bf24270 770 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
6566cae7
DL		 771 /* extra pixels in the division remainder need to go to pipes after
772 * the extra pixel index minus one(epimo) defined here as:
773 */
774 int epimo = split_count - data->recout.width % (split_count + 1);
775
5bf24270
DL		 776 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
777 if (split_idx > epimo)
778 data->recout.x += split_idx - epimo - 1;
6566cae7
DL		 779 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0);
780 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
781 } else {
782 /* odm */
783 if (split_idx == split_count) {
784 /* rightmost pipe is the remainder recout */
785 data->recout.width -= data->h_active * split_count - data->recout.x;
786 data->recout.x = 0;
787 } else
788 data->recout.width = data->h_active - data->recout.x;
5bf24270 789 }
5bf24270 790 }
4562236b
HW		 791}
792
b2d0a103 793static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 794{
3be5262e 795 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 796 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 797 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 798 const int in_w = stream->src.width;
799 const int in_h = stream->src.height;
800 const int out_w = stream->dst.width;
801 const int out_h = stream->dst.height;
4562236b 802
9b6067c0 803 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
3be5262e
HW		 804 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
805 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
9b6067c0 806 swap(surf_src.height, surf_src.width);
86006a7f 807
eb0e5154 808 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
86006a7f 809 surf_src.width,
3be5262e 810 plane_state->dst_rect.width);
eb0e5154 811 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
86006a7f 812 surf_src.height,
3be5262e 813 plane_state->dst_rect.height);
4562236b 814
4fa086b9 815 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 816 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 817 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 818 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 819
6702a9ac
HW		 820 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
821 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
822 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
823 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 824
6702a9ac
HW		 825 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
826 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 827
6702a9ac
HW		 828 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
829 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
830 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
831 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b 832 }
0002d3ac
DL		 833 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
834 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
835 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
836 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
837 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
838 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
839 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
840 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
4562236b
HW		 841}
842
6566cae7
DL		 843
844/*
845 * We completely calculate vp offset, size and inits here based entirely on scaling
846 * ratios and recout for pixel perfect pipe combine.
847 */
848static void calculate_init_and_vp(
9b6067c0 849 bool flip_scan_dir,
6566cae7
DL		 850 int recout_offset_within_recout_full,
851 int recout_size,
9b6067c0
DL		 852 int src_size,
853 int taps,
854 struct fixed31_32 ratio,
855 struct fixed31_32 *init,
856 int *vp_offset,
857 int *vp_size)
b2d0a103 858{
6566cae7
DL		 859 struct fixed31_32 temp;
860 int int_part;
b2d0a103 861
6566cae7
DL		 862 /*
863 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
864 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
865 * All following calculations are based on this logic.
866 *
867 * Init calculated according to formula:
868 * init = (scaling_ratio + number_of_taps + 1) / 2
869 * init_bot = init + scaling_ratio
870 * to get pixel perfect combine add the fraction from calculating vp offset
871 */
872 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
873 *vp_offset = dc_fixpt_floor(temp);
874 temp.value &= 0xffffffff;
875 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
876 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
877 /*
878 * If viewport has non 0 offset and there are more taps than covered by init then
879 * we should decrease the offset and increase init so we are never sampling
880 * outside of viewport.
881 */
882 int_part = dc_fixpt_floor(*init);
883 if (int_part < taps) {
884 int_part = taps - int_part;
885 if (int_part > *vp_offset)
886 int_part = *vp_offset;
887 *vp_offset -= int_part;
888 *init = dc_fixpt_add_int(*init, int_part);
b2d0a103 889 }
6566cae7
DL		 890 /*
891 * If taps are sampling outside of viewport at end of recout and there are more pixels
892 * available in the surface we should increase the viewport size, regardless set vp to
893 * only what is used.
894 */
895 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
896 *vp_size = dc_fixpt_floor(temp);
897 if (*vp_size + *vp_offset > src_size)
898 *vp_size = src_size - *vp_offset;
899
900 /* We did all the math assuming we are scanning same direction as display does,
901 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
902 * is flipped we simply need to calculate offset from the other side of plane.
903 * Note that outside of viewport all scaling hardware works in recout space.
904 */
905 if (flip_scan_dir)
906 *vp_offset = src_size - *vp_offset - *vp_size;
9b6067c0 907}
9a08f51f 908
6566cae7 909static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
9b6067c0
DL		 910{
911 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
912 const struct dc_stream_state *stream = pipe_ctx->stream;
913 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
6566cae7 914 struct rect src = plane_state->src_rect;
9b6067c0 915 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
6566cae7
DL		 916 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
917 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y;
9b6067c0 918 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
6566cae7
DL		 919
920 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
921 /*
922 * recout full is what the recout would have been if we didnt clip
923 * the source plane at all. We only care about left(ro_lb) and top(ro_tb)
924 * offsets of recout within recout full because those are the directions
925 * we scan from and therefore the only ones that affect inits.
926 */
927 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
928 * stream->dst.width / stream->src.width;
929 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
930 * stream->dst.height / stream->src.height;
931 if (pipe_ctx->prev_odm_pipe && split_idx)
932 ro_lb = data->h_active * split_idx - recout_full_x;
933 else
934 ro_lb = data->recout.x - recout_full_x;
935 ro_tb = data->recout.y - recout_full_y;
936 ASSERT(ro_lb >= 0 && ro_tb >= 0);
9a08f51f 937
9b6067c0 938 /*
6566cae7 939 * Work in recout rotation since that requires less transformations
9b6067c0
DL		 940 */
941 get_vp_scan_direction(
942 plane_state->rotation,
943 plane_state->horizontal_mirror,
944 &orthogonal_rotation,
945 &flip_vert_scan_dir,
946 &flip_horz_scan_dir);
947
9b6067c0 948 if (orthogonal_rotation) {
9b6067c0 949 swap(src.width, src.height);
6566cae7 950 swap(flip_vert_scan_dir, flip_horz_scan_dir);
9b6067c0 951 }
9a08f51f 952
6566cae7 953 calculate_init_and_vp(
9b6067c0 954 flip_horz_scan_dir,
6566cae7
DL		 955 ro_lb,
956 data->recout.width,
957 src.width,
958 data->taps.h_taps,
959 data->ratios.horz,
960 &data->inits.h,
9b6067c0
DL		 961 &data->viewport.x,
962 &data->viewport.width);
6566cae7 963 calculate_init_and_vp(
9b6067c0 964 flip_horz_scan_dir,
6566cae7
DL		 965 ro_lb,
966 data->recout.width,
967 src.width / vpc_div,
968 data->taps.h_taps_c,
969 data->ratios.horz_c,
970 &data->inits.h_c,
9b6067c0
DL		 971 &data->viewport_c.x,
972 &data->viewport_c.width);
6566cae7 973 calculate_init_and_vp(
9b6067c0 974 flip_vert_scan_dir,
6566cae7
DL		 975 ro_tb,
976 data->recout.height,
977 src.height,
978 data->taps.v_taps,
979 data->ratios.vert,
980 &data->inits.v,
9b6067c0
DL		 981 &data->viewport.y,
982 &data->viewport.height);
6566cae7 983 calculate_init_and_vp(
9b6067c0 984 flip_vert_scan_dir,
6566cae7
DL		 985 ro_tb,
986 data->recout.height,
987 src.height / vpc_div,
988 data->taps.v_taps_c,
989 data->ratios.vert_c,
990 &data->inits.v_c,
9b6067c0
DL		 991 &data->viewport_c.y,
992 &data->viewport_c.height);
6566cae7
DL		 993 if (orthogonal_rotation) {
994 swap(data->viewport.x, data->viewport.y);
995 swap(data->viewport.width, data->viewport.height);
996 swap(data->viewport_c.x, data->viewport_c.y);
997 swap(data->viewport_c.width, data->viewport_c.height);
89d07b66 998 }
6566cae7
DL		 999 data->viewport.x += src.x;
1000 data->viewport.y += src.y;
1001 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1002 data->viewport_c.x += src.x / vpc_div;
1003 data->viewport_c.y += src.y / vpc_div;
89d07b66
ST		 1004}
1005
b2d0a103 1006bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 1007{
3be5262e 1008 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 1009 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103 1010 bool res = false;
5d4b05dd 1011 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
6566cae7 1012
6702a9ac 1013 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 1014 pipe_ctx->plane_state->format);
b2d0a103 1015
6566cae7
DL		 1016 /* Timing borders are part of vactive that we are also supposed to skip in addition
1017 * to any stream dst offset. Since dm logic assumes dst is in addressable
1018 * space we need to add the the left and top borders to dst offsets temporarily.
1019 * TODO: fix in DM, stream dst is supposed to be in vactive
1020 */
1021 pipe_ctx->stream->dst.x += timing->h_border_left;
1022 pipe_ctx->stream->dst.y += timing->v_border_top;
4562236b 1023
6566cae7
DL		 1024 /* Calculate H and V active size */
1025 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1026 timing->h_border_left + timing->h_border_right;
1027 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1028 timing->v_border_top + timing->v_border_bottom;
1029 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1030 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
4562236b 1031
6566cae7 1032 /* depends on h_active */
9b6067c0 1033 calculate_recout(pipe_ctx);
6566cae7
DL		 1034 /* depends on pixel format */
1035 calculate_scaling_ratios(pipe_ctx);
1036 /* depends on scaling ratios and recout, does not calculate offset yet */
1037 calculate_viewport_size(pipe_ctx);
4562236b 1038
6566cae7
DL		 1039 /*
1040 * LB calculations depend on vp size, h/v_active and scaling ratios
4562236b 1041 * Setting line buffer pixel depth to 24bpp yields banding
a316db72
MK		 1042 * on certain displays, such as the Sharp 4k. 36bpp is needed
1043 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1044 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1045 * precision on at least DCN display engines.
4562236b 1046 */
a316db72 1047 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
33eef72f 1048 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
4562236b 1049
d94585a0
YHL		 1050 if (pipe_ctx->plane_res.xfm != NULL)
1051 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1052 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1053
1054 if (pipe_ctx->plane_res.dpp != NULL)
1055 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1056 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
f7938bc0 1057
f7938bc0 1058
4562236b
HW		 1059 if (!res) {
1060 /* Try 24 bpp linebuffer */
6702a9ac 1061 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 1062
1b6c8067
BL		 1063 if (pipe_ctx->plane_res.xfm != NULL)
1064 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1065 pipe_ctx->plane_res.xfm,
1066 &pipe_ctx->plane_res.scl_data,
1067 &plane_state->scaling_quality);
1068
1069 if (pipe_ctx->plane_res.dpp != NULL)
1070 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1071 pipe_ctx->plane_res.dpp,
1072 &pipe_ctx->plane_res.scl_data,
1073 &plane_state->scaling_quality);
4562236b
HW		 1074 }
1075
6566cae7
DL		 1076 /*
1077 * Depends on recout, scaling ratios, h_active and taps
1078 * May need to re-check lb size after this in some obscure scenario
1079 */
b2d0a103 1080 if (res)
6566cae7
DL		 1081 calculate_inits_and_viewports(pipe_ctx);
1082
1083 /*
1084 * Handle side by side and top bottom 3d recout offsets after vp calculation
1085 * since 3d is special and needs to calculate vp as if there is no recout offset
1086 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1087 */
1088 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1089 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1090 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1091 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1092 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1093 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1094 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1095 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1096 }
1097
1098 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
1099 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1100 res = false;
b2d0a103 1101
3c0dcf9f
DL		 1102 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1103 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1104 __func__,
1105 pipe_ctx->pipe_idx,
1106 pipe_ctx->plane_res.scl_data.viewport.height,
1107 pipe_ctx->plane_res.scl_data.viewport.width,
1108 pipe_ctx->plane_res.scl_data.viewport.x,
1109 pipe_ctx->plane_res.scl_data.viewport.y,
1110 pipe_ctx->plane_res.scl_data.recout.height,
1111 pipe_ctx->plane_res.scl_data.recout.width,
1112 pipe_ctx->plane_res.scl_data.recout.x,
1113 pipe_ctx->plane_res.scl_data.recout.y,
1114 pipe_ctx->plane_res.scl_data.h_active,
1115 pipe_ctx->plane_res.scl_data.v_active,
1116 plane_state->src_rect.height,
1117 plane_state->src_rect.width,
1118 plane_state->src_rect.x,
1119 plane_state->src_rect.y,
1120 plane_state->dst_rect.height,
1121 plane_state->dst_rect.width,
1122 plane_state->dst_rect.x,
1123 plane_state->dst_rect.y,
1124 plane_state->clip_rect.height,
1125 plane_state->clip_rect.width,
1126 plane_state->clip_rect.x,
1127 plane_state->clip_rect.y);
4562236b 1128
6566cae7
DL		 1129 pipe_ctx->stream->dst.x -= timing->h_border_left;
1130 pipe_ctx->stream->dst.y -= timing->v_border_top;
89d07b66 1131
4562236b
HW		 1132 return res;
1133}
1134
1135
1136enum dc_status resource_build_scaling_params_for_context(
fb3466a4 1137 const struct dc *dc,
608ac7bb 1138 struct dc_state *context)
4562236b
HW		 1139{
1140 int i;
1141
1142 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 1143 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 1144 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 1145 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 1146 return DC_FAIL_SCALING;
4562236b
HW		 1147 }
1148
1149 return DC_OK;
1150}
1151
a2b8659d
TC		 1152struct pipe_ctx *find_idle_secondary_pipe(
1153 struct resource_context *res_ctx,
5581192d
JL		 1154 const struct resource_pool *pool,
1155 const struct pipe_ctx *primary_pipe)
4562236b
HW		 1156{
1157 int i;
1158 struct pipe_ctx *secondary_pipe = NULL;
1159
1160 /*
5581192d
JL		 1161 * We add a preferred pipe mapping to avoid the chance that
1162 * MPCCs already in use will need to be reassigned to other trees.
1163 * For example, if we went with the strict, assign backwards logic:
1164 *
1165 * (State 1)
1166 * Display A on, no surface, top pipe = 0
1167 * Display B on, no surface, top pipe = 1
1168 *
1169 * (State 2)
1170 * Display A on, no surface, top pipe = 0
1171 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1172 *
1173 * (State 3)
1174 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1175 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1176 *
1177 * The state 2->3 transition requires remapping MPCC 5 from display B
1178 * to display A.
1179 *
1180 * However, with the preferred pipe logic, state 2 would look like:
1181 *
1182 * (State 2)
1183 * Display A on, no surface, top pipe = 0
1184 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1185 *
1186 * This would then cause 2->3 to not require remapping any MPCCs.
4562236b 1187 */
5581192d
JL		 1188 if (primary_pipe) {
1189 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1190 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1191 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1192 secondary_pipe->pipe_idx = preferred_pipe_idx;
4562236b
HW		 1193 }
1194 }
1195
5581192d
JL		 1196 /*
1197 * search backwards for the second pipe to keep pipe
1198 * assignment more consistent
1199 */
1200 if (!secondary_pipe)
1201 for (i = pool->pipe_count - 1; i >= 0; i--) {
1202 if (res_ctx->pipe_ctx[i].stream == NULL) {
1203 secondary_pipe = &res_ctx->pipe_ctx[i];
1204 secondary_pipe->pipe_idx = i;
1205 break;
1206 }
1207 }
4562236b
HW		 1208
1209 return secondary_pipe;
1210}
1211
1212struct pipe_ctx *resource_get_head_pipe_for_stream(
1213 struct resource_context *res_ctx,
0971c40e 1214 struct dc_stream_state *stream)
4562236b
HW		 1215{
1216 int i;
22498036 1217
a2b8659d 1218 for (i = 0; i < MAX_PIPES; i++) {
b1f6d01c
DL		 1219 if (res_ctx->pipe_ctx[i].stream == stream
1220 && !res_ctx->pipe_ctx[i].top_pipe
22498036 1221 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
4562236b 1222 return &res_ctx->pipe_ctx[i];
4562236b
HW		 1223 }
1224 return NULL;
1225}
1226
b1f6d01c 1227static struct pipe_ctx *resource_get_tail_pipe(
19f89e23 1228 struct resource_context *res_ctx,
b1f6d01c 1229 struct pipe_ctx *head_pipe)
19f89e23 1230{
b1f6d01c 1231 struct pipe_ctx *tail_pipe;
19f89e23
AG		 1232
1233 tail_pipe = head_pipe->bottom_pipe;
1234
1235 while (tail_pipe) {
1236 head_pipe = tail_pipe;
1237 tail_pipe = tail_pipe->bottom_pipe;
1238 }
1239
1240 return head_pipe;
1241}
1242
4562236b 1243/*
ab2541b6
AC		 1244 * A free_pipe for a stream is defined here as a pipe
1245 * that has no surface attached yet
4562236b 1246 */
b1f6d01c 1247static struct pipe_ctx *acquire_free_pipe_for_head(
608ac7bb 1248 struct dc_state *context,
a2b8659d 1249 const struct resource_pool *pool,
b1f6d01c 1250 struct pipe_ctx *head_pipe)
4562236b
HW		 1251{
1252 int i;
745cc746 1253 struct resource_context *res_ctx = &context->res_ctx;
4562236b 1254
3be5262e 1255 if (!head_pipe->plane_state)
4562236b
HW		 1256 return head_pipe;
1257
1258 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1259 for (i = pool->pipe_count - 1; i >= 0; i--) {
b1f6d01c 1260 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
3be5262e 1261 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1262 return &res_ctx->pipe_ctx[i];
1263 }
1264 }
1265
1266 /*
1267 * At this point we have no re-useable pipe for this stream and we need
1268 * to acquire an idle one to satisfy the request
1269 */
1270
a2b8659d 1271 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1272 return NULL;
1273
b1f6d01c 1274 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
4562236b
HW		 1275}
1276
b86a1aa3 1277#if defined(CONFIG_DRM_AMD_DC_DCN)
0f9a536f
DL		 1278static int acquire_first_split_pipe(
1279 struct resource_context *res_ctx,
1280 const struct resource_pool *pool,
0971c40e 1281 struct dc_stream_state *stream)
0f9a536f
DL		 1282{
1283 int i;
1284
1285 for (i = 0; i < pool->pipe_count; i++) {
79592db3
DL		 1286 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1287
b1f6d01c 1288 if (split_pipe->top_pipe &&
79592db3
DL		 1289 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1290 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1291 if (split_pipe->bottom_pipe)
1292 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1293
1294 if (split_pipe->top_pipe->plane_state)
1295 resource_build_scaling_params(split_pipe->top_pipe);
1296
1297 memset(split_pipe, 0, sizeof(*split_pipe));
1298 split_pipe->stream_res.tg = pool->timing_generators[i];
1299 split_pipe->plane_res.hubp = pool->hubps[i];
1300 split_pipe->plane_res.ipp = pool->ipps[i];
1301 split_pipe->plane_res.dpp = pool->dpps[i];
1302 split_pipe->stream_res.opp = pool->opps[i];
1303 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1304 split_pipe->pipe_idx = i;
1305
1306 split_pipe->stream = stream;
0f9a536f
DL		 1307 return i;
1308 }
1309 }
1310 return -1;
1311}
1312#endif
1313
19f89e23
AG		 1314bool dc_add_plane_to_context(
1315 const struct dc *dc,
0971c40e 1316 struct dc_stream_state *stream,
19f89e23 1317 struct dc_plane_state *plane_state,
608ac7bb 1318 struct dc_state *context)
4562236b
HW		 1319{
1320 int i;
19f89e23
AG		 1321 struct resource_pool *pool = dc->res_pool;
1322 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1323 struct dc_stream_status *stream_status = NULL;
4562236b 1324
19f89e23
AG		 1325 for (i = 0; i < context->stream_count; i++)
1326 if (context->streams[i] == stream) {
1327 stream_status = &context->stream_status[i];
1328 break;
1329 }
1330 if (stream_status == NULL) {
1331 dm_error("Existing stream not found; failed to attach surface!\n");
1332 return false;
1333 }
1334
4562236b 1335
19f89e23
AG		 1336 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1337 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1338 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1339 return false;
1340 }
1341
19f89e23
AG		 1342 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1343
1344 if (!head_pipe) {
1345 dm_error("Head pipe not found for stream_state %p !\n", stream);
1346 return false;
1347 }
1348
b1f6d01c
DL		 1349 /* retain new surface, but only once per stream */
1350 dc_plane_state_retain(plane_state);
00737c59 1351
b1f6d01c 1352 while (head_pipe) {
b1f6d01c 1353 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
19f89e23 1354
b86a1aa3 1355 #if defined(CONFIG_DRM_AMD_DC_DCN)
b1f6d01c
DL		 1356 if (!free_pipe) {
1357 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1358 if (pipe_idx >= 0)
1359 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1360 }
1361 #endif
1362 if (!free_pipe) {
1363 dc_plane_state_release(plane_state);
1364 return false;
1365 }
19f89e23 1366
b1f6d01c
DL		 1367 free_pipe->plane_state = plane_state;
1368
1369 if (head_pipe != free_pipe) {
5b5c1777
JP		 1370 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1371 ASSERT(tail_pipe);
b1f6d01c
DL		 1372 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1373 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1374 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1375 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1376 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1377 free_pipe->clock_source = tail_pipe->clock_source;
1378 free_pipe->top_pipe = tail_pipe;
1379 tail_pipe->bottom_pipe = free_pipe;
2e7b43e6
DL		 1380 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1381 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1382 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1383 }
1384 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1385 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1386 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1387 }
b1f6d01c
DL		 1388 }
1389 head_pipe = head_pipe->next_odm_pipe;
1390 }
19f89e23
AG		 1391 /* assign new surfaces*/
1392 stream_status->plane_states[stream_status->plane_count] = plane_state;
1393
1394 stream_status->plane_count++;
1395
1396 return true;
1397}
1398
1399bool dc_remove_plane_from_context(
1400 const struct dc *dc,
1401 struct dc_stream_state *stream,
1402 struct dc_plane_state *plane_state,
608ac7bb 1403 struct dc_state *context)
19f89e23
AG		 1404{
1405 int i;
1406 struct dc_stream_status *stream_status = NULL;
1407 struct resource_pool *pool = dc->res_pool;
1408
ab2541b6 1409 for (i = 0; i < context->stream_count; i++)
4fa086b9 1410 if (context->streams[i] == stream) {
ab2541b6 1411 stream_status = &context->stream_status[i];
4562236b
HW		 1412 break;
1413 }
19f89e23 1414
ab2541b6 1415 if (stream_status == NULL) {
19f89e23 1416 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1417 return false;
1418 }
1419
19f89e23
AG		 1420 /* release pipe for plane*/
1421 for (i = pool->pipe_count - 1; i >= 0; i--) {
6ffaa6fc 1422 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1423
6ffaa6fc 1424 if (pipe_ctx->plane_state == plane_state) {
19f89e23
AG		 1425 if (pipe_ctx->top_pipe)
1426 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1427
19f89e23
AG		 1428 /* Second condition is to avoid setting NULL to top pipe
1429 * of tail pipe making it look like head pipe in subsequent
1430 * deletes
1431 */
1432 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1433 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1434
19f89e23
AG		 1435 /*
1436 * For head pipe detach surfaces from pipe for tail
1437 * pipe just zero it out
1438 */
b1f6d01c 1439 if (!pipe_ctx->top_pipe)
19f89e23 1440 pipe_ctx->plane_state = NULL;
b1f6d01c 1441 else
19f89e23 1442 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
4562236b 1443 }
19f89e23 1444 }
4562236b 1445
4562236b 1446
19f89e23
AG		 1447 for (i = 0; i < stream_status->plane_count; i++) {
1448 if (stream_status->plane_states[i] == plane_state) {
1449
1450 dc_plane_state_release(stream_status->plane_states[i]);
1451 break;
4562236b 1452 }
19f89e23 1453 }
4562236b 1454
19f89e23
AG		 1455 if (i == stream_status->plane_count) {
1456 dm_error("Existing plane_state not found; failed to detach it!\n");
1457 return false;
4562236b
HW		 1458 }
1459
19f89e23 1460 stream_status->plane_count--;
4562236b 1461
abb4986e
AJ		 1462 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1463 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1464 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1465
1466 stream_status->plane_states[stream_status->plane_count] = NULL;
1467
1468 return true;
1469}
1470
1471bool dc_rem_all_planes_for_stream(
1472 const struct dc *dc,
1473 struct dc_stream_state *stream,
608ac7bb 1474 struct dc_state *context)
19f89e23
AG		 1475{
1476 int i, old_plane_count;
1477 struct dc_stream_status *stream_status = NULL;
1478 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1479
1480 for (i = 0; i < context->stream_count; i++)
1481 if (context->streams[i] == stream) {
1482 stream_status = &context->stream_status[i];
1483 break;
1484 }
1485
1486 if (stream_status == NULL) {
1487 dm_error("Existing stream %p not found!\n", stream);
1488 return false;
1489 }
1490
1491 old_plane_count = stream_status->plane_count;
1492
1493 for (i = 0; i < old_plane_count; i++)
1494 del_planes[i] = stream_status->plane_states[i];
1495
1496 for (i = 0; i < old_plane_count; i++)
1497 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1498 return false;
1499
1500 return true;
1501}
1502
1503static bool add_all_planes_for_stream(
1504 const struct dc *dc,
1505 struct dc_stream_state *stream,
1506 const struct dc_validation_set set[],
1507 int set_count,
608ac7bb 1508 struct dc_state *context)
19f89e23
AG		 1509{
1510 int i, j;
1511
1512 for (i = 0; i < set_count; i++)
1513 if (set[i].stream == stream)
1514 break;
1515
1516 if (i == set_count) {
1517 dm_error("Stream %p not found in set!\n", stream);
1518 return false;
1519 }
4562236b 1520
19f89e23
AG		 1521 for (j = 0; j < set[i].plane_count; j++)
1522 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1523 return false;
4562236b
HW		 1524
1525 return true;
1526}
1527
19f89e23
AG		 1528bool dc_add_all_planes_for_stream(
1529 const struct dc *dc,
1530 struct dc_stream_state *stream,
1531 struct dc_plane_state * const *plane_states,
1532 int plane_count,
608ac7bb 1533 struct dc_state *context)
19f89e23
AG		 1534{
1535 struct dc_validation_set set;
1536 int i;
1537
1538 set.stream = stream;
1539 set.plane_count = plane_count;
1540
1541 for (i = 0; i < plane_count; i++)
1542 set.plane_states[i] = plane_states[i];
1543
1544 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1545}
1546
0971c40e
HW		 1547static bool is_timing_changed(struct dc_stream_state *cur_stream,
1548 struct dc_stream_state *new_stream)
4562236b
HW		 1549{
1550 if (cur_stream == NULL)
1551 return true;
1552
4562236b 1553 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1554 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1555 return true;
1556
1557 return memcmp(
4fa086b9
LSL		 1558 &cur_stream->timing,
1559 &new_stream->timing,
4562236b
HW		 1560 sizeof(struct dc_crtc_timing)) != 0;
1561}
1562
1563static bool are_stream_backends_same(
0971c40e 1564 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1565{
1566 if (stream_a == stream_b)
1567 return true;
1568
1569 if (stream_a == NULL || stream_b == NULL)
1570 return false;
1571
1572 if (is_timing_changed(stream_a, stream_b))
1573 return false;
1574
1e7e86c4
ST		 1575 if (stream_a->dpms_off != stream_b->dpms_off)
1576 return false;
1577
4562236b
HW		 1578 return true;
1579}
1580
625a15bf 1581/*
2119aa17
DF		 1582 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1583 *
1584 * Checks if there a difference between the two states
1585 * that would require a mode change.
1586 *
1587 * Does not compare cursor position or attributes.
1588 */
d54d29db 1589bool dc_is_stream_unchanged(
0971c40e 1590 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1591{
4562236b 1592
ab2541b6
AC		 1593 if (!are_stream_backends_same(old_stream, stream))
1594 return false;
4562236b 1595
0460f9ab
JL		 1596 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1597 return false;
1598
4562236b
HW		 1599 return true;
1600}
1601
625a15bf 1602/*
2119aa17
DF		 1603 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1604 */
9a5d9c48
LSL		 1605bool dc_is_stream_scaling_unchanged(
1606 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1607{
1608 if (old_stream == stream)
1609 return true;
1610
1611 if (old_stream == NULL || stream == NULL)
1612 return false;
1613
1614 if (memcmp(&old_stream->src,
1615 &stream->src,
1616 sizeof(struct rect)) != 0)
1617 return false;
1618
1619 if (memcmp(&old_stream->dst,
1620 &stream->dst,
1621 sizeof(struct rect)) != 0)
1622 return false;
1623
1624 return true;
1625}
1626
1dc90497 1627static void update_stream_engine_usage(
4562236b 1628 struct resource_context *res_ctx,
a2b8659d 1629 const struct resource_pool *pool,
1dc90497
AG		 1630 struct stream_encoder *stream_enc,
1631 bool acquired)
4562236b
HW		 1632{
1633 int i;
1634
a2b8659d
TC		 1635 for (i = 0; i < pool->stream_enc_count; i++) {
1636 if (pool->stream_enc[i] == stream_enc)
1dc90497 1637 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1638 }
1639}
1640
1641/* TODO: release audio object */
4176664b 1642void update_audio_usage(
4562236b 1643 struct resource_context *res_ctx,
a2b8659d 1644 const struct resource_pool *pool,
1dc90497
AG		 1645 struct audio *audio,
1646 bool acquired)
4562236b
HW		 1647{
1648 int i;
a2b8659d
TC		 1649 for (i = 0; i < pool->audio_count; i++) {
1650 if (pool->audios[i] == audio)
1dc90497 1651 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1652 }
1653}
1654
1655static int acquire_first_free_pipe(
1656 struct resource_context *res_ctx,
a2b8659d 1657 const struct resource_pool *pool,
0971c40e 1658 struct dc_stream_state *stream)
4562236b
HW		 1659{
1660 int i;
1661
a2b8659d 1662 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1663 if (!res_ctx->pipe_ctx[i].stream) {
1664 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1665
6b670fa9 1666 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1667 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1668 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1669 pipe_ctx->plane_res.ipp = pool->ipps[i];
1670 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1671 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1672 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1673 if (pool->dpps[i])
1674 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1675 pipe_ctx->pipe_idx = i;
1676
ff5ef992 1677
4562236b
HW		 1678 pipe_ctx->stream = stream;
1679 return i;
1680 }
1681 }
1682 return -1;
1683}
1684
a2b8659d
TC		 1685static struct audio *find_first_free_audio(
1686 struct resource_context *res_ctx,
cfb071f7 1687 const struct resource_pool *pool,
f24b0522
PH		 1688 enum engine_id id,
1689 enum dce_version dc_version)
4562236b 1690{
b5a41620
CL		 1691 int i, available_audio_count;
1692
1693 available_audio_count = pool->audio_count;
1694
1695 for (i = 0; i < available_audio_count; i++) {
66bfd4fd 1696 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1697 /*we have enough audio endpoint, find the matching inst*/
1698 if (id != i)
1699 continue;
66bfd4fd 1700 return pool->audios[i];
4562236b 1701 }
66bfd4fd 1702 }
5feb9f07 1703
b5a41620
CL		 1704 /* use engine id to find free audio */
1705 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
5feb9f07
TM		 1706 return pool->audios[id];
1707 }
66bfd4fd 1708 /*not found the matching one, first come first serve*/
b5a41620 1709 for (i = 0; i < available_audio_count; i++) {
66bfd4fd
CL		 1710 if (res_ctx->is_audio_acquired[i] == false) {
1711 return pool->audios[i];
4176664b
CL		 1712 }
1713 }
4562236b
HW		 1714 return 0;
1715}
1716
625a15bf 1717/*
2119aa17
DF		 1718 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1719 */
13ab1b44 1720enum dc_status dc_add_stream_to_ctx(
1dc90497 1721 struct dc *dc,
608ac7bb 1722 struct dc_state *new_ctx,
1dc90497
AG		 1723 struct dc_stream_state *stream)
1724{
1dc90497 1725 enum dc_status res;
eb9714a2 1726 DC_LOGGER_INIT(dc->ctx->logger);
1dc90497 1727
ece4147f 1728 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
eb9714a2 1729 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1dc90497
AG		 1730 return DC_ERROR_UNEXPECTED;
1731 }
1732
1733 new_ctx->streams[new_ctx->stream_count] = stream;
1734 dc_stream_retain(stream);
1735 new_ctx->stream_count++;
1736
1737 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1738 if (res != DC_OK)
eb9714a2 1739 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1dc90497 1740
13ab1b44 1741 return res;
1dc90497
AG		 1742}
1743
625a15bf 1744/*
2119aa17
DF		 1745 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1746 */
62c933f9 1747enum dc_status dc_remove_stream_from_ctx(
1dc90497 1748 struct dc *dc,
608ac7bb 1749 struct dc_state *new_ctx,
1dc90497
AG		 1750 struct dc_stream_state *stream)
1751{
19f89e23 1752 int i;
1dc90497 1753 struct dc_context *dc_ctx = dc->ctx;
22498036
DL		 1754 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1755 struct pipe_ctx *odm_pipe;
1dc90497
AG		 1756
1757 if (!del_pipe) {
1758 DC_ERROR("Pipe not found for stream %p !\n", stream);
1759 return DC_ERROR_UNEXPECTED;
1760 }
1761
22498036
DL		 1762 odm_pipe = del_pipe->next_odm_pipe;
1763
1764 /* Release primary pipe */
1765 ASSERT(del_pipe->stream_res.stream_enc);
1766 update_stream_engine_usage(
1767 &new_ctx->res_ctx,
1768 dc->res_pool,
1769 del_pipe->stream_res.stream_enc,
1770 false);
f42ef862
JK		 1771 /* Release link encoder from stream in new dc_state. */
1772 if (dc->res_pool->funcs->link_enc_unassign)
1773 dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
22498036
DL		 1774
1775 if (del_pipe->stream_res.audio)
1776 update_audio_usage(
1777 &new_ctx->res_ctx,
1778 dc->res_pool,
1779 del_pipe->stream_res.audio,
1780 false);
1781
1782 resource_unreference_clock_source(&new_ctx->res_ctx,
1783 dc->res_pool,
1784 del_pipe->clock_source);
1785
1786 if (dc->res_pool->funcs->remove_stream_from_ctx)
1787 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1788
1789 while (odm_pipe) {
1790 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1791
1792 memset(odm_pipe, 0, sizeof(*odm_pipe));
1793 odm_pipe = next_odm_pipe;
1794 }
1795 memset(del_pipe, 0, sizeof(*del_pipe));
1796
1dc90497
AG		 1797 for (i = 0; i < new_ctx->stream_count; i++)
1798 if (new_ctx->streams[i] == stream)
1799 break;
1800
1801 if (new_ctx->streams[i] != stream) {
1802 DC_ERROR("Context doesn't have stream %p !\n", stream);
1803 return DC_ERROR_UNEXPECTED;
1804 }
1805
1806 dc_stream_release(new_ctx->streams[i]);
1807 new_ctx->stream_count--;
1808
1dc90497
AG		 1809 /* Trim back arrays */
1810 for (; i < new_ctx->stream_count; i++) {
1811 new_ctx->streams[i] = new_ctx->streams[i + 1];
1812 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1813 }
1814
1815 new_ctx->streams[new_ctx->stream_count] = NULL;
1816 memset(
1817 &new_ctx->stream_status[new_ctx->stream_count],
1818 0,
1819 sizeof(new_ctx->stream_status[0]));
1820
1821 return DC_OK;
1822}
1823
0971c40e
HW		 1824static struct dc_stream_state *find_pll_sharable_stream(
1825 struct dc_stream_state *stream_needs_pll,
608ac7bb 1826 struct dc_state *context)
4562236b 1827{
ab2541b6 1828 int i;
4562236b 1829
ab2541b6 1830 for (i = 0; i < context->stream_count; i++) {
0971c40e 1831 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1832
ab2541b6
AC		 1833 /* We are looking for non dp, non virtual stream */
1834 if (resource_are_streams_timing_synchronizable(
1835 stream_needs_pll, stream_has_pll)
1836 && !dc_is_dp_signal(stream_has_pll->signal)
ceb3dbb4 1837 && stream_has_pll->link->connector_signal
ab2541b6
AC		 1838 != SIGNAL_TYPE_VIRTUAL)
1839 return stream_has_pll;
4562236b 1840
4562236b
HW		 1841 }
1842
1843 return NULL;
1844}
1845
1846static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1847{
380604e2 1848 uint32_t pix_clk = timing->pix_clk_100hz;
4562236b
HW		 1849 uint32_t normalized_pix_clk = pix_clk;
1850
1851 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1852 pix_clk /= 2;
cc4d99b8
CL		 1853 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1854 switch (timing->display_color_depth) {
8897810a 1855 case COLOR_DEPTH_666:
cc4d99b8
CL		 1856 case COLOR_DEPTH_888:
1857 normalized_pix_clk = pix_clk;
1858 break;
1859 case COLOR_DEPTH_101010:
1860 normalized_pix_clk = (pix_clk * 30) / 24;
1861 break;
1862 case COLOR_DEPTH_121212:
1863 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1864 break;
cc4d99b8
CL		 1865 case COLOR_DEPTH_161616:
1866 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1867 break;
cc4d99b8
CL		 1868 default:
1869 ASSERT(0);
4562236b 1870 break;
cc4d99b8 1871 }
4562236b 1872 }
4562236b
HW		 1873 return normalized_pix_clk;
1874}
1875
0971c40e 1876static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1877{
9345d987
AG		 1878 /* update actual pixel clock on all streams */
1879 if (dc_is_hdmi_signal(stream->signal))
1880 stream->phy_pix_clk = get_norm_pix_clk(
380604e2 1881 &stream->timing) / 10;
9345d987
AG		 1882 else
1883 stream->phy_pix_clk =
380604e2 1884 stream->timing.pix_clk_100hz / 10;
39c03e00
CL		 1885
1886 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1887 stream->phy_pix_clk *= 2;
4562236b
HW		 1888}
1889
d2d7885f
AK		 1890static int acquire_resource_from_hw_enabled_state(
1891 struct resource_context *res_ctx,
1892 const struct resource_pool *pool,
1893 struct dc_stream_state *stream)
1894{
1895 struct dc_link *link = stream->link;
08b66279 1896 unsigned int i, inst, tg_inst = 0;
d2d7885f
AK		 1897
1898 /* Check for enabled DIG to identify enabled display */
1899 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1900 return -1;
1901
5ec43eda 1902 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
d2d7885f 1903
7f7652ee 1904 if (inst == ENGINE_ID_UNKNOWN)
75441d9d 1905 return -1;
d2d7885f 1906
7f7652ee
ML		 1907 for (i = 0; i < pool->stream_enc_count; i++) {
1908 if (pool->stream_enc[i]->id == inst) {
1909 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
1910 pool->stream_enc[i]);
1911 break;
1912 }
1913 }
5ec43eda 1914
7f7652ee
ML		 1915 // tg_inst not found
1916 if (i == pool->stream_enc_count)
75441d9d 1917 return -1;
5ec43eda
ML		 1918
1919 if (tg_inst >= pool->timing_generator_count)
75441d9d 1920 return -1;
5ec43eda
ML		 1921
1922 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1923 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1924
1925 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1926 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1927 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1928 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1929 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1930 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1931 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
d2d7885f 1932
ccce745c 1933 if (pool->dpps[tg_inst]) {
5ec43eda 1934 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
ccce745c
ML		 1935
1936 // Read DPP->MPCC->OPP Pipe from HW State
1937 if (pool->mpc->funcs->read_mpcc_state) {
1938 struct mpcc_state s = {0};
1939
1940 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
1941
1942 if (s.dpp_id < MAX_MPCC)
1943 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
1944
1945 if (s.bot_mpcc_id < MAX_MPCC)
1946 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
1947 &pool->mpc->mpcc_array[s.bot_mpcc_id];
1948
1949 if (s.opp_id < MAX_OPP)
1950 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
1951 }
1952 }
5ec43eda 1953 pipe_ctx->pipe_idx = tg_inst;
d2d7885f
AK		 1954
1955 pipe_ctx->stream = stream;
5ec43eda 1956 return tg_inst;
d2d7885f
AK		 1957 }
1958
1959 return -1;
1960}
1961
96b5e3e1
RY		 1962static void mark_seamless_boot_stream(
1963 const struct dc *dc,
1964 struct dc_stream_state *stream)
1965{
1966 struct dc_bios *dcb = dc->ctx->dc_bios;
1967
1968 /* TODO: Check Linux */
1969 if (dc->config.allow_seamless_boot_optimization &&
1970 !dcb->funcs->is_accelerated_mode(dcb)) {
1971 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1972 stream->apply_seamless_boot_optimization = true;
1973 }
1974}
1975
4562236b 1976enum dc_status resource_map_pool_resources(
fb3466a4 1977 const struct dc *dc,
608ac7bb 1978 struct dc_state *context,
1dc90497 1979 struct dc_stream_state *stream)
4562236b 1980{
a2b8659d 1981 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1982 int i;
1983 struct dc_context *dc_ctx = dc->ctx;
1984 struct pipe_ctx *pipe_ctx = NULL;
1985 int pipe_idx = -1;
4562236b 1986
08e1c28d
YMM		 1987 calculate_phy_pix_clks(stream);
1988
96b5e3e1 1989 mark_seamless_boot_stream(dc, stream);
46570f09 1990
96b5e3e1 1991 if (stream->apply_seamless_boot_optimization) {
d2d7885f
AK		 1992 pipe_idx = acquire_resource_from_hw_enabled_state(
1993 &context->res_ctx,
1994 pool,
1995 stream);
96b5e3e1
RY		 1996 if (pipe_idx < 0)
1997 /* hw resource was assigned to other stream */
1998 stream->apply_seamless_boot_optimization = false;
1999 }
d2d7885f
AK		 2000
2001 if (pipe_idx < 0)
2002 /* acquire new resources */
2003 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 2004
b86a1aa3 2005#ifdef CONFIG_DRM_AMD_DC_DCN
1dc90497 2006 if (pipe_idx < 0)
13ab1b44 2007 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 2008#endif
13ab1b44 2009
c5b38aec 2010 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 2011 return DC_NO_CONTROLLER_RESOURCE;
2012
2013 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2014
2015 pipe_ctx->stream_res.stream_enc =
78cc70b1 2016 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1dc90497
AG		 2017 &context->res_ctx, pool, stream);
2018
2019 if (!pipe_ctx->stream_res.stream_enc)
38684e46 2020 return DC_NO_STREAM_ENC_RESOURCE;
1dc90497
AG		 2021
2022 update_stream_engine_usage(
2023 &context->res_ctx, pool,
2024 pipe_ctx->stream_res.stream_enc,
2025 true);
2026
2027 /* TODO: Add check if ASIC support and EDID audio */
ceb3dbb4 2028 if (!stream->converter_disable_audio &&
1dc90497 2029 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
ce08aad3 2030 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 2031 pipe_ctx->stream_res.audio = find_first_free_audio(
f24b0522 2032 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
1dc90497
AG		 2033
2034 /*
2035 * Audio assigned in order first come first get.
2036 * There are asics which has number of audio
2037 * resources less then number of pipes
2038 */
2039 if (pipe_ctx->stream_res.audio)
2040 update_audio_usage(&context->res_ctx, pool,
2041 pipe_ctx->stream_res.audio, true);
2042 }
268cadbd 2043
9aef1a31 2044 /* Add ABM to the resource if on EDP */
5dba4991 2045 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
20f2ffe5 2046#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 2047 if (pool->abm)
2048 pipe_ctx->stream_res.abm = pool->abm;
2049 else
2050 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2051#else
9aef1a31 2052 pipe_ctx->stream_res.abm = pool->abm;
5dba4991
BL		 2053#endif
2054 }
9aef1a31 2055
1dc90497
AG		 2056 for (i = 0; i < context->stream_count; i++)
2057 if (context->streams[i] == stream) {
2058 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3f0940f8 2059 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
5fdb7c4c
NK		 2060 context->stream_status[i].audio_inst =
2061 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2062
1dc90497
AG		 2063 return DC_OK;
2064 }
4562236b 2065
1dc90497
AG		 2066 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2067 return DC_ERROR_UNEXPECTED;
2068}
4562236b 2069
2119aa17
DF		 2070/**
2071 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2072 * Is a shallow copy. Increments refcounts on existing streams and planes.
2073 * @dc: copy out of dc->current_state
2074 * @dst_ctx: copy into this
2075 */
f36cc577 2076void dc_resource_state_copy_construct_current(
1dc90497 2077 const struct dc *dc,
608ac7bb 2078 struct dc_state *dst_ctx)
1dc90497 2079{
f36cc577 2080 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 2081}
2082
ab8db3e1
AG		 2083
2084void dc_resource_state_construct(
2085 const struct dc *dc,
2086 struct dc_state *dst_ctx)
2087{
dc88b4a6 2088 dst_ctx->clk_mgr = dc->clk_mgr;
ab8db3e1
AG		 2089}
2090
6d822156
NC		 2091
2092bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2093{
2094 return dc->res_pool->res_cap->num_dsc > 0;
2095}
2096
2097
2119aa17
DF		 2098/**
2099 * dc_validate_global_state() - Determine if HW can support a given state
2100 * Checks HW resource availability and bandwidth requirement.
2101 * @dc: dc struct for this driver
2102 * @new_ctx: state to be validated
afcd526b 2103 * @fast_validate: set to true if only yes/no to support matters
2119aa17
DF		 2104 *
2105 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2106 */
e750d56d 2107enum dc_status dc_validate_global_state(
1dc90497 2108 struct dc *dc,
afcd526b
JA		 2109 struct dc_state *new_ctx,
2110 bool fast_validate)
4562236b 2111{
1dc90497 2112 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 2113 int i, j;
4562236b 2114
e41ab030
HW		 2115 if (!new_ctx)
2116 return DC_ERROR_UNEXPECTED;
2117
d596e5d0 2118 if (dc->res_pool->funcs->validate_global) {
ada8ce15
HW		 2119 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2120 if (result != DC_OK)
2121 return result;
d596e5d0 2122 }
4562236b 2123
e41ab030 2124 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 2125 struct dc_stream_state *stream = new_ctx->streams[i];
2126
2127 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2128 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2129
2130 if (pipe_ctx->stream != stream)
2131 continue;
2132
8d8c82b6 2133 if (dc->res_pool->funcs->patch_unknown_plane_state &&
74eac5f3
SSC		 2134 pipe_ctx->plane_state &&
2135 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
8d8c82b6 2136 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
74eac5f3
SSC		 2137 if (result != DC_OK)
2138 return result;
2139 }
2140
1dc90497
AG		 2141 /* Switch to dp clock source only if there is
2142 * no non dp stream that shares the same timing
2143 * with the dp stream.
2144 */
2145 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2146 !find_pll_sharable_stream(stream, new_ctx)) {
2147
9d0dcecd 2148 resource_unreference_clock_source(
1dc90497
AG		 2149 &new_ctx->res_ctx,
2150 dc->res_pool,
9d0dcecd 2151 pipe_ctx->clock_source);
4a629536 2152
1dc90497
AG		 2153 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2154 resource_reference_clock_source(
2155 &new_ctx->res_ctx,
2156 dc->res_pool,
2157 pipe_ctx->clock_source);
2158 }
2159 }
2160 }
2161
1dc90497
AG		 2162 result = resource_build_scaling_params_for_context(dc, new_ctx);
2163
2164 if (result == DC_OK)
afcd526b 2165 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
1dc90497
AG		 2166 result = DC_FAIL_BANDWIDTH_VALIDATE;
2167
2168 return result;
4562236b
HW		 2169}
2170
6e4d6bee 2171static void patch_gamut_packet_checksum(
e09b6473 2172 struct dc_info_packet *gamut_packet)
4562236b 2173{
4562236b 2174 /* For gamut we recalc checksum */
6e4d6bee 2175 if (gamut_packet->valid) {
4562236b
HW		 2176 uint8_t chk_sum = 0;
2177 uint8_t *ptr;
2178 uint8_t i;
2179
4562236b 2180 /*start of the Gamut data. */
6e4d6bee 2181 ptr = &gamut_packet->sb[3];
4562236b 2182
6e4d6bee 2183 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 2184 chk_sum += ptr[i];
2185
6e4d6bee 2186 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 2187 }
4562236b
HW		 2188}
2189
2190static void set_avi_info_frame(
e09b6473 2191 struct dc_info_packet *info_packet,
4562236b
HW		 2192 struct pipe_ctx *pipe_ctx)
2193{
0971c40e 2194 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 2195 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 2196 uint32_t pixel_encoding = 0;
2197 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2198 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2199 bool itc = false;
50e27654 2200 uint8_t itc_value = 0;
4562236b 2201 uint8_t cn0_cn1 = 0;
50e27654 2202 unsigned int cn0_cn1_value = 0;
4562236b
HW		 2203 uint8_t *check_sum = NULL;
2204 uint8_t byte_index = 0;
754e3673 2205 union hdmi_info_packet hdmi_info;
50e27654 2206 union display_content_support support = {0};
4fa086b9 2207 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 2208 enum dc_timing_3d_format format;
4562236b 2209
754e3673
AK		 2210 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2211
4fa086b9 2212 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 2213 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 2214 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 2215 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 2216
2217 /* Initialize header */
e09b6473 2218 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 2219 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2220 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 2221 hdmi_info.bits.header.version = 2;
2222 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 2223
2224 /*
2225 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2226 * according to HDMI 2.0 spec (Section 10.1)
2227 */
2228
4fa086b9 2229 switch (stream->timing.pixel_encoding) {
4562236b
HW		 2230 case PIXEL_ENCODING_YCBCR422:
2231 pixel_encoding = 1;
2232 break;
2233
2234 case PIXEL_ENCODING_YCBCR444:
2235 pixel_encoding = 2;
2236 break;
2237 case PIXEL_ENCODING_YCBCR420:
2238 pixel_encoding = 3;
2239 break;
2240
2241 case PIXEL_ENCODING_RGB:
2242 default:
2243 pixel_encoding = 0;
2244 }
2245
2246 /* Y0_Y1_Y2 : The pixel encoding */
2247 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 2248 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 2249
2250 /* A0 = 1 Active Format Information valid */
e09b6473 2251 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 2252
2253 /* B0, B1 = 3; Bar info data is valid */
e09b6473 2254 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 2255
e09b6473 2256 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 2257
2258 /* S0, S1 : Underscan / Overscan */
2259 /* TODO: un-hardcode scan type */
2260 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 2261 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 2262
2263 /* C0, C1 : Colorimetry */
8fde5884 2264 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 2265 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 2266 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 2267 else if (color_space == COLOR_SPACE_YCBCR601 ||
2268 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 2269 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 2270 else {
e09b6473 2271 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 2272 }
534db198 2273 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 2274 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2275 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 2276 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2277 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 2278 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 2279 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2280 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 2281 }
2282
4562236b 2283 /* TODO: un-hardcode aspect ratio */
4fa086b9 2284 aspect = stream->timing.aspect_ratio;
4562236b
HW		 2285
2286 switch (aspect) {
2287 case ASPECT_RATIO_4_3:
2288 case ASPECT_RATIO_16_9:
e09b6473 2289 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 2290 break;
2291
2292 case ASPECT_RATIO_NO_DATA:
2293 case ASPECT_RATIO_64_27:
2294 case ASPECT_RATIO_256_135:
2295 default:
e09b6473 2296 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 2297 }
2298
2299 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 2300 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2301
2302 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2303
4562236b 2304 cn0_cn1 = 0;
50e27654
ZF		 2305 cn0_cn1_value = 0;
2306
2307 itc = true;
2308 itc_value = 1;
2309
ceb3dbb4 2310 support = stream->content_support;
4562236b
HW		 2311
2312 if (itc) {
50e27654
ZF		 2313 if (!support.bits.valid_content_type) {
2314 cn0_cn1_value = 0;
2315 } else {
2316 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2317 if (support.bits.graphics_content == 1) {
2318 cn0_cn1_value = 0;
2319 }
2320 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2321 if (support.bits.photo_content == 1) {
2322 cn0_cn1_value = 1;
2323 } else {
2324 cn0_cn1_value = 0;
2325 itc_value = 0;
2326 }
2327 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2328 if (support.bits.cinema_content == 1) {
2329 cn0_cn1_value = 2;
2330 } else {
2331 cn0_cn1_value = 0;
2332 itc_value = 0;
2333 }
2334 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2335 if (support.bits.game_content == 1) {
2336 cn0_cn1_value = 3;
2337 } else {
2338 cn0_cn1_value = 0;
2339 itc_value = 0;
2340 }
2341 }
2342 }
e09b6473
AK		 2343 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2344 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 2345 }
2346
fdf7d4f5
DV		 2347 if (stream->qs_bit == 1) {
2348 if (color_space == COLOR_SPACE_SRGB ||
2349 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
2350 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2351 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2352 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
2353 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2354 else
2355 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2356 } else
2357 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2358
4562236b
HW		 2359 /* TODO : We should handle YCC quantization */
2360 /* but we do not have matrix calculation */
fdf7d4f5 2361 if (stream->qy_bit == 1) {
50e27654 2362 if (color_space == COLOR_SPACE_SRGB ||
fdf7d4f5 2363 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
993dca3e 2364 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
fdf7d4f5
DV		 2365 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2366 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
e09b6473 2367 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
fdf7d4f5 2368 else
e09b6473 2369 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
fdf7d4f5
DV		 2370 } else
2371 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2372
15e17335 2373 ///VIC
4fa086b9 2374 format = stream->timing.timing_3d_format;
15e17335
CL		 2375 /*todo, add 3DStereo support*/
2376 if (format != TIMING_3D_FORMAT_NONE) {
2377 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2378 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2379 case 1:
2380 vic = 95;
2381 break;
2382 case 2:
2383 vic = 94;
2384 break;
2385 case 3:
2386 vic = 93;
2387 break;
2388 case 4:
2389 vic = 98;
2390 break;
2391 default:
2392 break;
2393 }
2394 }
efa02336 2395 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
e09b6473 2396 hdmi_info.bits.VIC0_VIC7 = vic;
efa02336
CP		 2397 if (vic >= 128)
2398 hdmi_info.bits.header.version = 3;
2399 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2400 * the Source shall use 20 AVI InfoFrame Version 4
2401 */
2402 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2403 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2404 hdmi_info.bits.header.version = 4;
2405 hdmi_info.bits.header.length = 14;
2406 }
4562236b
HW		 2407
2408 /* pixel repetition
2409 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2410 * repetition start from 1 */
e09b6473 2411 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2412
2413 /* Bar Info
2414 * barTop: Line Number of End of Top Bar.
2415 * barBottom: Line Number of Start of Bottom Bar.
2416 * barLeft: Pixel Number of End of Left Bar.
2417 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2418 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2419 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2420 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2421 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2422 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2423 - stream->timing.h_border_right + 1);
4562236b 2424
2f482c4f
CP		 2425 /* Additional Colorimetry Extension
2426 * Used in conduction with C0-C1 and EC0-EC2
2427 * 0 = DCI-P3 RGB (D65)
2428 * 1 = DCI-P3 RGB (theater)
2429 */
2430 hdmi_info.bits.ACE0_ACE3 = 0;
2431
4562236b 2432 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2433 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2434
efa02336 2435 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4562236b 2436
efa02336 2437 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
e09b6473 2438 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2439
2440 /* one byte complement */
2441 *check_sum = (uint8_t) (0x100 - *check_sum);
2442
2443 /* Store in hw_path_mode */
e09b6473
AK		 2444 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2445 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2446 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2447
e09b6473
AK		 2448 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2449 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2450
2451 info_packet->valid = true;
2452}
2453
6e4d6bee 2454static void set_vendor_info_packet(
e09b6473 2455 struct dc_info_packet *info_packet,
0971c40e 2456 struct dc_stream_state *stream)
4562236b 2457{
ecd0136b 2458 /* SPD info packet for FreeSync */
4562236b 2459
ecd0136b
HT		 2460 /* Check if Freesync is supported. Return if false. If true,
2461 * set the corresponding bit in the info packet
2462 */
2463 if (!stream->vsp_infopacket.valid)
4562236b
HW		 2464 return;
2465
ecd0136b 2466 *info_packet = stream->vsp_infopacket;
4562236b
HW		 2467}
2468
6e4d6bee 2469static void set_spd_info_packet(
e09b6473 2470 struct dc_info_packet *info_packet,
0971c40e 2471 struct dc_stream_state *stream)
4562236b
HW		 2472{
2473 /* SPD info packet for FreeSync */
2474
4562236b
HW		 2475 /* Check if Freesync is supported. Return if false. If true,
2476 * set the corresponding bit in the info packet
2477 */
98e6436d 2478 if (!stream->vrr_infopacket.valid)
4562236b
HW		 2479 return;
2480
98e6436d 2481 *info_packet = stream->vrr_infopacket;
4562236b
HW		 2482}
2483
1646a6fe 2484static void set_hdr_static_info_packet(
e09b6473 2485 struct dc_info_packet *info_packet,
0971c40e 2486 struct dc_stream_state *stream)
1646a6fe 2487{
0eeef690 2488 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2489
a10dc97a
KK		 2490 if (!stream->hdr_static_metadata.valid ||
2491 stream->use_dynamic_meta)
10bff005
YS		 2492 return;
2493
0eeef690 2494 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2495}
2496
6e4d6bee 2497static void set_vsc_info_packet(
e09b6473 2498 struct dc_info_packet *info_packet,
0971c40e 2499 struct dc_stream_state *stream)
4562236b 2500{
1336926f 2501 if (!stream->vsc_infopacket.valid)
4562236b
HW		 2502 return;
2503
1336926f 2504 *info_packet = stream->vsc_infopacket;
4562236b
HW		 2505}
2506
f36cc577 2507void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2508{
2509 int i, j;
2510
ab2541b6 2511 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2512 for (j = 0; j < context->stream_status[i].plane_count; j++)
2513 dc_plane_state_release(
2514 context->stream_status[i].plane_states[j]);
4562236b 2515
3be5262e 2516 context->stream_status[i].plane_count = 0;
4fa086b9 2517 dc_stream_release(context->streams[i]);
ab2541b6 2518 context->streams[i] = NULL;
4562236b 2519 }
5728d5e5 2520 context->stream_count = 0;
4562236b
HW		 2521}
2522
f36cc577 2523void dc_resource_state_copy_construct(
608ac7bb
JZ		 2524 const struct dc_state *src_ctx,
2525 struct dc_state *dst_ctx)
4562236b
HW		 2526{
2527 int i, j;
8ee5702a 2528 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2529
2530 *dst_ctx = *src_ctx;
2531
a2b8659d 2532 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2533 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2534
2535 if (cur_pipe->top_pipe)
2536 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2537
2538 if (cur_pipe->bottom_pipe)
2539 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
b1f6d01c
DL		 2540
2541 if (cur_pipe->next_odm_pipe)
2542 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2543
2544 if (cur_pipe->prev_odm_pipe)
2545 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
4562236b
HW		 2546 }
2547
ab2541b6 2548 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2549 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2550 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2551 dc_plane_state_retain(
2552 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2553 }
9a3afbb3
AG		 2554
2555 /* context refcount should not be overridden */
8ee5702a 2556 dst_ctx->refcount = refcount;
9a3afbb3 2557
4562236b
HW		 2558}
2559
2560struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2561 struct resource_context *res_ctx,
2562 const struct resource_pool *pool)
4562236b
HW		 2563{
2564 int i;
2565
a2b8659d 2566 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2567 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2568 return pool->clock_sources[i];
4562236b
HW		 2569 }
2570
2571 return NULL;
2572}
2573
2574void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2575{
2576 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2577 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2578
2579 /* default all packets to invalid */
6e4d6bee
TC		 2580 info->avi.valid = false;
2581 info->gamut.valid = false;
2582 info->vendor.valid = false;
630e3573 2583 info->spd.valid = false;
6e4d6bee
TC		 2584 info->hdrsmd.valid = false;
2585 info->vsc.valid = false;
4562236b
HW		 2586
2587 signal = pipe_ctx->stream->signal;
2588
2589 /* HDMi and DP have different info packets*/
2590 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2591 set_avi_info_frame(&info->avi, pipe_ctx);
2592
2593 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2594
2595 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2596
56ef6ed9 2597 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2598
a33fa99d 2599 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2600 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2601
2602 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2603
56ef6ed9 2604 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2605 }
4562236b 2606
6e4d6bee 2607 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2608}
2609
2610enum dc_status resource_map_clock_resources(
fb3466a4 2611 const struct dc *dc,
608ac7bb 2612 struct dc_state *context,
1dc90497 2613 struct dc_stream_state *stream)
4562236b 2614{
4562236b 2615 /* acquire new resources */
1dc90497
AG		 2616 const struct resource_pool *pool = dc->res_pool;
2617 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2618 &context->res_ctx, stream);
ab2541b6 2619
1dc90497
AG		 2620 if (!pipe_ctx)
2621 return DC_ERROR_UNEXPECTED;
4562236b 2622
1dc90497
AG		 2623 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2624 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2625 pipe_ctx->clock_source = pool->dp_clock_source;
2626 else {
2627 pipe_ctx->clock_source = NULL;
4562236b 2628
1dc90497 2629 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2630 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2631 &context->res_ctx,
2632 pipe_ctx);
4562236b 2633
1dc90497
AG		 2634 if (pipe_ctx->clock_source == NULL)
2635 pipe_ctx->clock_source =
2636 dc_resource_find_first_free_pll(
2637 &context->res_ctx,
2638 pool);
2639 }
4562236b 2640
1dc90497
AG		 2641 if (pipe_ctx->clock_source == NULL)
2642 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2643
1dc90497
AG		 2644 resource_reference_clock_source(
2645 &context->res_ctx, pool,
2646 pipe_ctx->clock_source);
4562236b
HW		 2647
2648 return DC_OK;
2649}
2650
2651/*
2652 * Note: We need to disable output if clock sources change,
2653 * since bios does optimization and doesn't apply if changing
2654 * PHY when not already disabled.
2655 */
2656bool pipe_need_reprogram(
2657 struct pipe_ctx *pipe_ctx_old,
2658 struct pipe_ctx *pipe_ctx)
2659{
cfe4645e
DL		 2660 if (!pipe_ctx_old->stream)
2661 return false;
2662
4562236b
HW		 2663 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2664 return true;
2665
2666 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2667 return true;
2668
afaacef4 2669 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2670 return true;
2671
2672 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2673 && pipe_ctx_old->stream != pipe_ctx->stream)
2674 return true;
2675
8e9c4c8c 2676 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2677 return true;
2678
2679 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2680 return true;
2681
1e7e86c4
ST		 2682 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2683 return true;
2684
eed928dc
CL		 2685 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2686 false == pipe_ctx_old->stream->dpms_off)
2687 return true;
2688
14e49bb3
NC		 2689 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2690 return true;
2691
f42ef862
JK		 2692 /* DIG link encoder resource assignment for stream changed. */
2693 if (pipe_ctx_old->stream->link_enc != pipe_ctx->stream->link_enc)
2694 return true;
2695
4562236b
HW		 2696 return false;
2697}
529cad0f 2698
0971c40e 2699void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2700 struct bit_depth_reduction_params *fmt_bit_depth)
2701{
4fa086b9 2702 enum dc_dither_option option = stream->dither_option;
529cad0f 2703 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2704 stream->timing.pixel_encoding;
529cad0f
DW		 2705
2706 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2707
603767f9
TC		 2708 if (option == DITHER_OPTION_DEFAULT) {
2709 switch (stream->timing.display_color_depth) {
2710 case COLOR_DEPTH_666:
2711 option = DITHER_OPTION_SPATIAL6;
2712 break;
2713 case COLOR_DEPTH_888:
2714 option = DITHER_OPTION_SPATIAL8;
2715 break;
2716 case COLOR_DEPTH_101010:
2717 option = DITHER_OPTION_SPATIAL10;
2718 break;
2719 default:
2720 option = DITHER_OPTION_DISABLE;
2721 }
2722 }
2723
529cad0f
DW		 2724 if (option == DITHER_OPTION_DISABLE)
2725 return;
2726
2727 if (option == DITHER_OPTION_TRUN6) {
2728 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2729 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2730 } else if (option == DITHER_OPTION_TRUN8 ||
2731 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2732 option == DITHER_OPTION_TRUN8_FM6) {
2733 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2734 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2735 } else if (option == DITHER_OPTION_TRUN10 ||
2736 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2737 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2738 option == DITHER_OPTION_TRUN10_FM8 ||
2739 option == DITHER_OPTION_TRUN10_FM6 ||
2740 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2741 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2742 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2743 }
2744
2745 /* special case - Formatter can only reduce by 4 bits at most.
2746 * When reducing from 12 to 6 bits,
2747 * HW recommends we use trunc with round mode
2748 * (if we did nothing, trunc to 10 bits would be used)
2749 * note that any 12->10 bit reduction is ignored prior to DCE8,
2750 * as the input was 10 bits.
2751 */
2752 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2753 option == DITHER_OPTION_SPATIAL6 ||
2754 option == DITHER_OPTION_FM6) {
2755 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2756 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2757 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2758 }
2759
2760 /* spatial dither
2761 * note that spatial modes 1-3 are never used
2762 */
2763 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2764 option == DITHER_OPTION_SPATIAL6 ||
2765 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2766 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2767 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2768 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2769 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2770 fmt_bit_depth->flags.RGB_RANDOM =
2771 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2772 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2773 option == DITHER_OPTION_SPATIAL8 ||
2774 option == DITHER_OPTION_SPATIAL8_FM6 ||
2775 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2776 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2777 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2778 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2779 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2780 fmt_bit_depth->flags.RGB_RANDOM =
2781 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2782 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2783 option == DITHER_OPTION_SPATIAL10 ||
2784 option == DITHER_OPTION_SPATIAL10_FM8 ||
2785 option == DITHER_OPTION_SPATIAL10_FM6) {
2786 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2787 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2788 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2789 fmt_bit_depth->flags.RGB_RANDOM =
2790 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2791 }
2792
2793 if (option == DITHER_OPTION_SPATIAL6 ||
2794 option == DITHER_OPTION_SPATIAL8 ||
2795 option == DITHER_OPTION_SPATIAL10) {
2796 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2797 } else {
2798 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2799 }
2800
2801 //////////////////////
2802 //// temporal dither
2803 //////////////////////
2804 if (option == DITHER_OPTION_FM6 ||
2805 option == DITHER_OPTION_SPATIAL8_FM6 ||
2806 option == DITHER_OPTION_SPATIAL10_FM6 ||
2807 option == DITHER_OPTION_TRUN10_FM6 ||
2808 option == DITHER_OPTION_TRUN8_FM6 ||
2809 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2810 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2811 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2812 } else if (option == DITHER_OPTION_FM8 ||
2813 option == DITHER_OPTION_SPATIAL10_FM8 ||
2814 option == DITHER_OPTION_TRUN10_FM8) {
2815 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2816 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2817 } else if (option == DITHER_OPTION_FM10) {
2818 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2819 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2820 }
2821
2822 fmt_bit_depth->pixel_encoding = pixel_encoding;
2823}
9345d987 2824
62c933f9 2825enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2826{
ceb3dbb4 2827 struct dc_link *link = stream->link;
2b77dcc5 2828 struct timing_generator *tg = dc->res_pool->timing_generators[0];
9345d987
AG		 2829 enum dc_status res = DC_OK;
2830
4fa086b9 2831 calculate_phy_pix_clks(stream);
9345d987 2832
4fa086b9 2833 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2834 res = DC_FAIL_CONTROLLER_VALIDATE;
2835
248cbed6 2836 if (res == DC_OK) {
9345d987 2837 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2838 link->link_enc, stream))
9345d987 2839 res = DC_FAIL_ENC_VALIDATE;
248cbed6 2840 }
9345d987
AG		 2841
2842 /* TODO: validate audio ASIC caps, encoder */
2843
2844 if (res == DC_OK)
4fa086b9 2845 res = dc_link_validate_mode_timing(stream,
9345d987 2846 link,
4fa086b9 2847 &stream->timing);
9345d987 2848
62c933f9 2849 return res;
9345d987 2850}
792671d7 2851
62c933f9 2852enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2853{
62c933f9
YS		 2854 enum dc_status res = DC_OK;
2855
792671d7 2856 /* TODO For now validates pixel format only */
8e7095b9 2857 if (dc->res_pool->funcs->validate_plane)
62c933f9 2858 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2859
62c933f9 2860 return res;
792671d7 2861}
74eac5f3
SSC		 2862
2863unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2864{
2865 switch (format) {
2866 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2867 return 8;
2868 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2869 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2870 return 12;
2871 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2872 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2873 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2874 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2875 return 16;
2876 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2877 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2878 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2879 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2880 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
20f2ffe5 2881#if defined(CONFIG_DRM_AMD_DC_DCN)
5dba4991
BL		 2882 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
2883 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2884#endif
74eac5f3
SSC		 2885 return 32;
2886 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
050cd3d6 2887 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
74eac5f3
SSC		 2888 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2889 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2890 return 64;
2891 default:
2892 ASSERT_CRITICAL(false);
2893 return -1;
2894 }
2895}
3ab4cc65
CL		 2896static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
2897{
2898 if (modes) {
2899 if (modes->sample_rates.rate.RATE_192)
2900 return 192000;
2901 if (modes->sample_rates.rate.RATE_176_4)
2902 return 176400;
2903 if (modes->sample_rates.rate.RATE_96)
2904 return 96000;
2905 if (modes->sample_rates.rate.RATE_88_2)
2906 return 88200;
2907 if (modes->sample_rates.rate.RATE_48)
2908 return 48000;
2909 if (modes->sample_rates.rate.RATE_44_1)
2910 return 44100;
2911 if (modes->sample_rates.rate.RATE_32)
2912 return 32000;
2913 }
2914 /*original logic when no audio info*/
2915 return 441000;
2916}
2917
2918void get_audio_check(struct audio_info *aud_modes,
2919 struct audio_check *audio_chk)
2920{
2921 unsigned int i;
2922 unsigned int max_sample_rate = 0;
2923
2924 if (aud_modes) {
2925 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
2926
2927 audio_chk->max_audiosample_rate = 0;
2928 for (i = 0; i < aud_modes->mode_count; i++) {
2929 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
2930 if (audio_chk->max_audiosample_rate < max_sample_rate)
2931 audio_chk->max_audiosample_rate = max_sample_rate;
2932 /*dts takes the same as type 2: AP = 0.25*/
2933 }
2934 /*check which one take more bandwidth*/
2935 if (audio_chk->max_audiosample_rate > 192000)
2936 audio_chk->audio_packet_type = 0x9;/*AP =1*/
2937 audio_chk->acat = 0;/*not support*/
2938 }
2939}
2940
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