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drm/amd/display: use extended receiver cap for dpcd ver
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b
HW		 1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
5ac3d3c9 34#include "core_types.h"
4562236b 35#include "set_mode_types.h"
4562236b
HW		 36#include "virtual/virtual_stream_encoder.h"
37
38#include "dce80/dce80_resource.h"
39#include "dce100/dce100_resource.h"
40#include "dce110/dce110_resource.h"
41#include "dce112/dce112_resource.h"
2c8ad2d5 42#include "dce120/dce120_resource.h"
4562236b
HW		 43
44enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
45{
46 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
47 switch (asic_id.chip_family) {
48
49 case FAMILY_CI:
50 case FAMILY_KV:
51 dc_version = DCE_VERSION_8_0;
52 break;
53 case FAMILY_CZ:
54 dc_version = DCE_VERSION_11_0;
55 break;
56
57 case FAMILY_VI:
58 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
59 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
60 dc_version = DCE_VERSION_10_0;
61 break;
62 }
63 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 64 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
65 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 66 dc_version = DCE_VERSION_11_2;
67 }
68 break;
2c8ad2d5
AD		 69 case FAMILY_AI:
70 dc_version = DCE_VERSION_12_0;
71 break;
4562236b
HW		 72 default:
73 dc_version = DCE_VERSION_UNKNOWN;
74 break;
75 }
76 return dc_version;
77}
78
79struct resource_pool *dc_create_resource_pool(
80 struct core_dc *dc,
81 int num_virtual_links,
82 enum dce_version dc_version,
83 struct hw_asic_id asic_id)
84{
5ac3d3c9 85 struct resource_pool *res_pool = NULL;
4562236b
HW		 86
87 switch (dc_version) {
88 case DCE_VERSION_8_0:
5ac3d3c9 89 res_pool = dce80_create_resource_pool(
4562236b 90 num_virtual_links, dc);
5ac3d3c9 91 break;
4562236b 92 case DCE_VERSION_10_0:
5ac3d3c9 93 res_pool = dce100_create_resource_pool(
4562236b 94 num_virtual_links, dc);
5ac3d3c9 95 break;
4562236b 96 case DCE_VERSION_11_0:
5ac3d3c9 97 res_pool = dce110_create_resource_pool(
4562236b 98 num_virtual_links, dc, asic_id);
5ac3d3c9 99 break;
4562236b 100 case DCE_VERSION_11_2:
5ac3d3c9 101 res_pool = dce112_create_resource_pool(
4562236b 102 num_virtual_links, dc);
5ac3d3c9 103 break;
2c8ad2d5
AD		 104 case DCE_VERSION_12_0:
105 res_pool = dce120_create_resource_pool(
106 num_virtual_links, dc);
107 break;
4562236b
HW		 108 default:
109 break;
110 }
5ac3d3c9
CL		 111 if (res_pool != NULL) {
112 struct firmware_info fw_info = { { 0 } };
113
114 if (dc->ctx->dc_bios->funcs->get_firmware_info(
115 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
116 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
117 } else
118 ASSERT_CRITICAL(false);
119 }
4562236b 120
5ac3d3c9 121 return res_pool;
4562236b
HW		 122}
123
124void dc_destroy_resource_pool(struct core_dc *dc)
125{
126 if (dc) {
127 if (dc->res_pool)
128 dc->res_pool->funcs->destroy(&dc->res_pool);
129
130 if (dc->hwseq)
131 dm_free(dc->hwseq);
132 }
133}
134
135static void update_num_audio(
136 const struct resource_straps *straps,
137 unsigned int *num_audio,
138 struct audio_support *aud_support)
139{
140 if (straps->hdmi_disable == 0) {
141 aud_support->hdmi_audio_native = true;
142 aud_support->hdmi_audio_on_dongle = true;
143 aud_support->dp_audio = true;
144 } else {
145 if (straps->dc_pinstraps_audio & 0x2) {
146 aud_support->hdmi_audio_on_dongle = true;
147 aud_support->dp_audio = true;
148 } else {
149 aud_support->dp_audio = true;
150 }
151 }
152
153 switch (straps->audio_stream_number) {
154 case 0: /* multi streams supported */
155 break;
156 case 1: /* multi streams not supported */
157 *num_audio = 1;
158 break;
159 default:
160 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 161 }
4562236b
HW		 162}
163
164bool resource_construct(
165 unsigned int num_virtual_links,
166 struct core_dc *dc,
167 struct resource_pool *pool,
168 const struct resource_create_funcs *create_funcs)
169{
170 struct dc_context *ctx = dc->ctx;
171 const struct resource_caps *caps = pool->res_cap;
172 int i;
173 unsigned int num_audio = caps->num_audio;
174 struct resource_straps straps = {0};
175
176 if (create_funcs->read_dce_straps)
177 create_funcs->read_dce_straps(dc->ctx, &straps);
178
179 pool->audio_count = 0;
180 if (create_funcs->create_audio) {
181 /* find the total number of streams available via the
182 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
183 * registers (one for each pin) starting from pin 1
184 * up to the max number of audio pins.
185 * We stop on the first pin where
186 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
187 */
188 update_num_audio(&straps, &num_audio, &pool->audio_support);
189 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
190 struct audio *aud = create_funcs->create_audio(ctx, i);
191
192 if (aud == NULL) {
193 DC_ERR("DC: failed to create audio!\n");
194 return false;
195 }
196
197 if (!aud->funcs->endpoint_valid(aud)) {
198 aud->funcs->destroy(&aud);
199 break;
200 }
201
202 pool->audios[i] = aud;
203 pool->audio_count++;
204 }
205 }
206
207 pool->stream_enc_count = 0;
208 if (create_funcs->create_stream_encoder) {
209 for (i = 0; i < caps->num_stream_encoder; i++) {
210 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
211 if (pool->stream_enc[i] == NULL)
212 DC_ERR("DC: failed to create stream_encoder!\n");
213 pool->stream_enc_count++;
214 }
215 }
216
217 for (i = 0; i < num_virtual_links; i++) {
218 pool->stream_enc[pool->stream_enc_count] =
219 virtual_stream_encoder_create(
220 ctx, ctx->dc_bios);
221 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
222 DC_ERR("DC: failed to create stream_encoder!\n");
223 return false;
224 }
225 pool->stream_enc_count++;
226 }
227
228 dc->hwseq = create_funcs->create_hwseq(ctx);
229
230 return true;
231}
232
233
234void resource_unreference_clock_source(
235 struct resource_context *res_ctx,
8c737fcc 236 struct clock_source **clock_source)
4562236b
HW		 237{
238 int i;
239 for (i = 0; i < res_ctx->pool->clk_src_count; i++) {
8c737fcc 240 if (res_ctx->pool->clock_sources[i] != *clock_source)
4562236b
HW		 241 continue;
242
243 res_ctx->clock_source_ref_count[i]--;
244
245 if (res_ctx->clock_source_ref_count[i] == 0)
8c737fcc 246 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b
HW		 247
248 break;
249 }
250
8c737fcc 251 if (res_ctx->pool->dp_clock_source == *clock_source) {
4562236b
HW		 252 res_ctx->dp_clock_source_ref_count--;
253
254 if (res_ctx->dp_clock_source_ref_count == 0)
8c737fcc 255 (*clock_source)->funcs->cs_power_down(*clock_source);
4562236b 256 }
8c737fcc 257 *clock_source = NULL;
4562236b
HW		 258}
259
260void resource_reference_clock_source(
261 struct resource_context *res_ctx,
262 struct clock_source *clock_source)
263{
264 int i;
265 for (i = 0; i < res_ctx->pool->clk_src_count; i++) {
266 if (res_ctx->pool->clock_sources[i] != clock_source)
267 continue;
268
269 res_ctx->clock_source_ref_count[i]++;
270 break;
271 }
272
273 if (res_ctx->pool->dp_clock_source == clock_source)
274 res_ctx->dp_clock_source_ref_count++;
275}
276
277bool resource_are_streams_timing_synchronizable(
278 const struct core_stream *stream1,
279 const struct core_stream *stream2)
280{
281 if (stream1->public.timing.h_total != stream2->public.timing.h_total)
282 return false;
283
284 if (stream1->public.timing.v_total != stream2->public.timing.v_total)
285 return false;
286
287 if (stream1->public.timing.h_addressable
288 != stream2->public.timing.h_addressable)
289 return false;
290
291 if (stream1->public.timing.v_addressable
292 != stream2->public.timing.v_addressable)
293 return false;
294
295 if (stream1->public.timing.pix_clk_khz
296 != stream2->public.timing.pix_clk_khz)
297 return false;
298
299 if (stream1->phy_pix_clk != stream2->phy_pix_clk
300 && !dc_is_dp_signal(stream1->signal)
301 && !dc_is_dp_signal(stream2->signal))
302 return false;
303
304 return true;
305}
306
307static bool is_sharable_clk_src(
308 const struct pipe_ctx *pipe_with_clk_src,
309 const struct pipe_ctx *pipe)
310{
311 if (pipe_with_clk_src->clock_source == NULL)
312 return false;
313
314 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
315 return false;
316
317 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
318 return false;
319
320 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
321 && dc_is_dvi_signal(pipe->stream->signal))
322 return false;
323
324 if (dc_is_hdmi_signal(pipe->stream->signal)
325 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
326 return false;
327
328 if (!resource_are_streams_timing_synchronizable(
329 pipe_with_clk_src->stream, pipe->stream))
330 return false;
331
332 return true;
333}
334
335struct clock_source *resource_find_used_clk_src_for_sharing(
336 struct resource_context *res_ctx,
337 struct pipe_ctx *pipe_ctx)
338{
339 int i;
340
341 for (i = 0; i < MAX_PIPES; i++) {
342 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
343 return res_ctx->pipe_ctx[i].clock_source;
344 }
345
346 return NULL;
347}
348
349static enum pixel_format convert_pixel_format_to_dalsurface(
350 enum surface_pixel_format surface_pixel_format)
351{
352 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
353
354 switch (surface_pixel_format) {
355 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
356 dal_pixel_format = PIXEL_FORMAT_INDEX8;
357 break;
358 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
359 dal_pixel_format = PIXEL_FORMAT_RGB565;
360 break;
361 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
362 dal_pixel_format = PIXEL_FORMAT_RGB565;
363 break;
364 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
365 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
366 break;
8693049a 367 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 368 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
369 break;
370 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
371 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
372 break;
373 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
374 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
375 break;
376 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
377 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
378 break;
379 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
380 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
381 dal_pixel_format = PIXEL_FORMAT_FP16;
382 break;
383 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b
HW		 384 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
385 dal_pixel_format = PIXEL_FORMAT_420BPP12;
386 break;
ffbcd19a
VP		 387 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
388 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
389 dal_pixel_format = PIXEL_FORMAT_420BPP15;
390 break;
4562236b
HW		 391 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
392 default:
393 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
394 break;
395 }
396 return dal_pixel_format;
397}
398
399static void rect_swap_helper(struct rect *rect)
400{
401 uint32_t temp = 0;
402
403 temp = rect->height;
404 rect->height = rect->width;
405 rect->width = temp;
406
407 temp = rect->x;
408 rect->x = rect->y;
409 rect->y = temp;
410}
411
b2d0a103 412static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 413{
b2d0a103 414 const struct dc_surface *surface = &pipe_ctx->surface->public;
1fbd2cfc 415 const struct dc_stream *stream = &pipe_ctx->stream->public;
b2d0a103 416 struct scaler_data *data = &pipe_ctx->scl_data;
1fbd2cfc 417 struct rect clip = { 0 };
b2d0a103
DL		 418 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
419 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
1fbd2cfc
DL		 420 bool pri_split = pipe_ctx->bottom_pipe &&
421 pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
422 bool sec_split = pipe_ctx->top_pipe &&
423 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
4562236b
HW		 424
425 /* The actual clip is an intersection between stream
426 * source and surface clip
427 */
1fbd2cfc
DL		 428 clip.x = stream->src.x > surface->clip_rect.x ?
429 stream->src.x : surface->clip_rect.x;
4562236b 430
1fbd2cfc
DL		 431 clip.width = stream->src.x + stream->src.width <
432 surface->clip_rect.x + surface->clip_rect.width ?
433 stream->src.x + stream->src.width - clip.x :
434 surface->clip_rect.x + surface->clip_rect.width - clip.x ;
4562236b 435
1fbd2cfc
DL		 436 clip.y = stream->src.y > surface->clip_rect.y ?
437 stream->src.y : surface->clip_rect.y;
4562236b 438
1fbd2cfc
DL		 439 clip.height = stream->src.y + stream->src.height <
440 surface->clip_rect.y + surface->clip_rect.height ?
441 stream->src.y + stream->src.height - clip.y :
442 surface->clip_rect.y + surface->clip_rect.height - clip.y ;
4562236b 443
1fbd2cfc 444 /* offset = src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 445 * num_pixels = clip.num_pix * scl_ratio
446 */
1fbd2cfc
DL		 447 data->viewport.x = surface->src_rect.x + (clip.x - surface->dst_rect.x) *
448 surface->src_rect.width / surface->dst_rect.width;
b2d0a103 449 data->viewport.width = clip.width *
1fbd2cfc 450 surface->src_rect.width / surface->dst_rect.width;
4562236b 451
1fbd2cfc
DL		 452 data->viewport.y = surface->src_rect.y + (clip.y - surface->dst_rect.y) *
453 surface->src_rect.height / surface->dst_rect.height;
b2d0a103 454 data->viewport.height = clip.height *
1fbd2cfc 455 surface->src_rect.height / surface->dst_rect.height;
4562236b 456
b2d0a103
DL		 457 /* Round down, compensate in init */
458 data->viewport_c.x = data->viewport.x / vpc_div;
459 data->viewport_c.y = data->viewport.y / vpc_div;
460 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
461 dal_fixed31_32_half : dal_fixed31_32_zero;
462 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
463 dal_fixed31_32_half : dal_fixed31_32_zero;
464 /* Round up, assume original video size always even dimensions */
465 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
466 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
467
468 /* Handle hsplit */
1fbd2cfc
DL		 469 if (pri_split || sec_split) {
470 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
471 bool right_view = (sec_split != surface->horizontal_mirror) !=
472 (surface->rotation == ROTATION_ANGLE_180);
473
474 if (surface->rotation == ROTATION_ANGLE_90
475 || surface->rotation == ROTATION_ANGLE_270)
476 /* Secondary_pipe XOR Rotation_270 */
477 right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 478
479 if (right_view) {
480 data->viewport.width /= 2;
481 data->viewport_c.width /= 2;
482 data->viewport.x += data->viewport.width;
483 data->viewport_c.x += data->viewport_c.width;
484 /* Ceil offset pipe */
485 data->viewport.width += data->viewport.width % 2;
486 data->viewport_c.width += data->viewport_c.width % 2;
487 } else {
488 data->viewport.width /= 2;
489 data->viewport_c.width /= 2;
490 }
b2d0a103 491 }
1fbd2cfc
DL		 492
493 if (surface->rotation == ROTATION_ANGLE_90 ||
494 surface->rotation == ROTATION_ANGLE_270) {
495 rect_swap_helper(&data->viewport_c);
496 rect_swap_helper(&data->viewport);
497 }
4562236b
HW		 498}
499
b2d0a103 500static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 501{
b2d0a103 502 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b
HW		 503 struct core_stream *stream = pipe_ctx->stream;
504 struct rect clip = surface->clip_rect;
c802570e 505 int recout_full_x, recout_full_y;
4562236b
HW		 506
507 pipe_ctx->scl_data.recout.x = stream->public.dst.x;
508 if (stream->public.src.x < clip.x)
509 pipe_ctx->scl_data.recout.x += (clip.x
510 - stream->public.src.x) * stream->public.dst.width
511 / stream->public.src.width;
512
513 pipe_ctx->scl_data.recout.width = clip.width *
514 stream->public.dst.width / stream->public.src.width;
515 if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x >
516 stream->public.dst.x + stream->public.dst.width)
517 pipe_ctx->scl_data.recout.width =
518 stream->public.dst.x + stream->public.dst.width
519 - pipe_ctx->scl_data.recout.x;
520
521 pipe_ctx->scl_data.recout.y = stream->public.dst.y;
522 if (stream->public.src.y < clip.y)
523 pipe_ctx->scl_data.recout.y += (clip.y
524 - stream->public.src.y) * stream->public.dst.height
525 / stream->public.src.height;
526
527 pipe_ctx->scl_data.recout.height = clip.height *
528 stream->public.dst.height / stream->public.src.height;
529 if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y >
530 stream->public.dst.y + stream->public.dst.height)
531 pipe_ctx->scl_data.recout.height =
532 stream->public.dst.y + stream->public.dst.height
533 - pipe_ctx->scl_data.recout.y;
b2d0a103
DL		 534
535 /* Handle hsplit */
536 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
537 pipe_ctx->scl_data.recout.width /= 2;
538 pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
539 /* Floor primary pipe, ceil 2ndary pipe */
540 pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
541 } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
542 pipe_ctx->scl_data.recout.width /= 2;
543 }
544
c802570e
DL		 545 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream src offset)
546 * * 1/ stream scaling ratio) - (surf src offset * 1/ full scl
547 * ratio)
548 */
549 recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x)
550 * stream->public.dst.width / stream->public.src.width -
551 surface->src_rect.x * surface->dst_rect.width / surface->src_rect.width
552 * stream->public.dst.width / stream->public.src.width;
553 recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y)
554 * stream->public.dst.height / stream->public.src.height -
555 surface->src_rect.y * surface->dst_rect.height / surface->src_rect.height
556 * stream->public.dst.height / stream->public.src.height;
557
558 recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
559 recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
4562236b
HW		 560}
561
b2d0a103 562static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 563{
b2d0a103 564 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 565 struct core_stream *stream = pipe_ctx->stream;
1fbd2cfc
DL		 566 const int in_w = stream->public.src.width;
567 const int in_h = stream->public.src.height;
568 const int out_w = stream->public.dst.width;
569 const int out_h = stream->public.dst.height;
4562236b
HW		 570
571 pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
572 surface->src_rect.width,
573 surface->dst_rect.width);
574 pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
575 surface->src_rect.height,
576 surface->dst_rect.height);
577
578 if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
579 pipe_ctx->scl_data.ratios.horz.value *= 2;
580 else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
581 pipe_ctx->scl_data.ratios.vert.value *= 2;
582
583 pipe_ctx->scl_data.ratios.vert.value = div64_s64(
584 pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
585 pipe_ctx->scl_data.ratios.horz.value = div64_s64(
586 pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
587
588 pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
589 pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
590
b2d0a103
DL		 591 if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
592 || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
4562236b
HW		 593 pipe_ctx->scl_data.ratios.horz_c.value /= 2;
594 pipe_ctx->scl_data.ratios.vert_c.value /= 2;
595 }
596}
597
b2d0a103
DL		 598static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
599{
600 struct scaler_data *data = &pipe_ctx->scl_data;
601 struct rect src = pipe_ctx->surface->public.src_rect;
602 int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
603 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
604
1fbd2cfc
DL		 605 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
606 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
607 rect_swap_helper(&data->viewport_c);
608 rect_swap_helper(&data->viewport);
609 }
610
b2d0a103
DL		 611 /*
612 * Init calculated according to formula:
613 * init = (scaling_ratio + number_of_taps + 1) / 2
614 * init_bot = init + scaling_ratio
615 * init_c = init + truncated_vp_c_offset(from calculate viewport)
616 */
617 data->inits.h = dal_fixed31_32_div_int(
618 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
619
620 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
621 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
622
623 data->inits.v = dal_fixed31_32_div_int(
624 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
625
626 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
627 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
628
629
630 /* Adjust for viewport end clip-off */
631 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
632 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 633 int int_part = dal_fixed31_32_floor(
634 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 635
1fbd2cfc 636 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 637 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
638 }
639 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
640 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 641 int int_part = dal_fixed31_32_floor(
642 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 643
1fbd2cfc 644 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 645 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
646 }
647 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
648 int vp_clip = (src.x + src.width) / vpc_div -
649 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 650 int int_part = dal_fixed31_32_floor(
651 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 652
1fbd2cfc 653 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 654 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
655 }
656 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
657 int vp_clip = (src.y + src.height) / vpc_div -
658 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 659 int int_part = dal_fixed31_32_floor(
660 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 661
1fbd2cfc 662 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 663 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
664 }
665
666 /* Adjust for non-0 viewport offset */
667 if (data->viewport.x) {
668 int int_part;
669
670 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
671 data->ratios.horz, recout_skip->width));
672 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
673 if (int_part < data->taps.h_taps) {
674 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
675 (data->taps.h_taps - int_part) : data->viewport.x;
676 data->viewport.x -= int_adj;
677 data->viewport.width += int_adj;
678 int_part += int_adj;
679 } else if (int_part > data->taps.h_taps) {
680 data->viewport.x += int_part - data->taps.h_taps;
681 data->viewport.width -= int_part - data->taps.h_taps;
682 int_part = data->taps.h_taps;
683 }
684 data->inits.h.value &= 0xffffffff;
685 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
686 }
687
688 if (data->viewport_c.x) {
689 int int_part;
690
691 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
692 data->ratios.horz_c, recout_skip->width));
693 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
694 if (int_part < data->taps.h_taps_c) {
695 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
696 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
697 data->viewport_c.x -= int_adj;
698 data->viewport_c.width += int_adj;
699 int_part += int_adj;
700 } else if (int_part > data->taps.h_taps_c) {
701 data->viewport_c.x += int_part - data->taps.h_taps_c;
702 data->viewport_c.width -= int_part - data->taps.h_taps_c;
703 int_part = data->taps.h_taps_c;
704 }
705 data->inits.h_c.value &= 0xffffffff;
706 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
707 }
708
709 if (data->viewport.y) {
710 int int_part;
711
712 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
713 data->ratios.vert, recout_skip->height));
714 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
715 if (int_part < data->taps.v_taps) {
716 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
717 (data->taps.v_taps - int_part) : data->viewport.y;
718 data->viewport.y -= int_adj;
719 data->viewport.height += int_adj;
720 int_part += int_adj;
721 } else if (int_part > data->taps.v_taps) {
722 data->viewport.y += int_part - data->taps.v_taps;
723 data->viewport.height -= int_part - data->taps.v_taps;
724 int_part = data->taps.v_taps;
725 }
726 data->inits.v.value &= 0xffffffff;
727 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
728 }
729
730 if (data->viewport_c.y) {
731 int int_part;
732
733 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
734 data->ratios.vert_c, recout_skip->height));
735 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
736 if (int_part < data->taps.v_taps_c) {
737 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
738 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
739 data->viewport_c.y -= int_adj;
740 data->viewport_c.height += int_adj;
741 int_part += int_adj;
742 } else if (int_part > data->taps.v_taps_c) {
743 data->viewport_c.y += int_part - data->taps.v_taps_c;
744 data->viewport_c.height -= int_part - data->taps.v_taps_c;
745 int_part = data->taps.v_taps_c;
746 }
747 data->inits.v_c.value &= 0xffffffff;
748 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
749 }
750
751 /* Interlaced inits based on final vert inits */
752 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
753 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc
DL		 754
755 if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
756 pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
757 rect_swap_helper(&data->viewport_c);
758 rect_swap_helper(&data->viewport);
759 }
b2d0a103
DL		 760}
761
762bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 763{
b2d0a103 764 const struct dc_surface *surface = &pipe_ctx->surface->public;
4562236b 765 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
b2d0a103
DL		 766 struct view recout_skip = { 0 };
767 bool res = false;
768
4562236b
HW		 769 /* Important: scaling ratio calculation requires pixel format,
770 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 771 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 772 */
b2d0a103
DL		 773 pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
774 pipe_ctx->surface->public.format);
775
776 calculate_scaling_ratios(pipe_ctx);
4562236b 777
b2d0a103 778 calculate_viewport(pipe_ctx);
4562236b
HW		 779
780 if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
781 return false;
782
b2d0a103 783 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 784
785 /**
786 * Setting line buffer pixel depth to 24bpp yields banding
787 * on certain displays, such as the Sharp 4k
788 */
789 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
790
791 pipe_ctx->scl_data.h_active = timing->h_addressable;
792 pipe_ctx->scl_data.v_active = timing->v_addressable;
793
794 /* Taps calculations */
795 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
796 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
797
798 if (!res) {
799 /* Try 24 bpp linebuffer */
800 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
801
802 res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps(
803 pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
804 }
805
b2d0a103 806 if (res)
1fbd2cfc 807 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 808 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
809
4562236b
HW		 810 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
811 "%s: Viewport:\nheight:%d width:%d x:%d "
812 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
813 "y:%d\n",
814 __func__,
815 pipe_ctx->scl_data.viewport.height,
816 pipe_ctx->scl_data.viewport.width,
817 pipe_ctx->scl_data.viewport.x,
818 pipe_ctx->scl_data.viewport.y,
819 surface->dst_rect.height,
820 surface->dst_rect.width,
821 surface->dst_rect.x,
822 surface->dst_rect.y);
823
824 return res;
825}
826
827
828enum dc_status resource_build_scaling_params_for_context(
829 const struct core_dc *dc,
830 struct validate_context *context)
831{
832 int i;
833
834 for (i = 0; i < MAX_PIPES; i++) {
835 if (context->res_ctx.pipe_ctx[i].surface != NULL &&
836 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 837 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 838 return DC_FAIL_SCALING;
4562236b
HW		 839 }
840
841 return DC_OK;
842}
843
ab2541b6 844static void detach_surfaces_for_stream(
4562236b 845 struct validate_context *context,
ab2541b6 846 const struct dc_stream *dc_stream)
4562236b
HW		 847{
848 int i;
ab2541b6 849 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 850
851 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
852 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
853 if (cur_pipe->stream == stream) {
854 cur_pipe->surface = NULL;
855 cur_pipe->top_pipe = NULL;
856 cur_pipe->bottom_pipe = NULL;
857 }
858 }
859}
860
861struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx)
862{
863 int i;
864 struct pipe_ctx *secondary_pipe = NULL;
865
866 /*
867 * search backwards for the second pipe to keep pipe
868 * assignment more consistent
869 */
870
871 for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) {
872 if (res_ctx->pipe_ctx[i].stream == NULL) {
873 secondary_pipe = &res_ctx->pipe_ctx[i];
874 secondary_pipe->pipe_idx = i;
875 break;
876 }
877 }
878
879
880 return secondary_pipe;
881}
882
883struct pipe_ctx *resource_get_head_pipe_for_stream(
884 struct resource_context *res_ctx,
885 const struct core_stream *stream)
886{
887 int i;
888 for (i = 0; i < res_ctx->pool->pipe_count; i++) {
889 if (res_ctx->pipe_ctx[i].stream == stream &&
890 !res_ctx->pipe_ctx[i].top_pipe) {
891 return &res_ctx->pipe_ctx[i];
892 break;
893 }
894 }
895 return NULL;
896}
897
898/*
ab2541b6
AC		 899 * A free_pipe for a stream is defined here as a pipe
900 * that has no surface attached yet
4562236b 901 */
ab2541b6 902static struct pipe_ctx *acquire_free_pipe_for_stream(
4562236b 903 struct resource_context *res_ctx,
ab2541b6 904 const struct dc_stream *dc_stream)
4562236b
HW		 905{
906 int i;
ab2541b6 907 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 908
909 struct pipe_ctx *head_pipe = NULL;
910
911 /* Find head pipe, which has the back end set up*/
912
913 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
914
915 if (!head_pipe)
916 ASSERT(0);
917
918 if (!head_pipe->surface)
919 return head_pipe;
920
921 /* Re-use pipe already acquired for this stream if available*/
922 for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) {
923 if (res_ctx->pipe_ctx[i].stream == stream &&
924 !res_ctx->pipe_ctx[i].surface) {
925 return &res_ctx->pipe_ctx[i];
926 }
927 }
928
929 /*
930 * At this point we have no re-useable pipe for this stream and we need
931 * to acquire an idle one to satisfy the request
932 */
933
934 if(!res_ctx->pool->funcs->acquire_idle_pipe_for_layer)
935 return NULL;
936
937 return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(res_ctx, stream);
938
939}
940
ab2541b6 941static void release_free_pipes_for_stream(
4562236b 942 struct resource_context *res_ctx,
ab2541b6 943 const struct dc_stream *dc_stream)
4562236b
HW		 944{
945 int i;
ab2541b6 946 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
4562236b
HW		 947
948 for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) {
949 if (res_ctx->pipe_ctx[i].stream == stream &&
950 !res_ctx->pipe_ctx[i].surface) {
951 res_ctx->pipe_ctx[i].stream = NULL;
952 }
953 }
954}
955
956bool resource_attach_surfaces_to_context(
957 const struct dc_surface * const *surfaces,
958 int surface_count,
ab2541b6 959 const struct dc_stream *dc_stream,
4562236b
HW		 960 struct validate_context *context)
961{
962 int i;
963 struct pipe_ctx *tail_pipe;
ab2541b6 964 struct dc_stream_status *stream_status = NULL;
4562236b
HW		 965
966
967 if (surface_count > MAX_SURFACE_NUM) {
968 dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
969 surface_count, MAX_SURFACE_NUM);
970 return false;
971 }
972
ab2541b6
AC		 973 for (i = 0; i < context->stream_count; i++)
974 if (&context->streams[i]->public == dc_stream) {
975 stream_status = &context->stream_status[i];
4562236b
HW		 976 break;
977 }
ab2541b6
AC		 978 if (stream_status == NULL) {
979 dm_error("Existing stream not found; failed to attach surfaces\n");
4562236b
HW		 980 return false;
981 }
982
983 /* retain new surfaces */
984 for (i = 0; i < surface_count; i++)
985 dc_surface_retain(surfaces[i]);
986
ab2541b6 987 detach_surfaces_for_stream(context, dc_stream);
4562236b
HW		 988
989 /* release existing surfaces*/
ab2541b6
AC		 990 for (i = 0; i < stream_status->surface_count; i++)
991 dc_surface_release(stream_status->surfaces[i]);
4562236b 992
ab2541b6
AC		 993 for (i = surface_count; i < stream_status->surface_count; i++)
994 stream_status->surfaces[i] = NULL;
4562236b 995
ab2541b6 996 stream_status->surface_count = 0;
4562236b
HW		 997
998 if (surface_count == 0)
999 return true;
1000
1001 tail_pipe = NULL;
1002 for (i = 0; i < surface_count; i++) {
1003 struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
ab2541b6
AC		 1004 struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(
1005 &context->res_ctx, dc_stream);
4562236b
HW		 1006
1007 if (!free_pipe) {
ab2541b6 1008 stream_status->surfaces[i] = NULL;
4562236b
HW		 1009 return false;
1010 }
1011
1012 free_pipe->surface = surface;
1013
1014 if (tail_pipe) {
1015 free_pipe->top_pipe = tail_pipe;
1016 tail_pipe->bottom_pipe = free_pipe;
1017 }
1018
1019 tail_pipe = free_pipe;
1020 }
1021
ab2541b6 1022 release_free_pipes_for_stream(&context->res_ctx, dc_stream);
4562236b
HW		 1023
1024 /* assign new surfaces*/
1025 for (i = 0; i < surface_count; i++)
ab2541b6 1026 stream_status->surfaces[i] = surfaces[i];
4562236b 1027
ab2541b6 1028 stream_status->surface_count = surface_count;
4562236b
HW		 1029
1030 return true;
1031}
1032
1033
1034static bool is_timing_changed(const struct core_stream *cur_stream,
1035 const struct core_stream *new_stream)
1036{
1037 if (cur_stream == NULL)
1038 return true;
1039
1040 /* If sink pointer changed, it means this is a hotplug, we should do
1041 * full hw setting.
1042 */
1043 if (cur_stream->sink != new_stream->sink)
1044 return true;
1045
1046 /* If output color space is changed, need to reprogram info frames */
1047 if (cur_stream->public.output_color_space !=
1048 new_stream->public.output_color_space)
1049 return true;
1050
1051 return memcmp(
1052 &cur_stream->public.timing,
1053 &new_stream->public.timing,
1054 sizeof(struct dc_crtc_timing)) != 0;
1055}
1056
1057static bool are_stream_backends_same(
1058 const struct core_stream *stream_a, const struct core_stream *stream_b)
1059{
1060 if (stream_a == stream_b)
1061 return true;
1062
1063 if (stream_a == NULL || stream_b == NULL)
1064 return false;
1065
1066 if (is_timing_changed(stream_a, stream_b))
1067 return false;
1068
1069 return true;
1070}
1071
ab2541b6
AC		 1072bool is_stream_unchanged(
1073 const struct core_stream *old_stream, const struct core_stream *stream)
4562236b 1074{
ab2541b6 1075 if (old_stream == stream)
4562236b 1076 return true;
4562236b 1077
ab2541b6
AC		 1078 if (!are_stream_backends_same(old_stream, stream))
1079 return false;
4562236b
HW		 1080
1081 return true;
1082}
1083
1084bool resource_validate_attach_surfaces(
1085 const struct dc_validation_set set[],
1086 int set_count,
1087 const struct validate_context *old_context,
1088 struct validate_context *context)
1089{
1090 int i, j;
1091
1092 for (i = 0; i < set_count; i++) {
ab2541b6
AC		 1093 for (j = 0; j < old_context->stream_count; j++)
1094 if (is_stream_unchanged(
1095 old_context->streams[j],
1096 context->streams[i])) {
4562236b 1097 if (!resource_attach_surfaces_to_context(
ab2541b6
AC		 1098 old_context->stream_status[j].surfaces,
1099 old_context->stream_status[j].surface_count,
1100 &context->streams[i]->public,
4562236b
HW		 1101 context))
1102 return false;
ab2541b6 1103 context->stream_status[i] = old_context->stream_status[j];
4562236b
HW		 1104 }
1105 if (set[i].surface_count != 0)
1106 if (!resource_attach_surfaces_to_context(
1107 set[i].surfaces,
1108 set[i].surface_count,
ab2541b6 1109 &context->streams[i]->public,
4562236b
HW		 1110 context))
1111 return false;
1112
1113 }
1114
1115 return true;
1116}
1117
1118/* Maximum TMDS single link pixel clock 165MHz */
1119#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1120
1121static void set_stream_engine_in_use(
1122 struct resource_context *res_ctx,
1123 struct stream_encoder *stream_enc)
1124{
1125 int i;
1126
1127 for (i = 0; i < res_ctx->pool->stream_enc_count; i++) {
1128 if (res_ctx->pool->stream_enc[i] == stream_enc)
1129 res_ctx->is_stream_enc_acquired[i] = true;
1130 }
1131}
1132
1133/* TODO: release audio object */
1134static void set_audio_in_use(
1135 struct resource_context *res_ctx,
1136 struct audio *audio)
1137{
1138 int i;
1139 for (i = 0; i < res_ctx->pool->audio_count; i++) {
1140 if (res_ctx->pool->audios[i] == audio) {
1141 res_ctx->is_audio_acquired[i] = true;
1142 }
1143 }
1144}
1145
1146static int acquire_first_free_pipe(
1147 struct resource_context *res_ctx,
1148 struct core_stream *stream)
1149{
1150 int i;
1151
1152 for (i = 0; i < res_ctx->pool->pipe_count; i++) {
1153 if (!res_ctx->pipe_ctx[i].stream) {
1154 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1155
1156 pipe_ctx->tg = res_ctx->pool->timing_generators[i];
1157 pipe_ctx->mi = res_ctx->pool->mis[i];
1158 pipe_ctx->ipp = res_ctx->pool->ipps[i];
1159 pipe_ctx->xfm = res_ctx->pool->transforms[i];
1160 pipe_ctx->opp = res_ctx->pool->opps[i];
1161 pipe_ctx->dis_clk = res_ctx->pool->display_clock;
1162 pipe_ctx->pipe_idx = i;
1163
1164 pipe_ctx->stream = stream;
1165 return i;
1166 }
1167 }
1168 return -1;
1169}
1170
1171static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1172 struct resource_context *res_ctx,
1173 struct core_stream *stream)
1174{
1175 int i;
1176 int j = -1;
1177 struct core_link *link = stream->sink->link;
1178
1179 for (i = 0; i < res_ctx->pool->stream_enc_count; i++) {
1180 if (!res_ctx->is_stream_enc_acquired[i] &&
1181 res_ctx->pool->stream_enc[i]) {
1182 /* Store first available for MST second display
1183 * in daisy chain use case */
1184 j = i;
1185 if (res_ctx->pool->stream_enc[i]->id ==
1186 link->link_enc->preferred_engine)
1187 return res_ctx->pool->stream_enc[i];
1188 }
1189 }
1190
1191 /*
1192 * below can happen in cases when stream encoder is acquired:
1193 * 1) for second MST display in chain, so preferred engine already
1194 * acquired;
1195 * 2) for another link, which preferred engine already acquired by any
1196 * MST configuration.
1197 *
1198 * If signal is of DP type and preferred engine not found, return last available
1199 *
1200 * TODO - This is just a patch up and a generic solution is
1201 * required for non DP connectors.
1202 */
1203
1204 if (j >= 0 && dc_is_dp_signal(stream->signal))
1205 return res_ctx->pool->stream_enc[j];
1206
1207 return NULL;
1208}
1209
1210static struct audio *find_first_free_audio(struct resource_context *res_ctx)
1211{
1212 int i;
1213 for (i = 0; i < res_ctx->pool->audio_count; i++) {
1214 if (res_ctx->is_audio_acquired[i] == false) {
1215 return res_ctx->pool->audios[i];
1216 }
1217 }
1218
1219 return 0;
1220}
1221
1222static void update_stream_signal(struct core_stream *stream)
1223{
1224 const struct dc_sink *dc_sink = stream->public.sink;
1225
2796eaee
JA		 1226 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
1227 stream->signal = stream->sink->link->public.connector_signal;
1228 else if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
1229 dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK)
1230 /* For asic supports dual link DVI, we should adjust signal type
1231 * based on timing pixel clock. If pixel clock more than 165Mhz,
1232 * signal is dual link, otherwise, single link.
1233 */
1234 if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
4562236b
HW		 1235 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1236 else
1237 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2796eaee
JA		 1238 else
1239 stream->signal = dc_sink->sink_signal;
4562236b
HW		 1240}
1241
1242bool resource_is_stream_unchanged(
ab2541b6 1243 const struct validate_context *old_context, const struct core_stream *stream)
4562236b 1244{
ab2541b6 1245 int i;
4562236b 1246
ab2541b6
AC		 1247 for (i = 0; i < old_context->stream_count; i++) {
1248 const struct core_stream *old_stream = old_context->streams[i];
4562236b 1249
ab2541b6 1250 if (are_stream_backends_same(old_stream, stream))
4562236b 1251 return true;
4562236b
HW		 1252 }
1253
1254 return false;
1255}
1256
1257static void copy_pipe_ctx(
1258 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1259{
1260 struct core_surface *surface = to_pipe_ctx->surface;
1261 struct core_stream *stream = to_pipe_ctx->stream;
1262
1263 *to_pipe_ctx = *from_pipe_ctx;
1264 to_pipe_ctx->stream = stream;
1265 if (surface != NULL)
1266 to_pipe_ctx->surface = surface;
1267}
1268
1269static struct core_stream *find_pll_sharable_stream(
1270 const struct core_stream *stream_needs_pll,
1271 struct validate_context *context)
1272{
ab2541b6 1273 int i;
4562236b 1274
ab2541b6
AC		 1275 for (i = 0; i < context->stream_count; i++) {
1276 struct core_stream *stream_has_pll = context->streams[i];
4562236b 1277
ab2541b6
AC		 1278 /* We are looking for non dp, non virtual stream */
1279 if (resource_are_streams_timing_synchronizable(
1280 stream_needs_pll, stream_has_pll)
1281 && !dc_is_dp_signal(stream_has_pll->signal)
1282 && stream_has_pll->sink->link->public.connector_signal
1283 != SIGNAL_TYPE_VIRTUAL)
1284 return stream_has_pll;
4562236b 1285
4562236b
HW		 1286 }
1287
1288 return NULL;
1289}
1290
1291static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1292{
1293 uint32_t pix_clk = timing->pix_clk_khz;
1294 uint32_t normalized_pix_clk = pix_clk;
1295
1296 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1297 pix_clk /= 2;
cc4d99b8
CL		 1298 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1299 switch (timing->display_color_depth) {
1300 case COLOR_DEPTH_888:
1301 normalized_pix_clk = pix_clk;
1302 break;
1303 case COLOR_DEPTH_101010:
1304 normalized_pix_clk = (pix_clk * 30) / 24;
1305 break;
1306 case COLOR_DEPTH_121212:
1307 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1308 break;
cc4d99b8
CL		 1309 case COLOR_DEPTH_161616:
1310 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1311 break;
cc4d99b8
CL		 1312 default:
1313 ASSERT(0);
4562236b 1314 break;
cc4d99b8 1315 }
4562236b 1316 }
4562236b
HW		 1317 return normalized_pix_clk;
1318}
1319
1320static void calculate_phy_pix_clks(
1321 const struct core_dc *dc,
1322 struct validate_context *context)
1323{
ab2541b6 1324 int i;
4562236b 1325
ab2541b6
AC		 1326 for (i = 0; i < context->stream_count; i++) {
1327 struct core_stream *stream = context->streams[i];
4562236b 1328
ab2541b6 1329 update_stream_signal(stream);
4562236b 1330
ab2541b6
AC		 1331 /* update actual pixel clock on all streams */
1332 if (dc_is_hdmi_signal(stream->signal))
1333 stream->phy_pix_clk = get_norm_pix_clk(
1334 &stream->public.timing);
1335 else
1336 stream->phy_pix_clk =
1337 stream->public.timing.pix_clk_khz;
4562236b
HW		 1338 }
1339}
1340
1341enum dc_status resource_map_pool_resources(
1342 const struct core_dc *dc,
1343 struct validate_context *context)
1344{
ab2541b6 1345 int i, j;
4562236b
HW		 1346
1347 calculate_phy_pix_clks(dc, context);
1348
ab2541b6
AC		 1349 for (i = 0; i < context->stream_count; i++) {
1350 struct core_stream *stream = context->streams[i];
4562236b 1351
4b679bc3
CL		 1352 if (!resource_is_stream_unchanged(dc->current_context, stream)) {
1353 if (stream != NULL && dc->current_context->streams[i] != NULL) {
1354 stream->bit_depth_params =
1355 dc->current_context->streams[i]->bit_depth_params;
1356 stream->clamping = dc->current_context->streams[i]->clamping;
ab2541b6 1357 continue;
4b679bc3
CL		 1358 }
1359 }
ab2541b6
AC		 1360 /* mark resources used for stream that is already active */
1361 for (j = 0; j < MAX_PIPES; j++) {
1362 struct pipe_ctx *pipe_ctx =
1363 &context->res_ctx.pipe_ctx[j];
1364 const struct pipe_ctx *old_pipe_ctx =
1365 &dc->current_context->res_ctx.pipe_ctx[j];
4562236b 1366
ab2541b6
AC		 1367 if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
1368 continue;
8c737fcc 1369
268cadbd
YS		 1370 if (old_pipe_ctx->top_pipe)
1371 continue;
1372
ab2541b6
AC		 1373 pipe_ctx->stream = stream;
1374 copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
4562236b 1375
ab2541b6
AC		 1376 /* Split pipe resource, do not acquire back end */
1377 if (!pipe_ctx->stream_enc)
1378 continue;
4562236b 1379
ab2541b6
AC		 1380 set_stream_engine_in_use(
1381 &context->res_ctx,
1382 pipe_ctx->stream_enc);
1383
1384 /* Switch to dp clock source only if there is
1385 * no non dp stream that shares the same timing
1386 * with the dp stream.
1387 */
1388 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1389 !find_pll_sharable_stream(stream, context))
1390 pipe_ctx->clock_source =
1391 context->res_ctx.pool->dp_clock_source;
1392
1393 resource_reference_clock_source(
1394 &context->res_ctx,
1395 pipe_ctx->clock_source);
1396
1397 set_audio_in_use(&context->res_ctx,
1398 pipe_ctx->audio);
4562236b
HW		 1399 }
1400 }
1401
ab2541b6
AC		 1402 for (i = 0; i < context->stream_count; i++) {
1403 struct core_stream *stream = context->streams[i];
1404 struct pipe_ctx *pipe_ctx = NULL;
1405 int pipe_idx = -1;
4562236b 1406
ab2541b6
AC		 1407 if (resource_is_stream_unchanged(dc->current_context, stream))
1408 continue;
1409 /* acquire new resources */
1410 pipe_idx = acquire_first_free_pipe(&context->res_ctx, stream);
1411 if (pipe_idx < 0)
1412 return DC_NO_CONTROLLER_RESOURCE;
1413
1414
1415 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1416
1417 pipe_ctx->stream_enc =
1418 find_first_free_match_stream_enc_for_link(
1419 &context->res_ctx, stream);
1420
1421 if (!pipe_ctx->stream_enc)
1422 return DC_NO_STREAM_ENG_RESOURCE;
1423
1424 set_stream_engine_in_use(
1425 &context->res_ctx,
1426 pipe_ctx->stream_enc);
1427
1428 /* TODO: Add check if ASIC support and EDID audio */
4a9a5d62 1429 if (!stream->sink->public.converter_disable_audio &&
ab2541b6
AC		 1430 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1431 stream->public.audio_info.mode_count) {
1432 pipe_ctx->audio = find_first_free_audio(
1433 &context->res_ctx);
1434
1435 /*
1436 * Audio assigned in order first come first get.
1437 * There are asics which has number of audio
1438 * resources less then number of pipes
1439 */
1440 if (pipe_ctx->audio)
1441 set_audio_in_use(
4562236b 1442 &context->res_ctx,
ab2541b6 1443 pipe_ctx->audio);
4562236b 1444 }
ab2541b6
AC		 1445
1446 context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
4562236b
HW		 1447 }
1448
1449 return DC_OK;
1450}
1451
ab2541b6
AC		 1452/* first stream in the context is used to populate the rest */
1453void validate_guaranteed_copy_streams(
4562236b 1454 struct validate_context *context,
ab2541b6 1455 int max_streams)
4562236b
HW		 1456{
1457 int i;
1458
ab2541b6
AC		 1459 for (i = 1; i < max_streams; i++) {
1460 context->streams[i] = context->streams[0];
4562236b
HW		 1461
1462 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1463 &context->res_ctx.pipe_ctx[i]);
1464 context->res_ctx.pipe_ctx[i].stream =
1465 context->res_ctx.pipe_ctx[0].stream;
1466
ab2541b6
AC		 1467 dc_stream_retain(&context->streams[i]->public);
1468 context->stream_count++;
4562236b
HW		 1469 }
1470}
1471
6e4d6bee
TC		 1472static void patch_gamut_packet_checksum(
1473 struct encoder_info_packet *gamut_packet)
4562236b 1474{
4562236b 1475 /* For gamut we recalc checksum */
6e4d6bee 1476 if (gamut_packet->valid) {
4562236b
HW		 1477 uint8_t chk_sum = 0;
1478 uint8_t *ptr;
1479 uint8_t i;
1480
4562236b 1481 /*start of the Gamut data. */
6e4d6bee 1482 ptr = &gamut_packet->sb[3];
4562236b 1483
6e4d6bee 1484 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1485 chk_sum += ptr[i];
1486
6e4d6bee 1487 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1488 }
4562236b
HW		 1489}
1490
1491static void set_avi_info_frame(
6e4d6bee 1492 struct encoder_info_packet *info_packet,
4562236b
HW		 1493 struct pipe_ctx *pipe_ctx)
1494{
1495 struct core_stream *stream = pipe_ctx->stream;
1496 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1497 struct info_frame info_frame = { {0} };
1498 uint32_t pixel_encoding = 0;
1499 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1500 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1501 bool itc = false;
1502 uint8_t cn0_cn1 = 0;
1503 uint8_t *check_sum = NULL;
1504 uint8_t byte_index = 0;
1505
4562236b
HW		 1506 color_space = pipe_ctx->stream->public.output_color_space;
1507
1508 /* Initialize header */
1509 info_frame.avi_info_packet.info_packet_hdmi.bits.header.
3e183c5f 1510 info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1511 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1512 * not be used in HDMI 2.0 (Section 10.1) */
3e183c5f 1513 info_frame.avi_info_packet.info_packet_hdmi.bits.header.version = 2;
4562236b 1514 info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
3e183c5f 1515 HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1516
1517 /*
1518 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1519 * according to HDMI 2.0 spec (Section 10.1)
1520 */
1521
1522 switch (stream->public.timing.pixel_encoding) {
1523 case PIXEL_ENCODING_YCBCR422:
1524 pixel_encoding = 1;
1525 break;
1526
1527 case PIXEL_ENCODING_YCBCR444:
1528 pixel_encoding = 2;
1529 break;
1530 case PIXEL_ENCODING_YCBCR420:
1531 pixel_encoding = 3;
1532 break;
1533
1534 case PIXEL_ENCODING_RGB:
1535 default:
1536 pixel_encoding = 0;
1537 }
1538
1539 /* Y0_Y1_Y2 : The pixel encoding */
1540 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
1541 info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
1542 pixel_encoding;
1543
1544 /* A0 = 1 Active Format Information valid */
1545 info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
1546 ACTIVE_FORMAT_VALID;
1547
1548 /* B0, B1 = 3; Bar info data is valid */
1549 info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
1550 BAR_INFO_BOTH_VALID;
1551
1552 info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
1553 PICTURE_SCALING_UNIFORM;
1554
1555 /* S0, S1 : Underscan / Overscan */
1556 /* TODO: un-hardcode scan type */
1557 scan_type = SCANNING_TYPE_UNDERSCAN;
1558 info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
1559
1560 /* C0, C1 : Colorimetry */
8fde5884
CL		 1561 if (color_space == COLOR_SPACE_YCBCR709 ||
1562 color_space == COLOR_SPACE_YCBCR709_LIMITED)
4562236b
HW		 1563 info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
1564 COLORIMETRY_ITU709;
8fde5884
CL		 1565 else if (color_space == COLOR_SPACE_YCBCR601 ||
1566 color_space == COLOR_SPACE_YCBCR601_LIMITED)
4562236b
HW		 1567 info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
1568 COLORIMETRY_ITU601;
8fde5884
CL		 1569 else {
1570 if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
1571 BREAK_TO_DEBUGGER();
4562236b
HW		 1572 info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
1573 COLORIMETRY_NO_DATA;
8fde5884 1574 }
534db198 1575 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1576 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1577 color_space == COLOR_SPACE_2020_YCBCR) {
534db198
AZ		 1578 info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 =
1579 COLORIMETRYEX_BT2020RGBYCBCR;
1580 info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
1581 COLORIMETRY_EXTENDED;
1582 } else if (color_space == COLOR_SPACE_ADOBERGB) {
1583 info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 =
1584 COLORIMETRYEX_ADOBERGB;
1585 info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
1586 COLORIMETRY_EXTENDED;
1587 }
1588
4562236b
HW		 1589 /* TODO: un-hardcode aspect ratio */
1590 aspect = stream->public.timing.aspect_ratio;
1591
1592 switch (aspect) {
1593 case ASPECT_RATIO_4_3:
1594 case ASPECT_RATIO_16_9:
1595 info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
1596 break;
1597
1598 case ASPECT_RATIO_NO_DATA:
1599 case ASPECT_RATIO_64_27:
1600 case ASPECT_RATIO_256_135:
1601 default:
1602 info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
1603 }
1604
1605 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
1606 info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
1607 ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
1608
1609 /* TODO: un-hardcode cn0_cn1 and itc */
1610 cn0_cn1 = 0;
1611 itc = false;
1612
1613 if (itc) {
1614 info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
1615 info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
1616 cn0_cn1;
1617 }
1618
1619 /* TODO : We should handle YCC quantization */
1620 /* but we do not have matrix calculation */
1621 if (color_space == COLOR_SPACE_SRGB) {
1622 info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
1623 RGB_QUANTIZATION_FULL_RANGE;
1624 info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
1625 YYC_QUANTIZATION_FULL_RANGE;
1626 } else if (color_space == COLOR_SPACE_SRGB_LIMITED) {
1627 info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
1628 RGB_QUANTIZATION_LIMITED_RANGE;
1629 info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
1630 YYC_QUANTIZATION_LIMITED_RANGE;
1631 } else {
1632 info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
1633 RGB_QUANTIZATION_DEFAULT_RANGE;
1634 info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
1635 YYC_QUANTIZATION_LIMITED_RANGE;
1636 }
1637
1638 info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
1639 stream->public.timing.vic;
1640
1641 /* pixel repetition
1642 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
1643 * repetition start from 1 */
1644 info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
1645
1646 /* Bar Info
1647 * barTop: Line Number of End of Top Bar.
1648 * barBottom: Line Number of Start of Bottom Bar.
1649 * barLeft: Pixel Number of End of Left Bar.
1650 * barRight: Pixel Number of Start of Right Bar. */
1651 info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
1652 stream->public.timing.v_border_top;
1653 info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
1654 (stream->public.timing.v_border_top
1655 - stream->public.timing.v_border_bottom + 1);
1656 info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
1657 stream->public.timing.h_border_left;
1658 info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
1659 (stream->public.timing.h_total
1660 - stream->public.timing.h_border_right + 1);
1661
1662 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
1663 check_sum =
1664 &info_frame.
1665 avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
3e183c5f 1666 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 1667
3e183c5f 1668 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
4562236b
HW		 1669 *check_sum += info_frame.avi_info_packet.info_packet_hdmi.
1670 packet_raw_data.sb[byte_index];
1671
1672 /* one byte complement */
1673 *check_sum = (uint8_t) (0x100 - *check_sum);
1674
1675 /* Store in hw_path_mode */
1676 info_packet->hb0 =
1677 info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
1678 info_packet->hb1 =
1679 info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
1680 info_packet->hb2 =
1681 info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
1682
e66e4d64
HW		 1683 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
1684 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 1685 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 1686 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 1687
1688 info_packet->valid = true;
1689}
1690
6e4d6bee
TC		 1691static void set_vendor_info_packet(
1692 struct encoder_info_packet *info_packet,
1693 struct core_stream *stream)
4562236b
HW		 1694{
1695 uint32_t length = 0;
1696 bool hdmi_vic_mode = false;
1697 uint8_t checksum = 0;
1698 uint32_t i = 0;
1699 enum dc_timing_3d_format format;
1700
4562236b
HW		 1701 format = stream->public.timing.timing_3d_format;
1702
1703 /* Can be different depending on packet content */
1704 length = 5;
1705
1706 if (stream->public.timing.hdmi_vic != 0
1707 && stream->public.timing.h_total >= 3840
1708 && stream->public.timing.v_total >= 2160)
1709 hdmi_vic_mode = true;
1710
1711 /* According to HDMI 1.4a CTS, VSIF should be sent
1712 * for both 3D stereo and HDMI VIC modes.
1713 * For all other modes, there is no VSIF sent. */
1714
1715 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
1716 return;
1717
1718 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
1719 info_packet->sb[1] = 0x03;
1720 info_packet->sb[2] = 0x0C;
1721 info_packet->sb[3] = 0x00;
1722
1723 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
1724 * The value for HDMI_Video_Format are:
1725 * 0x0 (0b000) - No additional HDMI video format is presented in this
1726 * packet
1727 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
1728 * parameter follows
1729 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
1730 * potentially 3D_Ext_Data follows
1731 * 0x3..0x7 (0b011..0b111) - reserved for future use */
1732 if (format != TIMING_3D_FORMAT_NONE)
1733 info_packet->sb[4] = (2 << 5);
1734 else if (hdmi_vic_mode)
1735 info_packet->sb[4] = (1 << 5);
1736
1737 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
1738 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
1739 * The value for 3D_Structure are:
1740 * 0x0 - Frame Packing
1741 * 0x1 - Field Alternative
1742 * 0x2 - Line Alternative
1743 * 0x3 - Side-by-Side (full)
1744 * 0x4 - L + depth
1745 * 0x5 - L + depth + graphics + graphics-depth
1746 * 0x6 - Top-and-Bottom
1747 * 0x7 - Reserved for future use
1748 * 0x8 - Side-by-Side (Half)
1749 * 0x9..0xE - Reserved for future use
1750 * 0xF - Not used */
1751 switch (format) {
1752 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
1753 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
1754 info_packet->sb[5] = (0x0 << 4);
1755 break;
1756
1757 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
1758 case TIMING_3D_FORMAT_SBS_SW_PACKED:
1759 info_packet->sb[5] = (0x8 << 4);
1760 length = 6;
1761 break;
1762
1763 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
1764 case TIMING_3D_FORMAT_TB_SW_PACKED:
1765 info_packet->sb[5] = (0x6 << 4);
1766 break;
1767
1768 default:
1769 break;
1770 }
1771
1772 /*PB5: If PB4 is set to 0x1 (extended resolution format)
1773 * fill PB5 with the correct HDMI VIC code */
1774 if (hdmi_vic_mode)
1775 info_packet->sb[5] = stream->public.timing.hdmi_vic;
1776
1777 /* Header */
3e183c5f 1778 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 1779 info_packet->hb1 = 0x01; /* Version */
1780
1781 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
1782 info_packet->hb2 = (uint8_t) (length);
1783
1784 /* Calculate checksum */
1785 checksum = 0;
1786 checksum += info_packet->hb0;
1787 checksum += info_packet->hb1;
1788 checksum += info_packet->hb2;
1789
1790 for (i = 1; i <= length; i++)
1791 checksum += info_packet->sb[i];
1792
1793 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
1794
1795 info_packet->valid = true;
1796}
1797
6e4d6bee
TC		 1798static void set_spd_info_packet(
1799 struct encoder_info_packet *info_packet,
1800 struct core_stream *stream)
4562236b
HW		 1801{
1802 /* SPD info packet for FreeSync */
1803
1804 unsigned char checksum = 0;
1805 unsigned int idx, payload_size = 0;
1806
1807 /* Check if Freesync is supported. Return if false. If true,
1808 * set the corresponding bit in the info packet
1809 */
1810 if (stream->public.freesync_ctx.supported == false)
1811 return;
1812
1813 if (dc_is_hdmi_signal(stream->signal)) {
1814
1815 /* HEADER */
1816
1817 /* HB0 = Packet Type = 0x83 (Source Product
1818 * Descriptor InfoFrame)
1819 */
3e183c5f 1820 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1821
1822 /* HB1 = Version = 0x01 */
1823 info_packet->hb1 = 0x01;
1824
1825 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1826 info_packet->hb2 = 0x08;
1827
1828 payload_size = 0x08;
1829
1830 } else if (dc_is_dp_signal(stream->signal)) {
1831
1832 /* HEADER */
1833
1834 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1835 * when used to associate audio related info packets
1836 */
1837 info_packet->hb0 = 0x00;
1838
1839 /* HB1 = Packet Type = 0x83 (Source Product
1840 * Descriptor InfoFrame)
1841 */
3e183c5f 1842 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 1843
1844 /* HB2 = [Bits 7:0 = Least significant eight bits -
1845 * For INFOFRAME, the value must be 1Bh]
1846 */
1847 info_packet->hb2 = 0x1B;
1848
1849 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
1850 * [Bits 1:0 = Most significant two bits = 0x00]
1851 */
1852 info_packet->hb3 = 0x04;
1853
1854 payload_size = 0x1B;
1855 }
1856
1857 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
1858 info_packet->sb[1] = 0x1A;
1859
1860 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
1861 info_packet->sb[2] = 0x00;
1862
1863 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
1864 info_packet->sb[3] = 0x00;
1865
1866 /* PB4 = Reserved */
1867 info_packet->sb[4] = 0x00;
1868
1869 /* PB5 = Reserved */
1870 info_packet->sb[5] = 0x00;
1871
1872 /* PB6 = [Bits 7:3 = Reserved] */
1873 info_packet->sb[6] = 0x00;
1874
1875 if (stream->public.freesync_ctx.supported == true)
1876 /* PB6 = [Bit 0 = FreeSync Supported] */
1877 info_packet->sb[6] |= 0x01;
1878
1879 if (stream->public.freesync_ctx.enabled == true)
1880 /* PB6 = [Bit 1 = FreeSync Enabled] */
1881 info_packet->sb[6] |= 0x02;
1882
1883 if (stream->public.freesync_ctx.active == true)
1884 /* PB6 = [Bit 2 = FreeSync Active] */
1885 info_packet->sb[6] |= 0x04;
1886
1887 /* PB7 = FreeSync Minimum refresh rate (Hz) */
1888 info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx.
1889 min_refresh_in_micro_hz / 1000000);
1890
1891 /* PB8 = FreeSync Maximum refresh rate (Hz)
1892 *
1893 * Note: We do not use the maximum capable refresh rate
1894 * of the panel, because we should never go above the field
1895 * rate of the mode timing set.
1896 */
1897 info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx.
1898 nominal_refresh_in_micro_hz / 1000000);
1899
1900 /* PB9 - PB27 = Reserved */
1901 for (idx = 9; idx <= 27; idx++)
1902 info_packet->sb[idx] = 0x00;
1903
1904 /* Calculate checksum */
1905 checksum += info_packet->hb0;
1906 checksum += info_packet->hb1;
1907 checksum += info_packet->hb2;
1908 checksum += info_packet->hb3;
1909
1910 for (idx = 1; idx <= payload_size; idx++)
1911 checksum += info_packet->sb[idx];
1912
1913 /* PB0 = Checksum (one byte complement) */
1914 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
1915
1916 info_packet->valid = true;
1917}
1918
1646a6fe 1919static void set_hdr_static_info_packet(
6e4d6bee 1920 struct encoder_info_packet *info_packet,
1646a6fe 1921 struct core_surface *surface,
6e4d6bee 1922 struct core_stream *stream)
1646a6fe 1923{
e5cf325b 1924 uint16_t i = 0;
1646a6fe 1925 enum signal_type signal = stream->signal;
e5cf325b
HW		 1926 struct dc_hdr_static_metadata hdr_metadata;
1927 uint32_t data;
1646a6fe
AW		 1928
1929 if (!surface)
1930 return;
1931
e5cf325b 1932 hdr_metadata = surface->public.hdr_static_ctx;
1646a6fe 1933
70063a59 1934 if (!hdr_metadata.hdr_supported)
10bff005
YS		 1935 return;
1936
1646a6fe
AW		 1937 if (dc_is_hdmi_signal(signal)) {
1938 info_packet->valid = true;
1939
1940 info_packet->hb0 = 0x87;
1941 info_packet->hb1 = 0x01;
1942 info_packet->hb2 = 0x1A;
1943 i = 1;
1944 } else if (dc_is_dp_signal(signal)) {
1945 info_packet->valid = true;
1946
1947 info_packet->hb0 = 0x00;
1948 info_packet->hb1 = 0x87;
1949 info_packet->hb2 = 0x1D;
1950 info_packet->hb3 = (0x13 << 2);
1951 i = 2;
1952 }
1953
1646a6fe
AW		 1954 data = hdr_metadata.is_hdr;
1955 info_packet->sb[i++] = data ? 0x02 : 0x00;
1956 info_packet->sb[i++] = 0x00;
1957
1958 data = hdr_metadata.chromaticity_green_x / 2;
1959 info_packet->sb[i++] = data & 0xFF;
1960 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1961
1962 data = hdr_metadata.chromaticity_green_y / 2;
1963 info_packet->sb[i++] = data & 0xFF;
1964 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1965
1966 data = hdr_metadata.chromaticity_blue_x / 2;
1967 info_packet->sb[i++] = data & 0xFF;
1968 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1969
1970 data = hdr_metadata.chromaticity_blue_y / 2;
1971 info_packet->sb[i++] = data & 0xFF;
1972 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1973
1974 data = hdr_metadata.chromaticity_red_x / 2;
1975 info_packet->sb[i++] = data & 0xFF;
1976 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1977
1978 data = hdr_metadata.chromaticity_red_y / 2;
1979 info_packet->sb[i++] = data & 0xFF;
1980 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1981
1982 data = hdr_metadata.chromaticity_white_point_x / 2;
1983 info_packet->sb[i++] = data & 0xFF;
1984 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1985
1986 data = hdr_metadata.chromaticity_white_point_y / 2;
1987 info_packet->sb[i++] = data & 0xFF;
1988 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1989
1990 data = hdr_metadata.max_luminance;
1991 info_packet->sb[i++] = data & 0xFF;
1992 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1993
1994 data = hdr_metadata.min_luminance;
1995 info_packet->sb[i++] = data & 0xFF;
1996 info_packet->sb[i++] = (data & 0xFF00) >> 8;
1997
1998 data = hdr_metadata.maximum_content_light_level;
1999 info_packet->sb[i++] = data & 0xFF;
2000 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2001
2002 data = hdr_metadata.maximum_frame_average_light_level;
2003 info_packet->sb[i++] = data & 0xFF;
2004 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2005
2006 if (dc_is_hdmi_signal(signal)) {
2007 uint32_t checksum = 0;
2008
2009 checksum += info_packet->hb0;
2010 checksum += info_packet->hb1;
2011 checksum += info_packet->hb2;
2012
2013 for (i = 1; i <= info_packet->hb2; i++)
2014 checksum += info_packet->sb[i];
2015
2016 info_packet->sb[0] = 0x100 - checksum;
2017 } else if (dc_is_dp_signal(signal)) {
2018 info_packet->sb[0] = 0x01;
2019 info_packet->sb[1] = 0x1A;
2020 }
2021}
2022
6e4d6bee
TC		 2023static void set_vsc_info_packet(
2024 struct encoder_info_packet *info_packet,
2025 struct core_stream *stream)
4562236b
HW		 2026{
2027 unsigned int vscPacketRevision = 0;
2028 unsigned int i;
2029
2030 if (stream->sink->link->public.psr_caps.psr_version != 0) {
2031 vscPacketRevision = 2;
2032 }
2033
2034 /* VSC packet not needed based on the features
2035 * supported by this DP display
2036 */
2037 if (vscPacketRevision == 0)
2038 return;
2039
2040 if (vscPacketRevision == 0x2) {
2041 /* Secondary-data Packet ID = 0*/
2042 info_packet->hb0 = 0x00;
2043 /* 07h - Packet Type Value indicating Video
2044 * Stream Configuration packet
2045 */
2046 info_packet->hb1 = 0x07;
2047 /* 02h = VSC SDP supporting 3D stereo and PSR
2048 * (applies to eDP v1.3 or higher).
2049 */
2050 info_packet->hb2 = 0x02;
2051 /* 08h = VSC packet supporting 3D stereo + PSR
2052 * (HB2 = 02h).
2053 */
2054 info_packet->hb3 = 0x08;
2055
2056 for (i = 0; i < 28; i++)
2057 info_packet->sb[i] = 0;
2058
2059 info_packet->valid = true;
2060 }
2061
2062 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2063}
2064
2065void resource_validate_ctx_destruct(struct validate_context *context)
2066{
2067 int i, j;
2068
ab2541b6
AC		 2069 for (i = 0; i < context->stream_count; i++) {
2070 for (j = 0; j < context->stream_status[i].surface_count; j++)
4562236b 2071 dc_surface_release(
ab2541b6 2072 context->stream_status[i].surfaces[j]);
4562236b 2073
ab2541b6
AC		 2074 context->stream_status[i].surface_count = 0;
2075 dc_stream_release(&context->streams[i]->public);
2076 context->streams[i] = NULL;
4562236b
HW		 2077 }
2078}
2079
2080/*
ab2541b6 2081 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2082 * by the src_ctx
2083 */
2084void resource_validate_ctx_copy_construct(
2085 const struct validate_context *src_ctx,
2086 struct validate_context *dst_ctx)
2087{
2088 int i, j;
2089
2090 *dst_ctx = *src_ctx;
2091
2092 for (i = 0; i < dst_ctx->res_ctx.pool->pipe_count; i++) {
2093 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2094
2095 if (cur_pipe->top_pipe)
2096 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2097
2098 if (cur_pipe->bottom_pipe)
2099 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2100
2101 }
2102
ab2541b6
AC		 2103 for (i = 0; i < dst_ctx->stream_count; i++) {
2104 dc_stream_retain(&dst_ctx->streams[i]->public);
2105 for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++)
4562236b 2106 dc_surface_retain(
ab2541b6 2107 dst_ctx->stream_status[i].surfaces[j]);
4562236b
HW		 2108 }
2109}
2110
2111struct clock_source *dc_resource_find_first_free_pll(
2112 struct resource_context *res_ctx)
2113{
2114 int i;
2115
2116 for (i = 0; i < res_ctx->pool->clk_src_count; ++i) {
2117 if (res_ctx->clock_source_ref_count[i] == 0)
2118 return res_ctx->pool->clock_sources[i];
2119 }
2120
2121 return NULL;
2122}
2123
2124void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2125{
2126 enum signal_type signal = SIGNAL_TYPE_NONE;
6e4d6bee 2127 struct encoder_info_frame *info = &pipe_ctx->encoder_info_frame;
4562236b
HW		 2128
2129 /* default all packets to invalid */
6e4d6bee
TC		 2130 info->avi.valid = false;
2131 info->gamut.valid = false;
2132 info->vendor.valid = false;
2133 info->hdrsmd.valid = false;
2134 info->vsc.valid = false;
4562236b
HW		 2135
2136 signal = pipe_ctx->stream->signal;
2137
2138 /* HDMi and DP have different info packets*/
2139 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2140 set_avi_info_frame(&info->avi, pipe_ctx);
2141
2142 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2143
2144 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2145
2146 set_hdr_static_info_packet(&info->hdrsmd,
2147 pipe_ctx->surface, pipe_ctx->stream);
2148
a33fa99d 2149 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2150 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2151
2152 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2153
2154 set_hdr_static_info_packet(&info->hdrsmd,
2155 pipe_ctx->surface, pipe_ctx->stream);
a33fa99d 2156 }
4562236b 2157
6e4d6bee 2158 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2159}
2160
2161enum dc_status resource_map_clock_resources(
2162 const struct core_dc *dc,
2163 struct validate_context *context)
2164{
ab2541b6 2165 int i, j;
4562236b
HW		 2166
2167 /* acquire new resources */
ab2541b6
AC		 2168 for (i = 0; i < context->stream_count; i++) {
2169 const struct core_stream *stream = context->streams[i];
4562236b 2170
ab2541b6
AC		 2171 if (resource_is_stream_unchanged(dc->current_context, stream))
2172 continue;
2173
2174 for (j = 0; j < MAX_PIPES; j++) {
2175 struct pipe_ctx *pipe_ctx =
2176 &context->res_ctx.pipe_ctx[j];
4562236b 2177
ab2541b6 2178 if (context->res_ctx.pipe_ctx[j].stream != stream)
4562236b
HW		 2179 continue;
2180
ab2541b6
AC		 2181 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2182 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2183 pipe_ctx->clock_source =
2184 context->res_ctx.pool->dp_clock_source;
2185 else {
2186 pipe_ctx->clock_source = NULL;
4562236b 2187
ab2541b6
AC		 2188 if (!dc->public.config.disable_disp_pll_sharing)
2189 resource_find_used_clk_src_for_sharing(
2190 &context->res_ctx,
2191 pipe_ctx);
4562236b 2192
ab2541b6 2193 if (pipe_ctx->clock_source == NULL)
4562236b 2194 pipe_ctx->clock_source =
ab2541b6
AC		 2195 dc_resource_find_first_free_pll(&context->res_ctx);
2196 }
4562236b 2197
ab2541b6
AC		 2198 if (pipe_ctx->clock_source == NULL)
2199 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2200
ab2541b6
AC		 2201 resource_reference_clock_source(
2202 &context->res_ctx,
2203 pipe_ctx->clock_source);
4562236b 2204
ab2541b6
AC		 2205 /* only one cs per stream regardless of mpo */
2206 break;
4562236b
HW		 2207 }
2208 }
2209
2210 return DC_OK;
2211}
2212
2213/*
2214 * Note: We need to disable output if clock sources change,
2215 * since bios does optimization and doesn't apply if changing
2216 * PHY when not already disabled.
2217 */
2218bool pipe_need_reprogram(
2219 struct pipe_ctx *pipe_ctx_old,
2220 struct pipe_ctx *pipe_ctx)
2221{
2222 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2223 return true;
2224
2225 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2226 return true;
2227
2228 if (pipe_ctx_old->audio != pipe_ctx->audio)
2229 return true;
2230
2231 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2232 && pipe_ctx_old->stream != pipe_ctx->stream)
2233 return true;
2234
2235 if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
2236 return true;
2237
2238 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2239 return true;
2240
2241
2242 return false;
2243}
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