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drm/amdgpu: add VEGAM pci ids
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
CommitLineData
4562236b 1/*
9ce6aae1 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b 37#include "virtual/virtual_stream_encoder.h"
3b94a400 38#include "dpcd_defs.h"
4562236b
HW		 39
40#include "dce80/dce80_resource.h"
41#include "dce100/dce100_resource.h"
42#include "dce110/dce110_resource.h"
43#include "dce112/dce112_resource.h"
ff5ef992
AD		 44#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
45#include "dcn10/dcn10_resource.h"
46#endif
2c8ad2d5 47#include "dce120/dce120_resource.h"
5d4b05dd
BL		 48
49#define DC_LOGGER_INIT(logger)
50
4562236b
HW		 51enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
52{
53 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
54 switch (asic_id.chip_family) {
55
56 case FAMILY_CI:
4562236b
HW		 57 dc_version = DCE_VERSION_8_0;
58 break;
ebfdf0d0
AD		 59 case FAMILY_KV:
60 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
61 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
62 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
63 dc_version = DCE_VERSION_8_3;
64 else
65 dc_version = DCE_VERSION_8_1;
66 break;
4562236b
HW		 67 case FAMILY_CZ:
68 dc_version = DCE_VERSION_11_0;
69 break;
70
71 case FAMILY_VI:
72 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
74 dc_version = DCE_VERSION_10_0;
75 break;
76 }
77 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 78 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
79 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 80 dc_version = DCE_VERSION_11_2;
81 }
82 break;
2c8ad2d5
AD		 83 case FAMILY_AI:
84 dc_version = DCE_VERSION_12_0;
85 break;
ff5ef992
AD		 86#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
87 case FAMILY_RV:
88 dc_version = DCN_VERSION_1_0;
89 break;
90#endif
4562236b
HW		 91 default:
92 dc_version = DCE_VERSION_UNKNOWN;
93 break;
94 }
95 return dc_version;
96}
97
98struct resource_pool *dc_create_resource_pool(
fb3466a4 99 struct dc *dc,
4562236b
HW		 100 int num_virtual_links,
101 enum dce_version dc_version,
102 struct hw_asic_id asic_id)
103{
5ac3d3c9 104 struct resource_pool *res_pool = NULL;
4562236b
HW		 105
106 switch (dc_version) {
107 case DCE_VERSION_8_0:
7992a629
AD		 108 res_pool = dce80_create_resource_pool(
109 num_virtual_links, dc);
110 break;
ebfdf0d0 111 case DCE_VERSION_8_1:
7992a629
AD		 112 res_pool = dce81_create_resource_pool(
113 num_virtual_links, dc);
114 break;
ebfdf0d0 115 case DCE_VERSION_8_3:
7992a629 116 res_pool = dce83_create_resource_pool(
4562236b 117 num_virtual_links, dc);
5ac3d3c9 118 break;
4562236b 119 case DCE_VERSION_10_0:
5ac3d3c9 120 res_pool = dce100_create_resource_pool(
4562236b 121 num_virtual_links, dc);
5ac3d3c9 122 break;
4562236b 123 case DCE_VERSION_11_0:
5ac3d3c9 124 res_pool = dce110_create_resource_pool(
4562236b 125 num_virtual_links, dc, asic_id);
5ac3d3c9 126 break;
4562236b 127 case DCE_VERSION_11_2:
5ac3d3c9 128 res_pool = dce112_create_resource_pool(
4562236b 129 num_virtual_links, dc);
5ac3d3c9 130 break;
2c8ad2d5
AD		 131 case DCE_VERSION_12_0:
132 res_pool = dce120_create_resource_pool(
133 num_virtual_links, dc);
134 break;
ff5ef992
AD		 135
136#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
137 case DCN_VERSION_1_0:
138 res_pool = dcn10_create_resource_pool(
503a7c6f 139 num_virtual_links, dc);
ff5ef992
AD		 140 break;
141#endif
3639fa68
ZF		 142
143
4562236b
HW		 144 default:
145 break;
146 }
5ac3d3c9 147 if (res_pool != NULL) {
1515a47b 148 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 149
150 if (dc->ctx->dc_bios->funcs->get_firmware_info(
151 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
152 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
153 } else
154 ASSERT_CRITICAL(false);
155 }
4562236b 156
5ac3d3c9 157 return res_pool;
4562236b
HW		 158}
159
fb3466a4 160void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 161{
162 if (dc) {
163 if (dc->res_pool)
164 dc->res_pool->funcs->destroy(&dc->res_pool);
165
d029810c 166 kfree(dc->hwseq);
4562236b
HW		 167 }
168}
169
170static void update_num_audio(
171 const struct resource_straps *straps,
172 unsigned int *num_audio,
173 struct audio_support *aud_support)
174{
b8e9eb72
CL		 175 aud_support->dp_audio = true;
176 aud_support->hdmi_audio_native = false;
177 aud_support->hdmi_audio_on_dongle = false;
178
4562236b 179 if (straps->hdmi_disable == 0) {
4562236b
HW		 180 if (straps->dc_pinstraps_audio & 0x2) {
181 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 182 aud_support->hdmi_audio_native = true;
4562236b
HW		 183 }
184 }
185
186 switch (straps->audio_stream_number) {
187 case 0: /* multi streams supported */
188 break;
189 case 1: /* multi streams not supported */
190 *num_audio = 1;
191 break;
192 default:
193 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 194 }
4562236b
HW		 195}
196
197bool resource_construct(
198 unsigned int num_virtual_links,
fb3466a4 199 struct dc *dc,
4562236b
HW		 200 struct resource_pool *pool,
201 const struct resource_create_funcs *create_funcs)
202{
203 struct dc_context *ctx = dc->ctx;
204 const struct resource_caps *caps = pool->res_cap;
205 int i;
206 unsigned int num_audio = caps->num_audio;
207 struct resource_straps straps = {0};
208
209 if (create_funcs->read_dce_straps)
210 create_funcs->read_dce_straps(dc->ctx, &straps);
211
212 pool->audio_count = 0;
213 if (create_funcs->create_audio) {
214 /* find the total number of streams available via the
215 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
216 * registers (one for each pin) starting from pin 1
217 * up to the max number of audio pins.
218 * We stop on the first pin where
219 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
220 */
221 update_num_audio(&straps, &num_audio, &pool->audio_support);
222 for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
223 struct audio *aud = create_funcs->create_audio(ctx, i);
224
225 if (aud == NULL) {
226 DC_ERR("DC: failed to create audio!\n");
227 return false;
228 }
229
230 if (!aud->funcs->endpoint_valid(aud)) {
231 aud->funcs->destroy(&aud);
232 break;
233 }
234
235 pool->audios[i] = aud;
236 pool->audio_count++;
237 }
238 }
239
240 pool->stream_enc_count = 0;
241 if (create_funcs->create_stream_encoder) {
242 for (i = 0; i < caps->num_stream_encoder; i++) {
243 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
244 if (pool->stream_enc[i] == NULL)
245 DC_ERR("DC: failed to create stream_encoder!\n");
246 pool->stream_enc_count++;
247 }
248 }
4176664b
CL		 249 dc->caps.dynamic_audio = false;
250 if (pool->audio_count < pool->stream_enc_count) {
251 dc->caps.dynamic_audio = true;
252 }
4562236b
HW		 253 for (i = 0; i < num_virtual_links; i++) {
254 pool->stream_enc[pool->stream_enc_count] =
255 virtual_stream_encoder_create(
256 ctx, ctx->dc_bios);
257 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
258 DC_ERR("DC: failed to create stream_encoder!\n");
259 return false;
260 }
261 pool->stream_enc_count++;
262 }
263
264 dc->hwseq = create_funcs->create_hwseq(ctx);
265
266 return true;
267}
268
269
21e67d4d 270void resource_unreference_clock_source(
4562236b 271 struct resource_context *res_ctx,
a2b8659d 272 const struct resource_pool *pool,
4a629536 273 struct clock_source *clock_source)
4562236b
HW		 274{
275 int i;
4a629536 276
a2b8659d 277 for (i = 0; i < pool->clk_src_count; i++) {
4a629536 278 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 279 continue;
280
281 res_ctx->clock_source_ref_count[i]--;
282
4562236b
HW		 283 break;
284 }
285
21e67d4d 286 if (pool->dp_clock_source == clock_source)
4562236b 287 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 288}
289
290void resource_reference_clock_source(
291 struct resource_context *res_ctx,
a2b8659d 292 const struct resource_pool *pool,
4562236b
HW		 293 struct clock_source *clock_source)
294{
295 int i;
a2b8659d
TC		 296 for (i = 0; i < pool->clk_src_count; i++) {
297 if (pool->clock_sources[i] != clock_source)
4562236b
HW		 298 continue;
299
300 res_ctx->clock_source_ref_count[i]++;
301 break;
302 }
303
a2b8659d 304 if (pool->dp_clock_source == clock_source)
4562236b
HW		 305 res_ctx->dp_clock_source_ref_count++;
306}
307
308bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 309 struct dc_stream_state *stream1,
310 struct dc_stream_state *stream2)
4562236b 311{
4fa086b9 312 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 313 return false;
314
4fa086b9 315 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 316 return false;
317
4fa086b9
LSL		 318 if (stream1->timing.h_addressable
319 != stream2->timing.h_addressable)
4562236b
HW		 320 return false;
321
4fa086b9
LSL		 322 if (stream1->timing.v_addressable
323 != stream2->timing.v_addressable)
4562236b
HW		 324 return false;
325
4fa086b9
LSL		 326 if (stream1->timing.pix_clk_khz
327 != stream2->timing.pix_clk_khz)
4562236b
HW		 328 return false;
329
330 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 331 && (!dc_is_dp_signal(stream1->signal)
332 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 333 return false;
334
335 return true;
336}
337
338static bool is_sharable_clk_src(
339 const struct pipe_ctx *pipe_with_clk_src,
340 const struct pipe_ctx *pipe)
341{
342 if (pipe_with_clk_src->clock_source == NULL)
343 return false;
344
345 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
346 return false;
347
348 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
349 return false;
350
351 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
352 && dc_is_dvi_signal(pipe->stream->signal))
353 return false;
354
355 if (dc_is_hdmi_signal(pipe->stream->signal)
356 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
357 return false;
358
359 if (!resource_are_streams_timing_synchronizable(
360 pipe_with_clk_src->stream, pipe->stream))
361 return false;
362
363 return true;
364}
365
366struct clock_source *resource_find_used_clk_src_for_sharing(
367 struct resource_context *res_ctx,
368 struct pipe_ctx *pipe_ctx)
369{
370 int i;
371
372 for (i = 0; i < MAX_PIPES; i++) {
373 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
374 return res_ctx->pipe_ctx[i].clock_source;
375 }
376
377 return NULL;
378}
379
380static enum pixel_format convert_pixel_format_to_dalsurface(
381 enum surface_pixel_format surface_pixel_format)
382{
383 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
384
385 switch (surface_pixel_format) {
386 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
387 dal_pixel_format = PIXEL_FORMAT_INDEX8;
388 break;
389 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
390 dal_pixel_format = PIXEL_FORMAT_RGB565;
391 break;
392 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
393 dal_pixel_format = PIXEL_FORMAT_RGB565;
394 break;
395 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
396 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
397 break;
8693049a 398 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 399 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
400 break;
401 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
402 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
403 break;
404 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
406 break;
407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
408 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
409 break;
410 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
411 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
412 dal_pixel_format = PIXEL_FORMAT_FP16;
413 break;
414 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 415 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 416 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 417 break;
ffbcd19a
VP		 418 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
419 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 420 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 421 break;
4562236b
HW		 422 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
423 default:
424 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
425 break;
426 }
427 return dal_pixel_format;
428}
429
430static void rect_swap_helper(struct rect *rect)
431{
99676f20
GS		 432 swap(rect->height, rect->width);
433 swap(rect->x, rect->y);
4562236b
HW		 434}
435
b2d0a103 436static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 437{
3be5262e 438 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 439 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 440 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 441 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 442 struct rect clip = { 0 };
87449a90
AK		 443 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
444 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 445 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 446 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 447 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 448 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 449
7f5c22d1
VP		 450 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
451 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 452 pri_split = false;
453 sec_split = false;
454 }
86006a7f 455
3be5262e
HW		 456 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
457 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 458 rect_swap_helper(&surf_src);
459
4562236b
HW		 460 /* The actual clip is an intersection between stream
461 * source and surface clip
462 */
3be5262e
HW		 463 clip.x = stream->src.x > plane_state->clip_rect.x ?
464 stream->src.x : plane_state->clip_rect.x;
4562236b 465
1fbd2cfc 466 clip.width = stream->src.x + stream->src.width <
3be5262e 467 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 468 stream->src.x + stream->src.width - clip.x :
3be5262e 469 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 470
3be5262e
HW		 471 clip.y = stream->src.y > plane_state->clip_rect.y ?
472 stream->src.y : plane_state->clip_rect.y;
4562236b 473
1fbd2cfc 474 clip.height = stream->src.y + stream->src.height <
3be5262e 475 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 476 stream->src.y + stream->src.height - clip.y :
3be5262e 477 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 478
86006a7f 479 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 480 * num_pixels = clip.num_pix * scl_ratio
481 */
3be5262e
HW		 482 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
483 surf_src.width / plane_state->dst_rect.width;
b2d0a103 484 data->viewport.width = clip.width *
3be5262e 485 surf_src.width / plane_state->dst_rect.width;
4562236b 486
3be5262e
HW		 487 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
488 surf_src.height / plane_state->dst_rect.height;
b2d0a103 489 data->viewport.height = clip.height *
3be5262e 490 surf_src.height / plane_state->dst_rect.height;
4562236b 491
b2d0a103
DL		 492 /* Round down, compensate in init */
493 data->viewport_c.x = data->viewport.x / vpc_div;
494 data->viewport_c.y = data->viewport.y / vpc_div;
495 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
496 dal_fixed31_32_half : dal_fixed31_32_zero;
497 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
498 dal_fixed31_32_half : dal_fixed31_32_zero;
499 /* Round up, assume original video size always even dimensions */
500 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
501 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
502
503 /* Handle hsplit */
0c31a821
YS		 504 if (sec_split) {
505 data->viewport.x += data->viewport.width / 2;
506 data->viewport_c.x += data->viewport_c.width / 2;
507 /* Ceil offset pipe */
508 data->viewport.width = (data->viewport.width + 1) / 2;
509 data->viewport_c.width = (data->viewport_c.width + 1) / 2;
510 } else if (pri_split) {
511 data->viewport.width /= 2;
512 data->viewport_c.width /= 2;
b2d0a103 513 }
1fbd2cfc 514
3be5262e
HW		 515 if (plane_state->rotation == ROTATION_ANGLE_90 ||
516 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 517 rect_swap_helper(&data->viewport_c);
518 rect_swap_helper(&data->viewport);
519 }
4562236b
HW		 520}
521
b2d0a103 522static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 523{
3be5262e 524 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 525 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW		 526 struct rect surf_src = plane_state->src_rect;
527 struct rect surf_clip = plane_state->clip_rect;
c802570e 528 int recout_full_x, recout_full_y;
0c31a821
YS		 529 bool pri_split = pipe_ctx->bottom_pipe &&
530 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
531 bool sec_split = pipe_ctx->top_pipe &&
532 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
b0131391 533 bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
4562236b 534
3be5262e
HW		 535 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
536 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 537 rect_swap_helper(&surf_src);
538
6702a9ac 539 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 540 if (stream->src.x < surf_clip.x)
6702a9ac 541 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 542 - stream->src.x) * stream->dst.width
543 / stream->src.width;
4562236b 544
6702a9ac 545 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 546 stream->dst.width / stream->src.width;
6702a9ac 547 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 548 stream->dst.x + stream->dst.width)
6702a9ac 549 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 550 stream->dst.x + stream->dst.width
6702a9ac 551 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 552
6702a9ac 553 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 554 if (stream->src.y < surf_clip.y)
6702a9ac 555 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 556 - stream->src.y) * stream->dst.height
557 / stream->src.height;
4562236b 558
6702a9ac 559 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 560 stream->dst.height / stream->src.height;
6702a9ac 561 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 562 stream->dst.y + stream->dst.height)
6702a9ac 563 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 564 stream->dst.y + stream->dst.height
6702a9ac 565 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 566
7b779c99 567 /* Handle h & vsplit */
b0131391
DL		 568 if (sec_split && top_bottom_split) {
569 pipe_ctx->plane_res.scl_data.recout.y +=
570 pipe_ctx->plane_res.scl_data.recout.height / 2;
0c31a821 571 /* Floor primary pipe, ceil 2ndary pipe */
b0131391
DL		 572 pipe_ctx->plane_res.scl_data.recout.height =
573 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
574 } else if (pri_split && top_bottom_split)
0c31a821 575 pipe_ctx->plane_res.scl_data.recout.height /= 2;
b0131391 576 else if (pri_split || sec_split) {
0c31a821
YS		 577 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
578 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
579 (plane_state->rotation == ROTATION_ANGLE_180);
580
581 if (plane_state->rotation == ROTATION_ANGLE_90
582 || plane_state->rotation == ROTATION_ANGLE_270)
583 /* Secondary_pipe XOR Rotation_270 */
584 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
585
586 if (right_view) {
587 pipe_ctx->plane_res.scl_data.recout.x +=
588 pipe_ctx->plane_res.scl_data.recout.width / 2;
589 /* Ceil offset pipe */
590 pipe_ctx->plane_res.scl_data.recout.width =
591 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
592 } else {
6702a9ac 593 pipe_ctx->plane_res.scl_data.recout.width /= 2;
0c31a821 594 }
b2d0a103 595 }
86006a7f
DL		 596 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
597 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 598 * ratio)
599 */
b0131391 600 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 601 * stream->dst.width / stream->src.width -
3be5262e 602 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 603 * stream->dst.width / stream->src.width;
b0131391 604 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 605 * stream->dst.height / stream->src.height -
3be5262e 606 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 607 * stream->dst.height / stream->src.height;
c802570e 608
6702a9ac
HW		 609 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
610 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
4562236b
HW		 611}
612
b2d0a103 613static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 614{
3be5262e 615 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 616 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 617 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 618 const int in_w = stream->src.width;
619 const int in_h = stream->src.height;
620 const int out_w = stream->dst.width;
621 const int out_h = stream->dst.height;
4562236b 622
3be5262e
HW		 623 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
624 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 625 rect_swap_helper(&surf_src);
626
6702a9ac 627 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 628 surf_src.width,
3be5262e 629 plane_state->dst_rect.width);
6702a9ac 630 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 631 surf_src.height,
3be5262e 632 plane_state->dst_rect.height);
4562236b 633
4fa086b9 634 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 635 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 636 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 637 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 638
6702a9ac
HW		 639 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
640 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
641 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
642 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 643
6702a9ac
HW		 644 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
645 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 646
6702a9ac
HW		 647 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
648 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
649 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
650 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b
HW		 651 }
652}
653
b2d0a103
DL		 654static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
655{
6702a9ac 656 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 657 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK		 658 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
659 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b0131391 660 bool flip_vert_scan_dir = false, flip_horz_scan_dir = false;
b2d0a103 661
b0131391
DL		 662 /*
663 * Need to calculate the scan direction for viewport to make adjustments
664 */
665 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_180) {
666 flip_vert_scan_dir = true;
667 flip_horz_scan_dir = true;
668 } else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90)
669 flip_vert_scan_dir = true;
670 else if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
671 flip_horz_scan_dir = true;
672 if (pipe_ctx->plane_state->horizontal_mirror)
673 flip_horz_scan_dir = !flip_horz_scan_dir;
674
3be5262e
HW		 675 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
676 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 677 rect_swap_helper(&src);
1fbd2cfc
DL		 678 rect_swap_helper(&data->viewport_c);
679 rect_swap_helper(&data->viewport);
680 }
681
b2d0a103
DL		 682 /*
683 * Init calculated according to formula:
684 * init = (scaling_ratio + number_of_taps + 1) / 2
685 * init_bot = init + scaling_ratio
686 * init_c = init + truncated_vp_c_offset(from calculate viewport)
687 */
688 data->inits.h = dal_fixed31_32_div_int(
689 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
690
691 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
692 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
693
694 data->inits.v = dal_fixed31_32_div_int(
695 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
696
697 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
698 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
699
700
701 /* Adjust for viewport end clip-off */
4ee778dc 702 if ((data->viewport.x + data->viewport.width) < (src.x + src.width) && !flip_horz_scan_dir) {
b2d0a103 703 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 704 int int_part = dal_fixed31_32_floor(
705 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 706
1fbd2cfc 707 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 708 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
709 }
4ee778dc 710 if ((data->viewport.y + data->viewport.height) < (src.y + src.height) && !flip_vert_scan_dir) {
b2d0a103 711 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 712 int int_part = dal_fixed31_32_floor(
713 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 714
1fbd2cfc 715 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 716 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
717 }
4ee778dc 718 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div && !flip_horz_scan_dir) {
b2d0a103
DL		 719 int vp_clip = (src.x + src.width) / vpc_div -
720 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 721 int int_part = dal_fixed31_32_floor(
722 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 723
1fbd2cfc 724 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 725 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
726 }
4ee778dc 727 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div && !flip_vert_scan_dir) {
b2d0a103
DL		 728 int vp_clip = (src.y + src.height) / vpc_div -
729 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 730 int int_part = dal_fixed31_32_floor(
731 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 732
1fbd2cfc 733 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 734 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
735 }
736
737 /* Adjust for non-0 viewport offset */
737ae4ea 738 if (data->viewport.x && !flip_horz_scan_dir) {
b2d0a103
DL		 739 int int_part;
740
741 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
742 data->ratios.horz, recout_skip->width));
743 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
744 if (int_part < data->taps.h_taps) {
745 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
746 (data->taps.h_taps - int_part) : data->viewport.x;
747 data->viewport.x -= int_adj;
748 data->viewport.width += int_adj;
749 int_part += int_adj;
750 } else if (int_part > data->taps.h_taps) {
751 data->viewport.x += int_part - data->taps.h_taps;
752 data->viewport.width -= int_part - data->taps.h_taps;
753 int_part = data->taps.h_taps;
754 }
755 data->inits.h.value &= 0xffffffff;
756 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
757 }
758
737ae4ea 759 if (data->viewport_c.x && !flip_horz_scan_dir) {
b2d0a103
DL		 760 int int_part;
761
762 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
763 data->ratios.horz_c, recout_skip->width));
764 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
765 if (int_part < data->taps.h_taps_c) {
766 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
767 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
768 data->viewport_c.x -= int_adj;
769 data->viewport_c.width += int_adj;
770 int_part += int_adj;
771 } else if (int_part > data->taps.h_taps_c) {
772 data->viewport_c.x += int_part - data->taps.h_taps_c;
773 data->viewport_c.width -= int_part - data->taps.h_taps_c;
774 int_part = data->taps.h_taps_c;
775 }
776 data->inits.h_c.value &= 0xffffffff;
777 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
778 }
779
737ae4ea 780 if (data->viewport.y && !flip_vert_scan_dir) {
b2d0a103
DL		 781 int int_part;
782
783 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
784 data->ratios.vert, recout_skip->height));
785 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
786 if (int_part < data->taps.v_taps) {
787 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
788 (data->taps.v_taps - int_part) : data->viewport.y;
789 data->viewport.y -= int_adj;
790 data->viewport.height += int_adj;
791 int_part += int_adj;
792 } else if (int_part > data->taps.v_taps) {
793 data->viewport.y += int_part - data->taps.v_taps;
794 data->viewport.height -= int_part - data->taps.v_taps;
795 int_part = data->taps.v_taps;
796 }
797 data->inits.v.value &= 0xffffffff;
798 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
799 }
800
737ae4ea 801 if (data->viewport_c.y && !flip_vert_scan_dir) {
b2d0a103
DL		 802 int int_part;
803
804 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
805 data->ratios.vert_c, recout_skip->height));
806 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
807 if (int_part < data->taps.v_taps_c) {
808 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
809 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
810 data->viewport_c.y -= int_adj;
811 data->viewport_c.height += int_adj;
812 int_part += int_adj;
813 } else if (int_part > data->taps.v_taps_c) {
814 data->viewport_c.y += int_part - data->taps.v_taps_c;
815 data->viewport_c.height -= int_part - data->taps.v_taps_c;
816 int_part = data->taps.v_taps_c;
817 }
818 data->inits.v_c.value &= 0xffffffff;
819 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
820 }
821
822 /* Interlaced inits based on final vert inits */
823 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
824 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 825
3be5262e
HW		 826 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
827 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 828 rect_swap_helper(&data->viewport_c);
829 rect_swap_helper(&data->viewport);
830 }
b2d0a103
DL		 831}
832
833bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 834{
3be5262e 835 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 836 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103
DL		 837 struct view recout_skip = { 0 };
838 bool res = false;
5d4b05dd 839 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4562236b
HW		 840 /* Important: scaling ratio calculation requires pixel format,
841 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 842 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 843 */
6702a9ac 844 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 845 pipe_ctx->plane_state->format);
b2d0a103 846
dc002a2e
DL		 847 if (pipe_ctx->stream->timing.flags.INTERLACE)
848 pipe_ctx->stream->dst.height *= 2;
849
b2d0a103 850 calculate_scaling_ratios(pipe_ctx);
4562236b 851
b2d0a103 852 calculate_viewport(pipe_ctx);
4562236b 853
6702a9ac 854 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 855 return false;
856
b2d0a103 857 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 858
859 /**
860 * Setting line buffer pixel depth to 24bpp yields banding
861 * on certain displays, such as the Sharp 4k
862 */
6702a9ac 863 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 864
199e458a 865 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 866 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 867
58bb0e63
AJ		 868 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
869 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
dc002a2e
DL		 870 if (pipe_ctx->stream->timing.flags.INTERLACE)
871 pipe_ctx->plane_res.scl_data.v_active *= 2;
4562236b 872
1b6c8067 873
4562236b 874 /* Taps calculations */
d94585a0
YHL		 875 if (pipe_ctx->plane_res.xfm != NULL)
876 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
877 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
878
879 if (pipe_ctx->plane_res.dpp != NULL)
880 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
881 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 882 if (!res) {
883 /* Try 24 bpp linebuffer */
6702a9ac 884 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 885
1b6c8067
BL		 886 if (pipe_ctx->plane_res.xfm != NULL)
887 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
888 pipe_ctx->plane_res.xfm,
889 &pipe_ctx->plane_res.scl_data,
890 &plane_state->scaling_quality);
891
892 if (pipe_ctx->plane_res.dpp != NULL)
893 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
894 pipe_ctx->plane_res.dpp,
895 &pipe_ctx->plane_res.scl_data,
896 &plane_state->scaling_quality);
4562236b
HW		 897 }
898
b2d0a103 899 if (res)
1fbd2cfc 900 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 901 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
902
1296423b 903 DC_LOG_SCALER(
4562236b
HW		 904 "%s: Viewport:\nheight:%d width:%d x:%d "
905 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
906 "y:%d\n",
907 __func__,
6702a9ac
HW		 908 pipe_ctx->plane_res.scl_data.viewport.height,
909 pipe_ctx->plane_res.scl_data.viewport.width,
910 pipe_ctx->plane_res.scl_data.viewport.x,
911 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 912 plane_state->dst_rect.height,
913 plane_state->dst_rect.width,
914 plane_state->dst_rect.x,
915 plane_state->dst_rect.y);
4562236b 916
dc002a2e
DL		 917 if (pipe_ctx->stream->timing.flags.INTERLACE)
918 pipe_ctx->stream->dst.height /= 2;
919
4562236b
HW		 920 return res;
921}
922
923
924enum dc_status resource_build_scaling_params_for_context(
fb3466a4 925 const struct dc *dc,
608ac7bb 926 struct dc_state *context)
4562236b
HW		 927{
928 int i;
929
930 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 931 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 932 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 933 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 934 return DC_FAIL_SCALING;
4562236b
HW		 935 }
936
937 return DC_OK;
938}
939
a2b8659d
TC		 940struct pipe_ctx *find_idle_secondary_pipe(
941 struct resource_context *res_ctx,
942 const struct resource_pool *pool)
4562236b
HW		 943{
944 int i;
945 struct pipe_ctx *secondary_pipe = NULL;
946
947 /*
948 * search backwards for the second pipe to keep pipe
949 * assignment more consistent
950 */
951
a2b8659d 952 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 953 if (res_ctx->pipe_ctx[i].stream == NULL) {
954 secondary_pipe = &res_ctx->pipe_ctx[i];
955 secondary_pipe->pipe_idx = i;
956 break;
957 }
958 }
959
960
961 return secondary_pipe;
962}
963
964struct pipe_ctx *resource_get_head_pipe_for_stream(
965 struct resource_context *res_ctx,
0971c40e 966 struct dc_stream_state *stream)
4562236b
HW		 967{
968 int i;
a2b8659d 969 for (i = 0; i < MAX_PIPES; i++) {
4562236b 970 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 971 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 972 return &res_ctx->pipe_ctx[i];
973 break;
974 }
975 }
976 return NULL;
977}
978
19f89e23
AG		 979static struct pipe_ctx *resource_get_tail_pipe_for_stream(
980 struct resource_context *res_ctx,
981 struct dc_stream_state *stream)
982{
983 struct pipe_ctx *head_pipe, *tail_pipe;
984 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
985
986 if (!head_pipe)
987 return NULL;
988
989 tail_pipe = head_pipe->bottom_pipe;
990
991 while (tail_pipe) {
992 head_pipe = tail_pipe;
993 tail_pipe = tail_pipe->bottom_pipe;
994 }
995
996 return head_pipe;
997}
998
4562236b 999/*
ab2541b6
AC		 1000 * A free_pipe for a stream is defined here as a pipe
1001 * that has no surface attached yet
4562236b 1002 */
ab2541b6 1003static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1004 struct dc_state *context,
a2b8659d 1005 const struct resource_pool *pool,
0971c40e 1006 struct dc_stream_state *stream)
4562236b
HW		 1007{
1008 int i;
745cc746 1009 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1010
1011 struct pipe_ctx *head_pipe = NULL;
1012
1013 /* Find head pipe, which has the back end set up*/
1014
1015 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1016
e41ab030 1017 if (!head_pipe) {
4562236b 1018 ASSERT(0);
e41ab030
HW		 1019 return NULL;
1020 }
4562236b 1021
3be5262e 1022 if (!head_pipe->plane_state)
4562236b
HW		 1023 return head_pipe;
1024
1025 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1026 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1027 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1028 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1029 return &res_ctx->pipe_ctx[i];
1030 }
1031 }
1032
1033 /*
1034 * At this point we have no re-useable pipe for this stream and we need
1035 * to acquire an idle one to satisfy the request
1036 */
1037
a2b8659d 1038 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1039 return NULL;
1040
a2b8659d 1041 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1042
1043}
1044
0f9a536f
DL		 1045#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1046static int acquire_first_split_pipe(
1047 struct resource_context *res_ctx,
1048 const struct resource_pool *pool,
0971c40e 1049 struct dc_stream_state *stream)
0f9a536f
DL		 1050{
1051 int i;
1052
1053 for (i = 0; i < pool->pipe_count; i++) {
1054 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1055
1056 if (pipe_ctx->top_pipe &&
3be5262e 1057 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1058 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1059 if (pipe_ctx->bottom_pipe)
1060 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1061
1062 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1063 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1064 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1065 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1066 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1067 pipe_ctx->stream_res.opp = pool->opps[i];
e07f541f 1068 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
0f9a536f 1069 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1070
1071 pipe_ctx->stream = stream;
1072 return i;
1073 }
1074 }
1075 return -1;
1076}
1077#endif
1078
19f89e23
AG		 1079bool dc_add_plane_to_context(
1080 const struct dc *dc,
0971c40e 1081 struct dc_stream_state *stream,
19f89e23 1082 struct dc_plane_state *plane_state,
608ac7bb 1083 struct dc_state *context)
4562236b
HW		 1084{
1085 int i;
19f89e23
AG		 1086 struct resource_pool *pool = dc->res_pool;
1087 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1088 struct dc_stream_status *stream_status = NULL;
4562236b 1089
19f89e23
AG		 1090 for (i = 0; i < context->stream_count; i++)
1091 if (context->streams[i] == stream) {
1092 stream_status = &context->stream_status[i];
1093 break;
1094 }
1095 if (stream_status == NULL) {
1096 dm_error("Existing stream not found; failed to attach surface!\n");
1097 return false;
1098 }
1099
4562236b 1100
19f89e23
AG		 1101 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1102 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1103 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1104 return false;
1105 }
1106
19f89e23
AG		 1107 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1108
1109 if (!head_pipe) {
1110 dm_error("Head pipe not found for stream_state %p !\n", stream);
1111 return false;
1112 }
1113
19f89e23
AG		 1114 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1115
1116#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1117 if (!free_pipe) {
1118 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1119 if (pipe_idx >= 0)
1120 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1121 }
1122#endif
abb4986e 1123 if (!free_pipe)
19f89e23 1124 return false;
19f89e23 1125
abb4986e
AJ		 1126 /* retain new surfaces */
1127 dc_plane_state_retain(plane_state);
19f89e23
AG		 1128 free_pipe->plane_state = plane_state;
1129
1130 if (head_pipe != free_pipe) {
1131
1132 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1133 ASSERT(tail_pipe);
1134
1135 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
9aef1a31 1136 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
19f89e23
AG		 1137 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1138 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1139 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1140 free_pipe->clock_source = tail_pipe->clock_source;
1141 free_pipe->top_pipe = tail_pipe;
1142 tail_pipe->bottom_pipe = free_pipe;
1143 }
1144
1145 /* assign new surfaces*/
1146 stream_status->plane_states[stream_status->plane_count] = plane_state;
1147
1148 stream_status->plane_count++;
1149
1150 return true;
1151}
1152
1153bool dc_remove_plane_from_context(
1154 const struct dc *dc,
1155 struct dc_stream_state *stream,
1156 struct dc_plane_state *plane_state,
608ac7bb 1157 struct dc_state *context)
19f89e23
AG		 1158{
1159 int i;
1160 struct dc_stream_status *stream_status = NULL;
1161 struct resource_pool *pool = dc->res_pool;
1162
ab2541b6 1163 for (i = 0; i < context->stream_count; i++)
4fa086b9 1164 if (context->streams[i] == stream) {
ab2541b6 1165 stream_status = &context->stream_status[i];
4562236b
HW		 1166 break;
1167 }
19f89e23 1168
ab2541b6 1169 if (stream_status == NULL) {
19f89e23 1170 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1171 return false;
1172 }
1173
19f89e23
AG		 1174 /* release pipe for plane*/
1175 for (i = pool->pipe_count - 1; i >= 0; i--) {
1176 struct pipe_ctx *pipe_ctx;
4562236b 1177
19f89e23
AG		 1178 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1179 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1180
19f89e23
AG		 1181 if (pipe_ctx->top_pipe)
1182 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1183
19f89e23
AG		 1184 /* Second condition is to avoid setting NULL to top pipe
1185 * of tail pipe making it look like head pipe in subsequent
1186 * deletes
1187 */
1188 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1189 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1190
19f89e23
AG		 1191 /*
1192 * For head pipe detach surfaces from pipe for tail
1193 * pipe just zero it out
1194 */
1195 if (!pipe_ctx->top_pipe) {
1196 pipe_ctx->plane_state = NULL;
1197 pipe_ctx->bottom_pipe = NULL;
1198 } else {
1199 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1200 }
4562236b 1201 }
19f89e23 1202 }
4562236b 1203
4562236b 1204
19f89e23
AG		 1205 for (i = 0; i < stream_status->plane_count; i++) {
1206 if (stream_status->plane_states[i] == plane_state) {
1207
1208 dc_plane_state_release(stream_status->plane_states[i]);
1209 break;
4562236b 1210 }
19f89e23 1211 }
4562236b 1212
19f89e23
AG		 1213 if (i == stream_status->plane_count) {
1214 dm_error("Existing plane_state not found; failed to detach it!\n");
1215 return false;
4562236b
HW		 1216 }
1217
19f89e23 1218 stream_status->plane_count--;
4562236b 1219
abb4986e
AJ		 1220 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1221 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1222 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1223
1224 stream_status->plane_states[stream_status->plane_count] = NULL;
1225
1226 return true;
1227}
1228
1229bool dc_rem_all_planes_for_stream(
1230 const struct dc *dc,
1231 struct dc_stream_state *stream,
608ac7bb 1232 struct dc_state *context)
19f89e23
AG		 1233{
1234 int i, old_plane_count;
1235 struct dc_stream_status *stream_status = NULL;
1236 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1237
1238 for (i = 0; i < context->stream_count; i++)
1239 if (context->streams[i] == stream) {
1240 stream_status = &context->stream_status[i];
1241 break;
1242 }
1243
1244 if (stream_status == NULL) {
1245 dm_error("Existing stream %p not found!\n", stream);
1246 return false;
1247 }
1248
1249 old_plane_count = stream_status->plane_count;
1250
1251 for (i = 0; i < old_plane_count; i++)
1252 del_planes[i] = stream_status->plane_states[i];
1253
1254 for (i = 0; i < old_plane_count; i++)
1255 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1256 return false;
1257
1258 return true;
1259}
1260
1261static bool add_all_planes_for_stream(
1262 const struct dc *dc,
1263 struct dc_stream_state *stream,
1264 const struct dc_validation_set set[],
1265 int set_count,
608ac7bb 1266 struct dc_state *context)
19f89e23
AG		 1267{
1268 int i, j;
1269
1270 for (i = 0; i < set_count; i++)
1271 if (set[i].stream == stream)
1272 break;
1273
1274 if (i == set_count) {
1275 dm_error("Stream %p not found in set!\n", stream);
1276 return false;
1277 }
4562236b 1278
19f89e23
AG		 1279 for (j = 0; j < set[i].plane_count; j++)
1280 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1281 return false;
4562236b
HW		 1282
1283 return true;
1284}
1285
19f89e23
AG		 1286bool dc_add_all_planes_for_stream(
1287 const struct dc *dc,
1288 struct dc_stream_state *stream,
1289 struct dc_plane_state * const *plane_states,
1290 int plane_count,
608ac7bb 1291 struct dc_state *context)
19f89e23
AG		 1292{
1293 struct dc_validation_set set;
1294 int i;
1295
1296 set.stream = stream;
1297 set.plane_count = plane_count;
1298
1299 for (i = 0; i < plane_count; i++)
1300 set.plane_states[i] = plane_states[i];
1301
1302 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1303}
1304
1305
4562236b 1306
0971c40e
HW		 1307static bool is_timing_changed(struct dc_stream_state *cur_stream,
1308 struct dc_stream_state *new_stream)
4562236b
HW		 1309{
1310 if (cur_stream == NULL)
1311 return true;
1312
1313 /* If sink pointer changed, it means this is a hotplug, we should do
1314 * full hw setting.
1315 */
1316 if (cur_stream->sink != new_stream->sink)
1317 return true;
1318
1319 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1320 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1321 return true;
1322
1323 return memcmp(
4fa086b9
LSL		 1324 &cur_stream->timing,
1325 &new_stream->timing,
4562236b
HW		 1326 sizeof(struct dc_crtc_timing)) != 0;
1327}
1328
1329static bool are_stream_backends_same(
0971c40e 1330 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1331{
1332 if (stream_a == stream_b)
1333 return true;
1334
1335 if (stream_a == NULL || stream_b == NULL)
1336 return false;
1337
1338 if (is_timing_changed(stream_a, stream_b))
1339 return false;
1340
1341 return true;
1342}
1343
d54d29db 1344bool dc_is_stream_unchanged(
0971c40e 1345 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1346{
4562236b 1347
ab2541b6
AC		 1348 if (!are_stream_backends_same(old_stream, stream))
1349 return false;
4562236b
HW		 1350
1351 return true;
1352}
1353
9a5d9c48
LSL		 1354bool dc_is_stream_scaling_unchanged(
1355 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1356{
1357 if (old_stream == stream)
1358 return true;
1359
1360 if (old_stream == NULL || stream == NULL)
1361 return false;
1362
1363 if (memcmp(&old_stream->src,
1364 &stream->src,
1365 sizeof(struct rect)) != 0)
1366 return false;
1367
1368 if (memcmp(&old_stream->dst,
1369 &stream->dst,
1370 sizeof(struct rect)) != 0)
1371 return false;
1372
1373 return true;
1374}
1375
1dc90497 1376static void update_stream_engine_usage(
4562236b 1377 struct resource_context *res_ctx,
a2b8659d 1378 const struct resource_pool *pool,
1dc90497
AG		 1379 struct stream_encoder *stream_enc,
1380 bool acquired)
4562236b
HW		 1381{
1382 int i;
1383
a2b8659d
TC		 1384 for (i = 0; i < pool->stream_enc_count; i++) {
1385 if (pool->stream_enc[i] == stream_enc)
1dc90497 1386 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1387 }
1388}
1389
1390/* TODO: release audio object */
4176664b 1391void update_audio_usage(
4562236b 1392 struct resource_context *res_ctx,
a2b8659d 1393 const struct resource_pool *pool,
1dc90497
AG		 1394 struct audio *audio,
1395 bool acquired)
4562236b
HW		 1396{
1397 int i;
a2b8659d
TC		 1398 for (i = 0; i < pool->audio_count; i++) {
1399 if (pool->audios[i] == audio)
1dc90497 1400 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1401 }
1402}
1403
1404static int acquire_first_free_pipe(
1405 struct resource_context *res_ctx,
a2b8659d 1406 const struct resource_pool *pool,
0971c40e 1407 struct dc_stream_state *stream)
4562236b
HW		 1408{
1409 int i;
1410
a2b8659d 1411 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1412 if (!res_ctx->pipe_ctx[i].stream) {
1413 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1414
6b670fa9 1415 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1416 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1417 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1418 pipe_ctx->plane_res.ipp = pool->ipps[i];
1419 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1420 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1421 pipe_ctx->stream_res.opp = pool->opps[i];
bc373a89
RL		 1422 if (pool->dpps[i])
1423 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
4562236b
HW		 1424 pipe_ctx->pipe_idx = i;
1425
ff5ef992 1426
4562236b
HW		 1427 pipe_ctx->stream = stream;
1428 return i;
1429 }
1430 }
1431 return -1;
1432}
1433
1434static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1435 struct resource_context *res_ctx,
a2b8659d 1436 const struct resource_pool *pool,
0971c40e 1437 struct dc_stream_state *stream)
4562236b
HW		 1438{
1439 int i;
1440 int j = -1;
d0778ebf 1441 struct dc_link *link = stream->sink->link;
4562236b 1442
a2b8659d 1443 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1444 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1445 pool->stream_enc[i]) {
4562236b
HW		 1446 /* Store first available for MST second display
1447 * in daisy chain use case */
1448 j = i;
a2b8659d 1449 if (pool->stream_enc[i]->id ==
4562236b 1450 link->link_enc->preferred_engine)
a2b8659d 1451 return pool->stream_enc[i];
4562236b
HW		 1452 }
1453 }
1454
1455 /*
1456 * below can happen in cases when stream encoder is acquired:
1457 * 1) for second MST display in chain, so preferred engine already
1458 * acquired;
1459 * 2) for another link, which preferred engine already acquired by any
1460 * MST configuration.
1461 *
1462 * If signal is of DP type and preferred engine not found, return last available
1463 *
1464 * TODO - This is just a patch up and a generic solution is
1465 * required for non DP connectors.
1466 */
1467
1468 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1469 return pool->stream_enc[j];
4562236b
HW		 1470
1471 return NULL;
1472}
1473
a2b8659d
TC		 1474static struct audio *find_first_free_audio(
1475 struct resource_context *res_ctx,
cfb071f7
CL		 1476 const struct resource_pool *pool,
1477 enum engine_id id)
4562236b
HW		 1478{
1479 int i;
66bfd4fd
CL		 1480 for (i = 0; i < pool->audio_count; i++) {
1481 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1482 /*we have enough audio endpoint, find the matching inst*/
1483 if (id != i)
1484 continue;
1485
66bfd4fd 1486 return pool->audios[i];
4562236b 1487 }
66bfd4fd
CL		 1488 }
1489 /*not found the matching one, first come first serve*/
1490 for (i = 0; i < pool->audio_count; i++) {
1491 if (res_ctx->is_audio_acquired[i] == false) {
1492 return pool->audios[i];
4176664b
CL		 1493 }
1494 }
4562236b
HW		 1495 return 0;
1496}
1497
4562236b 1498bool resource_is_stream_unchanged(
608ac7bb 1499 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1500{
ab2541b6 1501 int i;
4562236b 1502
ab2541b6 1503 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1504 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1505
ab2541b6 1506 if (are_stream_backends_same(old_stream, stream))
4562236b 1507 return true;
4562236b
HW		 1508 }
1509
1510 return false;
1511}
1512
13ab1b44 1513enum dc_status dc_add_stream_to_ctx(
1dc90497 1514 struct dc *dc,
608ac7bb 1515 struct dc_state *new_ctx,
1dc90497
AG		 1516 struct dc_stream_state *stream)
1517{
1518 struct dc_context *dc_ctx = dc->ctx;
1519 enum dc_status res;
1520
1521 if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
1522 DC_ERROR("Max streams reached, can add stream %p !\n", stream);
1523 return DC_ERROR_UNEXPECTED;
1524 }
1525
1526 new_ctx->streams[new_ctx->stream_count] = stream;
1527 dc_stream_retain(stream);
1528 new_ctx->stream_count++;
1529
1530 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1531 if (res != DC_OK)
1532 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1533
13ab1b44 1534 return res;
1dc90497
AG		 1535}
1536
62c933f9 1537enum dc_status dc_remove_stream_from_ctx(
1dc90497 1538 struct dc *dc,
608ac7bb 1539 struct dc_state *new_ctx,
1dc90497
AG		 1540 struct dc_stream_state *stream)
1541{
19f89e23 1542 int i;
1dc90497
AG		 1543 struct dc_context *dc_ctx = dc->ctx;
1544 struct pipe_ctx *del_pipe = NULL;
1545
19f89e23 1546 /* Release primary pipe */
1dc90497 1547 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1548 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1549 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1550 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1551
19f89e23
AG		 1552 ASSERT(del_pipe->stream_res.stream_enc);
1553 update_stream_engine_usage(
1554 &new_ctx->res_ctx,
1dc90497 1555 dc->res_pool,
19f89e23
AG		 1556 del_pipe->stream_res.stream_enc,
1557 false);
1dc90497
AG		 1558
1559 if (del_pipe->stream_res.audio)
1560 update_audio_usage(
1561 &new_ctx->res_ctx,
1562 dc->res_pool,
1563 del_pipe->stream_res.audio,
1564 false);
1565
9d0dcecd
HW		 1566 resource_unreference_clock_source(&new_ctx->res_ctx,
1567 dc->res_pool,
1568 del_pipe->clock_source);
1569
e56ae556
NC		 1570 if (dc->res_pool->funcs->remove_stream_from_ctx)
1571 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1572
1dc90497 1573 memset(del_pipe, 0, sizeof(*del_pipe));
19f89e23
AG		 1574
1575 break;
1dc90497
AG		 1576 }
1577 }
1578
1579 if (!del_pipe) {
1580 DC_ERROR("Pipe not found for stream %p !\n", stream);
1581 return DC_ERROR_UNEXPECTED;
1582 }
1583
1584 for (i = 0; i < new_ctx->stream_count; i++)
1585 if (new_ctx->streams[i] == stream)
1586 break;
1587
1588 if (new_ctx->streams[i] != stream) {
1589 DC_ERROR("Context doesn't have stream %p !\n", stream);
1590 return DC_ERROR_UNEXPECTED;
1591 }
1592
1593 dc_stream_release(new_ctx->streams[i]);
1594 new_ctx->stream_count--;
1595
1dc90497
AG		 1596 /* Trim back arrays */
1597 for (; i < new_ctx->stream_count; i++) {
1598 new_ctx->streams[i] = new_ctx->streams[i + 1];
1599 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1600 }
1601
1602 new_ctx->streams[new_ctx->stream_count] = NULL;
1603 memset(
1604 &new_ctx->stream_status[new_ctx->stream_count],
1605 0,
1606 sizeof(new_ctx->stream_status[0]));
1607
1608 return DC_OK;
1609}
1610
0971c40e
HW		 1611static struct dc_stream_state *find_pll_sharable_stream(
1612 struct dc_stream_state *stream_needs_pll,
608ac7bb 1613 struct dc_state *context)
4562236b 1614{
ab2541b6 1615 int i;
4562236b 1616
ab2541b6 1617 for (i = 0; i < context->stream_count; i++) {
0971c40e 1618 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1619
ab2541b6
AC		 1620 /* We are looking for non dp, non virtual stream */
1621 if (resource_are_streams_timing_synchronizable(
1622 stream_needs_pll, stream_has_pll)
1623 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1624 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1625 != SIGNAL_TYPE_VIRTUAL)
1626 return stream_has_pll;
4562236b 1627
4562236b
HW		 1628 }
1629
1630 return NULL;
1631}
1632
1633static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1634{
1635 uint32_t pix_clk = timing->pix_clk_khz;
1636 uint32_t normalized_pix_clk = pix_clk;
1637
1638 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1639 pix_clk /= 2;
cc4d99b8
CL		 1640 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1641 switch (timing->display_color_depth) {
1642 case COLOR_DEPTH_888:
1643 normalized_pix_clk = pix_clk;
1644 break;
1645 case COLOR_DEPTH_101010:
1646 normalized_pix_clk = (pix_clk * 30) / 24;
1647 break;
1648 case COLOR_DEPTH_121212:
1649 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1650 break;
cc4d99b8
CL		 1651 case COLOR_DEPTH_161616:
1652 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1653 break;
cc4d99b8
CL		 1654 default:
1655 ASSERT(0);
4562236b 1656 break;
cc4d99b8 1657 }
4562236b 1658 }
4562236b
HW		 1659 return normalized_pix_clk;
1660}
1661
0971c40e 1662static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1663{
9345d987
AG		 1664 /* update actual pixel clock on all streams */
1665 if (dc_is_hdmi_signal(stream->signal))
1666 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1667 &stream->timing);
9345d987
AG		 1668 else
1669 stream->phy_pix_clk =
4fa086b9 1670 stream->timing.pix_clk_khz;
4562236b
HW		 1671}
1672
1673enum dc_status resource_map_pool_resources(
fb3466a4 1674 const struct dc *dc,
608ac7bb 1675 struct dc_state *context,
1dc90497 1676 struct dc_stream_state *stream)
4562236b 1677{
a2b8659d 1678 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1679 int i;
1680 struct dc_context *dc_ctx = dc->ctx;
1681 struct pipe_ctx *pipe_ctx = NULL;
1682 int pipe_idx = -1;
4562236b 1683
1dc90497
AG		 1684 /* TODO Check if this is needed */
1685 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1686 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1687 stream->bit_depth_params =
430ef426
DL		 1688 old_context->streams[i]->bit_depth_params;
1689 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1690 continue;
1691 }
4b679bc3 1692 }
1dc90497 1693 */
7e2fe319 1694
1dc90497
AG		 1695 /* acquire new resources */
1696 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1697
94c6d735 1698#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1699 if (pipe_idx < 0)
13ab1b44 1700 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1701#endif
13ab1b44 1702
c5b38aec 1703 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1dc90497
AG		 1704 return DC_NO_CONTROLLER_RESOURCE;
1705
1706 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1707
1708 pipe_ctx->stream_res.stream_enc =
1709 find_first_free_match_stream_enc_for_link(
1710 &context->res_ctx, pool, stream);
1711
1712 if (!pipe_ctx->stream_res.stream_enc)
1713 return DC_NO_STREAM_ENG_RESOURCE;
1714
1715 update_stream_engine_usage(
1716 &context->res_ctx, pool,
1717 pipe_ctx->stream_res.stream_enc,
1718 true);
1719
1720 /* TODO: Add check if ASIC support and EDID audio */
1721 if (!stream->sink->converter_disable_audio &&
1722 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1723 stream->audio_info.mode_count) {
1724 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1725 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1726
1727 /*
1728 * Audio assigned in order first come first get.
1729 * There are asics which has number of audio
1730 * resources less then number of pipes
1731 */
1732 if (pipe_ctx->stream_res.audio)
1733 update_audio_usage(&context->res_ctx, pool,
1734 pipe_ctx->stream_res.audio, true);
1735 }
268cadbd 1736
9aef1a31
S		 1737 /* Add ABM to the resource if on EDP */
1738 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1739 pipe_ctx->stream_res.abm = pool->abm;
1740
1dc90497
AG		 1741 for (i = 0; i < context->stream_count; i++)
1742 if (context->streams[i] == stream) {
1743 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1744 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1745 return DC_OK;
1746 }
4562236b 1747
1dc90497
AG		 1748 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1749 return DC_ERROR_UNEXPECTED;
1750}
4562236b 1751
f36cc577 1752void dc_resource_state_copy_construct_current(
1dc90497 1753 const struct dc *dc,
608ac7bb 1754 struct dc_state *dst_ctx)
1dc90497 1755{
f36cc577 1756 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1757}
1758
ab8db3e1
AG		 1759
1760void dc_resource_state_construct(
1761 const struct dc *dc,
1762 struct dc_state *dst_ctx)
1763{
1764 dst_ctx->dis_clk = dc->res_pool->display_clock;
1765}
1766
e750d56d 1767enum dc_status dc_validate_global_state(
1dc90497 1768 struct dc *dc,
608ac7bb 1769 struct dc_state *new_ctx)
4562236b 1770{
1dc90497 1771 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1772 int i, j;
4562236b 1773
e41ab030
HW		 1774 if (!new_ctx)
1775 return DC_ERROR_UNEXPECTED;
1776
d596e5d0
YS		 1777 if (dc->res_pool->funcs->validate_global) {
1778 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1779 if (result != DC_OK)
1780 return result;
1781 }
4562236b 1782
e41ab030 1783 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 1784 struct dc_stream_state *stream = new_ctx->streams[i];
1785
1786 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1787 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1788
1789 if (pipe_ctx->stream != stream)
1790 continue;
1791
1792 /* Switch to dp clock source only if there is
1793 * no non dp stream that shares the same timing
1794 * with the dp stream.
1795 */
1796 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1797 !find_pll_sharable_stream(stream, new_ctx)) {
1798
9d0dcecd 1799 resource_unreference_clock_source(
1dc90497
AG		 1800 &new_ctx->res_ctx,
1801 dc->res_pool,
9d0dcecd 1802 pipe_ctx->clock_source);
4a629536 1803
1dc90497
AG		 1804 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1805 resource_reference_clock_source(
1806 &new_ctx->res_ctx,
1807 dc->res_pool,
1808 pipe_ctx->clock_source);
1809 }
1810 }
1811 }
1812
1dc90497
AG		 1813 result = resource_build_scaling_params_for_context(dc, new_ctx);
1814
1815 if (result == DC_OK)
1816 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1817 result = DC_FAIL_BANDWIDTH_VALIDATE;
1818
1819 return result;
4562236b
HW		 1820}
1821
6e4d6bee 1822static void patch_gamut_packet_checksum(
e09b6473 1823 struct dc_info_packet *gamut_packet)
4562236b 1824{
4562236b 1825 /* For gamut we recalc checksum */
6e4d6bee 1826 if (gamut_packet->valid) {
4562236b
HW		 1827 uint8_t chk_sum = 0;
1828 uint8_t *ptr;
1829 uint8_t i;
1830
4562236b 1831 /*start of the Gamut data. */
6e4d6bee 1832 ptr = &gamut_packet->sb[3];
4562236b 1833
6e4d6bee 1834 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1835 chk_sum += ptr[i];
1836
6e4d6bee 1837 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1838 }
4562236b
HW		 1839}
1840
1841static void set_avi_info_frame(
e09b6473 1842 struct dc_info_packet *info_packet,
4562236b
HW		 1843 struct pipe_ctx *pipe_ctx)
1844{
0971c40e 1845 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b 1846 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4562236b
HW		 1847 uint32_t pixel_encoding = 0;
1848 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1849 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1850 bool itc = false;
50e27654 1851 uint8_t itc_value = 0;
4562236b 1852 uint8_t cn0_cn1 = 0;
50e27654 1853 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1854 uint8_t *check_sum = NULL;
1855 uint8_t byte_index = 0;
754e3673 1856 union hdmi_info_packet hdmi_info;
50e27654 1857 union display_content_support support = {0};
4fa086b9 1858 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 1859 enum dc_timing_3d_format format;
4562236b 1860
754e3673
AK		 1861 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
1862
4fa086b9 1863 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 1864 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 1865 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 1866 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1867
1868 /* Initialize header */
e09b6473 1869 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1870 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1871 * not be used in HDMI 2.0 (Section 10.1) */
e09b6473
AK		 1872 hdmi_info.bits.header.version = 2;
1873 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1874
1875 /*
1876 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1877 * according to HDMI 2.0 spec (Section 10.1)
1878 */
1879
4fa086b9 1880 switch (stream->timing.pixel_encoding) {
4562236b
HW		 1881 case PIXEL_ENCODING_YCBCR422:
1882 pixel_encoding = 1;
1883 break;
1884
1885 case PIXEL_ENCODING_YCBCR444:
1886 pixel_encoding = 2;
1887 break;
1888 case PIXEL_ENCODING_YCBCR420:
1889 pixel_encoding = 3;
1890 break;
1891
1892 case PIXEL_ENCODING_RGB:
1893 default:
1894 pixel_encoding = 0;
1895 }
1896
1897 /* Y0_Y1_Y2 : The pixel encoding */
1898 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e09b6473 1899 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1900
1901 /* A0 = 1 Active Format Information valid */
e09b6473 1902 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1903
1904 /* B0, B1 = 3; Bar info data is valid */
e09b6473 1905 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1906
e09b6473 1907 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1908
1909 /* S0, S1 : Underscan / Overscan */
1910 /* TODO: un-hardcode scan type */
1911 scan_type = SCANNING_TYPE_UNDERSCAN;
e09b6473 1912 hdmi_info.bits.S0_S1 = scan_type;
4562236b
HW		 1913
1914 /* C0, C1 : Colorimetry */
8fde5884 1915 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1916 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e09b6473 1917 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1918 else if (color_space == COLOR_SPACE_YCBCR601 ||
1919 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e09b6473 1920 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 1921 else {
e09b6473 1922 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1923 }
534db198 1924 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1925 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1926 color_space == COLOR_SPACE_2020_YCBCR) {
e09b6473
AK		 1927 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1928 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1929 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e09b6473
AK		 1930 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1931 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1932 }
1933
4562236b 1934 /* TODO: un-hardcode aspect ratio */
4fa086b9 1935 aspect = stream->timing.aspect_ratio;
4562236b
HW		 1936
1937 switch (aspect) {
1938 case ASPECT_RATIO_4_3:
1939 case ASPECT_RATIO_16_9:
e09b6473 1940 hdmi_info.bits.M0_M1 = aspect;
4562236b
HW		 1941 break;
1942
1943 case ASPECT_RATIO_NO_DATA:
1944 case ASPECT_RATIO_64_27:
1945 case ASPECT_RATIO_256_135:
1946 default:
e09b6473 1947 hdmi_info.bits.M0_M1 = 0;
4562236b
HW		 1948 }
1949
1950 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e09b6473 1951 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 1952
1953 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 1954
4562236b 1955 cn0_cn1 = 0;
50e27654
ZF		 1956 cn0_cn1_value = 0;
1957
1958 itc = true;
1959 itc_value = 1;
1960
4fa086b9 1961 support = stream->sink->edid_caps.content_support;
4562236b
HW		 1962
1963 if (itc) {
50e27654
ZF		 1964 if (!support.bits.valid_content_type) {
1965 cn0_cn1_value = 0;
1966 } else {
1967 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
1968 if (support.bits.graphics_content == 1) {
1969 cn0_cn1_value = 0;
1970 }
1971 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
1972 if (support.bits.photo_content == 1) {
1973 cn0_cn1_value = 1;
1974 } else {
1975 cn0_cn1_value = 0;
1976 itc_value = 0;
1977 }
1978 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
1979 if (support.bits.cinema_content == 1) {
1980 cn0_cn1_value = 2;
1981 } else {
1982 cn0_cn1_value = 0;
1983 itc_value = 0;
1984 }
1985 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
1986 if (support.bits.game_content == 1) {
1987 cn0_cn1_value = 3;
1988 } else {
1989 cn0_cn1_value = 0;
1990 itc_value = 0;
1991 }
1992 }
1993 }
e09b6473
AK		 1994 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
1995 hdmi_info.bits.ITC = itc_value;
4562236b
HW		 1996 }
1997
1998 /* TODO : We should handle YCC quantization */
1999 /* but we do not have matrix calculation */
4fa086b9
LSL		 2000 if (stream->sink->edid_caps.qs_bit == 1 &&
2001 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 2002 if (color_space == COLOR_SPACE_SRGB ||
2003 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
e09b6473
AK		 2004 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2005 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
50e27654
ZF		 2006 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2007 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
e09b6473
AK		 2008 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2009 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2010 } else {
e09b6473
AK		 2011 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2012 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
50e27654 2013 }
4562236b 2014 } else {
e09b6473
AK		 2015 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2016 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2017 }
50e27654 2018
15e17335 2019 ///VIC
4fa086b9 2020 format = stream->timing.timing_3d_format;
15e17335
CL		 2021 /*todo, add 3DStereo support*/
2022 if (format != TIMING_3D_FORMAT_NONE) {
2023 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2024 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2025 case 1:
2026 vic = 95;
2027 break;
2028 case 2:
2029 vic = 94;
2030 break;
2031 case 3:
2032 vic = 93;
2033 break;
2034 case 4:
2035 vic = 98;
2036 break;
2037 default:
2038 break;
2039 }
2040 }
e09b6473 2041 hdmi_info.bits.VIC0_VIC7 = vic;
4562236b
HW		 2042
2043 /* pixel repetition
2044 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2045 * repetition start from 1 */
e09b6473 2046 hdmi_info.bits.PR0_PR3 = 0;
4562236b
HW		 2047
2048 /* Bar Info
2049 * barTop: Line Number of End of Top Bar.
2050 * barBottom: Line Number of Start of Bottom Bar.
2051 * barLeft: Pixel Number of End of Left Bar.
2052 * barRight: Pixel Number of Start of Right Bar. */
e09b6473
AK		 2053 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2054 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4fa086b9 2055 - stream->timing.v_border_bottom + 1);
e09b6473
AK		 2056 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2057 hdmi_info.bits.bar_right = (stream->timing.h_total
4fa086b9 2058 - stream->timing.h_border_right + 1);
4562236b
HW		 2059
2060 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e09b6473 2061 check_sum = &hdmi_info.packet_raw_data.sb[0];
e8d726b7 2062
3e183c5f 2063 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2064
3e183c5f 2065 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e09b6473 2066 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2067
2068 /* one byte complement */
2069 *check_sum = (uint8_t) (0x100 - *check_sum);
2070
2071 /* Store in hw_path_mode */
e09b6473
AK		 2072 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2073 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2074 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4562236b 2075
e09b6473
AK		 2076 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2077 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4562236b
HW		 2078
2079 info_packet->valid = true;
2080}
2081
6e4d6bee 2082static void set_vendor_info_packet(
e09b6473 2083 struct dc_info_packet *info_packet,
0971c40e 2084 struct dc_stream_state *stream)
4562236b
HW		 2085{
2086 uint32_t length = 0;
2087 bool hdmi_vic_mode = false;
2088 uint8_t checksum = 0;
2089 uint32_t i = 0;
2090 enum dc_timing_3d_format format;
15e17335
CL		 2091 // Can be different depending on packet content /*todo*/
2092 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2093
2094 info_packet->valid = false;
4562236b 2095
4fa086b9
LSL		 2096 format = stream->timing.timing_3d_format;
2097 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2098 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2099
2100 /* Can be different depending on packet content */
2101 length = 5;
2102
4fa086b9
LSL		 2103 if (stream->timing.hdmi_vic != 0
2104 && stream->timing.h_total >= 3840
2105 && stream->timing.v_total >= 2160)
4562236b
HW		 2106 hdmi_vic_mode = true;
2107
2108 /* According to HDMI 1.4a CTS, VSIF should be sent
2109 * for both 3D stereo and HDMI VIC modes.
2110 * For all other modes, there is no VSIF sent. */
2111
2112 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2113 return;
2114
2115 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2116 info_packet->sb[1] = 0x03;
2117 info_packet->sb[2] = 0x0C;
2118 info_packet->sb[3] = 0x00;
2119
2120 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2121 * The value for HDMI_Video_Format are:
2122 * 0x0 (0b000) - No additional HDMI video format is presented in this
2123 * packet
2124 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2125 * parameter follows
2126 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2127 * potentially 3D_Ext_Data follows
2128 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2129 if (format != TIMING_3D_FORMAT_NONE)
2130 info_packet->sb[4] = (2 << 5);
2131 else if (hdmi_vic_mode)
2132 info_packet->sb[4] = (1 << 5);
2133
2134 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2135 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2136 * The value for 3D_Structure are:
2137 * 0x0 - Frame Packing
2138 * 0x1 - Field Alternative
2139 * 0x2 - Line Alternative
2140 * 0x3 - Side-by-Side (full)
2141 * 0x4 - L + depth
2142 * 0x5 - L + depth + graphics + graphics-depth
2143 * 0x6 - Top-and-Bottom
2144 * 0x7 - Reserved for future use
2145 * 0x8 - Side-by-Side (Half)
2146 * 0x9..0xE - Reserved for future use
2147 * 0xF - Not used */
2148 switch (format) {
2149 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2150 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2151 info_packet->sb[5] = (0x0 << 4);
2152 break;
2153
2154 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2155 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2156 info_packet->sb[5] = (0x8 << 4);
2157 length = 6;
2158 break;
2159
2160 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2161 case TIMING_3D_FORMAT_TB_SW_PACKED:
2162 info_packet->sb[5] = (0x6 << 4);
2163 break;
2164
2165 default:
2166 break;
2167 }
2168
2169 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2170 * fill PB5 with the correct HDMI VIC code */
2171 if (hdmi_vic_mode)
4fa086b9 2172 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2173
2174 /* Header */
3e183c5f 2175 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2176 info_packet->hb1 = 0x01; /* Version */
2177
2178 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2179 info_packet->hb2 = (uint8_t) (length);
2180
2181 /* Calculate checksum */
2182 checksum = 0;
2183 checksum += info_packet->hb0;
2184 checksum += info_packet->hb1;
2185 checksum += info_packet->hb2;
2186
2187 for (i = 1; i <= length; i++)
2188 checksum += info_packet->sb[i];
2189
2190 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2191
2192 info_packet->valid = true;
2193}
2194
6e4d6bee 2195static void set_spd_info_packet(
e09b6473 2196 struct dc_info_packet *info_packet,
0971c40e 2197 struct dc_stream_state *stream)
4562236b
HW		 2198{
2199 /* SPD info packet for FreeSync */
2200
2201 unsigned char checksum = 0;
2202 unsigned int idx, payload_size = 0;
2203
2204 /* Check if Freesync is supported. Return if false. If true,
2205 * set the corresponding bit in the info packet
2206 */
4fa086b9 2207 if (stream->freesync_ctx.supported == false)
4562236b
HW		 2208 return;
2209
2210 if (dc_is_hdmi_signal(stream->signal)) {
2211
2212 /* HEADER */
2213
2214 /* HB0 = Packet Type = 0x83 (Source Product
2215 * Descriptor InfoFrame)
2216 */
3e183c5f 2217 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2218
2219 /* HB1 = Version = 0x01 */
2220 info_packet->hb1 = 0x01;
2221
2222 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2223 info_packet->hb2 = 0x08;
2224
2225 payload_size = 0x08;
2226
2227 } else if (dc_is_dp_signal(stream->signal)) {
2228
2229 /* HEADER */
2230
2231 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2232 * when used to associate audio related info packets
2233 */
2234 info_packet->hb0 = 0x00;
2235
2236 /* HB1 = Packet Type = 0x83 (Source Product
2237 * Descriptor InfoFrame)
2238 */
3e183c5f 2239 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2240
2241 /* HB2 = [Bits 7:0 = Least significant eight bits -
2242 * For INFOFRAME, the value must be 1Bh]
2243 */
2244 info_packet->hb2 = 0x1B;
2245
2246 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2247 * [Bits 1:0 = Most significant two bits = 0x00]
2248 */
2249 info_packet->hb3 = 0x04;
2250
2251 payload_size = 0x1B;
2252 }
2253
2254 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2255 info_packet->sb[1] = 0x1A;
2256
2257 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2258 info_packet->sb[2] = 0x00;
2259
2260 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2261 info_packet->sb[3] = 0x00;
2262
2263 /* PB4 = Reserved */
2264 info_packet->sb[4] = 0x00;
2265
2266 /* PB5 = Reserved */
2267 info_packet->sb[5] = 0x00;
2268
2269 /* PB6 = [Bits 7:3 = Reserved] */
2270 info_packet->sb[6] = 0x00;
2271
4fa086b9 2272 if (stream->freesync_ctx.supported == true)
4562236b
HW		 2273 /* PB6 = [Bit 0 = FreeSync Supported] */
2274 info_packet->sb[6] |= 0x01;
2275
4fa086b9 2276 if (stream->freesync_ctx.enabled == true)
4562236b
HW		 2277 /* PB6 = [Bit 1 = FreeSync Enabled] */
2278 info_packet->sb[6] |= 0x02;
2279
4fa086b9 2280 if (stream->freesync_ctx.active == true)
4562236b
HW		 2281 /* PB6 = [Bit 2 = FreeSync Active] */
2282 info_packet->sb[6] |= 0x04;
2283
2284 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2285 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2286 min_refresh_in_micro_hz / 1000000);
2287
2288 /* PB8 = FreeSync Maximum refresh rate (Hz)
2289 *
2290 * Note: We do not use the maximum capable refresh rate
2291 * of the panel, because we should never go above the field
2292 * rate of the mode timing set.
2293 */
4fa086b9 2294 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2295 nominal_refresh_in_micro_hz / 1000000);
2296
2297 /* PB9 - PB27 = Reserved */
2298 for (idx = 9; idx <= 27; idx++)
2299 info_packet->sb[idx] = 0x00;
2300
2301 /* Calculate checksum */
2302 checksum += info_packet->hb0;
2303 checksum += info_packet->hb1;
2304 checksum += info_packet->hb2;
2305 checksum += info_packet->hb3;
2306
2307 for (idx = 1; idx <= payload_size; idx++)
2308 checksum += info_packet->sb[idx];
2309
2310 /* PB0 = Checksum (one byte complement) */
2311 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2312
2313 info_packet->valid = true;
2314}
2315
1646a6fe 2316static void set_hdr_static_info_packet(
e09b6473 2317 struct dc_info_packet *info_packet,
0971c40e 2318 struct dc_stream_state *stream)
1646a6fe 2319{
0eeef690 2320 /* HDR Static Metadata info packet for HDR10 */
1646a6fe 2321
0eeef690 2322 if (!stream->hdr_static_metadata.valid)
10bff005
YS		 2323 return;
2324
0eeef690 2325 *info_packet = stream->hdr_static_metadata;
1646a6fe
AW		 2326}
2327
6e4d6bee 2328static void set_vsc_info_packet(
e09b6473 2329 struct dc_info_packet *info_packet,
0971c40e 2330 struct dc_stream_state *stream)
4562236b
HW		 2331{
2332 unsigned int vscPacketRevision = 0;
2333 unsigned int i;
2334
3b94a400 2335 /*VSC packet set to 2 when DP revision >= 1.2*/
85075fa0 2336 if (stream->psr_version != 0) {
4562236b
HW		 2337 vscPacketRevision = 2;
2338 }
2339
2340 /* VSC packet not needed based on the features
2341 * supported by this DP display
2342 */
2343 if (vscPacketRevision == 0)
2344 return;
2345
2346 if (vscPacketRevision == 0x2) {
2347 /* Secondary-data Packet ID = 0*/
2348 info_packet->hb0 = 0x00;
2349 /* 07h - Packet Type Value indicating Video
2350 * Stream Configuration packet
2351 */
2352 info_packet->hb1 = 0x07;
2353 /* 02h = VSC SDP supporting 3D stereo and PSR
2354 * (applies to eDP v1.3 or higher).
2355 */
2356 info_packet->hb2 = 0x02;
2357 /* 08h = VSC packet supporting 3D stereo + PSR
2358 * (HB2 = 02h).
2359 */
2360 info_packet->hb3 = 0x08;
2361
2362 for (i = 0; i < 28; i++)
2363 info_packet->sb[i] = 0;
2364
2365 info_packet->valid = true;
2366 }
2367
2368 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2369}
2370
f36cc577 2371void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2372{
2373 int i, j;
2374
ab2541b6 2375 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2376 for (j = 0; j < context->stream_status[i].plane_count; j++)
2377 dc_plane_state_release(
2378 context->stream_status[i].plane_states[j]);
4562236b 2379
3be5262e 2380 context->stream_status[i].plane_count = 0;
4fa086b9 2381 dc_stream_release(context->streams[i]);
ab2541b6 2382 context->streams[i] = NULL;
4562236b
HW		 2383 }
2384}
2385
2386/*
ab2541b6 2387 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2388 * by the src_ctx
2389 */
f36cc577 2390void dc_resource_state_copy_construct(
608ac7bb
JZ		 2391 const struct dc_state *src_ctx,
2392 struct dc_state *dst_ctx)
4562236b
HW		 2393{
2394 int i, j;
8ee5702a 2395 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2396
2397 *dst_ctx = *src_ctx;
2398
a2b8659d 2399 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2400 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2401
2402 if (cur_pipe->top_pipe)
2403 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2404
2405 if (cur_pipe->bottom_pipe)
2406 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2407
2408 }
2409
ab2541b6 2410 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2411 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2412 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2413 dc_plane_state_retain(
2414 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2415 }
9a3afbb3
AG		 2416
2417 /* context refcount should not be overridden */
8ee5702a 2418 dst_ctx->refcount = refcount;
9a3afbb3 2419
4562236b
HW		 2420}
2421
2422struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2423 struct resource_context *res_ctx,
2424 const struct resource_pool *pool)
4562236b
HW		 2425{
2426 int i;
2427
a2b8659d 2428 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2429 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2430 return pool->clock_sources[i];
4562236b
HW		 2431 }
2432
2433 return NULL;
2434}
2435
2436void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2437{
2438 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2439 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2440
2441 /* default all packets to invalid */
6e4d6bee
TC		 2442 info->avi.valid = false;
2443 info->gamut.valid = false;
2444 info->vendor.valid = false;
630e3573 2445 info->spd.valid = false;
6e4d6bee
TC		 2446 info->hdrsmd.valid = false;
2447 info->vsc.valid = false;
4562236b
HW		 2448
2449 signal = pipe_ctx->stream->signal;
2450
2451 /* HDMi and DP have different info packets*/
2452 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2453 set_avi_info_frame(&info->avi, pipe_ctx);
2454
2455 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2456
2457 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2458
56ef6ed9 2459 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
6e4d6bee 2460
a33fa99d 2461 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2462 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2463
2464 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2465
56ef6ed9 2466 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
a33fa99d 2467 }
4562236b 2468
6e4d6bee 2469 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2470}
2471
2472enum dc_status resource_map_clock_resources(
fb3466a4 2473 const struct dc *dc,
608ac7bb 2474 struct dc_state *context,
1dc90497 2475 struct dc_stream_state *stream)
4562236b 2476{
4562236b 2477 /* acquire new resources */
1dc90497
AG		 2478 const struct resource_pool *pool = dc->res_pool;
2479 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2480 &context->res_ctx, stream);
ab2541b6 2481
1dc90497
AG		 2482 if (!pipe_ctx)
2483 return DC_ERROR_UNEXPECTED;
4562236b 2484
1dc90497
AG		 2485 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2486 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2487 pipe_ctx->clock_source = pool->dp_clock_source;
2488 else {
2489 pipe_ctx->clock_source = NULL;
4562236b 2490
1dc90497 2491 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2492 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2493 &context->res_ctx,
2494 pipe_ctx);
4562236b 2495
1dc90497
AG		 2496 if (pipe_ctx->clock_source == NULL)
2497 pipe_ctx->clock_source =
2498 dc_resource_find_first_free_pll(
2499 &context->res_ctx,
2500 pool);
2501 }
4562236b 2502
1dc90497
AG		 2503 if (pipe_ctx->clock_source == NULL)
2504 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2505
1dc90497
AG		 2506 resource_reference_clock_source(
2507 &context->res_ctx, pool,
2508 pipe_ctx->clock_source);
4562236b
HW		 2509
2510 return DC_OK;
2511}
2512
2513/*
2514 * Note: We need to disable output if clock sources change,
2515 * since bios does optimization and doesn't apply if changing
2516 * PHY when not already disabled.
2517 */
2518bool pipe_need_reprogram(
2519 struct pipe_ctx *pipe_ctx_old,
2520 struct pipe_ctx *pipe_ctx)
2521{
cfe4645e
DL		 2522 if (!pipe_ctx_old->stream)
2523 return false;
2524
4562236b
HW		 2525 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2526 return true;
2527
2528 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2529 return true;
2530
afaacef4 2531 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2532 return true;
2533
2534 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2535 && pipe_ctx_old->stream != pipe_ctx->stream)
2536 return true;
2537
8e9c4c8c 2538 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2539 return true;
2540
2541 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2542 return true;
2543
2544
2545 return false;
2546}
529cad0f 2547
0971c40e 2548void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2549 struct bit_depth_reduction_params *fmt_bit_depth)
2550{
4fa086b9 2551 enum dc_dither_option option = stream->dither_option;
529cad0f 2552 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2553 stream->timing.pixel_encoding;
529cad0f
DW		 2554
2555 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2556
603767f9
TC		 2557 if (option == DITHER_OPTION_DEFAULT) {
2558 switch (stream->timing.display_color_depth) {
2559 case COLOR_DEPTH_666:
2560 option = DITHER_OPTION_SPATIAL6;
2561 break;
2562 case COLOR_DEPTH_888:
2563 option = DITHER_OPTION_SPATIAL8;
2564 break;
2565 case COLOR_DEPTH_101010:
2566 option = DITHER_OPTION_SPATIAL10;
2567 break;
2568 default:
2569 option = DITHER_OPTION_DISABLE;
2570 }
2571 }
2572
529cad0f
DW		 2573 if (option == DITHER_OPTION_DISABLE)
2574 return;
2575
2576 if (option == DITHER_OPTION_TRUN6) {
2577 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2578 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2579 } else if (option == DITHER_OPTION_TRUN8 ||
2580 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2581 option == DITHER_OPTION_TRUN8_FM6) {
2582 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2583 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2584 } else if (option == DITHER_OPTION_TRUN10 ||
2585 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2586 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2587 option == DITHER_OPTION_TRUN10_FM8 ||
2588 option == DITHER_OPTION_TRUN10_FM6 ||
2589 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2590 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2591 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2592 }
2593
2594 /* special case - Formatter can only reduce by 4 bits at most.
2595 * When reducing from 12 to 6 bits,
2596 * HW recommends we use trunc with round mode
2597 * (if we did nothing, trunc to 10 bits would be used)
2598 * note that any 12->10 bit reduction is ignored prior to DCE8,
2599 * as the input was 10 bits.
2600 */
2601 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2602 option == DITHER_OPTION_SPATIAL6 ||
2603 option == DITHER_OPTION_FM6) {
2604 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2605 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2606 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2607 }
2608
2609 /* spatial dither
2610 * note that spatial modes 1-3 are never used
2611 */
2612 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2613 option == DITHER_OPTION_SPATIAL6 ||
2614 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2615 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2616 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2617 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2618 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2619 fmt_bit_depth->flags.RGB_RANDOM =
2620 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2621 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2622 option == DITHER_OPTION_SPATIAL8 ||
2623 option == DITHER_OPTION_SPATIAL8_FM6 ||
2624 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2625 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2626 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2627 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2628 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2629 fmt_bit_depth->flags.RGB_RANDOM =
2630 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2631 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2632 option == DITHER_OPTION_SPATIAL10 ||
2633 option == DITHER_OPTION_SPATIAL10_FM8 ||
2634 option == DITHER_OPTION_SPATIAL10_FM6) {
2635 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2636 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2637 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2638 fmt_bit_depth->flags.RGB_RANDOM =
2639 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2640 }
2641
2642 if (option == DITHER_OPTION_SPATIAL6 ||
2643 option == DITHER_OPTION_SPATIAL8 ||
2644 option == DITHER_OPTION_SPATIAL10) {
2645 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2646 } else {
2647 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2648 }
2649
2650 //////////////////////
2651 //// temporal dither
2652 //////////////////////
2653 if (option == DITHER_OPTION_FM6 ||
2654 option == DITHER_OPTION_SPATIAL8_FM6 ||
2655 option == DITHER_OPTION_SPATIAL10_FM6 ||
2656 option == DITHER_OPTION_TRUN10_FM6 ||
2657 option == DITHER_OPTION_TRUN8_FM6 ||
2658 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2659 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2660 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2661 } else if (option == DITHER_OPTION_FM8 ||
2662 option == DITHER_OPTION_SPATIAL10_FM8 ||
2663 option == DITHER_OPTION_TRUN10_FM8) {
2664 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2665 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2666 } else if (option == DITHER_OPTION_FM10) {
2667 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2668 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2669 }
2670
2671 fmt_bit_depth->pixel_encoding = pixel_encoding;
2672}
9345d987 2673
62c933f9 2674enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2675{
fb3466a4 2676 struct dc *core_dc = dc;
4fa086b9 2677 struct dc_link *link = stream->sink->link;
9345d987
AG		 2678 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2679 enum dc_status res = DC_OK;
2680
4fa086b9 2681 calculate_phy_pix_clks(stream);
9345d987 2682
4fa086b9 2683 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2684 res = DC_FAIL_CONTROLLER_VALIDATE;
2685
2686 if (res == DC_OK)
2687 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2688 link->link_enc, stream))
9345d987
AG		 2689 res = DC_FAIL_ENC_VALIDATE;
2690
2691 /* TODO: validate audio ASIC caps, encoder */
2692
2693 if (res == DC_OK)
4fa086b9 2694 res = dc_link_validate_mode_timing(stream,
9345d987 2695 link,
4fa086b9 2696 &stream->timing);
9345d987 2697
62c933f9 2698 return res;
9345d987 2699}
792671d7 2700
62c933f9 2701enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2702{
62c933f9
YS		 2703 enum dc_status res = DC_OK;
2704
792671d7 2705 /* TODO For now validates pixel format only */
8e7095b9 2706 if (dc->res_pool->funcs->validate_plane)
62c933f9 2707 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2708
62c933f9 2709 return res;
792671d7 2710}
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