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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_resource.c
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4562236b 1/*
bf93b448 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4562236b
HW		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "resource.h"
28#include "include/irq_service_interface.h"
29#include "link_encoder.h"
30#include "stream_encoder.h"
31#include "opp.h"
32#include "timing_generator.h"
33#include "transform.h"
d94585a0 34#include "dpp.h"
5ac3d3c9 35#include "core_types.h"
4562236b 36#include "set_mode_types.h"
4562236b 37#include "virtual/virtual_stream_encoder.h"
9665eb15 38#include "dpcd_defs.h"
4562236b
HW		 39
40#include "dce80/dce80_resource.h"
41#include "dce100/dce100_resource.h"
42#include "dce110/dce110_resource.h"
43#include "dce112/dce112_resource.h"
ff5ef992
AD		 44#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
45#include "dcn10/dcn10_resource.h"
46#endif
2c8ad2d5 47#include "dce120/dce120_resource.h"
4562236b
HW		 48
49enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
50{
51 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
52 switch (asic_id.chip_family) {
53
54 case FAMILY_CI:
4562236b
HW		 55 dc_version = DCE_VERSION_8_0;
56 break;
ebfdf0d0
AD		 57 case FAMILY_KV:
58 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
59 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
60 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
61 dc_version = DCE_VERSION_8_3;
62 else
63 dc_version = DCE_VERSION_8_1;
64 break;
4562236b
HW		 65 case FAMILY_CZ:
66 dc_version = DCE_VERSION_11_0;
67 break;
68
69 case FAMILY_VI:
70 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
71 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
72 dc_version = DCE_VERSION_10_0;
73 break;
74 }
75 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
b264d345
JL		 76 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
77 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
4562236b
HW		 78 dc_version = DCE_VERSION_11_2;
79 }
80 break;
2c8ad2d5
AD		 81 case FAMILY_AI:
82 dc_version = DCE_VERSION_12_0;
83 break;
ff5ef992
AD		 84#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
85 case FAMILY_RV:
86 dc_version = DCN_VERSION_1_0;
87 break;
88#endif
4562236b
HW		 89 default:
90 dc_version = DCE_VERSION_UNKNOWN;
91 break;
92 }
93 return dc_version;
94}
95
96struct resource_pool *dc_create_resource_pool(
fb3466a4 97 struct dc *dc,
4562236b
HW		 98 int num_virtual_links,
99 enum dce_version dc_version,
100 struct hw_asic_id asic_id)
101{
5ac3d3c9 102 struct resource_pool *res_pool = NULL;
4562236b
HW		 103
104 switch (dc_version) {
105 case DCE_VERSION_8_0:
7992a629
AD		 106 res_pool = dce80_create_resource_pool(
107 num_virtual_links, dc);
108 break;
ebfdf0d0 109 case DCE_VERSION_8_1:
7992a629
AD		 110 res_pool = dce81_create_resource_pool(
111 num_virtual_links, dc);
112 break;
ebfdf0d0 113 case DCE_VERSION_8_3:
7992a629 114 res_pool = dce83_create_resource_pool(
4562236b 115 num_virtual_links, dc);
5ac3d3c9 116 break;
4562236b 117 case DCE_VERSION_10_0:
5ac3d3c9 118 res_pool = dce100_create_resource_pool(
4562236b 119 num_virtual_links, dc);
5ac3d3c9 120 break;
4562236b 121 case DCE_VERSION_11_0:
5ac3d3c9 122 res_pool = dce110_create_resource_pool(
4562236b 123 num_virtual_links, dc, asic_id);
5ac3d3c9 124 break;
4562236b 125 case DCE_VERSION_11_2:
5ac3d3c9 126 res_pool = dce112_create_resource_pool(
4562236b 127 num_virtual_links, dc);
5ac3d3c9 128 break;
2c8ad2d5
AD		 129 case DCE_VERSION_12_0:
130 res_pool = dce120_create_resource_pool(
131 num_virtual_links, dc);
132 break;
ff5ef992
AD		 133
134#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
135 case DCN_VERSION_1_0:
136 res_pool = dcn10_create_resource_pool(
503a7c6f 137 num_virtual_links, dc);
ff5ef992
AD		 138 break;
139#endif
3639fa68
ZF		 140
141
4562236b
HW		 142 default:
143 break;
144 }
5ac3d3c9 145 if (res_pool != NULL) {
1515a47b 146 struct dc_firmware_info fw_info = { { 0 } };
5ac3d3c9
CL		 147
148 if (dc->ctx->dc_bios->funcs->get_firmware_info(
149 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
150 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
151 } else
152 ASSERT_CRITICAL(false);
153 }
4562236b 154
5ac3d3c9 155 return res_pool;
4562236b
HW		 156}
157
fb3466a4 158void dc_destroy_resource_pool(struct dc *dc)
4562236b
HW		 159{
160 if (dc) {
161 if (dc->res_pool)
162 dc->res_pool->funcs->destroy(&dc->res_pool);
163
d029810c 164 kfree(dc->hwseq);
4562236b
HW		 165 }
166}
167
168static void update_num_audio(
169 const struct resource_straps *straps,
170 unsigned int *num_audio,
171 struct audio_support *aud_support)
172{
b8e9eb72
CL		 173 aud_support->dp_audio = true;
174 aud_support->hdmi_audio_native = false;
175 aud_support->hdmi_audio_on_dongle = false;
176
4562236b 177 if (straps->hdmi_disable == 0) {
4562236b
HW		 178 if (straps->dc_pinstraps_audio & 0x2) {
179 aud_support->hdmi_audio_on_dongle = true;
b8e9eb72 180 aud_support->hdmi_audio_native = true;
4562236b
HW		 181 }
182 }
183
184 switch (straps->audio_stream_number) {
185 case 0: /* multi streams supported */
186 break;
187 case 1: /* multi streams not supported */
188 *num_audio = 1;
189 break;
190 default:
191 DC_ERR("DC: unexpected audio fuse!\n");
17a96033 192 }
4562236b
HW		 193}
194
195bool resource_construct(
196 unsigned int num_virtual_links,
fb3466a4 197 struct dc *dc,
4562236b
HW		 198 struct resource_pool *pool,
199 const struct resource_create_funcs *create_funcs)
200{
201 struct dc_context *ctx = dc->ctx;
202 const struct resource_caps *caps = pool->res_cap;
203 int i;
204 unsigned int num_audio = caps->num_audio;
205 struct resource_straps straps = {0};
206
207 if (create_funcs->read_dce_straps)
208 create_funcs->read_dce_straps(dc->ctx, &straps);
209
210 pool->audio_count = 0;
211 if (create_funcs->create_audio) {
212 /* find the total number of streams available via the
213 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
214 * registers (one for each pin) starting from pin 1
215 * up to the max number of audio pins.
216 * We stop on the first pin where
217 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
218 */
219 update_num_audio(&straps, &num_audio, &pool->audio_support);
f9aa3db5 220 for (i = 0; i < caps->num_audio; i++) {
4562236b
HW		 221 struct audio *aud = create_funcs->create_audio(ctx, i);
222
223 if (aud == NULL) {
224 DC_ERR("DC: failed to create audio!\n");
225 return false;
226 }
227
228 if (!aud->funcs->endpoint_valid(aud)) {
229 aud->funcs->destroy(&aud);
230 break;
231 }
232
233 pool->audios[i] = aud;
234 pool->audio_count++;
235 }
236 }
237
238 pool->stream_enc_count = 0;
239 if (create_funcs->create_stream_encoder) {
240 for (i = 0; i < caps->num_stream_encoder; i++) {
241 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
242 if (pool->stream_enc[i] == NULL)
243 DC_ERR("DC: failed to create stream_encoder!\n");
244 pool->stream_enc_count++;
245 }
246 }
4176664b
CL		 247 dc->caps.dynamic_audio = false;
248 if (pool->audio_count < pool->stream_enc_count) {
249 dc->caps.dynamic_audio = true;
250 }
4562236b
HW		 251 for (i = 0; i < num_virtual_links; i++) {
252 pool->stream_enc[pool->stream_enc_count] =
253 virtual_stream_encoder_create(
254 ctx, ctx->dc_bios);
255 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
256 DC_ERR("DC: failed to create stream_encoder!\n");
257 return false;
258 }
259 pool->stream_enc_count++;
260 }
261
262 dc->hwseq = create_funcs->create_hwseq(ctx);
263
264 return true;
265}
36b337e0
ML		 266static int find_matching_clock_source(
267 const struct resource_pool *pool,
268 struct clock_source *clock_source)
269{
4562236b 270
36b337e0
ML		 271 int i;
272
273 for (i = 0; i < pool->clk_src_count; i++) {
274 if (pool->clock_sources[i] == clock_source)
275 return i;
276 }
277 return -1;
278}
4562236b 279
21e67d4d 280void resource_unreference_clock_source(
4562236b 281 struct resource_context *res_ctx,
a2b8659d 282 const struct resource_pool *pool,
4a629536 283 struct clock_source *clock_source)
4562236b 284{
36b337e0 285 int i = find_matching_clock_source(pool, clock_source);
4562236b 286
36b337e0 287 if (i > -1)
4562236b
HW		 288 res_ctx->clock_source_ref_count[i]--;
289
21e67d4d 290 if (pool->dp_clock_source == clock_source)
4562236b 291 res_ctx->dp_clock_source_ref_count--;
4562236b
HW		 292}
293
294void resource_reference_clock_source(
295 struct resource_context *res_ctx,
a2b8659d 296 const struct resource_pool *pool,
4562236b
HW		 297 struct clock_source *clock_source)
298{
36b337e0 299 int i = find_matching_clock_source(pool, clock_source);
4562236b 300
36b337e0 301 if (i > -1)
4562236b 302 res_ctx->clock_source_ref_count[i]++;
4562236b 303
a2b8659d 304 if (pool->dp_clock_source == clock_source)
4562236b
HW		 305 res_ctx->dp_clock_source_ref_count++;
306}
307
36b337e0
ML		 308int resource_get_clock_source_reference(
309 struct resource_context *res_ctx,
310 const struct resource_pool *pool,
311 struct clock_source *clock_source)
312{
313 int i = find_matching_clock_source(pool, clock_source);
314
315 if (i > -1)
316 return res_ctx->clock_source_ref_count[i];
317
318 if (pool->dp_clock_source == clock_source)
319 return res_ctx->dp_clock_source_ref_count;
320
321 return -1;
322}
323
4562236b 324bool resource_are_streams_timing_synchronizable(
0971c40e
HW		 325 struct dc_stream_state *stream1,
326 struct dc_stream_state *stream2)
4562236b 327{
4fa086b9 328 if (stream1->timing.h_total != stream2->timing.h_total)
4562236b
HW		 329 return false;
330
4fa086b9 331 if (stream1->timing.v_total != stream2->timing.v_total)
4562236b
HW		 332 return false;
333
4fa086b9
LSL		 334 if (stream1->timing.h_addressable
335 != stream2->timing.h_addressable)
4562236b
HW		 336 return false;
337
4fa086b9
LSL		 338 if (stream1->timing.v_addressable
339 != stream2->timing.v_addressable)
4562236b
HW		 340 return false;
341
4fa086b9
LSL		 342 if (stream1->timing.pix_clk_khz
343 != stream2->timing.pix_clk_khz)
4562236b
HW		 344 return false;
345
b56b768c
ML		 346 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
347 return false;
348
4562236b 349 if (stream1->phy_pix_clk != stream2->phy_pix_clk
7e2fe319
CL		 350 && (!dc_is_dp_signal(stream1->signal)
351 || !dc_is_dp_signal(stream2->signal)))
4562236b
HW		 352 return false;
353
354 return true;
355}
b56b768c
ML		 356static bool is_dp_and_hdmi_sharable(
357 struct dc_stream_state *stream1,
358 struct dc_stream_state *stream2)
359{
360 if (stream1->ctx->dc->caps.disable_dp_clk_share)
361 return false;
362
363 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
364 stream2->clamping.c_depth != COLOR_DEPTH_888)
365 return false;
366
367 return true;
368
369}
4562236b
HW		 370
371static bool is_sharable_clk_src(
372 const struct pipe_ctx *pipe_with_clk_src,
373 const struct pipe_ctx *pipe)
374{
375 if (pipe_with_clk_src->clock_source == NULL)
376 return false;
377
378 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
379 return false;
380
b56b768c
ML		 381 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
382 (dc_is_dp_signal(pipe->stream->signal) &&
383 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
384 pipe->stream)))
4562236b
HW		 385 return false;
386
387 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
388 && dc_is_dvi_signal(pipe->stream->signal))
389 return false;
390
391 if (dc_is_hdmi_signal(pipe->stream->signal)
392 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
393 return false;
394
395 if (!resource_are_streams_timing_synchronizable(
396 pipe_with_clk_src->stream, pipe->stream))
397 return false;
398
399 return true;
400}
401
402struct clock_source *resource_find_used_clk_src_for_sharing(
403 struct resource_context *res_ctx,
404 struct pipe_ctx *pipe_ctx)
405{
406 int i;
407
408 for (i = 0; i < MAX_PIPES; i++) {
409 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
410 return res_ctx->pipe_ctx[i].clock_source;
411 }
412
413 return NULL;
414}
415
416static enum pixel_format convert_pixel_format_to_dalsurface(
417 enum surface_pixel_format surface_pixel_format)
418{
419 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
420
421 switch (surface_pixel_format) {
422 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
423 dal_pixel_format = PIXEL_FORMAT_INDEX8;
424 break;
425 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
426 dal_pixel_format = PIXEL_FORMAT_RGB565;
427 break;
428 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
429 dal_pixel_format = PIXEL_FORMAT_RGB565;
430 break;
431 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
432 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
433 break;
8693049a 434 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 435 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
436 break;
437 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
438 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
439 break;
440 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
441 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
442 break;
443 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
444 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
445 break;
446 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
447 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
448 dal_pixel_format = PIXEL_FORMAT_FP16;
449 break;
450 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4562236b 451 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
87449a90 452 dal_pixel_format = PIXEL_FORMAT_420BPP8;
4562236b 453 break;
ffbcd19a
VP		 454 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
455 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
87449a90 456 dal_pixel_format = PIXEL_FORMAT_420BPP10;
ffbcd19a 457 break;
4562236b
HW		 458 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
459 default:
460 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
461 break;
462 }
463 return dal_pixel_format;
464}
465
466static void rect_swap_helper(struct rect *rect)
467{
468 uint32_t temp = 0;
469
470 temp = rect->height;
471 rect->height = rect->width;
472 rect->width = temp;
473
474 temp = rect->x;
475 rect->x = rect->y;
476 rect->y = temp;
477}
478
b2d0a103 479static void calculate_viewport(struct pipe_ctx *pipe_ctx)
4562236b 480{
3be5262e 481 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 482 const struct dc_stream_state *stream = pipe_ctx->stream;
6702a9ac 483 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 484 struct rect surf_src = plane_state->src_rect;
1fbd2cfc 485 struct rect clip = { 0 };
87449a90
AK		 486 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
487 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1fbd2cfc 488 bool pri_split = pipe_ctx->bottom_pipe &&
3be5262e 489 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1fbd2cfc 490 bool sec_split = pipe_ctx->top_pipe &&
3be5262e 491 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
4562236b 492
7f5c22d1
VP		 493 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
494 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
7b779c99
VP		 495 pri_split = false;
496 sec_split = false;
497 }
86006a7f 498
3be5262e
HW		 499 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
500 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 501 rect_swap_helper(&surf_src);
502
4562236b
HW		 503 /* The actual clip is an intersection between stream
504 * source and surface clip
505 */
3be5262e
HW		 506 clip.x = stream->src.x > plane_state->clip_rect.x ?
507 stream->src.x : plane_state->clip_rect.x;
4562236b 508
1fbd2cfc 509 clip.width = stream->src.x + stream->src.width <
3be5262e 510 plane_state->clip_rect.x + plane_state->clip_rect.width ?
1fbd2cfc 511 stream->src.x + stream->src.width - clip.x :
3be5262e 512 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
4562236b 513
3be5262e
HW		 514 clip.y = stream->src.y > plane_state->clip_rect.y ?
515 stream->src.y : plane_state->clip_rect.y;
4562236b 516
1fbd2cfc 517 clip.height = stream->src.y + stream->src.height <
3be5262e 518 plane_state->clip_rect.y + plane_state->clip_rect.height ?
1fbd2cfc 519 stream->src.y + stream->src.height - clip.y :
3be5262e 520 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
4562236b 521
86006a7f 522 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
4562236b
HW		 523 * num_pixels = clip.num_pix * scl_ratio
524 */
3be5262e
HW		 525 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
526 surf_src.width / plane_state->dst_rect.width;
b2d0a103 527 data->viewport.width = clip.width *
3be5262e 528 surf_src.width / plane_state->dst_rect.width;
4562236b 529
3be5262e
HW		 530 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
531 surf_src.height / plane_state->dst_rect.height;
b2d0a103 532 data->viewport.height = clip.height *
3be5262e 533 surf_src.height / plane_state->dst_rect.height;
4562236b 534
b2d0a103
DL		 535 /* Round down, compensate in init */
536 data->viewport_c.x = data->viewport.x / vpc_div;
537 data->viewport_c.y = data->viewport.y / vpc_div;
538 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
539 dal_fixed31_32_half : dal_fixed31_32_zero;
540 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
541 dal_fixed31_32_half : dal_fixed31_32_zero;
542 /* Round up, assume original video size always even dimensions */
543 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
544 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
545
546 /* Handle hsplit */
1fbd2cfc
DL		 547 if (pri_split || sec_split) {
548 /* HMirror XOR Secondary_pipe XOR Rotation_180 */
3be5262e
HW		 549 bool right_view = (sec_split != plane_state->horizontal_mirror) !=
550 (plane_state->rotation == ROTATION_ANGLE_180);
1fbd2cfc 551
3be5262e
HW		 552 if (plane_state->rotation == ROTATION_ANGLE_90
553 || plane_state->rotation == ROTATION_ANGLE_270)
1fbd2cfc 554 /* Secondary_pipe XOR Rotation_270 */
3be5262e 555 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
9e6c74ce
DL		 556
557 if (right_view) {
16fb754a
DL		 558 data->viewport.x += data->viewport.width / 2;
559 data->viewport_c.x += data->viewport_c.width / 2;
9e6c74ce 560 /* Ceil offset pipe */
16fb754a
DL		 561 data->viewport.width = (data->viewport.width + 1) / 2;
562 data->viewport_c.width = (data->viewport_c.width + 1) / 2;
9e6c74ce
DL		 563 } else {
564 data->viewport.width /= 2;
565 data->viewport_c.width /= 2;
566 }
b2d0a103 567 }
1fbd2cfc 568
3be5262e
HW		 569 if (plane_state->rotation == ROTATION_ANGLE_90 ||
570 plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 571 rect_swap_helper(&data->viewport_c);
572 rect_swap_helper(&data->viewport);
573 }
4562236b
HW		 574}
575
b2d0a103 576static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
4562236b 577{
3be5262e 578 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 579 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e
HW		 580 struct rect surf_src = plane_state->src_rect;
581 struct rect surf_clip = plane_state->clip_rect;
c802570e 582 int recout_full_x, recout_full_y;
4562236b 583
3be5262e
HW		 584 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
585 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 586 rect_swap_helper(&surf_src);
587
6702a9ac 588 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
4fa086b9 589 if (stream->src.x < surf_clip.x)
6702a9ac 590 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
4fa086b9
LSL		 591 - stream->src.x) * stream->dst.width
592 / stream->src.width;
4562236b 593
6702a9ac 594 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
4fa086b9 595 stream->dst.width / stream->src.width;
6702a9ac 596 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
4fa086b9 597 stream->dst.x + stream->dst.width)
6702a9ac 598 pipe_ctx->plane_res.scl_data.recout.width =
4fa086b9 599 stream->dst.x + stream->dst.width
6702a9ac 600 - pipe_ctx->plane_res.scl_data.recout.x;
4562236b 601
6702a9ac 602 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
4fa086b9 603 if (stream->src.y < surf_clip.y)
6702a9ac 604 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
4fa086b9
LSL		 605 - stream->src.y) * stream->dst.height
606 / stream->src.height;
4562236b 607
6702a9ac 608 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
4fa086b9 609 stream->dst.height / stream->src.height;
6702a9ac 610 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
4fa086b9 611 stream->dst.y + stream->dst.height)
6702a9ac 612 pipe_ctx->plane_res.scl_data.recout.height =
4fa086b9 613 stream->dst.y + stream->dst.height
6702a9ac 614 - pipe_ctx->plane_res.scl_data.recout.y;
b2d0a103 615
7b779c99 616 /* Handle h & vsplit */
3be5262e
HW		 617 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
618 pipe_ctx->plane_state) {
4fa086b9 619 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
116b2632 620 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2;
7b779c99 621 /* Floor primary pipe, ceil 2ndary pipe */
4ddd76d1 622 pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
7b779c99 623 } else {
116b2632 624 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2;
4ddd76d1 625 pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
7b779c99
VP		 626 }
627 } else if (pipe_ctx->bottom_pipe &&
3be5262e 628 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
4fa086b9 629 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 630 pipe_ctx->plane_res.scl_data.recout.height /= 2;
7b779c99 631 else
6702a9ac 632 pipe_ctx->plane_res.scl_data.recout.width /= 2;
b2d0a103
DL		 633 }
634
86006a7f
DL		 635 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
636 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
c802570e
DL		 637 * ratio)
638 */
3be5262e 639 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
4fa086b9 640 * stream->dst.width / stream->src.width -
3be5262e 641 surf_src.x * plane_state->dst_rect.width / surf_src.width
4fa086b9 642 * stream->dst.width / stream->src.width;
3be5262e 643 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
4fa086b9 644 * stream->dst.height / stream->src.height -
3be5262e 645 surf_src.y * plane_state->dst_rect.height / surf_src.height
4fa086b9 646 * stream->dst.height / stream->src.height;
c802570e 647
6702a9ac
HW		 648 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
649 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
4562236b
HW		 650}
651
b2d0a103 652static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
4562236b 653{
3be5262e 654 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
0971c40e 655 const struct dc_stream_state *stream = pipe_ctx->stream;
3be5262e 656 struct rect surf_src = plane_state->src_rect;
4fa086b9
LSL		 657 const int in_w = stream->src.width;
658 const int in_h = stream->src.height;
659 const int out_w = stream->dst.width;
660 const int out_h = stream->dst.height;
4562236b 661
3be5262e
HW		 662 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
663 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
86006a7f
DL		 664 rect_swap_helper(&surf_src);
665
6702a9ac 666 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
86006a7f 667 surf_src.width,
3be5262e 668 plane_state->dst_rect.width);
6702a9ac 669 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
86006a7f 670 surf_src.height,
3be5262e 671 plane_state->dst_rect.height);
4562236b 672
4fa086b9 673 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
6702a9ac 674 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
4fa086b9 675 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
6702a9ac 676 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
4562236b 677
6702a9ac
HW		 678 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
679 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
680 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
681 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
4562236b 682
6702a9ac
HW		 683 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
684 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
4562236b 685
6702a9ac
HW		 686 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
687 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
688 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
689 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
4562236b
HW		 690 }
691}
692
b2d0a103
DL		 693static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
694{
6702a9ac 695 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
3be5262e 696 struct rect src = pipe_ctx->plane_state->src_rect;
87449a90
AK		 697 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
698 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
b2d0a103 699
86006a7f 700
3be5262e
HW		 701 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
702 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
86006a7f 703 rect_swap_helper(&src);
1fbd2cfc
DL		 704 rect_swap_helper(&data->viewport_c);
705 rect_swap_helper(&data->viewport);
706 }
707
b2d0a103
DL		 708 /*
709 * Init calculated according to formula:
710 * init = (scaling_ratio + number_of_taps + 1) / 2
711 * init_bot = init + scaling_ratio
712 * init_c = init + truncated_vp_c_offset(from calculate viewport)
713 */
714 data->inits.h = dal_fixed31_32_div_int(
715 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
716
717 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
718 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
719
720 data->inits.v = dal_fixed31_32_div_int(
721 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
722
723 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
724 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
725
726
727 /* Adjust for viewport end clip-off */
728 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
729 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
1fbd2cfc
DL		 730 int int_part = dal_fixed31_32_floor(
731 dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
b2d0a103 732
1fbd2cfc 733 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 734 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
735 }
736 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
737 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
1fbd2cfc
DL		 738 int int_part = dal_fixed31_32_floor(
739 dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
b2d0a103 740
1fbd2cfc 741 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 742 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
743 }
744 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
745 int vp_clip = (src.x + src.width) / vpc_div -
746 data->viewport_c.width - data->viewport_c.x;
1fbd2cfc
DL		 747 int int_part = dal_fixed31_32_floor(
748 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
b2d0a103 749
1fbd2cfc 750 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 751 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
752 }
753 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
754 int vp_clip = (src.y + src.height) / vpc_div -
755 data->viewport_c.height - data->viewport_c.y;
1fbd2cfc
DL		 756 int int_part = dal_fixed31_32_floor(
757 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
b2d0a103 758
1fbd2cfc 759 int_part = int_part > 0 ? int_part : 0;
b2d0a103
DL		 760 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
761 }
762
763 /* Adjust for non-0 viewport offset */
764 if (data->viewport.x) {
765 int int_part;
766
767 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
768 data->ratios.horz, recout_skip->width));
769 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
770 if (int_part < data->taps.h_taps) {
771 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
772 (data->taps.h_taps - int_part) : data->viewport.x;
773 data->viewport.x -= int_adj;
774 data->viewport.width += int_adj;
775 int_part += int_adj;
776 } else if (int_part > data->taps.h_taps) {
777 data->viewport.x += int_part - data->taps.h_taps;
778 data->viewport.width -= int_part - data->taps.h_taps;
779 int_part = data->taps.h_taps;
780 }
781 data->inits.h.value &= 0xffffffff;
782 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
783 }
784
785 if (data->viewport_c.x) {
786 int int_part;
787
788 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
789 data->ratios.horz_c, recout_skip->width));
790 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
791 if (int_part < data->taps.h_taps_c) {
792 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
793 (data->taps.h_taps_c - int_part) : data->viewport_c.x;
794 data->viewport_c.x -= int_adj;
795 data->viewport_c.width += int_adj;
796 int_part += int_adj;
797 } else if (int_part > data->taps.h_taps_c) {
798 data->viewport_c.x += int_part - data->taps.h_taps_c;
799 data->viewport_c.width -= int_part - data->taps.h_taps_c;
800 int_part = data->taps.h_taps_c;
801 }
802 data->inits.h_c.value &= 0xffffffff;
803 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
804 }
805
806 if (data->viewport.y) {
807 int int_part;
808
809 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
810 data->ratios.vert, recout_skip->height));
811 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
812 if (int_part < data->taps.v_taps) {
813 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
814 (data->taps.v_taps - int_part) : data->viewport.y;
815 data->viewport.y -= int_adj;
816 data->viewport.height += int_adj;
817 int_part += int_adj;
818 } else if (int_part > data->taps.v_taps) {
819 data->viewport.y += int_part - data->taps.v_taps;
820 data->viewport.height -= int_part - data->taps.v_taps;
821 int_part = data->taps.v_taps;
822 }
823 data->inits.v.value &= 0xffffffff;
824 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
825 }
826
827 if (data->viewport_c.y) {
828 int int_part;
829
830 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
831 data->ratios.vert_c, recout_skip->height));
832 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
833 if (int_part < data->taps.v_taps_c) {
834 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
835 (data->taps.v_taps_c - int_part) : data->viewport_c.y;
836 data->viewport_c.y -= int_adj;
837 data->viewport_c.height += int_adj;
838 int_part += int_adj;
839 } else if (int_part > data->taps.v_taps_c) {
840 data->viewport_c.y += int_part - data->taps.v_taps_c;
841 data->viewport_c.height -= int_part - data->taps.v_taps_c;
842 int_part = data->taps.v_taps_c;
843 }
844 data->inits.v_c.value &= 0xffffffff;
845 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
846 }
847
848 /* Interlaced inits based on final vert inits */
849 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
850 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
1fbd2cfc 851
3be5262e
HW		 852 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
853 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
1fbd2cfc
DL		 854 rect_swap_helper(&data->viewport_c);
855 rect_swap_helper(&data->viewport);
856 }
b2d0a103
DL		 857}
858
859bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
4562236b 860{
3be5262e 861 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
4fa086b9 862 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
b2d0a103
DL		 863 struct view recout_skip = { 0 };
864 bool res = false;
865
4562236b
HW		 866 /* Important: scaling ratio calculation requires pixel format,
867 * lb depth calculation requires recout and taps require scaling ratios.
b2d0a103 868 * Inits require viewport, taps, ratios and recout of split pipe
4562236b 869 */
6702a9ac 870 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
3be5262e 871 pipe_ctx->plane_state->format);
b2d0a103
DL		 872
873 calculate_scaling_ratios(pipe_ctx);
4562236b 874
b2d0a103 875 calculate_viewport(pipe_ctx);
4562236b 876
6702a9ac 877 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
4562236b
HW		 878 return false;
879
b2d0a103 880 calculate_recout(pipe_ctx, &recout_skip);
4562236b
HW		 881
882 /**
883 * Setting line buffer pixel depth to 24bpp yields banding
884 * on certain displays, such as the Sharp 4k
885 */
6702a9ac 886 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
4562236b 887
199e458a 888 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
58bb0e63 889 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
199e458a 890
58bb0e63
AJ		 891 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
892 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
4562236b 893
1b6c8067 894
4562236b 895 /* Taps calculations */
d94585a0
YHL		 896 if (pipe_ctx->plane_res.xfm != NULL)
897 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
898 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
899
900 if (pipe_ctx->plane_res.dpp != NULL)
901 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
902 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
4562236b
HW		 903 if (!res) {
904 /* Try 24 bpp linebuffer */
6702a9ac 905 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
4562236b 906
1b6c8067
BL		 907 if (pipe_ctx->plane_res.xfm != NULL)
908 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
909 pipe_ctx->plane_res.xfm,
910 &pipe_ctx->plane_res.scl_data,
911 &plane_state->scaling_quality);
912
913 if (pipe_ctx->plane_res.dpp != NULL)
914 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
915 pipe_ctx->plane_res.dpp,
916 &pipe_ctx->plane_res.scl_data,
917 &plane_state->scaling_quality);
4562236b
HW		 918 }
919
b2d0a103 920 if (res)
1fbd2cfc 921 /* May need to re-check lb size after this in some obscure scenario */
b2d0a103
DL		 922 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
923
4562236b
HW		 924 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
925 "%s: Viewport:\nheight:%d width:%d x:%d "
926 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
927 "y:%d\n",
928 __func__,
6702a9ac
HW		 929 pipe_ctx->plane_res.scl_data.viewport.height,
930 pipe_ctx->plane_res.scl_data.viewport.width,
931 pipe_ctx->plane_res.scl_data.viewport.x,
932 pipe_ctx->plane_res.scl_data.viewport.y,
3be5262e
HW		 933 plane_state->dst_rect.height,
934 plane_state->dst_rect.width,
935 plane_state->dst_rect.x,
936 plane_state->dst_rect.y);
4562236b
HW		 937
938 return res;
939}
940
941
942enum dc_status resource_build_scaling_params_for_context(
fb3466a4 943 const struct dc *dc,
608ac7bb 944 struct dc_state *context)
4562236b
HW		 945{
946 int i;
947
948 for (i = 0; i < MAX_PIPES; i++) {
3be5262e 949 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
4562236b 950 context->res_ctx.pipe_ctx[i].stream != NULL)
b2d0a103 951 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
f84a8161 952 return DC_FAIL_SCALING;
4562236b
HW		 953 }
954
955 return DC_OK;
956}
957
a2b8659d
TC		 958struct pipe_ctx *find_idle_secondary_pipe(
959 struct resource_context *res_ctx,
960 const struct resource_pool *pool)
4562236b
HW		 961{
962 int i;
963 struct pipe_ctx *secondary_pipe = NULL;
964
965 /*
966 * search backwards for the second pipe to keep pipe
967 * assignment more consistent
968 */
969
a2b8659d 970 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b
HW		 971 if (res_ctx->pipe_ctx[i].stream == NULL) {
972 secondary_pipe = &res_ctx->pipe_ctx[i];
973 secondary_pipe->pipe_idx = i;
974 break;
975 }
976 }
977
978
979 return secondary_pipe;
980}
981
982struct pipe_ctx *resource_get_head_pipe_for_stream(
983 struct resource_context *res_ctx,
0971c40e 984 struct dc_stream_state *stream)
4562236b
HW		 985{
986 int i;
a2b8659d 987 for (i = 0; i < MAX_PIPES; i++) {
4562236b 988 if (res_ctx->pipe_ctx[i].stream == stream &&
1dc90497 989 !res_ctx->pipe_ctx[i].top_pipe) {
4562236b
HW		 990 return &res_ctx->pipe_ctx[i];
991 break;
992 }
993 }
994 return NULL;
995}
996
19f89e23
AG		 997static struct pipe_ctx *resource_get_tail_pipe_for_stream(
998 struct resource_context *res_ctx,
999 struct dc_stream_state *stream)
1000{
1001 struct pipe_ctx *head_pipe, *tail_pipe;
1002 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1003
1004 if (!head_pipe)
1005 return NULL;
1006
1007 tail_pipe = head_pipe->bottom_pipe;
1008
1009 while (tail_pipe) {
1010 head_pipe = tail_pipe;
1011 tail_pipe = tail_pipe->bottom_pipe;
1012 }
1013
1014 return head_pipe;
1015}
1016
4562236b 1017/*
ab2541b6
AC		 1018 * A free_pipe for a stream is defined here as a pipe
1019 * that has no surface attached yet
4562236b 1020 */
ab2541b6 1021static struct pipe_ctx *acquire_free_pipe_for_stream(
608ac7bb 1022 struct dc_state *context,
a2b8659d 1023 const struct resource_pool *pool,
0971c40e 1024 struct dc_stream_state *stream)
4562236b
HW		 1025{
1026 int i;
745cc746 1027 struct resource_context *res_ctx = &context->res_ctx;
4562236b
HW		 1028
1029 struct pipe_ctx *head_pipe = NULL;
1030
1031 /* Find head pipe, which has the back end set up*/
1032
1033 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1034
e41ab030 1035 if (!head_pipe) {
4562236b 1036 ASSERT(0);
e41ab030
HW		 1037 return NULL;
1038 }
4562236b 1039
3be5262e 1040 if (!head_pipe->plane_state)
4562236b
HW		 1041 return head_pipe;
1042
1043 /* Re-use pipe already acquired for this stream if available*/
a2b8659d 1044 for (i = pool->pipe_count - 1; i >= 0; i--) {
4562236b 1045 if (res_ctx->pipe_ctx[i].stream == stream &&
3be5262e 1046 !res_ctx->pipe_ctx[i].plane_state) {
4562236b
HW		 1047 return &res_ctx->pipe_ctx[i];
1048 }
1049 }
1050
1051 /*
1052 * At this point we have no re-useable pipe for this stream and we need
1053 * to acquire an idle one to satisfy the request
1054 */
1055
a2b8659d 1056 if (!pool->funcs->acquire_idle_pipe_for_layer)
4562236b
HW		 1057 return NULL;
1058
a2b8659d 1059 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
4562236b
HW		 1060
1061}
1062
0f9a536f
DL		 1063#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1064static int acquire_first_split_pipe(
1065 struct resource_context *res_ctx,
1066 const struct resource_pool *pool,
0971c40e 1067 struct dc_stream_state *stream)
0f9a536f
DL		 1068{
1069 int i;
1070
1071 for (i = 0; i < pool->pipe_count; i++) {
1072 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1073
1074 if (pipe_ctx->top_pipe &&
3be5262e 1075 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
0f9a536f
DL		 1076 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1077 if (pipe_ctx->bottom_pipe)
1078 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1079
1080 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
6b670fa9 1081 pipe_ctx->stream_res.tg = pool->timing_generators[i];
8feabd03 1082 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e 1083 pipe_ctx->plane_res.ipp = pool->ipps[i];
d94585a0 1084 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1085 pipe_ctx->stream_res.opp = pool->opps[i];
0f9a536f 1086 pipe_ctx->pipe_idx = i;
0f9a536f
DL		 1087
1088 pipe_ctx->stream = stream;
1089 return i;
1090 }
1091 }
1092 return -1;
1093}
1094#endif
1095
19f89e23
AG		 1096bool dc_add_plane_to_context(
1097 const struct dc *dc,
0971c40e 1098 struct dc_stream_state *stream,
19f89e23 1099 struct dc_plane_state *plane_state,
608ac7bb 1100 struct dc_state *context)
4562236b
HW		 1101{
1102 int i;
19f89e23
AG		 1103 struct resource_pool *pool = dc->res_pool;
1104 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
ab2541b6 1105 struct dc_stream_status *stream_status = NULL;
4562236b 1106
19f89e23
AG		 1107 for (i = 0; i < context->stream_count; i++)
1108 if (context->streams[i] == stream) {
1109 stream_status = &context->stream_status[i];
1110 break;
1111 }
1112 if (stream_status == NULL) {
1113 dm_error("Existing stream not found; failed to attach surface!\n");
1114 return false;
1115 }
1116
4562236b 1117
19f89e23
AG		 1118 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1119 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1120 plane_state, MAX_SURFACE_NUM);
4562236b
HW		 1121 return false;
1122 }
1123
19f89e23
AG		 1124 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1125
1126 if (!head_pipe) {
1127 dm_error("Head pipe not found for stream_state %p !\n", stream);
1128 return false;
1129 }
1130
19f89e23
AG		 1131 free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
1132
1133#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1134 if (!free_pipe) {
1135 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1136 if (pipe_idx >= 0)
1137 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1138 }
1139#endif
abb4986e 1140 if (!free_pipe)
19f89e23 1141 return false;
19f89e23 1142
abb4986e
AJ		 1143 /* retain new surfaces */
1144 dc_plane_state_retain(plane_state);
19f89e23
AG		 1145 free_pipe->plane_state = plane_state;
1146
1147 if (head_pipe != free_pipe) {
1148
1149 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
1150 ASSERT(tail_pipe);
1151
1152 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1153 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1154 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1155 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1156 free_pipe->clock_source = tail_pipe->clock_source;
1157 free_pipe->top_pipe = tail_pipe;
1158 tail_pipe->bottom_pipe = free_pipe;
1159 }
1160
1161 /* assign new surfaces*/
1162 stream_status->plane_states[stream_status->plane_count] = plane_state;
1163
1164 stream_status->plane_count++;
1165
1166 return true;
1167}
1168
1169bool dc_remove_plane_from_context(
1170 const struct dc *dc,
1171 struct dc_stream_state *stream,
1172 struct dc_plane_state *plane_state,
608ac7bb 1173 struct dc_state *context)
19f89e23
AG		 1174{
1175 int i;
1176 struct dc_stream_status *stream_status = NULL;
1177 struct resource_pool *pool = dc->res_pool;
1178
ab2541b6 1179 for (i = 0; i < context->stream_count; i++)
4fa086b9 1180 if (context->streams[i] == stream) {
ab2541b6 1181 stream_status = &context->stream_status[i];
4562236b
HW		 1182 break;
1183 }
19f89e23 1184
ab2541b6 1185 if (stream_status == NULL) {
19f89e23 1186 dm_error("Existing stream not found; failed to remove plane.\n");
4562236b
HW		 1187 return false;
1188 }
1189
19f89e23
AG		 1190 /* release pipe for plane*/
1191 for (i = pool->pipe_count - 1; i >= 0; i--) {
1192 struct pipe_ctx *pipe_ctx;
4562236b 1193
19f89e23
AG		 1194 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
1195 pipe_ctx = &context->res_ctx.pipe_ctx[i];
4562236b 1196
19f89e23
AG		 1197 if (pipe_ctx->top_pipe)
1198 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
4562236b 1199
19f89e23
AG		 1200 /* Second condition is to avoid setting NULL to top pipe
1201 * of tail pipe making it look like head pipe in subsequent
1202 * deletes
1203 */
1204 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1205 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
4562236b 1206
19f89e23
AG		 1207 /*
1208 * For head pipe detach surfaces from pipe for tail
1209 * pipe just zero it out
1210 */
354787ec 1211 if (!pipe_ctx->top_pipe || (!pipe_ctx->top_pipe->top_pipe &&
66960b6d 1212 pipe_ctx->top_pipe->stream_res.opp != pipe_ctx->stream_res.opp)) {
354787ec 1213 pipe_ctx->top_pipe = NULL;
19f89e23
AG		 1214 pipe_ctx->plane_state = NULL;
1215 pipe_ctx->bottom_pipe = NULL;
66960b6d 1216 } else {
19f89e23
AG		 1217 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1218 }
4562236b 1219 }
19f89e23 1220 }
4562236b 1221
4562236b 1222
19f89e23
AG		 1223 for (i = 0; i < stream_status->plane_count; i++) {
1224 if (stream_status->plane_states[i] == plane_state) {
1225
1226 dc_plane_state_release(stream_status->plane_states[i]);
1227 break;
4562236b 1228 }
19f89e23 1229 }
4562236b 1230
19f89e23
AG		 1231 if (i == stream_status->plane_count) {
1232 dm_error("Existing plane_state not found; failed to detach it!\n");
1233 return false;
4562236b
HW		 1234 }
1235
19f89e23 1236 stream_status->plane_count--;
4562236b 1237
abb4986e
AJ		 1238 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1239 for (; i < stream_status->plane_count; i++)
19f89e23
AG		 1240 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1241
1242 stream_status->plane_states[stream_status->plane_count] = NULL;
1243
1244 return true;
1245}
1246
1247bool dc_rem_all_planes_for_stream(
1248 const struct dc *dc,
1249 struct dc_stream_state *stream,
608ac7bb 1250 struct dc_state *context)
19f89e23
AG		 1251{
1252 int i, old_plane_count;
1253 struct dc_stream_status *stream_status = NULL;
1254 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1255
1256 for (i = 0; i < context->stream_count; i++)
1257 if (context->streams[i] == stream) {
1258 stream_status = &context->stream_status[i];
1259 break;
1260 }
1261
1262 if (stream_status == NULL) {
1263 dm_error("Existing stream %p not found!\n", stream);
1264 return false;
1265 }
1266
1267 old_plane_count = stream_status->plane_count;
1268
1269 for (i = 0; i < old_plane_count; i++)
1270 del_planes[i] = stream_status->plane_states[i];
1271
1272 for (i = 0; i < old_plane_count; i++)
1273 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1274 return false;
1275
1276 return true;
1277}
1278
1279static bool add_all_planes_for_stream(
1280 const struct dc *dc,
1281 struct dc_stream_state *stream,
1282 const struct dc_validation_set set[],
1283 int set_count,
608ac7bb 1284 struct dc_state *context)
19f89e23
AG		 1285{
1286 int i, j;
1287
1288 for (i = 0; i < set_count; i++)
1289 if (set[i].stream == stream)
1290 break;
1291
1292 if (i == set_count) {
1293 dm_error("Stream %p not found in set!\n", stream);
1294 return false;
1295 }
4562236b 1296
19f89e23
AG		 1297 for (j = 0; j < set[i].plane_count; j++)
1298 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1299 return false;
4562236b
HW		 1300
1301 return true;
1302}
1303
19f89e23
AG		 1304bool dc_add_all_planes_for_stream(
1305 const struct dc *dc,
1306 struct dc_stream_state *stream,
1307 struct dc_plane_state * const *plane_states,
1308 int plane_count,
608ac7bb 1309 struct dc_state *context)
19f89e23
AG		 1310{
1311 struct dc_validation_set set;
1312 int i;
1313
1314 set.stream = stream;
1315 set.plane_count = plane_count;
1316
1317 for (i = 0; i < plane_count; i++)
1318 set.plane_states[i] = plane_states[i];
1319
1320 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1321}
1322
1323
4562236b 1324
0971c40e
HW		 1325static bool is_timing_changed(struct dc_stream_state *cur_stream,
1326 struct dc_stream_state *new_stream)
4562236b
HW		 1327{
1328 if (cur_stream == NULL)
1329 return true;
1330
1331 /* If sink pointer changed, it means this is a hotplug, we should do
1332 * full hw setting.
1333 */
1334 if (cur_stream->sink != new_stream->sink)
1335 return true;
1336
1337 /* If output color space is changed, need to reprogram info frames */
4fa086b9 1338 if (cur_stream->output_color_space != new_stream->output_color_space)
4562236b
HW		 1339 return true;
1340
1341 return memcmp(
4fa086b9
LSL		 1342 &cur_stream->timing,
1343 &new_stream->timing,
4562236b
HW		 1344 sizeof(struct dc_crtc_timing)) != 0;
1345}
1346
1347static bool are_stream_backends_same(
0971c40e 1348 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
4562236b
HW		 1349{
1350 if (stream_a == stream_b)
1351 return true;
1352
1353 if (stream_a == NULL || stream_b == NULL)
1354 return false;
1355
1356 if (is_timing_changed(stream_a, stream_b))
1357 return false;
1358
1359 return true;
1360}
1361
d54d29db 1362bool dc_is_stream_unchanged(
0971c40e 1363 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
4562236b 1364{
4562236b 1365
ab2541b6
AC		 1366 if (!are_stream_backends_same(old_stream, stream))
1367 return false;
4562236b
HW		 1368
1369 return true;
1370}
1371
9a5d9c48
LSL		 1372bool dc_is_stream_scaling_unchanged(
1373 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1374{
1375 if (old_stream == stream)
1376 return true;
1377
1378 if (old_stream == NULL || stream == NULL)
1379 return false;
1380
1381 if (memcmp(&old_stream->src,
1382 &stream->src,
1383 sizeof(struct rect)) != 0)
1384 return false;
1385
1386 if (memcmp(&old_stream->dst,
1387 &stream->dst,
1388 sizeof(struct rect)) != 0)
1389 return false;
1390
1391 return true;
1392}
1393
4562236b
HW		 1394/* Maximum TMDS single link pixel clock 165MHz */
1395#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1396
1dc90497 1397static void update_stream_engine_usage(
4562236b 1398 struct resource_context *res_ctx,
a2b8659d 1399 const struct resource_pool *pool,
1dc90497
AG		 1400 struct stream_encoder *stream_enc,
1401 bool acquired)
4562236b
HW		 1402{
1403 int i;
1404
a2b8659d
TC		 1405 for (i = 0; i < pool->stream_enc_count; i++) {
1406 if (pool->stream_enc[i] == stream_enc)
1dc90497 1407 res_ctx->is_stream_enc_acquired[i] = acquired;
4562236b
HW		 1408 }
1409}
1410
1411/* TODO: release audio object */
4176664b 1412void update_audio_usage(
4562236b 1413 struct resource_context *res_ctx,
a2b8659d 1414 const struct resource_pool *pool,
1dc90497
AG		 1415 struct audio *audio,
1416 bool acquired)
4562236b
HW		 1417{
1418 int i;
a2b8659d
TC		 1419 for (i = 0; i < pool->audio_count; i++) {
1420 if (pool->audios[i] == audio)
1dc90497 1421 res_ctx->is_audio_acquired[i] = acquired;
4562236b
HW		 1422 }
1423}
1424
1425static int acquire_first_free_pipe(
1426 struct resource_context *res_ctx,
a2b8659d 1427 const struct resource_pool *pool,
0971c40e 1428 struct dc_stream_state *stream)
4562236b
HW		 1429{
1430 int i;
1431
a2b8659d 1432 for (i = 0; i < pool->pipe_count; i++) {
4562236b
HW		 1433 if (!res_ctx->pipe_ctx[i].stream) {
1434 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1435
6b670fa9 1436 pipe_ctx->stream_res.tg = pool->timing_generators[i];
86a66c4e 1437 pipe_ctx->plane_res.mi = pool->mis[i];
8feabd03 1438 pipe_ctx->plane_res.hubp = pool->hubps[i];
86a66c4e
HW		 1439 pipe_ctx->plane_res.ipp = pool->ipps[i];
1440 pipe_ctx->plane_res.xfm = pool->transforms[i];
d94585a0 1441 pipe_ctx->plane_res.dpp = pool->dpps[i];
a6a6cb34 1442 pipe_ctx->stream_res.opp = pool->opps[i];
4562236b
HW		 1443 pipe_ctx->pipe_idx = i;
1444
ff5ef992 1445
4562236b
HW		 1446 pipe_ctx->stream = stream;
1447 return i;
1448 }
1449 }
1450 return -1;
1451}
1452
1453static struct stream_encoder *find_first_free_match_stream_enc_for_link(
1454 struct resource_context *res_ctx,
a2b8659d 1455 const struct resource_pool *pool,
0971c40e 1456 struct dc_stream_state *stream)
4562236b
HW		 1457{
1458 int i;
1459 int j = -1;
d0778ebf 1460 struct dc_link *link = stream->sink->link;
4562236b 1461
a2b8659d 1462 for (i = 0; i < pool->stream_enc_count; i++) {
4562236b 1463 if (!res_ctx->is_stream_enc_acquired[i] &&
a2b8659d 1464 pool->stream_enc[i]) {
4562236b
HW		 1465 /* Store first available for MST second display
1466 * in daisy chain use case */
1467 j = i;
a2b8659d 1468 if (pool->stream_enc[i]->id ==
4562236b 1469 link->link_enc->preferred_engine)
a2b8659d 1470 return pool->stream_enc[i];
4562236b
HW		 1471 }
1472 }
1473
1474 /*
1475 * below can happen in cases when stream encoder is acquired:
1476 * 1) for second MST display in chain, so preferred engine already
1477 * acquired;
1478 * 2) for another link, which preferred engine already acquired by any
1479 * MST configuration.
1480 *
1481 * If signal is of DP type and preferred engine not found, return last available
1482 *
1483 * TODO - This is just a patch up and a generic solution is
1484 * required for non DP connectors.
1485 */
1486
1487 if (j >= 0 && dc_is_dp_signal(stream->signal))
a2b8659d 1488 return pool->stream_enc[j];
4562236b
HW		 1489
1490 return NULL;
1491}
1492
a2b8659d
TC		 1493static struct audio *find_first_free_audio(
1494 struct resource_context *res_ctx,
cfb071f7
CL		 1495 const struct resource_pool *pool,
1496 enum engine_id id)
4562236b
HW		 1497{
1498 int i;
66bfd4fd
CL		 1499 for (i = 0; i < pool->audio_count; i++) {
1500 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
cfb071f7
CL		 1501 /*we have enough audio endpoint, find the matching inst*/
1502 if (id != i)
1503 continue;
1504
66bfd4fd 1505 return pool->audios[i];
4562236b 1506 }
66bfd4fd 1507 }
f9aa3db5
TM		 1508
1509 /* use engine id to find free audio */
1510 if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1511 return pool->audios[id];
1512 }
1513
66bfd4fd
CL		 1514 /*not found the matching one, first come first serve*/
1515 for (i = 0; i < pool->audio_count; i++) {
1516 if (res_ctx->is_audio_acquired[i] == false) {
1517 return pool->audios[i];
4176664b
CL		 1518 }
1519 }
4562236b
HW		 1520 return 0;
1521}
1522
4562236b 1523bool resource_is_stream_unchanged(
608ac7bb 1524 struct dc_state *old_context, struct dc_stream_state *stream)
4562236b 1525{
ab2541b6 1526 int i;
4562236b 1527
ab2541b6 1528 for (i = 0; i < old_context->stream_count; i++) {
0971c40e 1529 struct dc_stream_state *old_stream = old_context->streams[i];
4562236b 1530
ab2541b6 1531 if (are_stream_backends_same(old_stream, stream))
4562236b 1532 return true;
4562236b
HW		 1533 }
1534
1535 return false;
1536}
1537
13ab1b44 1538enum dc_status dc_add_stream_to_ctx(
1dc90497 1539 struct dc *dc,
608ac7bb 1540 struct dc_state *new_ctx,
1dc90497
AG		 1541 struct dc_stream_state *stream)
1542{
1543 struct dc_context *dc_ctx = dc->ctx;
1544 enum dc_status res;
1545
1546 if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
1547 DC_ERROR("Max streams reached, can add stream %p !\n", stream);
1548 return DC_ERROR_UNEXPECTED;
1549 }
1550
1551 new_ctx->streams[new_ctx->stream_count] = stream;
1552 dc_stream_retain(stream);
1553 new_ctx->stream_count++;
1554
1555 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1556 if (res != DC_OK)
1557 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
1558
13ab1b44 1559 return res;
1dc90497
AG		 1560}
1561
62c933f9 1562enum dc_status dc_remove_stream_from_ctx(
1dc90497 1563 struct dc *dc,
608ac7bb 1564 struct dc_state *new_ctx,
1dc90497
AG		 1565 struct dc_stream_state *stream)
1566{
19f89e23 1567 int i;
1dc90497
AG		 1568 struct dc_context *dc_ctx = dc->ctx;
1569 struct pipe_ctx *del_pipe = NULL;
1570
19f89e23 1571 /* Release primary pipe */
1dc90497 1572 for (i = 0; i < MAX_PIPES; i++) {
19f89e23
AG		 1573 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
1574 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1dc90497
AG		 1575 del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1576
19f89e23
AG		 1577 ASSERT(del_pipe->stream_res.stream_enc);
1578 update_stream_engine_usage(
1579 &new_ctx->res_ctx,
1dc90497 1580 dc->res_pool,
19f89e23
AG		 1581 del_pipe->stream_res.stream_enc,
1582 false);
1dc90497
AG		 1583
1584 if (del_pipe->stream_res.audio)
1585 update_audio_usage(
1586 &new_ctx->res_ctx,
1587 dc->res_pool,
1588 del_pipe->stream_res.audio,
1589 false);
1590
9d0dcecd
HW		 1591 resource_unreference_clock_source(&new_ctx->res_ctx,
1592 dc->res_pool,
1593 del_pipe->clock_source);
1594
1dc90497
AG		 1595 memset(del_pipe, 0, sizeof(*del_pipe));
1596 }
1597 }
1598
1599 if (!del_pipe) {
1600 DC_ERROR("Pipe not found for stream %p !\n", stream);
1601 return DC_ERROR_UNEXPECTED;
1602 }
1603
1604 for (i = 0; i < new_ctx->stream_count; i++)
1605 if (new_ctx->streams[i] == stream)
1606 break;
1607
1608 if (new_ctx->streams[i] != stream) {
1609 DC_ERROR("Context doesn't have stream %p !\n", stream);
1610 return DC_ERROR_UNEXPECTED;
1611 }
1612
1613 dc_stream_release(new_ctx->streams[i]);
1614 new_ctx->stream_count--;
1615
1dc90497
AG		 1616 /* Trim back arrays */
1617 for (; i < new_ctx->stream_count; i++) {
1618 new_ctx->streams[i] = new_ctx->streams[i + 1];
1619 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1620 }
1621
1622 new_ctx->streams[new_ctx->stream_count] = NULL;
1623 memset(
1624 &new_ctx->stream_status[new_ctx->stream_count],
1625 0,
1626 sizeof(new_ctx->stream_status[0]));
1627
1628 return DC_OK;
1629}
1630
4562236b
HW		 1631static void copy_pipe_ctx(
1632 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
1633{
3be5262e 1634 struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
0971c40e 1635 struct dc_stream_state *stream = to_pipe_ctx->stream;
4562236b
HW		 1636
1637 *to_pipe_ctx = *from_pipe_ctx;
1638 to_pipe_ctx->stream = stream;
3be5262e
HW		 1639 if (plane_state != NULL)
1640 to_pipe_ctx->plane_state = plane_state;
4562236b
HW		 1641}
1642
0971c40e
HW		 1643static struct dc_stream_state *find_pll_sharable_stream(
1644 struct dc_stream_state *stream_needs_pll,
608ac7bb 1645 struct dc_state *context)
4562236b 1646{
ab2541b6 1647 int i;
4562236b 1648
ab2541b6 1649 for (i = 0; i < context->stream_count; i++) {
0971c40e 1650 struct dc_stream_state *stream_has_pll = context->streams[i];
4562236b 1651
ab2541b6
AC		 1652 /* We are looking for non dp, non virtual stream */
1653 if (resource_are_streams_timing_synchronizable(
1654 stream_needs_pll, stream_has_pll)
1655 && !dc_is_dp_signal(stream_has_pll->signal)
d0778ebf 1656 && stream_has_pll->sink->link->connector_signal
ab2541b6
AC		 1657 != SIGNAL_TYPE_VIRTUAL)
1658 return stream_has_pll;
4562236b 1659
4562236b
HW		 1660 }
1661
1662 return NULL;
1663}
1664
1665static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1666{
1667 uint32_t pix_clk = timing->pix_clk_khz;
1668 uint32_t normalized_pix_clk = pix_clk;
1669
1670 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1671 pix_clk /= 2;
cc4d99b8
CL		 1672 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1673 switch (timing->display_color_depth) {
453048c7 1674 case COLOR_DEPTH_666:
cc4d99b8
CL		 1675 case COLOR_DEPTH_888:
1676 normalized_pix_clk = pix_clk;
1677 break;
1678 case COLOR_DEPTH_101010:
1679 normalized_pix_clk = (pix_clk * 30) / 24;
1680 break;
1681 case COLOR_DEPTH_121212:
1682 normalized_pix_clk = (pix_clk * 36) / 24;
4562236b 1683 break;
cc4d99b8
CL		 1684 case COLOR_DEPTH_161616:
1685 normalized_pix_clk = (pix_clk * 48) / 24;
4562236b 1686 break;
cc4d99b8
CL		 1687 default:
1688 ASSERT(0);
4562236b 1689 break;
cc4d99b8 1690 }
4562236b 1691 }
4562236b
HW		 1692 return normalized_pix_clk;
1693}
1694
0971c40e 1695static void calculate_phy_pix_clks(struct dc_stream_state *stream)
4562236b 1696{
9345d987
AG		 1697 /* update actual pixel clock on all streams */
1698 if (dc_is_hdmi_signal(stream->signal))
1699 stream->phy_pix_clk = get_norm_pix_clk(
4fa086b9 1700 &stream->timing);
9345d987
AG		 1701 else
1702 stream->phy_pix_clk =
4fa086b9 1703 stream->timing.pix_clk_khz;
4562236b
HW		 1704}
1705
1706enum dc_status resource_map_pool_resources(
fb3466a4 1707 const struct dc *dc,
608ac7bb 1708 struct dc_state *context,
1dc90497 1709 struct dc_stream_state *stream)
4562236b 1710{
a2b8659d 1711 const struct resource_pool *pool = dc->res_pool;
1dc90497
AG		 1712 int i;
1713 struct dc_context *dc_ctx = dc->ctx;
1714 struct pipe_ctx *pipe_ctx = NULL;
1715 int pipe_idx = -1;
4562236b 1716
1dc90497
AG		 1717 /* TODO Check if this is needed */
1718 /*if (!resource_is_stream_unchanged(old_context, stream)) {
430ef426 1719 if (stream != NULL && old_context->streams[i] != NULL) {
4b679bc3 1720 stream->bit_depth_params =
430ef426
DL		 1721 old_context->streams[i]->bit_depth_params;
1722 stream->clamping = old_context->streams[i]->clamping;
a2b8659d
TC		 1723 continue;
1724 }
4b679bc3 1725 }
1dc90497 1726 */
7e2fe319 1727
4c787df9
YMM		 1728 calculate_phy_pix_clks(stream);
1729
1dc90497
AG		 1730 /* acquire new resources */
1731 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
8c737fcc 1732
94c6d735 1733#ifdef CONFIG_DRM_AMD_DC_DCN1_0
1dc90497 1734 if (pipe_idx < 0)
13ab1b44 1735 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
94c6d735 1736#endif
13ab1b44 1737
1dc90497
AG		 1738 if (pipe_idx < 0)
1739 return DC_NO_CONTROLLER_RESOURCE;
1740
1741 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1742
1743 pipe_ctx->stream_res.stream_enc =
1744 find_first_free_match_stream_enc_for_link(
1745 &context->res_ctx, pool, stream);
1746
1747 if (!pipe_ctx->stream_res.stream_enc)
1748 return DC_NO_STREAM_ENG_RESOURCE;
1749
1750 update_stream_engine_usage(
1751 &context->res_ctx, pool,
1752 pipe_ctx->stream_res.stream_enc,
1753 true);
1754
1755 /* TODO: Add check if ASIC support and EDID audio */
1756 if (!stream->sink->converter_disable_audio &&
1757 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
6ef353dd 1758 stream->audio_info.mode_count && stream->audio_info.flags.all) {
1dc90497 1759 pipe_ctx->stream_res.audio = find_first_free_audio(
cfb071f7 1760 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1dc90497
AG		 1761
1762 /*
1763 * Audio assigned in order first come first get.
1764 * There are asics which has number of audio
1765 * resources less then number of pipes
1766 */
1767 if (pipe_ctx->stream_res.audio)
1768 update_audio_usage(&context->res_ctx, pool,
1769 pipe_ctx->stream_res.audio, true);
1770 }
268cadbd 1771
1dc90497
AG		 1772 for (i = 0; i < context->stream_count; i++)
1773 if (context->streams[i] == stream) {
1774 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
0f0bdca5 1775 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1dc90497
AG		 1776 return DC_OK;
1777 }
4562236b 1778
1dc90497
AG		 1779 DC_ERROR("Stream %p not found in new ctx!\n", stream);
1780 return DC_ERROR_UNEXPECTED;
1781}
4562236b 1782
1dc90497
AG		 1783/* first stream in the context is used to populate the rest */
1784void validate_guaranteed_copy_streams(
608ac7bb 1785 struct dc_state *context,
1dc90497
AG		 1786 int max_streams)
1787{
1788 int i;
ab2541b6 1789
1dc90497
AG		 1790 for (i = 1; i < max_streams; i++) {
1791 context->streams[i] = context->streams[0];
ab2541b6 1792
1dc90497
AG		 1793 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1794 &context->res_ctx.pipe_ctx[i]);
1795 context->res_ctx.pipe_ctx[i].stream =
1796 context->res_ctx.pipe_ctx[0].stream;
ab2541b6 1797
1dc90497
AG		 1798 dc_stream_retain(context->streams[i]);
1799 context->stream_count++;
4562236b 1800 }
1dc90497 1801}
4562236b 1802
f36cc577 1803void dc_resource_state_copy_construct_current(
1dc90497 1804 const struct dc *dc,
608ac7bb 1805 struct dc_state *dst_ctx)
1dc90497 1806{
f36cc577 1807 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
1dc90497
AG		 1808}
1809
ab8db3e1
AG		 1810
1811void dc_resource_state_construct(
1812 const struct dc *dc,
1813 struct dc_state *dst_ctx)
1814{
1815 dst_ctx->dis_clk = dc->res_pool->display_clock;
1816}
1817
e750d56d 1818enum dc_status dc_validate_global_state(
1dc90497 1819 struct dc *dc,
608ac7bb 1820 struct dc_state *new_ctx)
4562236b 1821{
1dc90497 1822 enum dc_status result = DC_ERROR_UNEXPECTED;
1dc90497 1823 int i, j;
4562236b 1824
e41ab030
HW		 1825 if (!new_ctx)
1826 return DC_ERROR_UNEXPECTED;
1827
d596e5d0
YS		 1828 if (dc->res_pool->funcs->validate_global) {
1829 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1830 if (result != DC_OK)
1831 return result;
1832 }
4562236b 1833
e41ab030 1834 for (i = 0; i < new_ctx->stream_count; i++) {
1dc90497
AG		 1835 struct dc_stream_state *stream = new_ctx->streams[i];
1836
1837 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1838 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
1839
1840 if (pipe_ctx->stream != stream)
1841 continue;
1842
1843 /* Switch to dp clock source only if there is
1844 * no non dp stream that shares the same timing
1845 * with the dp stream.
1846 */
1847 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1848 !find_pll_sharable_stream(stream, new_ctx)) {
1849
9d0dcecd 1850 resource_unreference_clock_source(
1dc90497
AG		 1851 &new_ctx->res_ctx,
1852 dc->res_pool,
9d0dcecd 1853 pipe_ctx->clock_source);
4a629536 1854
1dc90497
AG		 1855 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
1856 resource_reference_clock_source(
1857 &new_ctx->res_ctx,
1858 dc->res_pool,
1859 pipe_ctx->clock_source);
1860 }
1861 }
1862 }
1863
1dc90497
AG		 1864 result = resource_build_scaling_params_for_context(dc, new_ctx);
1865
1866 if (result == DC_OK)
1867 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
1868 result = DC_FAIL_BANDWIDTH_VALIDATE;
1869
1870 return result;
4562236b
HW		 1871}
1872
6e4d6bee
TC		 1873static void patch_gamut_packet_checksum(
1874 struct encoder_info_packet *gamut_packet)
4562236b 1875{
4562236b 1876 /* For gamut we recalc checksum */
6e4d6bee 1877 if (gamut_packet->valid) {
4562236b
HW		 1878 uint8_t chk_sum = 0;
1879 uint8_t *ptr;
1880 uint8_t i;
1881
4562236b 1882 /*start of the Gamut data. */
6e4d6bee 1883 ptr = &gamut_packet->sb[3];
4562236b 1884
6e4d6bee 1885 for (i = 0; i <= gamut_packet->sb[1]; i++)
4562236b
HW		 1886 chk_sum += ptr[i];
1887
6e4d6bee 1888 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
1646a6fe 1889 }
4562236b
HW		 1890}
1891
1892static void set_avi_info_frame(
6e4d6bee 1893 struct encoder_info_packet *info_packet,
4562236b
HW		 1894 struct pipe_ctx *pipe_ctx)
1895{
0971c40e 1896 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b
HW		 1897 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1898 struct info_frame info_frame = { {0} };
1899 uint32_t pixel_encoding = 0;
1900 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1901 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
1902 bool itc = false;
50e27654 1903 uint8_t itc_value = 0;
4562236b 1904 uint8_t cn0_cn1 = 0;
50e27654 1905 unsigned int cn0_cn1_value = 0;
4562236b
HW		 1906 uint8_t *check_sum = NULL;
1907 uint8_t byte_index = 0;
e8d726b7 1908 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
50e27654 1909 union display_content_support support = {0};
4fa086b9 1910 unsigned int vic = pipe_ctx->stream->timing.vic;
15e17335 1911 enum dc_timing_3d_format format;
4562236b 1912
4fa086b9 1913 color_space = pipe_ctx->stream->output_color_space;
e5f2038e 1914 if (color_space == COLOR_SPACE_UNKNOWN)
4fa086b9 1915 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
e5f2038e 1916 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4562236b
HW		 1917
1918 /* Initialize header */
e8d726b7 1919 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4562236b
HW		 1920 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1921 * not be used in HDMI 2.0 (Section 10.1) */
e8d726b7
RA		 1922 hdmi_info->bits.header.version = 2;
1923 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4562236b
HW		 1924
1925 /*
1926 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
1927 * according to HDMI 2.0 spec (Section 10.1)
1928 */
1929
4fa086b9 1930 switch (stream->timing.pixel_encoding) {
4562236b
HW		 1931 case PIXEL_ENCODING_YCBCR422:
1932 pixel_encoding = 1;
1933 break;
1934
1935 case PIXEL_ENCODING_YCBCR444:
1936 pixel_encoding = 2;
1937 break;
1938 case PIXEL_ENCODING_YCBCR420:
1939 pixel_encoding = 3;
1940 break;
1941
1942 case PIXEL_ENCODING_RGB:
1943 default:
1944 pixel_encoding = 0;
1945 }
1946
1947 /* Y0_Y1_Y2 : The pixel encoding */
1948 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
e8d726b7 1949 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
4562236b
HW		 1950
1951 /* A0 = 1 Active Format Information valid */
e8d726b7 1952 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
4562236b
HW		 1953
1954 /* B0, B1 = 3; Bar info data is valid */
e8d726b7 1955 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
4562236b 1956
e8d726b7 1957 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4562236b
HW		 1958
1959 /* S0, S1 : Underscan / Overscan */
1960 /* TODO: un-hardcode scan type */
1961 scan_type = SCANNING_TYPE_UNDERSCAN;
e8d726b7 1962 hdmi_info->bits.S0_S1 = scan_type;
4562236b
HW		 1963
1964 /* C0, C1 : Colorimetry */
8fde5884 1965 if (color_space == COLOR_SPACE_YCBCR709 ||
15e17335 1966 color_space == COLOR_SPACE_YCBCR709_LIMITED)
e8d726b7 1967 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
8fde5884
CL		 1968 else if (color_space == COLOR_SPACE_YCBCR601 ||
1969 color_space == COLOR_SPACE_YCBCR601_LIMITED)
e8d726b7 1970 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
8fde5884 1971 else {
e8d726b7 1972 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
8fde5884 1973 }
534db198 1974 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
8fde5884
CL		 1975 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
1976 color_space == COLOR_SPACE_2020_YCBCR) {
e8d726b7
RA		 1977 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1978 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198 1979 } else if (color_space == COLOR_SPACE_ADOBERGB) {
e8d726b7
RA		 1980 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1981 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
534db198
AZ		 1982 }
1983
4562236b 1984 /* TODO: un-hardcode aspect ratio */
4fa086b9 1985 aspect = stream->timing.aspect_ratio;
4562236b
HW		 1986
1987 switch (aspect) {
1988 case ASPECT_RATIO_4_3:
1989 case ASPECT_RATIO_16_9:
e8d726b7 1990 hdmi_info->bits.M0_M1 = aspect;
4562236b
HW		 1991 break;
1992
1993 case ASPECT_RATIO_NO_DATA:
1994 case ASPECT_RATIO_64_27:
1995 case ASPECT_RATIO_256_135:
1996 default:
e8d726b7 1997 hdmi_info->bits.M0_M1 = 0;
4562236b
HW		 1998 }
1999
2000 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
e8d726b7 2001 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4562236b
HW		 2002
2003 /* TODO: un-hardcode cn0_cn1 and itc */
50e27654 2004
4562236b 2005 cn0_cn1 = 0;
50e27654
ZF		 2006 cn0_cn1_value = 0;
2007
2008 itc = true;
2009 itc_value = 1;
2010
4fa086b9 2011 support = stream->sink->edid_caps.content_support;
4562236b
HW		 2012
2013 if (itc) {
50e27654
ZF		 2014 if (!support.bits.valid_content_type) {
2015 cn0_cn1_value = 0;
2016 } else {
2017 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2018 if (support.bits.graphics_content == 1) {
2019 cn0_cn1_value = 0;
2020 }
2021 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2022 if (support.bits.photo_content == 1) {
2023 cn0_cn1_value = 1;
2024 } else {
2025 cn0_cn1_value = 0;
2026 itc_value = 0;
2027 }
2028 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2029 if (support.bits.cinema_content == 1) {
2030 cn0_cn1_value = 2;
2031 } else {
2032 cn0_cn1_value = 0;
2033 itc_value = 0;
2034 }
2035 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2036 if (support.bits.game_content == 1) {
2037 cn0_cn1_value = 3;
2038 } else {
2039 cn0_cn1_value = 0;
2040 itc_value = 0;
2041 }
2042 }
2043 }
2044 hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
2045 hdmi_info->bits.ITC = itc_value;
4562236b
HW		 2046 }
2047
2048 /* TODO : We should handle YCC quantization */
2049 /* but we do not have matrix calculation */
4fa086b9
LSL		 2050 if (stream->sink->edid_caps.qs_bit == 1 &&
2051 stream->sink->edid_caps.qy_bit == 1) {
50e27654
ZF		 2052 if (color_space == COLOR_SPACE_SRGB ||
2053 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2054 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2055 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
2056 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2057 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2058 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2059 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2060 } else {
2061 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2062 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2063 }
4562236b 2064 } else {
e8d726b7 2065 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
50e27654 2066 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4562236b 2067 }
50e27654 2068
15e17335 2069 ///VIC
4fa086b9 2070 format = stream->timing.timing_3d_format;
15e17335
CL		 2071 /*todo, add 3DStereo support*/
2072 if (format != TIMING_3D_FORMAT_NONE) {
2073 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4fa086b9 2074 switch (pipe_ctx->stream->timing.hdmi_vic) {
15e17335
CL		 2075 case 1:
2076 vic = 95;
2077 break;
2078 case 2:
2079 vic = 94;
2080 break;
2081 case 3:
2082 vic = 93;
2083 break;
2084 case 4:
2085 vic = 98;
2086 break;
2087 default:
2088 break;
2089 }
2090 }
2091 hdmi_info->bits.VIC0_VIC7 = vic;
4562236b
HW		 2092
2093 /* pixel repetition
2094 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2095 * repetition start from 1 */
e8d726b7 2096 hdmi_info->bits.PR0_PR3 = 0;
4562236b
HW		 2097
2098 /* Bar Info
2099 * barTop: Line Number of End of Top Bar.
2100 * barBottom: Line Number of Start of Bottom Bar.
2101 * barLeft: Pixel Number of End of Left Bar.
2102 * barRight: Pixel Number of Start of Right Bar. */
4fa086b9
LSL		 2103 hdmi_info->bits.bar_top = stream->timing.v_border_top;
2104 hdmi_info->bits.bar_bottom = (stream->timing.v_total
2105 - stream->timing.v_border_bottom + 1);
2106 hdmi_info->bits.bar_left = stream->timing.h_border_left;
2107 hdmi_info->bits.bar_right = (stream->timing.h_total
2108 - stream->timing.h_border_right + 1);
4562236b
HW		 2109
2110 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
e8d726b7
RA		 2111 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
2112
3e183c5f 2113 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
4562236b 2114
3e183c5f 2115 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
e8d726b7 2116 *check_sum += hdmi_info->packet_raw_data.sb[byte_index];
4562236b
HW		 2117
2118 /* one byte complement */
2119 *check_sum = (uint8_t) (0x100 - *check_sum);
2120
2121 /* Store in hw_path_mode */
e8d726b7
RA		 2122 info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
2123 info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
2124 info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
4562236b 2125
e66e4d64
HW		 2126 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
2127 info_packet_hdmi.packet_raw_data.sb); byte_index++)
4562236b 2128 info_packet->sb[byte_index] = info_frame.avi_info_packet.
e66e4d64 2129 info_packet_hdmi.packet_raw_data.sb[byte_index];
4562236b
HW		 2130
2131 info_packet->valid = true;
2132}
2133
6e4d6bee
TC		 2134static void set_vendor_info_packet(
2135 struct encoder_info_packet *info_packet,
0971c40e 2136 struct dc_stream_state *stream)
4562236b
HW		 2137{
2138 uint32_t length = 0;
2139 bool hdmi_vic_mode = false;
2140 uint8_t checksum = 0;
2141 uint32_t i = 0;
2142 enum dc_timing_3d_format format;
15e17335
CL		 2143 // Can be different depending on packet content /*todo*/
2144 // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
2145
2146 info_packet->valid = false;
4562236b 2147
4fa086b9
LSL		 2148 format = stream->timing.timing_3d_format;
2149 if (stream->view_format == VIEW_3D_FORMAT_NONE)
7f5c22d1 2150 format = TIMING_3D_FORMAT_NONE;
4562236b
HW		 2151
2152 /* Can be different depending on packet content */
2153 length = 5;
2154
4fa086b9
LSL		 2155 if (stream->timing.hdmi_vic != 0
2156 && stream->timing.h_total >= 3840
2157 && stream->timing.v_total >= 2160)
4562236b
HW		 2158 hdmi_vic_mode = true;
2159
2160 /* According to HDMI 1.4a CTS, VSIF should be sent
2161 * for both 3D stereo and HDMI VIC modes.
2162 * For all other modes, there is no VSIF sent. */
2163
2164 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
2165 return;
2166
2167 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */
2168 info_packet->sb[1] = 0x03;
2169 info_packet->sb[2] = 0x0C;
2170 info_packet->sb[3] = 0x00;
2171
2172 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
2173 * The value for HDMI_Video_Format are:
2174 * 0x0 (0b000) - No additional HDMI video format is presented in this
2175 * packet
2176 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
2177 * parameter follows
2178 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
2179 * potentially 3D_Ext_Data follows
2180 * 0x3..0x7 (0b011..0b111) - reserved for future use */
2181 if (format != TIMING_3D_FORMAT_NONE)
2182 info_packet->sb[4] = (2 << 5);
2183 else if (hdmi_vic_mode)
2184 info_packet->sb[4] = (1 << 5);
2185
2186 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
2187 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
2188 * The value for 3D_Structure are:
2189 * 0x0 - Frame Packing
2190 * 0x1 - Field Alternative
2191 * 0x2 - Line Alternative
2192 * 0x3 - Side-by-Side (full)
2193 * 0x4 - L + depth
2194 * 0x5 - L + depth + graphics + graphics-depth
2195 * 0x6 - Top-and-Bottom
2196 * 0x7 - Reserved for future use
2197 * 0x8 - Side-by-Side (Half)
2198 * 0x9..0xE - Reserved for future use
2199 * 0xF - Not used */
2200 switch (format) {
2201 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
2202 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
2203 info_packet->sb[5] = (0x0 << 4);
2204 break;
2205
2206 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
2207 case TIMING_3D_FORMAT_SBS_SW_PACKED:
2208 info_packet->sb[5] = (0x8 << 4);
2209 length = 6;
2210 break;
2211
2212 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
2213 case TIMING_3D_FORMAT_TB_SW_PACKED:
2214 info_packet->sb[5] = (0x6 << 4);
2215 break;
2216
2217 default:
2218 break;
2219 }
2220
2221 /*PB5: If PB4 is set to 0x1 (extended resolution format)
2222 * fill PB5 with the correct HDMI VIC code */
2223 if (hdmi_vic_mode)
4fa086b9 2224 info_packet->sb[5] = stream->timing.hdmi_vic;
4562236b
HW		 2225
2226 /* Header */
3e183c5f 2227 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
4562236b
HW		 2228 info_packet->hb1 = 0x01; /* Version */
2229
2230 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
2231 info_packet->hb2 = (uint8_t) (length);
2232
2233 /* Calculate checksum */
2234 checksum = 0;
2235 checksum += info_packet->hb0;
2236 checksum += info_packet->hb1;
2237 checksum += info_packet->hb2;
2238
2239 for (i = 1; i <= length; i++)
2240 checksum += info_packet->sb[i];
2241
2242 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
2243
2244 info_packet->valid = true;
2245}
2246
6e4d6bee
TC		 2247static void set_spd_info_packet(
2248 struct encoder_info_packet *info_packet,
0971c40e 2249 struct dc_stream_state *stream)
4562236b
HW		 2250{
2251 /* SPD info packet for FreeSync */
2252
2253 unsigned char checksum = 0;
2254 unsigned int idx, payload_size = 0;
2255
2256 /* Check if Freesync is supported. Return if false. If true,
2257 * set the corresponding bit in the info packet
2258 */
4fa086b9 2259 if (stream->freesync_ctx.supported == false)
4562236b
HW		 2260 return;
2261
2262 if (dc_is_hdmi_signal(stream->signal)) {
2263
2264 /* HEADER */
2265
2266 /* HB0 = Packet Type = 0x83 (Source Product
2267 * Descriptor InfoFrame)
2268 */
3e183c5f 2269 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2270
2271 /* HB1 = Version = 0x01 */
2272 info_packet->hb1 = 0x01;
2273
2274 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2275 info_packet->hb2 = 0x08;
2276
2277 payload_size = 0x08;
2278
2279 } else if (dc_is_dp_signal(stream->signal)) {
2280
2281 /* HEADER */
2282
2283 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2284 * when used to associate audio related info packets
2285 */
2286 info_packet->hb0 = 0x00;
2287
2288 /* HB1 = Packet Type = 0x83 (Source Product
2289 * Descriptor InfoFrame)
2290 */
3e183c5f 2291 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
4562236b
HW		 2292
2293 /* HB2 = [Bits 7:0 = Least significant eight bits -
2294 * For INFOFRAME, the value must be 1Bh]
2295 */
2296 info_packet->hb2 = 0x1B;
2297
2298 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2299 * [Bits 1:0 = Most significant two bits = 0x00]
2300 */
2301 info_packet->hb3 = 0x04;
2302
2303 payload_size = 0x1B;
2304 }
2305
2306 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2307 info_packet->sb[1] = 0x1A;
2308
2309 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2310 info_packet->sb[2] = 0x00;
2311
2312 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2313 info_packet->sb[3] = 0x00;
2314
2315 /* PB4 = Reserved */
2316 info_packet->sb[4] = 0x00;
2317
2318 /* PB5 = Reserved */
2319 info_packet->sb[5] = 0x00;
2320
2321 /* PB6 = [Bits 7:3 = Reserved] */
2322 info_packet->sb[6] = 0x00;
2323
4fa086b9 2324 if (stream->freesync_ctx.supported == true)
4562236b
HW		 2325 /* PB6 = [Bit 0 = FreeSync Supported] */
2326 info_packet->sb[6] |= 0x01;
2327
4fa086b9 2328 if (stream->freesync_ctx.enabled == true)
4562236b
HW		 2329 /* PB6 = [Bit 1 = FreeSync Enabled] */
2330 info_packet->sb[6] |= 0x02;
2331
4fa086b9 2332 if (stream->freesync_ctx.active == true)
4562236b
HW		 2333 /* PB6 = [Bit 2 = FreeSync Active] */
2334 info_packet->sb[6] |= 0x04;
2335
2336 /* PB7 = FreeSync Minimum refresh rate (Hz) */
4fa086b9 2337 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2338 min_refresh_in_micro_hz / 1000000);
2339
2340 /* PB8 = FreeSync Maximum refresh rate (Hz)
2341 *
2342 * Note: We do not use the maximum capable refresh rate
2343 * of the panel, because we should never go above the field
2344 * rate of the mode timing set.
2345 */
4fa086b9 2346 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
4562236b
HW		 2347 nominal_refresh_in_micro_hz / 1000000);
2348
2349 /* PB9 - PB27 = Reserved */
2350 for (idx = 9; idx <= 27; idx++)
2351 info_packet->sb[idx] = 0x00;
2352
2353 /* Calculate checksum */
2354 checksum += info_packet->hb0;
2355 checksum += info_packet->hb1;
2356 checksum += info_packet->hb2;
2357 checksum += info_packet->hb3;
2358
2359 for (idx = 1; idx <= payload_size; idx++)
2360 checksum += info_packet->sb[idx];
2361
2362 /* PB0 = Checksum (one byte complement) */
2363 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2364
2365 info_packet->valid = true;
2366}
2367
1646a6fe 2368static void set_hdr_static_info_packet(
6e4d6bee 2369 struct encoder_info_packet *info_packet,
3be5262e 2370 struct dc_plane_state *plane_state,
0971c40e 2371 struct dc_stream_state *stream)
1646a6fe 2372{
e5cf325b 2373 uint16_t i = 0;
1646a6fe 2374 enum signal_type signal = stream->signal;
e5cf325b
HW		 2375 struct dc_hdr_static_metadata hdr_metadata;
2376 uint32_t data;
1646a6fe 2377
3be5262e 2378 if (!plane_state)
1646a6fe
AW		 2379 return;
2380
3be5262e 2381 hdr_metadata = plane_state->hdr_static_ctx;
1646a6fe 2382
70063a59 2383 if (!hdr_metadata.hdr_supported)
10bff005
YS		 2384 return;
2385
1646a6fe
AW		 2386 if (dc_is_hdmi_signal(signal)) {
2387 info_packet->valid = true;
2388
2389 info_packet->hb0 = 0x87;
2390 info_packet->hb1 = 0x01;
2391 info_packet->hb2 = 0x1A;
2392 i = 1;
2393 } else if (dc_is_dp_signal(signal)) {
2394 info_packet->valid = true;
2395
2396 info_packet->hb0 = 0x00;
2397 info_packet->hb1 = 0x87;
2398 info_packet->hb2 = 0x1D;
2399 info_packet->hb3 = (0x13 << 2);
2400 i = 2;
2401 }
2402
1646a6fe
AW		 2403 data = hdr_metadata.is_hdr;
2404 info_packet->sb[i++] = data ? 0x02 : 0x00;
2405 info_packet->sb[i++] = 0x00;
2406
2407 data = hdr_metadata.chromaticity_green_x / 2;
2408 info_packet->sb[i++] = data & 0xFF;
2409 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2410
2411 data = hdr_metadata.chromaticity_green_y / 2;
2412 info_packet->sb[i++] = data & 0xFF;
2413 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2414
2415 data = hdr_metadata.chromaticity_blue_x / 2;
2416 info_packet->sb[i++] = data & 0xFF;
2417 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2418
2419 data = hdr_metadata.chromaticity_blue_y / 2;
2420 info_packet->sb[i++] = data & 0xFF;
2421 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2422
2423 data = hdr_metadata.chromaticity_red_x / 2;
2424 info_packet->sb[i++] = data & 0xFF;
2425 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2426
2427 data = hdr_metadata.chromaticity_red_y / 2;
2428 info_packet->sb[i++] = data & 0xFF;
2429 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2430
2431 data = hdr_metadata.chromaticity_white_point_x / 2;
2432 info_packet->sb[i++] = data & 0xFF;
2433 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2434
2435 data = hdr_metadata.chromaticity_white_point_y / 2;
2436 info_packet->sb[i++] = data & 0xFF;
2437 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2438
2439 data = hdr_metadata.max_luminance;
2440 info_packet->sb[i++] = data & 0xFF;
2441 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2442
2443 data = hdr_metadata.min_luminance;
2444 info_packet->sb[i++] = data & 0xFF;
2445 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2446
2447 data = hdr_metadata.maximum_content_light_level;
2448 info_packet->sb[i++] = data & 0xFF;
2449 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2450
2451 data = hdr_metadata.maximum_frame_average_light_level;
2452 info_packet->sb[i++] = data & 0xFF;
2453 info_packet->sb[i++] = (data & 0xFF00) >> 8;
2454
2455 if (dc_is_hdmi_signal(signal)) {
2456 uint32_t checksum = 0;
2457
2458 checksum += info_packet->hb0;
2459 checksum += info_packet->hb1;
2460 checksum += info_packet->hb2;
2461
2462 for (i = 1; i <= info_packet->hb2; i++)
2463 checksum += info_packet->sb[i];
2464
2465 info_packet->sb[0] = 0x100 - checksum;
2466 } else if (dc_is_dp_signal(signal)) {
2467 info_packet->sb[0] = 0x01;
2468 info_packet->sb[1] = 0x1A;
2469 }
2470}
2471
6e4d6bee
TC		 2472static void set_vsc_info_packet(
2473 struct encoder_info_packet *info_packet,
0971c40e 2474 struct dc_stream_state *stream)
4562236b
HW		 2475{
2476 unsigned int vscPacketRevision = 0;
2477 unsigned int i;
2478
9665eb15
T		 2479 /*VSC packet set to 2 when DP revision >= 1.2*/
2480 if (stream->sink->link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 2481 vscPacketRevision = 2;
2482 }
2483
2484 /* VSC packet not needed based on the features
2485 * supported by this DP display
2486 */
2487 if (vscPacketRevision == 0)
2488 return;
2489
2490 if (vscPacketRevision == 0x2) {
2491 /* Secondary-data Packet ID = 0*/
2492 info_packet->hb0 = 0x00;
2493 /* 07h - Packet Type Value indicating Video
2494 * Stream Configuration packet
2495 */
2496 info_packet->hb1 = 0x07;
2497 /* 02h = VSC SDP supporting 3D stereo and PSR
2498 * (applies to eDP v1.3 or higher).
2499 */
2500 info_packet->hb2 = 0x02;
2501 /* 08h = VSC packet supporting 3D stereo + PSR
2502 * (HB2 = 02h).
2503 */
2504 info_packet->hb3 = 0x08;
2505
2506 for (i = 0; i < 28; i++)
2507 info_packet->sb[i] = 0;
2508
2509 info_packet->valid = true;
2510 }
2511
2512 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/
2513}
2514
f36cc577 2515void dc_resource_state_destruct(struct dc_state *context)
4562236b
HW		 2516{
2517 int i, j;
2518
ab2541b6 2519 for (i = 0; i < context->stream_count; i++) {
3be5262e
HW		 2520 for (j = 0; j < context->stream_status[i].plane_count; j++)
2521 dc_plane_state_release(
2522 context->stream_status[i].plane_states[j]);
4562236b 2523
3be5262e 2524 context->stream_status[i].plane_count = 0;
4fa086b9 2525 dc_stream_release(context->streams[i]);
ab2541b6 2526 context->streams[i] = NULL;
4562236b
HW		 2527 }
2528}
2529
2530/*
ab2541b6 2531 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
4562236b
HW		 2532 * by the src_ctx
2533 */
f36cc577 2534void dc_resource_state_copy_construct(
608ac7bb
JZ		 2535 const struct dc_state *src_ctx,
2536 struct dc_state *dst_ctx)
4562236b
HW		 2537{
2538 int i, j;
8ee5702a 2539 struct kref refcount = dst_ctx->refcount;
4562236b
HW		 2540
2541 *dst_ctx = *src_ctx;
2542
a2b8659d 2543 for (i = 0; i < MAX_PIPES; i++) {
4562236b
HW		 2544 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2545
2546 if (cur_pipe->top_pipe)
2547 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2548
2549 if (cur_pipe->bottom_pipe)
2550 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2551
2552 }
2553
ab2541b6 2554 for (i = 0; i < dst_ctx->stream_count; i++) {
4fa086b9 2555 dc_stream_retain(dst_ctx->streams[i]);
3be5262e
HW		 2556 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2557 dc_plane_state_retain(
2558 dst_ctx->stream_status[i].plane_states[j]);
4562236b 2559 }
9a3afbb3
AG		 2560
2561 /* context refcount should not be overridden */
8ee5702a 2562 dst_ctx->refcount = refcount;
9a3afbb3 2563
4562236b
HW		 2564}
2565
2566struct clock_source *dc_resource_find_first_free_pll(
a2b8659d
TC		 2567 struct resource_context *res_ctx,
2568 const struct resource_pool *pool)
4562236b
HW		 2569{
2570 int i;
2571
a2b8659d 2572 for (i = 0; i < pool->clk_src_count; ++i) {
4562236b 2573 if (res_ctx->clock_source_ref_count[i] == 0)
a2b8659d 2574 return pool->clock_sources[i];
4562236b
HW		 2575 }
2576
2577 return NULL;
2578}
2579
2580void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2581{
2582 enum signal_type signal = SIGNAL_TYPE_NONE;
96c50c0d 2583 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4562236b
HW		 2584
2585 /* default all packets to invalid */
6e4d6bee
TC		 2586 info->avi.valid = false;
2587 info->gamut.valid = false;
2588 info->vendor.valid = false;
630e3573 2589 info->spd.valid = false;
6e4d6bee
TC		 2590 info->hdrsmd.valid = false;
2591 info->vsc.valid = false;
4562236b
HW		 2592
2593 signal = pipe_ctx->stream->signal;
2594
2595 /* HDMi and DP have different info packets*/
2596 if (dc_is_hdmi_signal(signal)) {
6e4d6bee
TC		 2597 set_avi_info_frame(&info->avi, pipe_ctx);
2598
2599 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2600
2601 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2602
2603 set_hdr_static_info_packet(&info->hdrsmd,
3be5262e 2604 pipe_ctx->plane_state, pipe_ctx->stream);
6e4d6bee 2605
a33fa99d 2606 } else if (dc_is_dp_signal(signal)) {
6e4d6bee
TC		 2607 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2608
2609 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2610
2611 set_hdr_static_info_packet(&info->hdrsmd,
3be5262e 2612 pipe_ctx->plane_state, pipe_ctx->stream);
a33fa99d 2613 }
4562236b 2614
6e4d6bee 2615 patch_gamut_packet_checksum(&info->gamut);
4562236b
HW		 2616}
2617
2618enum dc_status resource_map_clock_resources(
fb3466a4 2619 const struct dc *dc,
608ac7bb 2620 struct dc_state *context,
1dc90497 2621 struct dc_stream_state *stream)
4562236b 2622{
4562236b 2623 /* acquire new resources */
1dc90497
AG		 2624 const struct resource_pool *pool = dc->res_pool;
2625 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2626 &context->res_ctx, stream);
ab2541b6 2627
1dc90497
AG		 2628 if (!pipe_ctx)
2629 return DC_ERROR_UNEXPECTED;
4562236b 2630
1dc90497
AG		 2631 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2632 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2633 pipe_ctx->clock_source = pool->dp_clock_source;
2634 else {
2635 pipe_ctx->clock_source = NULL;
4562236b 2636
1dc90497 2637 if (!dc->config.disable_disp_pll_sharing)
4ed4e51b 2638 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
1dc90497
AG		 2639 &context->res_ctx,
2640 pipe_ctx);
4562236b 2641
1dc90497
AG		 2642 if (pipe_ctx->clock_source == NULL)
2643 pipe_ctx->clock_source =
2644 dc_resource_find_first_free_pll(
2645 &context->res_ctx,
2646 pool);
2647 }
4562236b 2648
1dc90497
AG		 2649 if (pipe_ctx->clock_source == NULL)
2650 return DC_NO_CLOCK_SOURCE_RESOURCE;
4562236b 2651
1dc90497
AG		 2652 resource_reference_clock_source(
2653 &context->res_ctx, pool,
2654 pipe_ctx->clock_source);
4562236b
HW		 2655
2656 return DC_OK;
2657}
2658
2659/*
2660 * Note: We need to disable output if clock sources change,
2661 * since bios does optimization and doesn't apply if changing
2662 * PHY when not already disabled.
2663 */
2664bool pipe_need_reprogram(
2665 struct pipe_ctx *pipe_ctx_old,
2666 struct pipe_ctx *pipe_ctx)
2667{
cfe4645e
DL		 2668 if (!pipe_ctx_old->stream)
2669 return false;
2670
4562236b
HW		 2671 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2672 return true;
2673
2674 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2675 return true;
2676
afaacef4 2677 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4562236b
HW		 2678 return true;
2679
2680 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2681 && pipe_ctx_old->stream != pipe_ctx->stream)
2682 return true;
2683
8e9c4c8c 2684 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4562236b
HW		 2685 return true;
2686
2687 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2688 return true;
2689
2690
2691 return false;
2692}
529cad0f 2693
0971c40e 2694void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
529cad0f
DW		 2695 struct bit_depth_reduction_params *fmt_bit_depth)
2696{
4fa086b9 2697 enum dc_dither_option option = stream->dither_option;
529cad0f 2698 enum dc_pixel_encoding pixel_encoding =
4fa086b9 2699 stream->timing.pixel_encoding;
529cad0f
DW		 2700
2701 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2702
603767f9
TC		 2703 if (option == DITHER_OPTION_DEFAULT) {
2704 switch (stream->timing.display_color_depth) {
2705 case COLOR_DEPTH_666:
2706 option = DITHER_OPTION_SPATIAL6;
2707 break;
2708 case COLOR_DEPTH_888:
2709 option = DITHER_OPTION_SPATIAL8;
2710 break;
2711 case COLOR_DEPTH_101010:
2712 option = DITHER_OPTION_SPATIAL10;
2713 break;
2714 default:
2715 option = DITHER_OPTION_DISABLE;
2716 }
2717 }
2718
529cad0f
DW		 2719 if (option == DITHER_OPTION_DISABLE)
2720 return;
2721
2722 if (option == DITHER_OPTION_TRUN6) {
2723 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2724 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2725 } else if (option == DITHER_OPTION_TRUN8 ||
2726 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2727 option == DITHER_OPTION_TRUN8_FM6) {
2728 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2729 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2730 } else if (option == DITHER_OPTION_TRUN10 ||
2731 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2732 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2733 option == DITHER_OPTION_TRUN10_FM8 ||
2734 option == DITHER_OPTION_TRUN10_FM6 ||
2735 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2736 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2737 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2738 }
2739
2740 /* special case - Formatter can only reduce by 4 bits at most.
2741 * When reducing from 12 to 6 bits,
2742 * HW recommends we use trunc with round mode
2743 * (if we did nothing, trunc to 10 bits would be used)
2744 * note that any 12->10 bit reduction is ignored prior to DCE8,
2745 * as the input was 10 bits.
2746 */
2747 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2748 option == DITHER_OPTION_SPATIAL6 ||
2749 option == DITHER_OPTION_FM6) {
2750 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2751 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2752 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2753 }
2754
2755 /* spatial dither
2756 * note that spatial modes 1-3 are never used
2757 */
2758 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2759 option == DITHER_OPTION_SPATIAL6 ||
2760 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2761 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2762 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2763 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2764 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2765 fmt_bit_depth->flags.RGB_RANDOM =
2766 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2767 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2768 option == DITHER_OPTION_SPATIAL8 ||
2769 option == DITHER_OPTION_SPATIAL8_FM6 ||
2770 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2771 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2772 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2773 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2774 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2775 fmt_bit_depth->flags.RGB_RANDOM =
2776 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2777 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2778 option == DITHER_OPTION_SPATIAL10 ||
2779 option == DITHER_OPTION_SPATIAL10_FM8 ||
2780 option == DITHER_OPTION_SPATIAL10_FM6) {
2781 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2782 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2783 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2784 fmt_bit_depth->flags.RGB_RANDOM =
2785 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2786 }
2787
2788 if (option == DITHER_OPTION_SPATIAL6 ||
2789 option == DITHER_OPTION_SPATIAL8 ||
2790 option == DITHER_OPTION_SPATIAL10) {
2791 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2792 } else {
2793 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2794 }
2795
2796 //////////////////////
2797 //// temporal dither
2798 //////////////////////
2799 if (option == DITHER_OPTION_FM6 ||
2800 option == DITHER_OPTION_SPATIAL8_FM6 ||
2801 option == DITHER_OPTION_SPATIAL10_FM6 ||
2802 option == DITHER_OPTION_TRUN10_FM6 ||
2803 option == DITHER_OPTION_TRUN8_FM6 ||
2804 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2805 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2806 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2807 } else if (option == DITHER_OPTION_FM8 ||
2808 option == DITHER_OPTION_SPATIAL10_FM8 ||
2809 option == DITHER_OPTION_TRUN10_FM8) {
2810 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2811 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2812 } else if (option == DITHER_OPTION_FM10) {
2813 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2814 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2815 }
2816
2817 fmt_bit_depth->pixel_encoding = pixel_encoding;
2818}
9345d987 2819
62c933f9 2820enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
9345d987 2821{
fb3466a4 2822 struct dc *core_dc = dc;
4fa086b9 2823 struct dc_link *link = stream->sink->link;
9345d987
AG		 2824 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2825 enum dc_status res = DC_OK;
2826
4fa086b9 2827 calculate_phy_pix_clks(stream);
9345d987 2828
4fa086b9 2829 if (!tg->funcs->validate_timing(tg, &stream->timing))
9345d987
AG		 2830 res = DC_FAIL_CONTROLLER_VALIDATE;
2831
2832 if (res == DC_OK)
2833 if (!link->link_enc->funcs->validate_output_with_stream(
4fa086b9 2834 link->link_enc, stream))
9345d987
AG		 2835 res = DC_FAIL_ENC_VALIDATE;
2836
2837 /* TODO: validate audio ASIC caps, encoder */
2838
2839 if (res == DC_OK)
4fa086b9 2840 res = dc_link_validate_mode_timing(stream,
9345d987 2841 link,
4fa086b9 2842 &stream->timing);
9345d987 2843
62c933f9 2844 return res;
9345d987 2845}
792671d7 2846
62c933f9 2847enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
792671d7 2848{
62c933f9
YS		 2849 enum dc_status res = DC_OK;
2850
792671d7 2851 /* TODO For now validates pixel format only */
8e7095b9 2852 if (dc->res_pool->funcs->validate_plane)
62c933f9 2853 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
792671d7 2854
62c933f9 2855 return res;
792671d7 2856}
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