[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_stream.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"
#include "dc.h"
#include "core_types.h"
#include "resource.h"
#include "ipp.h"
#include "timing_generator.h"

/*******************************************************************************
 * Private functions
 ******************************************************************************/
#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
static void update_stream_signal(struct dc_stream_state *stream)
{
	if (stream->output_signal == SIGNAL_TYPE_NONE) {
		struct dc_sink *dc_sink = stream->sink;

		if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
			stream->signal = stream->sink->link->connector_signal;
		else
			stream->signal = dc_sink->sink_signal;
	} else {
		stream->signal = stream->output_signal;
	}

	if (dc_is_dvi_signal(stream->signal)) {
		if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
			stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
			stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
		else
			stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
	}
}

static bool construct(struct dc_stream_state *stream,
	struct dc_sink *dc_sink_data)
{
	uint32_t i = 0;

	stream->sink = dc_sink_data;
	stream->ctx = stream->sink->ctx;

	dc_sink_retain(dc_sink_data);

	/* Copy audio modes */
	/* TODO - Remove this translation */
	for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
	{
		stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
		stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
		stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
		stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
	}
	stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
	stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
	stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
	memmove(
		stream->audio_info.display_name,
		dc_sink_data->edid_caps.display_name,
		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
	stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
	stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
	stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;

	if (dc_sink_data->dc_container_id != NULL) {
		struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;

		stream->audio_info.port_id[0] = dc_container_id->portId[0];
		stream->audio_info.port_id[1] = dc_container_id->portId[1];
	} else {
		/* TODO - WindowDM has implemented,
		other DMs need Unhardcode port_id */
		stream->audio_info.port_id[0] = 0x5558859e;
		stream->audio_info.port_id[1] = 0xd989449;
	}

	/* EDID CAP translation for HDMI 2.0 */
	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;

	stream->status.link = stream->sink->link;

	update_stream_signal(stream);
	return true;
}

static void destruct(struct dc_stream_state *stream)
{
	dc_sink_release(stream->sink);
	if (stream->out_transfer_func != NULL) {
		dc_transfer_func_release(
				stream->out_transfer_func);
		stream->out_transfer_func = NULL;
	}
}

void dc_stream_retain(struct dc_stream_state *stream)
{
	ASSERT(atomic_read(&stream->ref_count) > 0);
	atomic_inc(&stream->ref_count);
}

void dc_stream_release(struct dc_stream_state *stream)
{
	if (stream != NULL) {
		ASSERT(atomic_read(&stream->ref_count) > 0);
		atomic_dec(&stream->ref_count);

		if (atomic_read(&stream->ref_count) == 0) {
			destruct(stream);
			kfree(stream);
		}
	}
}

struct dc_stream_state *dc_create_stream_for_sink(
		struct dc_sink *sink)
{
	struct dc_stream_state *stream;

	if (sink == NULL)
		goto alloc_fail;

	stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);

	if (NULL == stream)
		goto alloc_fail;

	if (false == construct(stream, sink))
			goto construct_fail;

	atomic_inc(&stream->ref_count);

	return stream;

construct_fail:
	kfree(stream);

alloc_fail:
	return NULL;
}

struct dc_stream_status *dc_stream_get_status(
	struct dc_stream_state *stream)
{
	uint8_t i;
	struct dc  *dc = stream->ctx->dc;

	for (i = 0; i < dc->current_state->stream_count; i++) {
		if (stream == dc->current_state->streams[i])
			return &dc->current_state->stream_status[i];
	}

	return NULL;
}

/**
 * Update the cursor attributes and set cursor surface address
 */
bool dc_stream_set_cursor_attributes(
	const struct dc_stream_state *stream,
	const struct dc_cursor_attributes *attributes)
{
	int i;
	struct dc  *core_dc;
	struct resource_context *res_ctx;

	if (NULL == stream) {
		dm_error("DC: dc_stream is NULL!\n");
			return false;
	}
	if (NULL == attributes) {
		dm_error("DC: attributes is NULL!\n");
			return false;
	}

	core_dc = stream->ctx->dc;
	res_ctx = &core_dc->current_state->res_ctx;

	for (i = 0; i < MAX_PIPES; i++) {
		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

		if (pipe_ctx->stream != stream || !pipe_ctx->plane_res.ipp)
			continue;
		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
			continue;

		pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
				pipe_ctx->plane_res.ipp, attributes);
	}

	return true;
}

bool dc_stream_set_cursor_position(
	struct dc_stream_state *stream,
	const struct dc_cursor_position *position)
{
	int i;
	struct dc  *core_dc;
	struct resource_context *res_ctx;

	if (NULL == stream) {
		dm_error("DC: dc_stream is NULL!\n");
		return false;
	}

	if (NULL == position) {
		dm_error("DC: cursor position is NULL!\n");
		return false;
	}

	core_dc = stream->ctx->dc;
	res_ctx = &core_dc->current_state->res_ctx;

	for (i = 0; i < MAX_PIPES; i++) {
		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
		struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
		struct dc_cursor_position pos_cpy = *position;
		struct dc_cursor_mi_param param = {
			.pixel_clk_khz = stream->timing.pix_clk_khz,
			.ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
			.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
			.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
			.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
		};

		if (pipe_ctx->stream != stream ||
				!pipe_ctx->plane_res.ipp || !pipe_ctx->plane_state)
			continue;

		if (pipe_ctx->plane_state->address.type
				== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
			pos_cpy.enable = false;

		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
			pos_cpy.enable = false;

		ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
	}

	return true;
}

uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
{
	uint8_t i;
	struct dc  *core_dc = stream->ctx->dc;
	struct resource_context *res_ctx =
		&core_dc->current_state->res_ctx;

	for (i = 0; i < MAX_PIPES; i++) {
		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

		if (res_ctx->pipe_ctx[i].stream != stream)
			continue;

		return tg->funcs->get_frame_count(tg);
	}

	return 0;
}

bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
				  uint32_t *v_blank_start,
				  uint32_t *v_blank_end,
				  uint32_t *h_position,
				  uint32_t *v_position)
{
	uint8_t i;
	bool ret = false;
	struct dc  *core_dc = stream->ctx->dc;
	struct resource_context *res_ctx =
		&core_dc->current_state->res_ctx;

	for (i = 0; i < MAX_PIPES; i++) {
		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

		if (res_ctx->pipe_ctx[i].stream != stream)
			continue;

		tg->funcs->get_scanoutpos(tg,
					  v_blank_start,
					  v_blank_end,
					  h_position,
					  v_position);

		ret = true;
		break;
	}

	return ret;
}


void dc_stream_log(
	const struct dc_stream_state *stream,
	struct dal_logger *dm_logger,
	enum dc_log_type log_type)
{

	dm_logger_write(dm_logger,
			log_type,
			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
			stream,
			stream->src.x,
			stream->src.y,
			stream->src.width,
			stream->src.height,
			stream->dst.x,
			stream->dst.y,
			stream->dst.width,
			stream->dst.height,
			stream->output_color_space);
	dm_logger_write(dm_logger,
			log_type,
			"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
			stream->timing.pix_clk_khz,
			stream->timing.h_total,
			stream->timing.v_total,
			stream->timing.pixel_encoding,
			stream->timing.display_color_depth);
	dm_logger_write(dm_logger,
			log_type,
			"\tsink name: %s, serial: %d\n",
			stream->sink->edid_caps.display_name,
			stream->sink->edid_caps.serial_number);
	dm_logger_write(dm_logger,
			log_type,
			"\tlink: %d\n",
			stream->sink->link->link_index);
}
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dm_services.h"
	27	#include "dc.h"
	28	#include "core_types.h"
	29	#include "resource.h"
ab2541b6 AC	30	#include "ipp.h"
ab2541b6 AC	31	#include "timing_generator.h"
4562236b	32
4562236b HW	33	/*******************************************************************************
	34	* Private functions
	35	******************************************************************************/
96313f1b JZ	36	#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
	37	static void update_stream_signal(struct dc_stream_state *stream)
	38	{
	39	if (stream->output_signal == SIGNAL_TYPE_NONE) {
	40	struct dc_sink *dc_sink = stream->sink;
	41
	42	if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
	43	stream->signal = stream->sink->link->connector_signal;
	44	else
	45	stream->signal = dc_sink->sink_signal;
	46	} else {
	47	stream->signal = stream->output_signal;
	48	}
	49
	50	if (dc_is_dvi_signal(stream->signal)) {
	51	if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
	52	stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
	53	stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
	54	else
	55	stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
	56	}
	57	}
4562236b	58
0971c40e	59	static bool construct(struct dc_stream_state *stream,
b73a22d3	60	struct dc_sink *dc_sink_data)
4562236b HW	61	{
	62	uint32_t i = 0;
	63
b73a22d3	64	stream->sink = dc_sink_data;
4562236b	65	stream->ctx = stream->sink->ctx;
4562236b HW	66
	67	dc_sink_retain(dc_sink_data);
	68
	69	/* Copy audio modes */
	70	/* TODO - Remove this translation */
	71	for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
	72	{
4fa086b9 LSL	73	stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
	74	stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
	75	stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
	76	stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
4562236b	77	}
4fa086b9 LSL	78	stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
	79	stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
	80	stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
4562236b	81	memmove(
4fa086b9	82	stream->audio_info.display_name,
4562236b HW	83	dc_sink_data->edid_caps.display_name,
4562236b HW	84	AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
4fa086b9 LSL	85	stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
	86	stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
	87	stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
4562236b	88
8c895313	89	if (dc_sink_data->dc_container_id != NULL) {
	90	struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
	91
4fa086b9 LSL	92	stream->audio_info.port_id[0] = dc_container_id->portId[0];
4fa086b9 LSL	93	stream->audio_info.port_id[1] = dc_container_id->portId[1];
8c895313	94	} else {
	95	/* TODO - WindowDM has implemented,
	96	other DMs need Unhardcode port_id */
4fa086b9 LSL	97	stream->audio_info.port_id[0] = 0x5558859e;
4fa086b9 LSL	98	stream->audio_info.port_id[1] = 0xd989449;
8c895313	99	}
4562236b HW	100
4562236b HW	101	/* EDID CAP translation for HDMI 2.0 */
4fa086b9	102	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
4562236b	103
d0778ebf	104	stream->status.link = stream->sink->link;
96313f1b JZ	105
96313f1b JZ	106	update_stream_signal(stream);
4562236b HW	107	return true;
	108	}
	109
0971c40e	110	static void destruct(struct dc_stream_state *stream)
4562236b	111	{
b73a22d3	112	dc_sink_release(stream->sink);
4fa086b9	113	if (stream->out_transfer_func != NULL) {
90e508ba	114	dc_transfer_func_release(
4fa086b9 LSL	115	stream->out_transfer_func);
4fa086b9 LSL	116	stream->out_transfer_func = NULL;
80bd2096	117	}
4562236b HW	118	}
4562236b HW	119
0971c40e	120	void dc_stream_retain(struct dc_stream_state *stream)
4562236b	121	{
e8cd2643 JZ	122	ASSERT(atomic_read(&stream->ref_count) > 0);
e8cd2643 JZ	123	atomic_inc(&stream->ref_count);
4562236b HW	124	}
4562236b HW	125
0971c40e	126	void dc_stream_release(struct dc_stream_state *stream)
4562236b	127	{
a989ab08	128	if (stream != NULL) {
e8cd2643 JZ	129	ASSERT(atomic_read(&stream->ref_count) > 0);
e8cd2643 JZ	130	atomic_dec(&stream->ref_count);
4562236b	131
e8cd2643	132	if (atomic_read(&stream->ref_count) == 0) {
a989ab08	133	destruct(stream);
2004f45e	134	kfree(stream);
4562236b HW	135	}
	136	}
	137	}
	138
0971c40e	139	struct dc_stream_state *dc_create_stream_for_sink(
b73a22d3	140	struct dc_sink *sink)
4562236b	141	{
0971c40e	142	struct dc_stream_state *stream;
4562236b HW	143
	144	if (sink == NULL)
	145	goto alloc_fail;
	146
2004f45e	147	stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
4562236b HW	148
	149	if (NULL == stream)
	150	goto alloc_fail;
	151
a989ab08	152	if (false == construct(stream, sink))
4562236b HW	153	goto construct_fail;
4562236b HW	154
e8cd2643	155	atomic_inc(&stream->ref_count);
4562236b	156
a989ab08	157	return stream;
4562236b HW	158
4562236b HW	159	construct_fail:
2004f45e	160	kfree(stream);
4562236b HW	161
	162	alloc_fail:
	163	return NULL;
	164	}
ab2541b6	165
e12cfcb1	166	struct dc_stream_status *dc_stream_get_status(
0971c40e	167	struct dc_stream_state *stream)
ab2541b6 AC	168	{
ab2541b6 AC	169	uint8_t i;
fb3466a4	170	struct dc *dc = stream->ctx->dc;
ab2541b6	171
608ac7bb JZ	172	for (i = 0; i < dc->current_state->stream_count; i++) {
	173	if (stream == dc->current_state->streams[i])
	174	return &dc->current_state->stream_status[i];
e2c7bb12	175	}
ab2541b6 AC	176
	177	return NULL;
	178	}
	179
	180	/**
	181	* Update the cursor attributes and set cursor surface address
	182	*/
	183	bool dc_stream_set_cursor_attributes(
0971c40e	184	const struct dc_stream_state *stream,
ab2541b6 AC	185	const struct dc_cursor_attributes *attributes)
	186	{
	187	int i;
fb3466a4	188	struct dc *core_dc;
ab2541b6	189	struct resource_context *res_ctx;
ab2541b6	190
4fa086b9	191	if (NULL == stream) {
ab2541b6 AC	192	dm_error("DC: dc_stream is NULL!\n");
	193	return false;
	194	}
	195	if (NULL == attributes) {
	196	dm_error("DC: attributes is NULL!\n");
	197	return false;
	198	}
	199
fb3466a4	200	core_dc = stream->ctx->dc;
608ac7bb	201	res_ctx = &core_dc->current_state->res_ctx;
ab2541b6 AC	202
	203	for (i = 0; i < MAX_PIPES; i++) {
	204	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
	205
86a66c4e	206	if (pipe_ctx->stream != stream \|\| !pipe_ctx->plane_res.ipp)
beb16b6a	207	continue;
3be5262e	208	if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
beb16b6a	209	continue;
ab2541b6	210
86a66c4e HW	211	pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
86a66c4e HW	212	pipe_ctx->plane_res.ipp, attributes);
ab2541b6 AC	213	}
ab2541b6 AC	214
beb16b6a	215	return true;
ab2541b6 AC	216	}
	217
	218	bool dc_stream_set_cursor_position(
0971c40e	219	struct dc_stream_state *stream,
beb16b6a	220	const struct dc_cursor_position *position)
ab2541b6 AC	221	{
ab2541b6 AC	222	int i;
fb3466a4	223	struct dc *core_dc;
ab2541b6	224	struct resource_context *res_ctx;
ab2541b6	225
4fa086b9	226	if (NULL == stream) {
ab2541b6 AC	227	dm_error("DC: dc_stream is NULL!\n");
	228	return false;
	229	}
	230
	231	if (NULL == position) {
	232	dm_error("DC: cursor position is NULL!\n");
	233	return false;
	234	}
	235
fb3466a4	236	core_dc = stream->ctx->dc;
608ac7bb	237	res_ctx = &core_dc->current_state->res_ctx;
ab2541b6 AC	238
	239	for (i = 0; i < MAX_PIPES; i++) {
	240	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
86a66c4e	241	struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
beb16b6a DL	242	struct dc_cursor_position pos_cpy = *position;
beb16b6a DL	243	struct dc_cursor_mi_param param = {
4fa086b9	244	.pixel_clk_khz = stream->timing.pix_clk_khz,
a2b8659d	245	.ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
6702a9ac HW	246	.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
	247	.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
	248	.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
beb16b6a DL	249	};
	250
	251	if (pipe_ctx->stream != stream \|\|
86a66c4e	252	!pipe_ctx->plane_res.ipp \|\| !pipe_ctx->plane_state)
beb16b6a	253	continue;
ab2541b6	254
3be5262e	255	if (pipe_ctx->plane_state->address.type
cf4cde2b YS	256	== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
	257	pos_cpy.enable = false;
	258
3be5262e	259	if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
beb16b6a DL	260	pos_cpy.enable = false;
	261
	262	ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
ab2541b6 AC	263	}
ab2541b6 AC	264
beb16b6a	265	return true;
ab2541b6 AC	266	}
ab2541b6 AC	267
0971c40e	268	uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
ab2541b6 AC	269	{
ab2541b6 AC	270	uint8_t i;
fb3466a4	271	struct dc *core_dc = stream->ctx->dc;
ab2541b6	272	struct resource_context *res_ctx =
608ac7bb	273	&core_dc->current_state->res_ctx;
ab2541b6 AC	274
ab2541b6 AC	275	for (i = 0; i < MAX_PIPES; i++) {
6b670fa9	276	struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
ab2541b6 AC	277
	278	if (res_ctx->pipe_ctx[i].stream != stream)
	279	continue;
	280
	281	return tg->funcs->get_frame_count(tg);
	282	}
	283
	284	return 0;
	285	}
	286
0971c40e	287	bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
81c50963 ST	288	uint32_t *v_blank_start,
	289	uint32_t *v_blank_end,
	290	uint32_t *h_position,
	291	uint32_t *v_position)
ab2541b6 AC	292	{
ab2541b6 AC	293	uint8_t i;
81c50963	294	bool ret = false;
fb3466a4	295	struct dc *core_dc = stream->ctx->dc;
ab2541b6	296	struct resource_context *res_ctx =
608ac7bb	297	&core_dc->current_state->res_ctx;
ab2541b6 AC	298
ab2541b6 AC	299	for (i = 0; i < MAX_PIPES; i++) {
6b670fa9	300	struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
ab2541b6 AC	301
	302	if (res_ctx->pipe_ctx[i].stream != stream)
	303	continue;
	304
81c50963 ST	305	tg->funcs->get_scanoutpos(tg,
	306	v_blank_start,
	307	v_blank_end,
	308	h_position,
	309	v_position);
	310
	311	ret = true;
	312	break;
ab2541b6 AC	313	}
ab2541b6 AC	314
81c50963	315	return ret;
ab2541b6 AC	316	}
	317
	318
	319	void dc_stream_log(
0971c40e	320	const struct dc_stream_state *stream,
ab2541b6 AC	321	struct dal_logger *dm_logger,
	322	enum dc_log_type log_type)
	323	{
ab2541b6 AC	324
	325	dm_logger_write(dm_logger,
	326	log_type,
4b679bc3	327	"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
4fa086b9 LSL	328	stream,
	329	stream->src.x,
	330	stream->src.y,
	331	stream->src.width,
	332	stream->src.height,
	333	stream->dst.x,
	334	stream->dst.y,
	335	stream->dst.width,
	336	stream->dst.height,
	337	stream->output_color_space);
ab2541b6 AC	338	dm_logger_write(dm_logger,
ab2541b6 AC	339	log_type,
4b679bc3	340	"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
4fa086b9 LSL	341	stream->timing.pix_clk_khz,
	342	stream->timing.h_total,
	343	stream->timing.v_total,
	344	stream->timing.pixel_encoding,
	345	stream->timing.display_color_depth);
ab2541b6 AC	346	dm_logger_write(dm_logger,
	347	log_type,
	348	"\tsink name: %s, serial: %d\n",
4fa086b9 LSL	349	stream->sink->edid_caps.display_name,
4fa086b9 LSL	350	stream->sink->edid_caps.serial_number);
ab2541b6 AC	351	dm_logger_write(dm_logger,
	352	log_type,
	353	"\tlink: %d\n",
4fa086b9	354	stream->sink->link->link_index);
ab2541b6	355	}