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4562236b HW |
1 | /* |
2 | * Copyright 2012-14 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef DC_INTERFACE_H_ | |
27 | #define DC_INTERFACE_H_ | |
28 | ||
29 | #include "dc_types.h" | |
4562236b HW |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" | |
32 | #include "gpio_types.h" | |
33 | #include "link_service_types.h" | |
34 | ||
091a97e5 | 35 | #define MAX_SURFACES 3 |
ab2541b6 | 36 | #define MAX_STREAMS 6 |
4562236b HW |
37 | #define MAX_SINKS_PER_LINK 4 |
38 | ||
39 | /******************************************************************************* | |
40 | * Display Core Interfaces | |
41 | ******************************************************************************/ | |
42 | ||
43 | struct dc_caps { | |
ab2541b6 | 44 | uint32_t max_streams; |
4562236b HW |
45 | uint32_t max_links; |
46 | uint32_t max_audios; | |
47 | uint32_t max_slave_planes; | |
d4e13b0d | 48 | uint32_t max_surfaces; |
4562236b HW |
49 | uint32_t max_downscale_ratio; |
50 | uint32_t i2c_speed_in_khz; | |
a37656b9 TC |
51 | |
52 | unsigned int max_cursor_size; | |
4562236b HW |
53 | }; |
54 | ||
55 | ||
56 | struct dc_dcc_surface_param { | |
4562236b | 57 | struct dc_size surface_size; |
ebf055f9 | 58 | enum surface_pixel_format format; |
2c8ad2d5 | 59 | enum swizzle_mode_values swizzle_mode; |
4562236b HW |
60 | enum dc_scan_direction scan; |
61 | }; | |
62 | ||
63 | struct dc_dcc_setting { | |
64 | unsigned int max_compressed_blk_size; | |
65 | unsigned int max_uncompressed_blk_size; | |
66 | bool independent_64b_blks; | |
67 | }; | |
68 | ||
69 | struct dc_surface_dcc_cap { | |
4562236b HW |
70 | union { |
71 | struct { | |
72 | struct dc_dcc_setting rgb; | |
73 | } grph; | |
74 | ||
75 | struct { | |
76 | struct dc_dcc_setting luma; | |
77 | struct dc_dcc_setting chroma; | |
78 | } video; | |
79 | }; | |
ebf055f9 AK |
80 | |
81 | bool capable; | |
82 | bool const_color_support; | |
4562236b HW |
83 | }; |
84 | ||
94267b3d ST |
85 | struct dc_static_screen_events { |
86 | bool cursor_update; | |
87 | bool surface_update; | |
88 | bool overlay_update; | |
89 | }; | |
90 | ||
4562236b HW |
91 | /* Forward declaration*/ |
92 | struct dc; | |
93 | struct dc_surface; | |
94 | struct validate_context; | |
95 | ||
96 | struct dc_cap_funcs { | |
ff5ef992 AD |
97 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
98 | bool (*get_dcc_compression_cap)(const struct dc *dc, | |
99 | const struct dc_dcc_surface_param *input, | |
100 | struct dc_surface_dcc_cap *output); | |
101 | #else | |
4562236b | 102 | int i; |
ff5ef992 | 103 | #endif |
4562236b HW |
104 | }; |
105 | ||
106 | struct dc_stream_funcs { | |
107 | bool (*adjust_vmin_vmax)(struct dc *dc, | |
108 | const struct dc_stream **stream, | |
109 | int num_streams, | |
110 | int vmin, | |
111 | int vmax); | |
72ada5f7 EC |
112 | bool (*get_crtc_position)(struct dc *dc, |
113 | const struct dc_stream **stream, | |
114 | int num_streams, | |
115 | unsigned int *v_pos, | |
116 | unsigned int *nom_v_pos); | |
117 | ||
4562236b | 118 | bool (*set_gamut_remap)(struct dc *dc, |
f46661dd | 119 | const struct dc_stream *stream); |
94267b3d | 120 | |
abe07e80 YHL |
121 | bool (*program_csc_matrix)(struct dc *dc, |
122 | const struct dc_stream *stream); | |
123 | ||
94267b3d ST |
124 | void (*set_static_screen_events)(struct dc *dc, |
125 | const struct dc_stream **stream, | |
126 | int num_streams, | |
127 | const struct dc_static_screen_events *events); | |
529cad0f DW |
128 | |
129 | void (*set_dither_option)(const struct dc_stream *stream, | |
130 | enum dc_dither_option option); | |
4562236b HW |
131 | }; |
132 | ||
133 | struct link_training_settings; | |
134 | ||
135 | struct dc_link_funcs { | |
136 | void (*set_drive_settings)(struct dc *dc, | |
bf5cda33 HW |
137 | struct link_training_settings *lt_settings, |
138 | const struct dc_link *link); | |
4562236b HW |
139 | void (*perform_link_training)(struct dc *dc, |
140 | struct dc_link_settings *link_setting, | |
141 | bool skip_video_pattern); | |
142 | void (*set_preferred_link_settings)(struct dc *dc, | |
88639168 ZF |
143 | struct dc_link_settings *link_setting, |
144 | const struct dc_link *link); | |
4562236b HW |
145 | void (*enable_hpd)(const struct dc_link *link); |
146 | void (*disable_hpd)(const struct dc_link *link); | |
147 | void (*set_test_pattern)( | |
148 | const struct dc_link *link, | |
149 | enum dp_test_pattern test_pattern, | |
150 | const struct link_training_settings *p_link_settings, | |
151 | const unsigned char *p_custom_pattern, | |
152 | unsigned int cust_pattern_size); | |
153 | }; | |
154 | ||
155 | /* Structure to hold configuration flags set by dm at dc creation. */ | |
156 | struct dc_config { | |
157 | bool gpu_vm_support; | |
158 | bool disable_disp_pll_sharing; | |
159 | }; | |
160 | ||
161 | struct dc_debug { | |
162 | bool surface_visual_confirm; | |
163 | bool max_disp_clk; | |
4562236b | 164 | bool surface_trace; |
9474980a | 165 | bool timing_trace; |
c9742685 | 166 | bool clock_trace; |
4562236b HW |
167 | bool validation_trace; |
168 | bool disable_stutter; | |
169 | bool disable_dcc; | |
170 | bool disable_dfs_bypass; | |
ff5ef992 AD |
171 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
172 | bool disable_dpp_power_gate; | |
173 | bool disable_hubp_power_gate; | |
174 | bool disable_pplib_wm_range; | |
175 | bool use_dml_wm; | |
90f095c1 | 176 | bool disable_pipe_split; |
139cb65c DL |
177 | int sr_exit_time_dpm0_ns; |
178 | int sr_enter_plus_exit_time_dpm0_ns; | |
ff5ef992 AD |
179 | int sr_exit_time_ns; |
180 | int sr_enter_plus_exit_time_ns; | |
181 | int urgent_latency_ns; | |
182 | int percent_of_ideal_drambw; | |
183 | int dram_clock_change_latency_ns; | |
e73b59b7 | 184 | int always_scale; |
ff5ef992 | 185 | #endif |
2c8ad2d5 | 186 | bool disable_pplib_clock_request; |
4562236b | 187 | bool disable_clock_gate; |
aa66df58 | 188 | bool disable_dmcu; |
29eba8e8 | 189 | bool disable_psr; |
70814f6f | 190 | bool force_abm_enable; |
1a87fbfe | 191 | bool no_static_for_external_dp; |
4562236b HW |
192 | }; |
193 | ||
194 | struct dc { | |
195 | struct dc_caps caps; | |
196 | struct dc_cap_funcs cap_funcs; | |
197 | struct dc_stream_funcs stream_funcs; | |
198 | struct dc_link_funcs link_funcs; | |
199 | struct dc_config config; | |
200 | struct dc_debug debug; | |
201 | }; | |
202 | ||
2c8ad2d5 AD |
203 | enum frame_buffer_mode { |
204 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, | |
205 | FRAME_BUFFER_MODE_ZFB_ONLY, | |
206 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, | |
207 | } ; | |
208 | ||
209 | struct dchub_init_data { | |
2c8ad2d5 AD |
210 | int64_t zfb_phys_addr_base; |
211 | int64_t zfb_mc_base_addr; | |
212 | uint64_t zfb_size_in_byte; | |
213 | enum frame_buffer_mode fb_mode; | |
ebf055f9 AK |
214 | bool dchub_initialzied; |
215 | bool dchub_info_valid; | |
2c8ad2d5 | 216 | }; |
2c8ad2d5 | 217 | |
4562236b HW |
218 | struct dc_init_data { |
219 | struct hw_asic_id asic_id; | |
220 | void *driver; /* ctx */ | |
221 | struct cgs_device *cgs_device; | |
222 | ||
223 | int num_virtual_links; | |
224 | /* | |
225 | * If 'vbios_override' not NULL, it will be called instead | |
226 | * of the real VBIOS. Intended use is Diagnostics on FPGA. | |
227 | */ | |
228 | struct dc_bios *vbios_override; | |
229 | enum dce_environment dce_environment; | |
230 | ||
231 | struct dc_config flags; | |
232 | }; | |
233 | ||
234 | struct dc *dc_create(const struct dc_init_data *init_params); | |
235 | ||
236 | void dc_destroy(struct dc **dc); | |
237 | ||
2c8ad2d5 | 238 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); |
2c8ad2d5 | 239 | |
4562236b HW |
240 | /******************************************************************************* |
241 | * Surface Interfaces | |
242 | ******************************************************************************/ | |
243 | ||
244 | enum { | |
fb735a9f | 245 | TRANSFER_FUNC_POINTS = 1025 |
4562236b HW |
246 | }; |
247 | ||
1646a6fe | 248 | struct dc_hdr_static_metadata { |
1646a6fe AW |
249 | /* display chromaticities and white point in units of 0.00001 */ |
250 | unsigned int chromaticity_green_x; | |
251 | unsigned int chromaticity_green_y; | |
252 | unsigned int chromaticity_blue_x; | |
253 | unsigned int chromaticity_blue_y; | |
254 | unsigned int chromaticity_red_x; | |
255 | unsigned int chromaticity_red_y; | |
256 | unsigned int chromaticity_white_point_x; | |
257 | unsigned int chromaticity_white_point_y; | |
258 | ||
259 | uint32_t min_luminance; | |
260 | uint32_t max_luminance; | |
261 | uint32_t maximum_content_light_level; | |
262 | uint32_t maximum_frame_average_light_level; | |
ebf055f9 AK |
263 | |
264 | bool hdr_supported; | |
265 | bool is_hdr; | |
1646a6fe AW |
266 | }; |
267 | ||
fb735a9f AK |
268 | enum dc_transfer_func_type { |
269 | TF_TYPE_PREDEFINED, | |
270 | TF_TYPE_DISTRIBUTED_POINTS, | |
7950f0f9 | 271 | TF_TYPE_BYPASS |
fb735a9f AK |
272 | }; |
273 | ||
274 | struct dc_transfer_func_distributed_points { | |
fcd2f4bf AZ |
275 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
276 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; | |
277 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; | |
278 | ||
fb735a9f | 279 | uint16_t end_exponent; |
fcd2f4bf AZ |
280 | uint16_t x_point_at_y1_red; |
281 | uint16_t x_point_at_y1_green; | |
282 | uint16_t x_point_at_y1_blue; | |
fb735a9f AK |
283 | }; |
284 | ||
285 | enum dc_transfer_func_predefined { | |
286 | TRANSFER_FUNCTION_SRGB, | |
287 | TRANSFER_FUNCTION_BT709, | |
90e508ba | 288 | TRANSFER_FUNCTION_PQ, |
fb735a9f AK |
289 | TRANSFER_FUNCTION_LINEAR, |
290 | }; | |
291 | ||
292 | struct dc_transfer_func { | |
ebf055f9 | 293 | struct dc_transfer_func_distributed_points tf_pts; |
fb735a9f AK |
294 | enum dc_transfer_func_type type; |
295 | enum dc_transfer_func_predefined tf; | |
7b0c470f LSL |
296 | struct dc_context *ctx; |
297 | int ref_count; | |
fb735a9f AK |
298 | }; |
299 | ||
4562236b | 300 | struct dc_surface { |
4562236b HW |
301 | struct dc_plane_address address; |
302 | ||
303 | struct scaling_taps scaling_quality; | |
304 | struct rect src_rect; | |
305 | struct rect dst_rect; | |
306 | struct rect clip_rect; | |
307 | ||
308 | union plane_size plane_size; | |
309 | union dc_tiling_info tiling_info; | |
ebf055f9 | 310 | |
4562236b | 311 | struct dc_plane_dcc_param dcc; |
ebf055f9 AK |
312 | struct dc_hdr_static_metadata hdr_static_ctx; |
313 | ||
314 | const struct dc_gamma *gamma_correction; | |
7b0c470f | 315 | struct dc_transfer_func *in_transfer_func; |
4562236b | 316 | |
ebf055f9 | 317 | enum dc_color_space color_space; |
4562236b HW |
318 | enum surface_pixel_format format; |
319 | enum dc_rotation_angle rotation; | |
4562236b HW |
320 | enum plane_stereo_format stereo_format; |
321 | ||
ebf055f9 AK |
322 | bool per_pixel_alpha; |
323 | bool visible; | |
324 | bool flip_immediate; | |
325 | bool horizontal_mirror; | |
4562236b HW |
326 | }; |
327 | ||
328 | struct dc_plane_info { | |
329 | union plane_size plane_size; | |
330 | union dc_tiling_info tiling_info; | |
9cd09bfe | 331 | struct dc_plane_dcc_param dcc; |
4562236b HW |
332 | enum surface_pixel_format format; |
333 | enum dc_rotation_angle rotation; | |
4562236b HW |
334 | enum plane_stereo_format stereo_format; |
335 | enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ | |
ebf055f9 | 336 | bool horizontal_mirror; |
4562236b | 337 | bool visible; |
ebf055f9 | 338 | bool per_pixel_alpha; |
4562236b HW |
339 | }; |
340 | ||
341 | struct dc_scaling_info { | |
ebf055f9 AK |
342 | struct rect src_rect; |
343 | struct rect dst_rect; | |
344 | struct rect clip_rect; | |
345 | struct scaling_taps scaling_quality; | |
4562236b HW |
346 | }; |
347 | ||
348 | struct dc_surface_update { | |
349 | const struct dc_surface *surface; | |
350 | ||
351 | /* isr safe update parameters. null means no updates */ | |
352 | struct dc_flip_addrs *flip_addr; | |
353 | struct dc_plane_info *plane_info; | |
354 | struct dc_scaling_info *scaling_info; | |
355 | /* following updates require alloc/sleep/spin that is not isr safe, | |
356 | * null means no updates | |
357 | */ | |
fb735a9f | 358 | /* gamma TO BE REMOVED */ |
4562236b | 359 | struct dc_gamma *gamma; |
fb735a9f | 360 | struct dc_transfer_func *in_transfer_func; |
f46661dd | 361 | struct dc_hdr_static_metadata *hdr_static_metadata; |
4562236b HW |
362 | }; |
363 | /* | |
364 | * This structure is filled in by dc_surface_get_status and contains | |
365 | * the last requested address and the currently active address so the called | |
366 | * can determine if there are any outstanding flips | |
367 | */ | |
368 | struct dc_surface_status { | |
369 | struct dc_plane_address requested_address; | |
370 | struct dc_plane_address current_address; | |
371 | bool is_flip_pending; | |
9edba557 | 372 | bool is_right_eye; |
4562236b HW |
373 | }; |
374 | ||
375 | /* | |
376 | * Create a new surface with default parameters; | |
377 | */ | |
378 | struct dc_surface *dc_create_surface(const struct dc *dc); | |
379 | const struct dc_surface_status *dc_surface_get_status( | |
380 | const struct dc_surface *dc_surface); | |
381 | ||
382 | void dc_surface_retain(const struct dc_surface *dc_surface); | |
383 | void dc_surface_release(const struct dc_surface *dc_surface); | |
384 | ||
89e89630 | 385 | void dc_gamma_retain(const struct dc_gamma *dc_gamma); |
aff20230 | 386 | void dc_gamma_release(const struct dc_gamma **dc_gamma); |
4562236b HW |
387 | struct dc_gamma *dc_create_gamma(void); |
388 | ||
7b0c470f LSL |
389 | void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); |
390 | void dc_transfer_func_release(struct dc_transfer_func *dc_tf); | |
90e508ba | 391 | struct dc_transfer_func *dc_create_transfer_func(void); |
fb735a9f | 392 | |
4562236b HW |
393 | /* |
394 | * This structure holds a surface address. There could be multiple addresses | |
395 | * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such | |
396 | * as frame durations and DCC format can also be set. | |
397 | */ | |
398 | struct dc_flip_addrs { | |
399 | struct dc_plane_address address; | |
400 | bool flip_immediate; | |
4562236b HW |
401 | /* TODO: add flip duration for FreeSync */ |
402 | }; | |
403 | ||
4562236b | 404 | /* |
ab2541b6 AC |
405 | * Set up surface attributes and associate to a stream |
406 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
407 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
4562236b HW |
408 | * Any flip related attribute changes must be done through this interface. |
409 | * | |
410 | * After this call: | |
ab2541b6 | 411 | * Surfaces attributes are programmed and configured to be composed into stream. |
4562236b HW |
412 | * This does not trigger a flip. No surface address is programmed. |
413 | */ | |
414 | ||
ab2541b6 | 415 | bool dc_commit_surfaces_to_stream( |
4562236b HW |
416 | struct dc *dc, |
417 | const struct dc_surface **dc_surfaces, | |
418 | uint8_t surface_count, | |
ab2541b6 | 419 | const struct dc_stream *stream); |
4562236b | 420 | |
ab2541b6 | 421 | bool dc_post_update_surfaces_to_stream( |
4562236b HW |
422 | struct dc *dc); |
423 | ||
81e2b2de DL |
424 | /* Surface update type is used by dc_update_surfaces_and_stream |
425 | * The update type is determined at the very beginning of the function based | |
426 | * on parameters passed in and decides how much programming (or updating) is | |
427 | * going to be done during the call. | |
428 | * | |
429 | * UPDATE_TYPE_FAST is used for really fast updates that do not require much | |
430 | * logical calculations or hardware register programming. This update MUST be | |
431 | * ISR safe on windows. Currently fast update will only be used to flip surface | |
432 | * address. | |
433 | * | |
434 | * UPDATE_TYPE_MED is used for slower updates which require significant hw | |
435 | * re-programming however do not affect bandwidth consumption or clock | |
436 | * requirements. At present, this is the level at which front end updates | |
437 | * that do not require us to run bw_calcs happen. These are in/out transfer func | |
438 | * updates, viewport offset changes, recout size changes and pixel depth changes. | |
439 | * This update can be done at ISR, but we want to minimize how often this happens. | |
440 | * | |
441 | * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our | |
442 | * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front | |
443 | * end related. Any time viewport dimensions, recout dimensions, scaling ratios or | |
444 | * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do | |
445 | * a full update. This cannot be done at ISR level and should be a rare event. | |
446 | * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting | |
447 | * underscan we don't expect to see this call at all. | |
448 | */ | |
449 | ||
5869b0f6 LE |
450 | enum surface_update_type { |
451 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ | |
81e2b2de | 452 | UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ |
5869b0f6 LE |
453 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ |
454 | }; | |
455 | ||
4562236b | 456 | /******************************************************************************* |
ab2541b6 | 457 | * Stream Interfaces |
4562236b | 458 | ******************************************************************************/ |
ab2541b6 AC |
459 | struct dc_stream { |
460 | const struct dc_sink *sink; | |
461 | struct dc_crtc_timing timing; | |
4562236b | 462 | |
ab2541b6 AC |
463 | struct rect src; /* composition area */ |
464 | struct rect dst; /* stream addressable area */ | |
4562236b | 465 | |
ab2541b6 AC |
466 | struct audio_info audio_info; |
467 | ||
ab2541b6 AC |
468 | struct freesync_context freesync_ctx; |
469 | ||
7b0c470f | 470 | struct dc_transfer_func *out_transfer_func; |
ab2541b6 AC |
471 | struct colorspace_transform gamut_remap_matrix; |
472 | struct csc_transform csc_color_matrix; | |
ebf055f9 AK |
473 | |
474 | enum signal_type output_signal; | |
475 | ||
476 | enum dc_color_space output_color_space; | |
477 | enum dc_dither_option dither_option; | |
478 | ||
9edba557 | 479 | enum view_3d_format view_format; |
ebf055f9 AK |
480 | |
481 | bool ignore_msa_timing_param; | |
ab2541b6 AC |
482 | /* TODO: custom INFO packets */ |
483 | /* TODO: ABM info (DMCU) */ | |
484 | /* TODO: PSR info */ | |
485 | /* TODO: CEA VIC */ | |
486 | }; | |
4562236b | 487 | |
a783e7b5 | 488 | struct dc_stream_update { |
a783e7b5 | 489 | struct rect src; |
a783e7b5 | 490 | struct rect dst; |
f46661dd | 491 | struct dc_transfer_func *out_transfer_func; |
a783e7b5 LE |
492 | }; |
493 | ||
494 | ||
495 | /* | |
496 | * Setup stream attributes if no stream updates are provided | |
497 | * there will be no impact on the stream parameters | |
498 | * | |
499 | * Set up surface attributes and associate to a stream | |
500 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
501 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
502 | * Any flip related attribute changes must be done through this interface. | |
503 | * | |
504 | * After this call: | |
505 | * Surfaces attributes are programmed and configured to be composed into stream. | |
506 | * This does not trigger a flip. No surface address is programmed. | |
507 | * | |
508 | */ | |
509 | ||
510 | void dc_update_surfaces_and_stream(struct dc *dc, | |
511 | struct dc_surface_update *surface_updates, int surface_count, | |
512 | const struct dc_stream *dc_stream, | |
513 | struct dc_stream_update *stream_update); | |
514 | ||
4562236b | 515 | /* |
ab2541b6 | 516 | * Log the current stream state. |
4562236b | 517 | */ |
ab2541b6 AC |
518 | void dc_stream_log( |
519 | const struct dc_stream *stream, | |
4562236b HW |
520 | struct dal_logger *dc_logger, |
521 | enum dc_log_type log_type); | |
522 | ||
ab2541b6 AC |
523 | uint8_t dc_get_current_stream_count(const struct dc *dc); |
524 | struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); | |
4562236b | 525 | |
ab2541b6 AC |
526 | /* |
527 | * Return the current frame counter. | |
528 | */ | |
529 | uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); | |
4562236b HW |
530 | |
531 | /* TODO: Return parsed values rather than direct register read | |
532 | * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) | |
533 | * being refactored properly to be dce-specific | |
534 | */ | |
81c50963 ST |
535 | bool dc_stream_get_scanoutpos(const struct dc_stream *stream, |
536 | uint32_t *v_blank_start, | |
537 | uint32_t *v_blank_end, | |
538 | uint32_t *h_position, | |
539 | uint32_t *v_position); | |
4562236b HW |
540 | |
541 | /* | |
ab2541b6 | 542 | * Structure to store surface/stream associations for validation |
4562236b HW |
543 | */ |
544 | struct dc_validation_set { | |
ab2541b6 | 545 | const struct dc_stream *stream; |
4562236b HW |
546 | const struct dc_surface *surfaces[MAX_SURFACES]; |
547 | uint8_t surface_count; | |
548 | }; | |
549 | ||
550 | /* | |
551 | * This function takes a set of resources and checks that they are cofunctional. | |
552 | * | |
553 | * After this call: | |
554 | * No hardware is programmed for call. Only validation is done. | |
555 | */ | |
07d72b39 HW |
556 | struct validate_context *dc_get_validate_context( |
557 | const struct dc *dc, | |
558 | const struct dc_validation_set set[], | |
559 | uint8_t set_count); | |
560 | ||
4562236b HW |
561 | bool dc_validate_resources( |
562 | const struct dc *dc, | |
563 | const struct dc_validation_set set[], | |
564 | uint8_t set_count); | |
565 | ||
566 | /* | |
ab2541b6 AC |
567 | * This function takes a stream and checks if it is guaranteed to be supported. |
568 | * Guaranteed means that MAX_COFUNC similar streams are supported. | |
4562236b HW |
569 | * |
570 | * After this call: | |
571 | * No hardware is programmed for call. Only validation is done. | |
572 | */ | |
573 | ||
574 | bool dc_validate_guaranteed( | |
575 | const struct dc *dc, | |
ab2541b6 | 576 | const struct dc_stream *stream); |
4562236b | 577 | |
8122a253 HW |
578 | void dc_resource_validate_ctx_copy_construct( |
579 | const struct validate_context *src_ctx, | |
580 | struct validate_context *dst_ctx); | |
581 | ||
582 | void dc_resource_validate_ctx_destruct(struct validate_context *context); | |
583 | ||
7cf2c840 HW |
584 | /* |
585 | * TODO update to make it about validation sets | |
586 | * Set up streams and links associated to drive sinks | |
587 | * The streams parameter is an absolute set of all active streams. | |
588 | * | |
589 | * After this call: | |
590 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
591 | * New streams are enabled with blank stream; no memory read. | |
592 | */ | |
e2c7bb12 | 593 | bool dc_commit_context(struct dc *dc, struct validate_context *context); |
7cf2c840 | 594 | |
4562236b | 595 | /* |
ab2541b6 AC |
596 | * Set up streams and links associated to drive sinks |
597 | * The streams parameter is an absolute set of all active streams. | |
4562236b HW |
598 | * |
599 | * After this call: | |
600 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
ab2541b6 | 601 | * New streams are enabled with blank stream; no memory read. |
4562236b | 602 | */ |
ab2541b6 | 603 | bool dc_commit_streams( |
4562236b | 604 | struct dc *dc, |
ab2541b6 AC |
605 | const struct dc_stream *streams[], |
606 | uint8_t stream_count); | |
9edba557 VP |
607 | /* |
608 | * Enable stereo when commit_streams is not required, | |
609 | * for example, frame alternate. | |
610 | */ | |
611 | bool dc_enable_stereo( | |
612 | struct dc *dc, | |
613 | struct validate_context *context, | |
614 | const struct dc_stream *streams[], | |
615 | uint8_t stream_count); | |
4562236b HW |
616 | |
617 | /** | |
618 | * Create a new default stream for the requested sink | |
619 | */ | |
620 | struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink); | |
621 | ||
622 | void dc_stream_retain(const struct dc_stream *dc_stream); | |
623 | void dc_stream_release(const struct dc_stream *dc_stream); | |
624 | ||
625 | struct dc_stream_status { | |
ab2541b6 AC |
626 | int primary_otg_inst; |
627 | int surface_count; | |
628 | const struct dc_surface *surfaces[MAX_SURFACE_NUM]; | |
629 | ||
4562236b HW |
630 | /* |
631 | * link this stream passes through | |
632 | */ | |
633 | const struct dc_link *link; | |
634 | }; | |
635 | ||
636 | const struct dc_stream_status *dc_stream_get_status( | |
637 | const struct dc_stream *dc_stream); | |
638 | ||
5869b0f6 LE |
639 | enum surface_update_type dc_check_update_surfaces_for_stream( |
640 | struct dc *dc, | |
641 | struct dc_surface_update *updates, | |
642 | int surface_count, | |
ee8f63e1 | 643 | struct dc_stream_update *stream_update, |
5869b0f6 LE |
644 | const struct dc_stream_status *stream_status); |
645 | ||
8a76708e AG |
646 | |
647 | void dc_retain_validate_context(struct validate_context *context); | |
648 | void dc_release_validate_context(struct validate_context *context); | |
649 | ||
4562236b HW |
650 | /******************************************************************************* |
651 | * Link Interfaces | |
652 | ******************************************************************************/ | |
653 | ||
654 | /* | |
655 | * A link contains one or more sinks and their connected status. | |
656 | * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. | |
657 | */ | |
658 | struct dc_link { | |
659 | const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; | |
660 | unsigned int sink_count; | |
661 | const struct dc_sink *local_sink; | |
662 | unsigned int link_index; | |
663 | enum dc_connection_type type; | |
664 | enum signal_type connector_signal; | |
665 | enum dc_irq_source irq_source_hpd; | |
666 | enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ | |
667 | /* caps is the same as reported_link_cap. link_traing use | |
668 | * reported_link_cap. Will clean up. TODO | |
669 | */ | |
670 | struct dc_link_settings reported_link_cap; | |
671 | struct dc_link_settings verified_link_cap; | |
672 | struct dc_link_settings max_link_setting; | |
673 | struct dc_link_settings cur_link_settings; | |
674 | struct dc_lane_settings cur_lane_setting; | |
675 | ||
676 | uint8_t ddc_hw_inst; | |
7a096334 ZF |
677 | |
678 | uint8_t hpd_src; | |
679 | ||
4562236b HW |
680 | uint8_t link_enc_hw_inst; |
681 | ||
4562236b HW |
682 | bool test_pattern_enabled; |
683 | union compliance_test_state compliance_test_state; | |
9fb8de78 AG |
684 | |
685 | void *priv; | |
46df790c AG |
686 | |
687 | struct ddc_service *ddc; | |
ebf055f9 AK |
688 | |
689 | bool aux_mode; | |
4562236b HW |
690 | }; |
691 | ||
692 | struct dpcd_caps { | |
693 | union dpcd_rev dpcd_rev; | |
694 | union max_lane_count max_ln_count; | |
695 | union max_down_spread max_down_spread; | |
696 | ||
697 | /* dongle type (DP converter, CV smart dongle) */ | |
698 | enum display_dongle_type dongle_type; | |
699 | /* Dongle's downstream count. */ | |
700 | union sink_count sink_count; | |
701 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, | |
702 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
03f5c686 | 703 | struct dc_dongle_caps dongle_caps; |
4562236b | 704 | |
4562236b HW |
705 | uint32_t sink_dev_id; |
706 | uint32_t branch_dev_id; | |
707 | int8_t branch_dev_name[6]; | |
708 | int8_t branch_hw_revision; | |
ebf055f9 AK |
709 | |
710 | bool allow_invalid_MSA_timing_param; | |
711 | bool panel_mode_edp; | |
4562236b HW |
712 | }; |
713 | ||
714 | struct dc_link_status { | |
715 | struct dpcd_caps *dpcd_caps; | |
716 | }; | |
717 | ||
718 | const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); | |
719 | ||
720 | /* | |
721 | * Return an enumerated dc_link. dc_link order is constant and determined at | |
722 | * boot time. They cannot be created or destroyed. | |
723 | * Use dc_get_caps() to get number of links. | |
724 | */ | |
725 | const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); | |
726 | ||
727 | /* Return id of physical connector represented by a dc_link at link_index.*/ | |
728 | const struct graphics_object_id dc_get_link_id_at_index( | |
729 | struct dc *dc, uint32_t link_index); | |
730 | ||
731 | /* Set backlight level of an embedded panel (eDP, LVDS). */ | |
732 | bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, | |
733 | uint32_t frame_ramp, const struct dc_stream *stream); | |
734 | ||
aa7397df AZ |
735 | bool dc_link_set_abm_disable(const struct dc_link *dc_link); |
736 | ||
4562236b HW |
737 | bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); |
738 | ||
7db4dede AZ |
739 | bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); |
740 | ||
4562236b | 741 | bool dc_link_setup_psr(const struct dc_link *dc_link, |
9f72f51d AZ |
742 | const struct dc_stream *stream, struct psr_config *psr_config, |
743 | struct psr_context *psr_context); | |
4562236b HW |
744 | |
745 | /* Request DC to detect if there is a Panel connected. | |
746 | * boot - If this call is during initial boot. | |
747 | * Return false for any type of detection failure or MST detection | |
748 | * true otherwise. True meaning further action is required (status update | |
749 | * and OS notification). | |
750 | */ | |
751 | bool dc_link_detect(const struct dc_link *dc_link, bool boot); | |
752 | ||
753 | /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). | |
754 | * Return: | |
755 | * true - Downstream port status changed. DM should call DC to do the | |
756 | * detection. | |
757 | * false - no change in Downstream port status. No further action required | |
758 | * from DM. */ | |
759 | bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link); | |
760 | ||
761 | struct dc_sink_init_data; | |
762 | ||
763 | struct dc_sink *dc_link_add_remote_sink( | |
764 | const struct dc_link *dc_link, | |
765 | const uint8_t *edid, | |
766 | int len, | |
767 | struct dc_sink_init_data *init_data); | |
768 | ||
769 | void dc_link_remove_remote_sink( | |
770 | const struct dc_link *link, | |
771 | const struct dc_sink *sink); | |
772 | ||
773 | /* Used by diagnostics for virtual link at the moment */ | |
774 | void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink); | |
775 | ||
776 | void dc_link_dp_set_drive_settings( | |
d27383a2 | 777 | const struct dc_link *link, |
4562236b HW |
778 | struct link_training_settings *lt_settings); |
779 | ||
820e3935 | 780 | enum link_training_result dc_link_dp_perform_link_training( |
4562236b HW |
781 | struct dc_link *link, |
782 | const struct dc_link_settings *link_setting, | |
783 | bool skip_video_pattern); | |
784 | ||
785 | void dc_link_dp_enable_hpd(const struct dc_link *link); | |
786 | ||
787 | void dc_link_dp_disable_hpd(const struct dc_link *link); | |
788 | ||
789 | bool dc_link_dp_set_test_pattern( | |
790 | const struct dc_link *link, | |
791 | enum dp_test_pattern test_pattern, | |
792 | const struct link_training_settings *p_link_settings, | |
793 | const unsigned char *p_custom_pattern, | |
794 | unsigned int cust_pattern_size); | |
795 | ||
796 | /******************************************************************************* | |
797 | * Sink Interfaces - A sink corresponds to a display output device | |
798 | ******************************************************************************/ | |
799 | ||
8c895313 | 800 | struct dc_container_id { |
801 | // 128bit GUID in binary form | |
802 | unsigned char guid[16]; | |
803 | // 8 byte port ID -> ELD.PortID | |
804 | unsigned int portId[2]; | |
805 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName | |
806 | unsigned short manufacturerName; | |
807 | // 2 byte product code -> ELD.ProductCode | |
808 | unsigned short productCode; | |
809 | }; | |
810 | ||
b6d6103b | 811 | |
9edba557 | 812 | |
4562236b HW |
813 | /* |
814 | * The sink structure contains EDID and other display device properties | |
815 | */ | |
816 | struct dc_sink { | |
817 | enum signal_type sink_signal; | |
818 | struct dc_edid dc_edid; /* raw edid */ | |
819 | struct dc_edid_caps edid_caps; /* parse display caps */ | |
8c895313 | 820 | struct dc_container_id *dc_container_id; |
4a9a5d62 | 821 | uint32_t dongle_max_pix_clk; |
5c4e9806 | 822 | void *priv; |
9edba557 | 823 | struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; |
ebf055f9 | 824 | bool converter_disable_audio; |
4562236b HW |
825 | }; |
826 | ||
827 | void dc_sink_retain(const struct dc_sink *sink); | |
828 | void dc_sink_release(const struct dc_sink *sink); | |
829 | ||
830 | const struct audio **dc_get_audios(struct dc *dc); | |
831 | ||
832 | struct dc_sink_init_data { | |
833 | enum signal_type sink_signal; | |
834 | const struct dc_link *link; | |
835 | uint32_t dongle_max_pix_clk; | |
836 | bool converter_disable_audio; | |
837 | }; | |
838 | ||
839 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); | |
8c895313 | 840 | bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id); |
841 | bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id); | |
4562236b HW |
842 | |
843 | /******************************************************************************* | |
ab2541b6 | 844 | * Cursor interfaces - To manages the cursor within a stream |
4562236b HW |
845 | ******************************************************************************/ |
846 | /* TODO: Deprecated once we switch to dc_set_cursor_position */ | |
ab2541b6 AC |
847 | bool dc_stream_set_cursor_attributes( |
848 | const struct dc_stream *stream, | |
4562236b HW |
849 | const struct dc_cursor_attributes *attributes); |
850 | ||
ab2541b6 AC |
851 | bool dc_stream_set_cursor_position( |
852 | const struct dc_stream *stream, | |
beb16b6a | 853 | const struct dc_cursor_position *position); |
4562236b HW |
854 | |
855 | /* Newer interfaces */ | |
856 | struct dc_cursor { | |
857 | struct dc_plane_address address; | |
858 | struct dc_cursor_attributes attributes; | |
859 | }; | |
860 | ||
4562236b HW |
861 | /******************************************************************************* |
862 | * Interrupt interfaces | |
863 | ******************************************************************************/ | |
864 | enum dc_irq_source dc_interrupt_to_irq_source( | |
865 | struct dc *dc, | |
866 | uint32_t src_id, | |
867 | uint32_t ext_id); | |
868 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); | |
869 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); | |
870 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
871 | struct dc *dc, uint32_t link_index); | |
872 | ||
873 | /******************************************************************************* | |
874 | * Power Interfaces | |
875 | ******************************************************************************/ | |
876 | ||
877 | void dc_set_power_state( | |
878 | struct dc *dc, | |
a3621485 | 879 | enum dc_acpi_cm_power_state power_state); |
4562236b HW |
880 | void dc_resume(const struct dc *dc); |
881 | ||
4562236b HW |
882 | /* |
883 | * DPCD access interfaces | |
884 | */ | |
885 | ||
7c7f5b15 | 886 | bool dc_read_aux_dpcd( |
4562236b HW |
887 | struct dc *dc, |
888 | uint32_t link_index, | |
889 | uint32_t address, | |
890 | uint8_t *data, | |
891 | uint32_t size); | |
892 | ||
7c7f5b15 | 893 | bool dc_write_aux_dpcd( |
4562236b HW |
894 | struct dc *dc, |
895 | uint32_t link_index, | |
896 | uint32_t address, | |
897 | const uint8_t *data, | |
2b230ea3 ZF |
898 | uint32_t size); |
899 | ||
7c7f5b15 AG |
900 | bool dc_read_aux_i2c( |
901 | struct dc *dc, | |
902 | uint32_t link_index, | |
903 | enum i2c_mot_mode mot, | |
904 | uint32_t address, | |
905 | uint8_t *data, | |
906 | uint32_t size); | |
907 | ||
908 | bool dc_write_aux_i2c( | |
909 | struct dc *dc, | |
910 | uint32_t link_index, | |
911 | enum i2c_mot_mode mot, | |
912 | uint32_t address, | |
913 | const uint8_t *data, | |
914 | uint32_t size); | |
915 | ||
2b230ea3 ZF |
916 | bool dc_query_ddc_data( |
917 | struct dc *dc, | |
918 | uint32_t link_index, | |
919 | uint32_t address, | |
920 | uint8_t *write_buf, | |
921 | uint32_t write_size, | |
922 | uint8_t *read_buf, | |
923 | uint32_t read_size); | |
4562236b HW |
924 | |
925 | bool dc_submit_i2c( | |
926 | struct dc *dc, | |
927 | uint32_t link_index, | |
928 | struct i2c_command *cmd); | |
929 | ||
5e7773a2 | 930 | |
4562236b | 931 | #endif /* DC_INTERFACE_H_ */ |