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4562236b HW |
1 | /* |
2 | * Copyright 2012-14 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef DC_INTERFACE_H_ | |
27 | #define DC_INTERFACE_H_ | |
28 | ||
29 | #include "dc_types.h" | |
4562236b HW |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" | |
32 | #include "gpio_types.h" | |
33 | #include "link_service_types.h" | |
34 | ||
091a97e5 | 35 | #define MAX_SURFACES 3 |
ab2541b6 | 36 | #define MAX_STREAMS 6 |
4562236b HW |
37 | #define MAX_SINKS_PER_LINK 4 |
38 | ||
39 | /******************************************************************************* | |
40 | * Display Core Interfaces | |
41 | ******************************************************************************/ | |
42 | ||
43 | struct dc_caps { | |
ab2541b6 | 44 | uint32_t max_streams; |
4562236b HW |
45 | uint32_t max_links; |
46 | uint32_t max_audios; | |
47 | uint32_t max_slave_planes; | |
d4e13b0d | 48 | uint32_t max_surfaces; |
4562236b HW |
49 | uint32_t max_downscale_ratio; |
50 | uint32_t i2c_speed_in_khz; | |
a37656b9 TC |
51 | |
52 | unsigned int max_cursor_size; | |
4562236b HW |
53 | }; |
54 | ||
55 | ||
56 | struct dc_dcc_surface_param { | |
57 | enum surface_pixel_format format; | |
58 | struct dc_size surface_size; | |
2c8ad2d5 | 59 | enum swizzle_mode_values swizzle_mode; |
4562236b HW |
60 | enum dc_scan_direction scan; |
61 | }; | |
62 | ||
63 | struct dc_dcc_setting { | |
64 | unsigned int max_compressed_blk_size; | |
65 | unsigned int max_uncompressed_blk_size; | |
66 | bool independent_64b_blks; | |
67 | }; | |
68 | ||
69 | struct dc_surface_dcc_cap { | |
70 | bool capable; | |
71 | bool const_color_support; | |
72 | ||
73 | union { | |
74 | struct { | |
75 | struct dc_dcc_setting rgb; | |
76 | } grph; | |
77 | ||
78 | struct { | |
79 | struct dc_dcc_setting luma; | |
80 | struct dc_dcc_setting chroma; | |
81 | } video; | |
82 | }; | |
83 | }; | |
84 | ||
94267b3d ST |
85 | struct dc_static_screen_events { |
86 | bool cursor_update; | |
87 | bool surface_update; | |
88 | bool overlay_update; | |
89 | }; | |
90 | ||
4562236b HW |
91 | /* Forward declaration*/ |
92 | struct dc; | |
93 | struct dc_surface; | |
94 | struct validate_context; | |
95 | ||
96 | struct dc_cap_funcs { | |
ff5ef992 AD |
97 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
98 | bool (*get_dcc_compression_cap)(const struct dc *dc, | |
99 | const struct dc_dcc_surface_param *input, | |
100 | struct dc_surface_dcc_cap *output); | |
101 | #else | |
4562236b | 102 | int i; |
ff5ef992 | 103 | #endif |
4562236b HW |
104 | }; |
105 | ||
106 | struct dc_stream_funcs { | |
107 | bool (*adjust_vmin_vmax)(struct dc *dc, | |
108 | const struct dc_stream **stream, | |
109 | int num_streams, | |
110 | int vmin, | |
111 | int vmax); | |
72ada5f7 EC |
112 | bool (*get_crtc_position)(struct dc *dc, |
113 | const struct dc_stream **stream, | |
114 | int num_streams, | |
115 | unsigned int *v_pos, | |
116 | unsigned int *nom_v_pos); | |
117 | ||
4562236b | 118 | bool (*set_gamut_remap)(struct dc *dc, |
f46661dd | 119 | const struct dc_stream *stream); |
94267b3d ST |
120 | |
121 | void (*set_static_screen_events)(struct dc *dc, | |
122 | const struct dc_stream **stream, | |
123 | int num_streams, | |
124 | const struct dc_static_screen_events *events); | |
529cad0f DW |
125 | |
126 | void (*set_dither_option)(const struct dc_stream *stream, | |
127 | enum dc_dither_option option); | |
4562236b HW |
128 | }; |
129 | ||
130 | struct link_training_settings; | |
131 | ||
132 | struct dc_link_funcs { | |
133 | void (*set_drive_settings)(struct dc *dc, | |
bf5cda33 HW |
134 | struct link_training_settings *lt_settings, |
135 | const struct dc_link *link); | |
4562236b HW |
136 | void (*perform_link_training)(struct dc *dc, |
137 | struct dc_link_settings *link_setting, | |
138 | bool skip_video_pattern); | |
139 | void (*set_preferred_link_settings)(struct dc *dc, | |
88639168 ZF |
140 | struct dc_link_settings *link_setting, |
141 | const struct dc_link *link); | |
4562236b HW |
142 | void (*enable_hpd)(const struct dc_link *link); |
143 | void (*disable_hpd)(const struct dc_link *link); | |
144 | void (*set_test_pattern)( | |
145 | const struct dc_link *link, | |
146 | enum dp_test_pattern test_pattern, | |
147 | const struct link_training_settings *p_link_settings, | |
148 | const unsigned char *p_custom_pattern, | |
149 | unsigned int cust_pattern_size); | |
150 | }; | |
151 | ||
152 | /* Structure to hold configuration flags set by dm at dc creation. */ | |
153 | struct dc_config { | |
154 | bool gpu_vm_support; | |
155 | bool disable_disp_pll_sharing; | |
156 | }; | |
157 | ||
158 | struct dc_debug { | |
159 | bool surface_visual_confirm; | |
160 | bool max_disp_clk; | |
4562236b | 161 | bool surface_trace; |
9474980a | 162 | bool timing_trace; |
4562236b HW |
163 | bool validation_trace; |
164 | bool disable_stutter; | |
165 | bool disable_dcc; | |
166 | bool disable_dfs_bypass; | |
ff5ef992 AD |
167 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
168 | bool disable_dpp_power_gate; | |
169 | bool disable_hubp_power_gate; | |
170 | bool disable_pplib_wm_range; | |
171 | bool use_dml_wm; | |
172 | bool use_max_voltage; | |
173 | int sr_exit_time_ns; | |
174 | int sr_enter_plus_exit_time_ns; | |
175 | int urgent_latency_ns; | |
176 | int percent_of_ideal_drambw; | |
177 | int dram_clock_change_latency_ns; | |
e73b59b7 | 178 | int always_scale; |
ff5ef992 | 179 | #endif |
2c8ad2d5 | 180 | bool disable_pplib_clock_request; |
4562236b | 181 | bool disable_clock_gate; |
aa66df58 | 182 | bool disable_dmcu; |
29eba8e8 | 183 | bool disable_psr; |
70814f6f | 184 | bool force_abm_enable; |
4562236b HW |
185 | }; |
186 | ||
187 | struct dc { | |
188 | struct dc_caps caps; | |
189 | struct dc_cap_funcs cap_funcs; | |
190 | struct dc_stream_funcs stream_funcs; | |
191 | struct dc_link_funcs link_funcs; | |
192 | struct dc_config config; | |
193 | struct dc_debug debug; | |
194 | }; | |
195 | ||
2c8ad2d5 AD |
196 | enum frame_buffer_mode { |
197 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, | |
198 | FRAME_BUFFER_MODE_ZFB_ONLY, | |
199 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, | |
200 | } ; | |
201 | ||
202 | struct dchub_init_data { | |
203 | bool dchub_initialzied; | |
204 | bool dchub_info_valid; | |
205 | int64_t zfb_phys_addr_base; | |
206 | int64_t zfb_mc_base_addr; | |
207 | uint64_t zfb_size_in_byte; | |
208 | enum frame_buffer_mode fb_mode; | |
209 | }; | |
2c8ad2d5 | 210 | |
4562236b HW |
211 | struct dc_init_data { |
212 | struct hw_asic_id asic_id; | |
213 | void *driver; /* ctx */ | |
214 | struct cgs_device *cgs_device; | |
215 | ||
216 | int num_virtual_links; | |
217 | /* | |
218 | * If 'vbios_override' not NULL, it will be called instead | |
219 | * of the real VBIOS. Intended use is Diagnostics on FPGA. | |
220 | */ | |
221 | struct dc_bios *vbios_override; | |
222 | enum dce_environment dce_environment; | |
223 | ||
224 | struct dc_config flags; | |
225 | }; | |
226 | ||
227 | struct dc *dc_create(const struct dc_init_data *init_params); | |
228 | ||
229 | void dc_destroy(struct dc **dc); | |
230 | ||
2c8ad2d5 | 231 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); |
2c8ad2d5 | 232 | |
4562236b HW |
233 | /******************************************************************************* |
234 | * Surface Interfaces | |
235 | ******************************************************************************/ | |
236 | ||
237 | enum { | |
fb735a9f | 238 | TRANSFER_FUNC_POINTS = 1025 |
4562236b HW |
239 | }; |
240 | ||
1646a6fe | 241 | struct dc_hdr_static_metadata { |
70063a59 | 242 | bool hdr_supported; |
1646a6fe AW |
243 | bool is_hdr; |
244 | ||
245 | /* display chromaticities and white point in units of 0.00001 */ | |
246 | unsigned int chromaticity_green_x; | |
247 | unsigned int chromaticity_green_y; | |
248 | unsigned int chromaticity_blue_x; | |
249 | unsigned int chromaticity_blue_y; | |
250 | unsigned int chromaticity_red_x; | |
251 | unsigned int chromaticity_red_y; | |
252 | unsigned int chromaticity_white_point_x; | |
253 | unsigned int chromaticity_white_point_y; | |
254 | ||
255 | uint32_t min_luminance; | |
256 | uint32_t max_luminance; | |
257 | uint32_t maximum_content_light_level; | |
258 | uint32_t maximum_frame_average_light_level; | |
259 | }; | |
260 | ||
fb735a9f AK |
261 | enum dc_transfer_func_type { |
262 | TF_TYPE_PREDEFINED, | |
263 | TF_TYPE_DISTRIBUTED_POINTS, | |
f46661dd AZ |
264 | TF_TYPE_BYPASS, |
265 | TF_TYPE_UNKNOWN | |
fb735a9f AK |
266 | }; |
267 | ||
268 | struct dc_transfer_func_distributed_points { | |
fcd2f4bf AZ |
269 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
270 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; | |
271 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; | |
272 | ||
fb735a9f | 273 | uint16_t end_exponent; |
fcd2f4bf AZ |
274 | uint16_t x_point_at_y1_red; |
275 | uint16_t x_point_at_y1_green; | |
276 | uint16_t x_point_at_y1_blue; | |
fb735a9f AK |
277 | }; |
278 | ||
279 | enum dc_transfer_func_predefined { | |
280 | TRANSFER_FUNCTION_SRGB, | |
281 | TRANSFER_FUNCTION_BT709, | |
90e508ba | 282 | TRANSFER_FUNCTION_PQ, |
fb735a9f AK |
283 | TRANSFER_FUNCTION_LINEAR, |
284 | }; | |
285 | ||
286 | struct dc_transfer_func { | |
287 | enum dc_transfer_func_type type; | |
288 | enum dc_transfer_func_predefined tf; | |
289 | struct dc_transfer_func_distributed_points tf_pts; | |
290 | }; | |
291 | ||
4562236b | 292 | struct dc_surface { |
ba326a91 | 293 | bool per_pixel_alpha; |
4562236b HW |
294 | bool visible; |
295 | bool flip_immediate; | |
296 | struct dc_plane_address address; | |
297 | ||
298 | struct scaling_taps scaling_quality; | |
299 | struct rect src_rect; | |
300 | struct rect dst_rect; | |
301 | struct rect clip_rect; | |
302 | ||
303 | union plane_size plane_size; | |
304 | union dc_tiling_info tiling_info; | |
305 | struct dc_plane_dcc_param dcc; | |
306 | enum dc_color_space color_space; | |
307 | ||
308 | enum surface_pixel_format format; | |
309 | enum dc_rotation_angle rotation; | |
310 | bool horizontal_mirror; | |
311 | enum plane_stereo_format stereo_format; | |
312 | ||
1646a6fe AW |
313 | struct dc_hdr_static_metadata hdr_static_ctx; |
314 | ||
4562236b | 315 | const struct dc_gamma *gamma_correction; |
fb735a9f | 316 | const struct dc_transfer_func *in_transfer_func; |
4562236b HW |
317 | }; |
318 | ||
319 | struct dc_plane_info { | |
ba326a91 | 320 | bool per_pixel_alpha; |
4562236b HW |
321 | union plane_size plane_size; |
322 | union dc_tiling_info tiling_info; | |
9cd09bfe | 323 | struct dc_plane_dcc_param dcc; |
4562236b HW |
324 | enum surface_pixel_format format; |
325 | enum dc_rotation_angle rotation; | |
326 | bool horizontal_mirror; | |
327 | enum plane_stereo_format stereo_format; | |
328 | enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ | |
329 | bool visible; | |
330 | }; | |
331 | ||
332 | struct dc_scaling_info { | |
333 | struct rect src_rect; | |
334 | struct rect dst_rect; | |
335 | struct rect clip_rect; | |
336 | struct scaling_taps scaling_quality; | |
337 | }; | |
338 | ||
339 | struct dc_surface_update { | |
340 | const struct dc_surface *surface; | |
341 | ||
342 | /* isr safe update parameters. null means no updates */ | |
343 | struct dc_flip_addrs *flip_addr; | |
344 | struct dc_plane_info *plane_info; | |
345 | struct dc_scaling_info *scaling_info; | |
346 | /* following updates require alloc/sleep/spin that is not isr safe, | |
347 | * null means no updates | |
348 | */ | |
fb735a9f | 349 | /* gamma TO BE REMOVED */ |
4562236b | 350 | struct dc_gamma *gamma; |
fb735a9f | 351 | struct dc_transfer_func *in_transfer_func; |
f46661dd | 352 | struct dc_hdr_static_metadata *hdr_static_metadata; |
4562236b HW |
353 | }; |
354 | /* | |
355 | * This structure is filled in by dc_surface_get_status and contains | |
356 | * the last requested address and the currently active address so the called | |
357 | * can determine if there are any outstanding flips | |
358 | */ | |
359 | struct dc_surface_status { | |
360 | struct dc_plane_address requested_address; | |
361 | struct dc_plane_address current_address; | |
362 | bool is_flip_pending; | |
363 | }; | |
364 | ||
365 | /* | |
366 | * Create a new surface with default parameters; | |
367 | */ | |
368 | struct dc_surface *dc_create_surface(const struct dc *dc); | |
369 | const struct dc_surface_status *dc_surface_get_status( | |
370 | const struct dc_surface *dc_surface); | |
371 | ||
372 | void dc_surface_retain(const struct dc_surface *dc_surface); | |
373 | void dc_surface_release(const struct dc_surface *dc_surface); | |
374 | ||
89e89630 | 375 | void dc_gamma_retain(const struct dc_gamma *dc_gamma); |
aff20230 | 376 | void dc_gamma_release(const struct dc_gamma **dc_gamma); |
4562236b HW |
377 | struct dc_gamma *dc_create_gamma(void); |
378 | ||
fb735a9f AK |
379 | void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf); |
380 | void dc_transfer_func_release(const struct dc_transfer_func *dc_tf); | |
90e508ba | 381 | struct dc_transfer_func *dc_create_transfer_func(void); |
fb735a9f | 382 | |
4562236b HW |
383 | /* |
384 | * This structure holds a surface address. There could be multiple addresses | |
385 | * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such | |
386 | * as frame durations and DCC format can also be set. | |
387 | */ | |
388 | struct dc_flip_addrs { | |
389 | struct dc_plane_address address; | |
390 | bool flip_immediate; | |
4562236b HW |
391 | /* TODO: add flip duration for FreeSync */ |
392 | }; | |
393 | ||
4562236b | 394 | /* |
ab2541b6 AC |
395 | * Set up surface attributes and associate to a stream |
396 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
397 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
4562236b HW |
398 | * Any flip related attribute changes must be done through this interface. |
399 | * | |
400 | * After this call: | |
ab2541b6 | 401 | * Surfaces attributes are programmed and configured to be composed into stream. |
4562236b HW |
402 | * This does not trigger a flip. No surface address is programmed. |
403 | */ | |
404 | ||
ab2541b6 | 405 | bool dc_commit_surfaces_to_stream( |
4562236b HW |
406 | struct dc *dc, |
407 | const struct dc_surface **dc_surfaces, | |
408 | uint8_t surface_count, | |
ab2541b6 | 409 | const struct dc_stream *stream); |
4562236b | 410 | |
ab2541b6 | 411 | bool dc_pre_update_surfaces_to_stream( |
4562236b HW |
412 | struct dc *dc, |
413 | const struct dc_surface *const *new_surfaces, | |
414 | uint8_t new_surface_count, | |
ab2541b6 | 415 | const struct dc_stream *stream); |
4562236b | 416 | |
ab2541b6 | 417 | bool dc_post_update_surfaces_to_stream( |
4562236b HW |
418 | struct dc *dc); |
419 | ||
ab2541b6 AC |
420 | void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, |
421 | int surface_count, const struct dc_stream *stream); | |
4562236b | 422 | |
81e2b2de DL |
423 | /* Surface update type is used by dc_update_surfaces_and_stream |
424 | * The update type is determined at the very beginning of the function based | |
425 | * on parameters passed in and decides how much programming (or updating) is | |
426 | * going to be done during the call. | |
427 | * | |
428 | * UPDATE_TYPE_FAST is used for really fast updates that do not require much | |
429 | * logical calculations or hardware register programming. This update MUST be | |
430 | * ISR safe on windows. Currently fast update will only be used to flip surface | |
431 | * address. | |
432 | * | |
433 | * UPDATE_TYPE_MED is used for slower updates which require significant hw | |
434 | * re-programming however do not affect bandwidth consumption or clock | |
435 | * requirements. At present, this is the level at which front end updates | |
436 | * that do not require us to run bw_calcs happen. These are in/out transfer func | |
437 | * updates, viewport offset changes, recout size changes and pixel depth changes. | |
438 | * This update can be done at ISR, but we want to minimize how often this happens. | |
439 | * | |
440 | * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our | |
441 | * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front | |
442 | * end related. Any time viewport dimensions, recout dimensions, scaling ratios or | |
443 | * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do | |
444 | * a full update. This cannot be done at ISR level and should be a rare event. | |
445 | * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting | |
446 | * underscan we don't expect to see this call at all. | |
447 | */ | |
448 | ||
5869b0f6 LE |
449 | enum surface_update_type { |
450 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ | |
81e2b2de | 451 | UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ |
5869b0f6 LE |
452 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ |
453 | }; | |
454 | ||
4562236b | 455 | /******************************************************************************* |
ab2541b6 | 456 | * Stream Interfaces |
4562236b | 457 | ******************************************************************************/ |
ab2541b6 AC |
458 | struct dc_stream { |
459 | const struct dc_sink *sink; | |
460 | struct dc_crtc_timing timing; | |
8b32076c | 461 | enum signal_type output_signal; |
4562236b | 462 | |
ab2541b6 | 463 | enum dc_color_space output_color_space; |
b92033b6 | 464 | enum dc_dither_option dither_option; |
4562236b | 465 | |
ab2541b6 AC |
466 | struct rect src; /* composition area */ |
467 | struct rect dst; /* stream addressable area */ | |
4562236b | 468 | |
ab2541b6 AC |
469 | struct audio_info audio_info; |
470 | ||
471 | bool ignore_msa_timing_param; | |
472 | ||
473 | struct freesync_context freesync_ctx; | |
474 | ||
475 | const struct dc_transfer_func *out_transfer_func; | |
476 | struct colorspace_transform gamut_remap_matrix; | |
477 | struct csc_transform csc_color_matrix; | |
478 | ||
ab2541b6 AC |
479 | /* TODO: custom INFO packets */ |
480 | /* TODO: ABM info (DMCU) */ | |
481 | /* TODO: PSR info */ | |
482 | /* TODO: CEA VIC */ | |
483 | }; | |
4562236b | 484 | |
a783e7b5 | 485 | struct dc_stream_update { |
a783e7b5 | 486 | struct rect src; |
a783e7b5 | 487 | struct rect dst; |
f46661dd | 488 | struct dc_transfer_func *out_transfer_func; |
a783e7b5 LE |
489 | }; |
490 | ||
491 | ||
492 | /* | |
493 | * Setup stream attributes if no stream updates are provided | |
494 | * there will be no impact on the stream parameters | |
495 | * | |
496 | * Set up surface attributes and associate to a stream | |
497 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
498 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
499 | * Any flip related attribute changes must be done through this interface. | |
500 | * | |
501 | * After this call: | |
502 | * Surfaces attributes are programmed and configured to be composed into stream. | |
503 | * This does not trigger a flip. No surface address is programmed. | |
504 | * | |
505 | */ | |
506 | ||
507 | void dc_update_surfaces_and_stream(struct dc *dc, | |
508 | struct dc_surface_update *surface_updates, int surface_count, | |
509 | const struct dc_stream *dc_stream, | |
510 | struct dc_stream_update *stream_update); | |
511 | ||
4562236b | 512 | /* |
ab2541b6 | 513 | * Log the current stream state. |
4562236b | 514 | */ |
ab2541b6 AC |
515 | void dc_stream_log( |
516 | const struct dc_stream *stream, | |
4562236b HW |
517 | struct dal_logger *dc_logger, |
518 | enum dc_log_type log_type); | |
519 | ||
ab2541b6 AC |
520 | uint8_t dc_get_current_stream_count(const struct dc *dc); |
521 | struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); | |
4562236b | 522 | |
ab2541b6 AC |
523 | /* |
524 | * Return the current frame counter. | |
525 | */ | |
526 | uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); | |
4562236b HW |
527 | |
528 | /* TODO: Return parsed values rather than direct register read | |
529 | * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) | |
530 | * being refactored properly to be dce-specific | |
531 | */ | |
81c50963 ST |
532 | bool dc_stream_get_scanoutpos(const struct dc_stream *stream, |
533 | uint32_t *v_blank_start, | |
534 | uint32_t *v_blank_end, | |
535 | uint32_t *h_position, | |
536 | uint32_t *v_position); | |
4562236b HW |
537 | |
538 | /* | |
ab2541b6 | 539 | * Structure to store surface/stream associations for validation |
4562236b HW |
540 | */ |
541 | struct dc_validation_set { | |
ab2541b6 | 542 | const struct dc_stream *stream; |
4562236b HW |
543 | const struct dc_surface *surfaces[MAX_SURFACES]; |
544 | uint8_t surface_count; | |
545 | }; | |
546 | ||
547 | /* | |
548 | * This function takes a set of resources and checks that they are cofunctional. | |
549 | * | |
550 | * After this call: | |
551 | * No hardware is programmed for call. Only validation is done. | |
552 | */ | |
07d72b39 HW |
553 | struct validate_context *dc_get_validate_context( |
554 | const struct dc *dc, | |
555 | const struct dc_validation_set set[], | |
556 | uint8_t set_count); | |
557 | ||
4562236b HW |
558 | bool dc_validate_resources( |
559 | const struct dc *dc, | |
560 | const struct dc_validation_set set[], | |
561 | uint8_t set_count); | |
562 | ||
563 | /* | |
ab2541b6 AC |
564 | * This function takes a stream and checks if it is guaranteed to be supported. |
565 | * Guaranteed means that MAX_COFUNC similar streams are supported. | |
4562236b HW |
566 | * |
567 | * After this call: | |
568 | * No hardware is programmed for call. Only validation is done. | |
569 | */ | |
570 | ||
571 | bool dc_validate_guaranteed( | |
572 | const struct dc *dc, | |
ab2541b6 | 573 | const struct dc_stream *stream); |
4562236b | 574 | |
8122a253 HW |
575 | void dc_resource_validate_ctx_copy_construct( |
576 | const struct validate_context *src_ctx, | |
577 | struct validate_context *dst_ctx); | |
578 | ||
579 | void dc_resource_validate_ctx_destruct(struct validate_context *context); | |
580 | ||
4562236b | 581 | /* |
ab2541b6 AC |
582 | * Set up streams and links associated to drive sinks |
583 | * The streams parameter is an absolute set of all active streams. | |
4562236b HW |
584 | * |
585 | * After this call: | |
586 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
ab2541b6 | 587 | * New streams are enabled with blank stream; no memory read. |
4562236b | 588 | */ |
ab2541b6 | 589 | bool dc_commit_streams( |
4562236b | 590 | struct dc *dc, |
ab2541b6 AC |
591 | const struct dc_stream *streams[], |
592 | uint8_t stream_count); | |
4562236b HW |
593 | |
594 | /** | |
595 | * Create a new default stream for the requested sink | |
596 | */ | |
597 | struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink); | |
598 | ||
599 | void dc_stream_retain(const struct dc_stream *dc_stream); | |
600 | void dc_stream_release(const struct dc_stream *dc_stream); | |
601 | ||
602 | struct dc_stream_status { | |
ab2541b6 AC |
603 | int primary_otg_inst; |
604 | int surface_count; | |
605 | const struct dc_surface *surfaces[MAX_SURFACE_NUM]; | |
606 | ||
4562236b HW |
607 | /* |
608 | * link this stream passes through | |
609 | */ | |
610 | const struct dc_link *link; | |
611 | }; | |
612 | ||
613 | const struct dc_stream_status *dc_stream_get_status( | |
614 | const struct dc_stream *dc_stream); | |
615 | ||
5869b0f6 LE |
616 | enum surface_update_type dc_check_update_surfaces_for_stream( |
617 | struct dc *dc, | |
618 | struct dc_surface_update *updates, | |
619 | int surface_count, | |
ee8f63e1 | 620 | struct dc_stream_update *stream_update, |
5869b0f6 LE |
621 | const struct dc_stream_status *stream_status); |
622 | ||
4562236b HW |
623 | /******************************************************************************* |
624 | * Link Interfaces | |
625 | ******************************************************************************/ | |
626 | ||
627 | /* | |
628 | * A link contains one or more sinks and their connected status. | |
629 | * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. | |
630 | */ | |
631 | struct dc_link { | |
632 | const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; | |
633 | unsigned int sink_count; | |
634 | const struct dc_sink *local_sink; | |
635 | unsigned int link_index; | |
636 | enum dc_connection_type type; | |
637 | enum signal_type connector_signal; | |
638 | enum dc_irq_source irq_source_hpd; | |
639 | enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ | |
640 | /* caps is the same as reported_link_cap. link_traing use | |
641 | * reported_link_cap. Will clean up. TODO | |
642 | */ | |
643 | struct dc_link_settings reported_link_cap; | |
644 | struct dc_link_settings verified_link_cap; | |
645 | struct dc_link_settings max_link_setting; | |
646 | struct dc_link_settings cur_link_settings; | |
647 | struct dc_lane_settings cur_lane_setting; | |
648 | ||
649 | uint8_t ddc_hw_inst; | |
650 | uint8_t link_enc_hw_inst; | |
651 | ||
4562236b HW |
652 | bool test_pattern_enabled; |
653 | union compliance_test_state compliance_test_state; | |
9fb8de78 AG |
654 | |
655 | void *priv; | |
7c7f5b15 | 656 | bool aux_mode; |
46df790c AG |
657 | |
658 | struct ddc_service *ddc; | |
4562236b HW |
659 | }; |
660 | ||
661 | struct dpcd_caps { | |
662 | union dpcd_rev dpcd_rev; | |
663 | union max_lane_count max_ln_count; | |
664 | union max_down_spread max_down_spread; | |
665 | ||
666 | /* dongle type (DP converter, CV smart dongle) */ | |
667 | enum display_dongle_type dongle_type; | |
668 | /* Dongle's downstream count. */ | |
669 | union sink_count sink_count; | |
670 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, | |
671 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
03f5c686 | 672 | struct dc_dongle_caps dongle_caps; |
4562236b HW |
673 | |
674 | bool allow_invalid_MSA_timing_param; | |
675 | bool panel_mode_edp; | |
676 | uint32_t sink_dev_id; | |
677 | uint32_t branch_dev_id; | |
678 | int8_t branch_dev_name[6]; | |
679 | int8_t branch_hw_revision; | |
680 | }; | |
681 | ||
682 | struct dc_link_status { | |
683 | struct dpcd_caps *dpcd_caps; | |
684 | }; | |
685 | ||
686 | const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); | |
687 | ||
688 | /* | |
689 | * Return an enumerated dc_link. dc_link order is constant and determined at | |
690 | * boot time. They cannot be created or destroyed. | |
691 | * Use dc_get_caps() to get number of links. | |
692 | */ | |
693 | const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); | |
694 | ||
695 | /* Return id of physical connector represented by a dc_link at link_index.*/ | |
696 | const struct graphics_object_id dc_get_link_id_at_index( | |
697 | struct dc *dc, uint32_t link_index); | |
698 | ||
699 | /* Set backlight level of an embedded panel (eDP, LVDS). */ | |
700 | bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, | |
701 | uint32_t frame_ramp, const struct dc_stream *stream); | |
702 | ||
aa7397df AZ |
703 | bool dc_link_set_abm_disable(const struct dc_link *dc_link); |
704 | ||
4562236b HW |
705 | bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); |
706 | ||
7db4dede AZ |
707 | bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); |
708 | ||
4562236b | 709 | bool dc_link_setup_psr(const struct dc_link *dc_link, |
9f72f51d AZ |
710 | const struct dc_stream *stream, struct psr_config *psr_config, |
711 | struct psr_context *psr_context); | |
4562236b HW |
712 | |
713 | /* Request DC to detect if there is a Panel connected. | |
714 | * boot - If this call is during initial boot. | |
715 | * Return false for any type of detection failure or MST detection | |
716 | * true otherwise. True meaning further action is required (status update | |
717 | * and OS notification). | |
718 | */ | |
719 | bool dc_link_detect(const struct dc_link *dc_link, bool boot); | |
720 | ||
721 | /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). | |
722 | * Return: | |
723 | * true - Downstream port status changed. DM should call DC to do the | |
724 | * detection. | |
725 | * false - no change in Downstream port status. No further action required | |
726 | * from DM. */ | |
727 | bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link); | |
728 | ||
729 | struct dc_sink_init_data; | |
730 | ||
731 | struct dc_sink *dc_link_add_remote_sink( | |
732 | const struct dc_link *dc_link, | |
733 | const uint8_t *edid, | |
734 | int len, | |
735 | struct dc_sink_init_data *init_data); | |
736 | ||
737 | void dc_link_remove_remote_sink( | |
738 | const struct dc_link *link, | |
739 | const struct dc_sink *sink); | |
740 | ||
741 | /* Used by diagnostics for virtual link at the moment */ | |
742 | void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink); | |
743 | ||
744 | void dc_link_dp_set_drive_settings( | |
d27383a2 | 745 | const struct dc_link *link, |
4562236b HW |
746 | struct link_training_settings *lt_settings); |
747 | ||
748 | bool dc_link_dp_perform_link_training( | |
749 | struct dc_link *link, | |
750 | const struct dc_link_settings *link_setting, | |
751 | bool skip_video_pattern); | |
752 | ||
753 | void dc_link_dp_enable_hpd(const struct dc_link *link); | |
754 | ||
755 | void dc_link_dp_disable_hpd(const struct dc_link *link); | |
756 | ||
757 | bool dc_link_dp_set_test_pattern( | |
758 | const struct dc_link *link, | |
759 | enum dp_test_pattern test_pattern, | |
760 | const struct link_training_settings *p_link_settings, | |
761 | const unsigned char *p_custom_pattern, | |
762 | unsigned int cust_pattern_size); | |
763 | ||
764 | /******************************************************************************* | |
765 | * Sink Interfaces - A sink corresponds to a display output device | |
766 | ******************************************************************************/ | |
767 | ||
8c895313 | 768 | struct dc_container_id { |
769 | // 128bit GUID in binary form | |
770 | unsigned char guid[16]; | |
771 | // 8 byte port ID -> ELD.PortID | |
772 | unsigned int portId[2]; | |
773 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName | |
774 | unsigned short manufacturerName; | |
775 | // 2 byte product code -> ELD.ProductCode | |
776 | unsigned short productCode; | |
777 | }; | |
778 | ||
4562236b HW |
779 | /* |
780 | * The sink structure contains EDID and other display device properties | |
781 | */ | |
782 | struct dc_sink { | |
783 | enum signal_type sink_signal; | |
784 | struct dc_edid dc_edid; /* raw edid */ | |
785 | struct dc_edid_caps edid_caps; /* parse display caps */ | |
8c895313 | 786 | struct dc_container_id *dc_container_id; |
4a9a5d62 ZF |
787 | uint32_t dongle_max_pix_clk; |
788 | bool converter_disable_audio; | |
5c4e9806 | 789 | void *priv; |
4562236b HW |
790 | }; |
791 | ||
792 | void dc_sink_retain(const struct dc_sink *sink); | |
793 | void dc_sink_release(const struct dc_sink *sink); | |
794 | ||
795 | const struct audio **dc_get_audios(struct dc *dc); | |
796 | ||
797 | struct dc_sink_init_data { | |
798 | enum signal_type sink_signal; | |
799 | const struct dc_link *link; | |
800 | uint32_t dongle_max_pix_clk; | |
801 | bool converter_disable_audio; | |
802 | }; | |
803 | ||
804 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); | |
8c895313 | 805 | bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id); |
806 | bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id); | |
4562236b HW |
807 | |
808 | /******************************************************************************* | |
ab2541b6 | 809 | * Cursor interfaces - To manages the cursor within a stream |
4562236b HW |
810 | ******************************************************************************/ |
811 | /* TODO: Deprecated once we switch to dc_set_cursor_position */ | |
ab2541b6 AC |
812 | bool dc_stream_set_cursor_attributes( |
813 | const struct dc_stream *stream, | |
4562236b HW |
814 | const struct dc_cursor_attributes *attributes); |
815 | ||
ab2541b6 AC |
816 | bool dc_stream_set_cursor_position( |
817 | const struct dc_stream *stream, | |
beb16b6a | 818 | const struct dc_cursor_position *position); |
4562236b HW |
819 | |
820 | /* Newer interfaces */ | |
821 | struct dc_cursor { | |
822 | struct dc_plane_address address; | |
823 | struct dc_cursor_attributes attributes; | |
824 | }; | |
825 | ||
4562236b HW |
826 | /******************************************************************************* |
827 | * Interrupt interfaces | |
828 | ******************************************************************************/ | |
829 | enum dc_irq_source dc_interrupt_to_irq_source( | |
830 | struct dc *dc, | |
831 | uint32_t src_id, | |
832 | uint32_t ext_id); | |
833 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); | |
834 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); | |
835 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
836 | struct dc *dc, uint32_t link_index); | |
837 | ||
838 | /******************************************************************************* | |
839 | * Power Interfaces | |
840 | ******************************************************************************/ | |
841 | ||
842 | void dc_set_power_state( | |
843 | struct dc *dc, | |
a3621485 | 844 | enum dc_acpi_cm_power_state power_state); |
4562236b HW |
845 | void dc_resume(const struct dc *dc); |
846 | ||
4562236b HW |
847 | /* |
848 | * DPCD access interfaces | |
849 | */ | |
850 | ||
7c7f5b15 | 851 | bool dc_read_aux_dpcd( |
4562236b HW |
852 | struct dc *dc, |
853 | uint32_t link_index, | |
854 | uint32_t address, | |
855 | uint8_t *data, | |
856 | uint32_t size); | |
857 | ||
7c7f5b15 | 858 | bool dc_write_aux_dpcd( |
4562236b HW |
859 | struct dc *dc, |
860 | uint32_t link_index, | |
861 | uint32_t address, | |
862 | const uint8_t *data, | |
2b230ea3 ZF |
863 | uint32_t size); |
864 | ||
7c7f5b15 AG |
865 | bool dc_read_aux_i2c( |
866 | struct dc *dc, | |
867 | uint32_t link_index, | |
868 | enum i2c_mot_mode mot, | |
869 | uint32_t address, | |
870 | uint8_t *data, | |
871 | uint32_t size); | |
872 | ||
873 | bool dc_write_aux_i2c( | |
874 | struct dc *dc, | |
875 | uint32_t link_index, | |
876 | enum i2c_mot_mode mot, | |
877 | uint32_t address, | |
878 | const uint8_t *data, | |
879 | uint32_t size); | |
880 | ||
2b230ea3 ZF |
881 | bool dc_query_ddc_data( |
882 | struct dc *dc, | |
883 | uint32_t link_index, | |
884 | uint32_t address, | |
885 | uint8_t *write_buf, | |
886 | uint32_t write_size, | |
887 | uint8_t *read_buf, | |
888 | uint32_t read_size); | |
4562236b HW |
889 | |
890 | bool dc_submit_i2c( | |
891 | struct dc *dc, | |
892 | uint32_t link_index, | |
893 | struct i2c_command *cmd); | |
894 | ||
5e7773a2 | 895 | |
4562236b | 896 | #endif /* DC_INTERFACE_H_ */ |