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4562236b HW |
1 | /* |
2 | * Copyright 2012-14 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef DC_INTERFACE_H_ | |
27 | #define DC_INTERFACE_H_ | |
28 | ||
29 | #include "dc_types.h" | |
4562236b HW |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" | |
32 | #include "gpio_types.h" | |
33 | #include "link_service_types.h" | |
d0778ebf | 34 | #include "grph_object_ctrl_defs.h" |
4fa086b9 | 35 | #include <inc/hw/opp.h> |
4562236b | 36 | |
091a97e5 | 37 | #define MAX_SURFACES 3 |
ab2541b6 | 38 | #define MAX_STREAMS 6 |
4562236b HW |
39 | #define MAX_SINKS_PER_LINK 4 |
40 | ||
41 | /******************************************************************************* | |
42 | * Display Core Interfaces | |
43 | ******************************************************************************/ | |
44 | ||
45 | struct dc_caps { | |
ab2541b6 | 46 | uint32_t max_streams; |
4562236b HW |
47 | uint32_t max_links; |
48 | uint32_t max_audios; | |
49 | uint32_t max_slave_planes; | |
3be5262e | 50 | uint32_t max_planes; |
4562236b HW |
51 | uint32_t max_downscale_ratio; |
52 | uint32_t i2c_speed_in_khz; | |
a37656b9 TC |
53 | |
54 | unsigned int max_cursor_size; | |
4562236b HW |
55 | }; |
56 | ||
57 | ||
58 | struct dc_dcc_surface_param { | |
4562236b | 59 | struct dc_size surface_size; |
ebf055f9 | 60 | enum surface_pixel_format format; |
2c8ad2d5 | 61 | enum swizzle_mode_values swizzle_mode; |
4562236b HW |
62 | enum dc_scan_direction scan; |
63 | }; | |
64 | ||
65 | struct dc_dcc_setting { | |
66 | unsigned int max_compressed_blk_size; | |
67 | unsigned int max_uncompressed_blk_size; | |
68 | bool independent_64b_blks; | |
69 | }; | |
70 | ||
71 | struct dc_surface_dcc_cap { | |
4562236b HW |
72 | union { |
73 | struct { | |
74 | struct dc_dcc_setting rgb; | |
75 | } grph; | |
76 | ||
77 | struct { | |
78 | struct dc_dcc_setting luma; | |
79 | struct dc_dcc_setting chroma; | |
80 | } video; | |
81 | }; | |
ebf055f9 AK |
82 | |
83 | bool capable; | |
84 | bool const_color_support; | |
4562236b HW |
85 | }; |
86 | ||
94267b3d ST |
87 | struct dc_static_screen_events { |
88 | bool cursor_update; | |
89 | bool surface_update; | |
90 | bool overlay_update; | |
91 | }; | |
92 | ||
4562236b HW |
93 | /* Forward declaration*/ |
94 | struct dc; | |
c9614aeb | 95 | struct dc_plane_state; |
4562236b HW |
96 | struct validate_context; |
97 | ||
98 | struct dc_cap_funcs { | |
ff5ef992 AD |
99 | bool (*get_dcc_compression_cap)(const struct dc *dc, |
100 | const struct dc_dcc_surface_param *input, | |
101 | struct dc_surface_dcc_cap *output); | |
4562236b HW |
102 | }; |
103 | ||
0971c40e | 104 | struct dc_stream_state_funcs { |
4562236b | 105 | bool (*adjust_vmin_vmax)(struct dc *dc, |
0971c40e | 106 | struct dc_stream_state **stream, |
4562236b HW |
107 | int num_streams, |
108 | int vmin, | |
109 | int vmax); | |
72ada5f7 | 110 | bool (*get_crtc_position)(struct dc *dc, |
0971c40e | 111 | struct dc_stream_state **stream, |
72ada5f7 EC |
112 | int num_streams, |
113 | unsigned int *v_pos, | |
114 | unsigned int *nom_v_pos); | |
115 | ||
4562236b | 116 | bool (*set_gamut_remap)(struct dc *dc, |
0971c40e | 117 | const struct dc_stream_state *stream); |
94267b3d | 118 | |
abe07e80 | 119 | bool (*program_csc_matrix)(struct dc *dc, |
0971c40e | 120 | struct dc_stream_state *stream); |
abe07e80 | 121 | |
94267b3d | 122 | void (*set_static_screen_events)(struct dc *dc, |
0971c40e | 123 | struct dc_stream_state **stream, |
94267b3d ST |
124 | int num_streams, |
125 | const struct dc_static_screen_events *events); | |
529cad0f | 126 | |
0971c40e | 127 | void (*set_dither_option)(struct dc_stream_state *stream, |
529cad0f | 128 | enum dc_dither_option option); |
4562236b HW |
129 | }; |
130 | ||
131 | struct link_training_settings; | |
132 | ||
133 | struct dc_link_funcs { | |
134 | void (*set_drive_settings)(struct dc *dc, | |
bf5cda33 HW |
135 | struct link_training_settings *lt_settings, |
136 | const struct dc_link *link); | |
4562236b HW |
137 | void (*perform_link_training)(struct dc *dc, |
138 | struct dc_link_settings *link_setting, | |
139 | bool skip_video_pattern); | |
140 | void (*set_preferred_link_settings)(struct dc *dc, | |
88639168 | 141 | struct dc_link_settings *link_setting, |
d0778ebf | 142 | struct dc_link *link); |
4562236b HW |
143 | void (*enable_hpd)(const struct dc_link *link); |
144 | void (*disable_hpd)(const struct dc_link *link); | |
145 | void (*set_test_pattern)( | |
d0778ebf | 146 | struct dc_link *link, |
4562236b HW |
147 | enum dp_test_pattern test_pattern, |
148 | const struct link_training_settings *p_link_settings, | |
149 | const unsigned char *p_custom_pattern, | |
150 | unsigned int cust_pattern_size); | |
151 | }; | |
152 | ||
153 | /* Structure to hold configuration flags set by dm at dc creation. */ | |
154 | struct dc_config { | |
155 | bool gpu_vm_support; | |
156 | bool disable_disp_pll_sharing; | |
157 | }; | |
158 | ||
159 | struct dc_debug { | |
160 | bool surface_visual_confirm; | |
2b13d7d3 | 161 | bool sanity_checks; |
4562236b | 162 | bool max_disp_clk; |
4562236b | 163 | bool surface_trace; |
9474980a | 164 | bool timing_trace; |
c9742685 | 165 | bool clock_trace; |
4562236b HW |
166 | bool validation_trace; |
167 | bool disable_stutter; | |
168 | bool disable_dcc; | |
169 | bool disable_dfs_bypass; | |
ff5ef992 AD |
170 | bool disable_dpp_power_gate; |
171 | bool disable_hubp_power_gate; | |
172 | bool disable_pplib_wm_range; | |
173 | bool use_dml_wm; | |
90f095c1 | 174 | bool disable_pipe_split; |
139cb65c DL |
175 | int sr_exit_time_dpm0_ns; |
176 | int sr_enter_plus_exit_time_dpm0_ns; | |
ff5ef992 AD |
177 | int sr_exit_time_ns; |
178 | int sr_enter_plus_exit_time_ns; | |
179 | int urgent_latency_ns; | |
180 | int percent_of_ideal_drambw; | |
181 | int dram_clock_change_latency_ns; | |
e73b59b7 | 182 | int always_scale; |
2c8ad2d5 | 183 | bool disable_pplib_clock_request; |
4562236b | 184 | bool disable_clock_gate; |
aa66df58 | 185 | bool disable_dmcu; |
29eba8e8 | 186 | bool disable_psr; |
70814f6f | 187 | bool force_abm_enable; |
4562236b HW |
188 | }; |
189 | ||
190 | struct dc { | |
191 | struct dc_caps caps; | |
192 | struct dc_cap_funcs cap_funcs; | |
0971c40e | 193 | struct dc_stream_state_funcs stream_funcs; |
4562236b HW |
194 | struct dc_link_funcs link_funcs; |
195 | struct dc_config config; | |
196 | struct dc_debug debug; | |
197 | }; | |
198 | ||
2c8ad2d5 AD |
199 | enum frame_buffer_mode { |
200 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, | |
201 | FRAME_BUFFER_MODE_ZFB_ONLY, | |
202 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, | |
203 | } ; | |
204 | ||
205 | struct dchub_init_data { | |
2c8ad2d5 AD |
206 | int64_t zfb_phys_addr_base; |
207 | int64_t zfb_mc_base_addr; | |
208 | uint64_t zfb_size_in_byte; | |
209 | enum frame_buffer_mode fb_mode; | |
ebf055f9 AK |
210 | bool dchub_initialzied; |
211 | bool dchub_info_valid; | |
2c8ad2d5 | 212 | }; |
2c8ad2d5 | 213 | |
4562236b HW |
214 | struct dc_init_data { |
215 | struct hw_asic_id asic_id; | |
216 | void *driver; /* ctx */ | |
217 | struct cgs_device *cgs_device; | |
218 | ||
219 | int num_virtual_links; | |
220 | /* | |
221 | * If 'vbios_override' not NULL, it will be called instead | |
222 | * of the real VBIOS. Intended use is Diagnostics on FPGA. | |
223 | */ | |
224 | struct dc_bios *vbios_override; | |
225 | enum dce_environment dce_environment; | |
226 | ||
227 | struct dc_config flags; | |
690b5e39 RL |
228 | #ifdef ENABLE_FBC |
229 | uint64_t fbc_gpu_addr; | |
230 | #endif | |
4562236b HW |
231 | }; |
232 | ||
233 | struct dc *dc_create(const struct dc_init_data *init_params); | |
234 | ||
235 | void dc_destroy(struct dc **dc); | |
236 | ||
2c8ad2d5 | 237 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); |
2c8ad2d5 | 238 | |
6d244be8 TC |
239 | void dc_log_hw_state(struct dc *dc); |
240 | ||
4562236b HW |
241 | /******************************************************************************* |
242 | * Surface Interfaces | |
243 | ******************************************************************************/ | |
244 | ||
245 | enum { | |
fb735a9f | 246 | TRANSFER_FUNC_POINTS = 1025 |
4562236b HW |
247 | }; |
248 | ||
1646a6fe | 249 | struct dc_hdr_static_metadata { |
1646a6fe AW |
250 | /* display chromaticities and white point in units of 0.00001 */ |
251 | unsigned int chromaticity_green_x; | |
252 | unsigned int chromaticity_green_y; | |
253 | unsigned int chromaticity_blue_x; | |
254 | unsigned int chromaticity_blue_y; | |
255 | unsigned int chromaticity_red_x; | |
256 | unsigned int chromaticity_red_y; | |
257 | unsigned int chromaticity_white_point_x; | |
258 | unsigned int chromaticity_white_point_y; | |
259 | ||
260 | uint32_t min_luminance; | |
261 | uint32_t max_luminance; | |
262 | uint32_t maximum_content_light_level; | |
263 | uint32_t maximum_frame_average_light_level; | |
ebf055f9 AK |
264 | |
265 | bool hdr_supported; | |
266 | bool is_hdr; | |
1646a6fe AW |
267 | }; |
268 | ||
fb735a9f AK |
269 | enum dc_transfer_func_type { |
270 | TF_TYPE_PREDEFINED, | |
271 | TF_TYPE_DISTRIBUTED_POINTS, | |
7950f0f9 | 272 | TF_TYPE_BYPASS |
fb735a9f AK |
273 | }; |
274 | ||
275 | struct dc_transfer_func_distributed_points { | |
fcd2f4bf AZ |
276 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
277 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; | |
278 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; | |
279 | ||
fb735a9f | 280 | uint16_t end_exponent; |
fcd2f4bf AZ |
281 | uint16_t x_point_at_y1_red; |
282 | uint16_t x_point_at_y1_green; | |
283 | uint16_t x_point_at_y1_blue; | |
fb735a9f AK |
284 | }; |
285 | ||
286 | enum dc_transfer_func_predefined { | |
287 | TRANSFER_FUNCTION_SRGB, | |
288 | TRANSFER_FUNCTION_BT709, | |
90e508ba | 289 | TRANSFER_FUNCTION_PQ, |
fb735a9f AK |
290 | TRANSFER_FUNCTION_LINEAR, |
291 | }; | |
292 | ||
293 | struct dc_transfer_func { | |
ebf055f9 | 294 | struct dc_transfer_func_distributed_points tf_pts; |
fb735a9f AK |
295 | enum dc_transfer_func_type type; |
296 | enum dc_transfer_func_predefined tf; | |
7b0c470f LSL |
297 | struct dc_context *ctx; |
298 | int ref_count; | |
fb735a9f AK |
299 | }; |
300 | ||
e12cfcb1 HW |
301 | /* |
302 | * This structure is filled in by dc_surface_get_status and contains | |
303 | * the last requested address and the currently active address so the called | |
304 | * can determine if there are any outstanding flips | |
305 | */ | |
3be5262e | 306 | struct dc_plane_status { |
e12cfcb1 HW |
307 | struct dc_plane_address requested_address; |
308 | struct dc_plane_address current_address; | |
309 | bool is_flip_pending; | |
310 | bool is_right_eye; | |
311 | }; | |
312 | ||
c9614aeb | 313 | struct dc_plane_state { |
4562236b HW |
314 | struct dc_plane_address address; |
315 | ||
316 | struct scaling_taps scaling_quality; | |
317 | struct rect src_rect; | |
318 | struct rect dst_rect; | |
319 | struct rect clip_rect; | |
320 | ||
321 | union plane_size plane_size; | |
322 | union dc_tiling_info tiling_info; | |
ebf055f9 | 323 | |
4562236b | 324 | struct dc_plane_dcc_param dcc; |
ebf055f9 AK |
325 | struct dc_hdr_static_metadata hdr_static_ctx; |
326 | ||
7a6c4af6 | 327 | struct dc_gamma *gamma_correction; |
7b0c470f | 328 | struct dc_transfer_func *in_transfer_func; |
4562236b | 329 | |
ebf055f9 | 330 | enum dc_color_space color_space; |
4562236b HW |
331 | enum surface_pixel_format format; |
332 | enum dc_rotation_angle rotation; | |
4562236b HW |
333 | enum plane_stereo_format stereo_format; |
334 | ||
ebf055f9 AK |
335 | bool per_pixel_alpha; |
336 | bool visible; | |
337 | bool flip_immediate; | |
338 | bool horizontal_mirror; | |
e12cfcb1 HW |
339 | |
340 | /* private to DC core */ | |
3be5262e | 341 | struct dc_plane_status status; |
e12cfcb1 HW |
342 | struct dc_context *ctx; |
343 | ||
344 | /* private to dc_surface.c */ | |
345 | enum dc_irq_source irq_source; | |
346 | int ref_count; | |
4562236b HW |
347 | }; |
348 | ||
349 | struct dc_plane_info { | |
350 | union plane_size plane_size; | |
351 | union dc_tiling_info tiling_info; | |
9cd09bfe | 352 | struct dc_plane_dcc_param dcc; |
4562236b HW |
353 | enum surface_pixel_format format; |
354 | enum dc_rotation_angle rotation; | |
4562236b HW |
355 | enum plane_stereo_format stereo_format; |
356 | enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ | |
ebf055f9 | 357 | bool horizontal_mirror; |
4562236b | 358 | bool visible; |
ebf055f9 | 359 | bool per_pixel_alpha; |
4562236b HW |
360 | }; |
361 | ||
362 | struct dc_scaling_info { | |
ebf055f9 AK |
363 | struct rect src_rect; |
364 | struct rect dst_rect; | |
365 | struct rect clip_rect; | |
366 | struct scaling_taps scaling_quality; | |
4562236b HW |
367 | }; |
368 | ||
369 | struct dc_surface_update { | |
c9614aeb | 370 | struct dc_plane_state *surface; |
4562236b HW |
371 | |
372 | /* isr safe update parameters. null means no updates */ | |
373 | struct dc_flip_addrs *flip_addr; | |
374 | struct dc_plane_info *plane_info; | |
375 | struct dc_scaling_info *scaling_info; | |
376 | /* following updates require alloc/sleep/spin that is not isr safe, | |
377 | * null means no updates | |
378 | */ | |
fb735a9f | 379 | /* gamma TO BE REMOVED */ |
4562236b | 380 | struct dc_gamma *gamma; |
fb735a9f | 381 | struct dc_transfer_func *in_transfer_func; |
f46661dd | 382 | struct dc_hdr_static_metadata *hdr_static_metadata; |
4562236b | 383 | }; |
4562236b HW |
384 | |
385 | /* | |
386 | * Create a new surface with default parameters; | |
387 | */ | |
3be5262e HW |
388 | struct dc_plane_state *dc_create_plane_state(const struct dc *dc); |
389 | const struct dc_plane_status *dc_plane_get_status( | |
390 | const struct dc_plane_state *plane_state); | |
4562236b | 391 | |
3be5262e HW |
392 | void dc_plane_state_retain(struct dc_plane_state *plane_state); |
393 | void dc_plane_state_release(struct dc_plane_state *plane_state); | |
4562236b | 394 | |
7a6c4af6 HW |
395 | void dc_gamma_retain(struct dc_gamma *dc_gamma); |
396 | void dc_gamma_release(struct dc_gamma **dc_gamma); | |
4562236b HW |
397 | struct dc_gamma *dc_create_gamma(void); |
398 | ||
7b0c470f LSL |
399 | void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); |
400 | void dc_transfer_func_release(struct dc_transfer_func *dc_tf); | |
90e508ba | 401 | struct dc_transfer_func *dc_create_transfer_func(void); |
fb735a9f | 402 | |
4562236b HW |
403 | /* |
404 | * This structure holds a surface address. There could be multiple addresses | |
405 | * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such | |
406 | * as frame durations and DCC format can also be set. | |
407 | */ | |
408 | struct dc_flip_addrs { | |
409 | struct dc_plane_address address; | |
410 | bool flip_immediate; | |
4562236b HW |
411 | /* TODO: add flip duration for FreeSync */ |
412 | }; | |
413 | ||
4562236b | 414 | /* |
ab2541b6 AC |
415 | * Set up surface attributes and associate to a stream |
416 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
417 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
4562236b HW |
418 | * Any flip related attribute changes must be done through this interface. |
419 | * | |
420 | * After this call: | |
ab2541b6 | 421 | * Surfaces attributes are programmed and configured to be composed into stream. |
4562236b HW |
422 | * This does not trigger a flip. No surface address is programmed. |
423 | */ | |
424 | ||
3be5262e | 425 | bool dc_commit_planes_to_stream( |
4562236b | 426 | struct dc *dc, |
3be5262e HW |
427 | struct dc_plane_state **plane_states, |
428 | uint8_t new_plane_count, | |
0971c40e | 429 | struct dc_stream_state *stream); |
4562236b | 430 | |
ab2541b6 | 431 | bool dc_post_update_surfaces_to_stream( |
4562236b HW |
432 | struct dc *dc); |
433 | ||
81e2b2de DL |
434 | /* Surface update type is used by dc_update_surfaces_and_stream |
435 | * The update type is determined at the very beginning of the function based | |
436 | * on parameters passed in and decides how much programming (or updating) is | |
437 | * going to be done during the call. | |
438 | * | |
439 | * UPDATE_TYPE_FAST is used for really fast updates that do not require much | |
440 | * logical calculations or hardware register programming. This update MUST be | |
441 | * ISR safe on windows. Currently fast update will only be used to flip surface | |
442 | * address. | |
443 | * | |
444 | * UPDATE_TYPE_MED is used for slower updates which require significant hw | |
445 | * re-programming however do not affect bandwidth consumption or clock | |
446 | * requirements. At present, this is the level at which front end updates | |
447 | * that do not require us to run bw_calcs happen. These are in/out transfer func | |
448 | * updates, viewport offset changes, recout size changes and pixel depth changes. | |
449 | * This update can be done at ISR, but we want to minimize how often this happens. | |
450 | * | |
451 | * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our | |
452 | * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front | |
453 | * end related. Any time viewport dimensions, recout dimensions, scaling ratios or | |
454 | * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do | |
455 | * a full update. This cannot be done at ISR level and should be a rare event. | |
456 | * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting | |
457 | * underscan we don't expect to see this call at all. | |
458 | */ | |
459 | ||
5869b0f6 LE |
460 | enum surface_update_type { |
461 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ | |
81e2b2de | 462 | UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ |
5869b0f6 LE |
463 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ |
464 | }; | |
465 | ||
4562236b | 466 | /******************************************************************************* |
ab2541b6 | 467 | * Stream Interfaces |
4562236b | 468 | ******************************************************************************/ |
4fa086b9 LSL |
469 | |
470 | struct dc_stream_status { | |
471 | int primary_otg_inst; | |
3be5262e HW |
472 | int plane_count; |
473 | struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; | |
4fa086b9 LSL |
474 | |
475 | /* | |
476 | * link this stream passes through | |
477 | */ | |
478 | struct dc_link *link; | |
479 | }; | |
480 | ||
0971c40e | 481 | struct dc_stream_state { |
b3d6c3f0 | 482 | struct dc_sink *sink; |
ab2541b6 | 483 | struct dc_crtc_timing timing; |
4562236b | 484 | |
ab2541b6 AC |
485 | struct rect src; /* composition area */ |
486 | struct rect dst; /* stream addressable area */ | |
4562236b | 487 | |
ab2541b6 AC |
488 | struct audio_info audio_info; |
489 | ||
ab2541b6 AC |
490 | struct freesync_context freesync_ctx; |
491 | ||
7b0c470f | 492 | struct dc_transfer_func *out_transfer_func; |
ab2541b6 AC |
493 | struct colorspace_transform gamut_remap_matrix; |
494 | struct csc_transform csc_color_matrix; | |
ebf055f9 AK |
495 | |
496 | enum signal_type output_signal; | |
497 | ||
498 | enum dc_color_space output_color_space; | |
499 | enum dc_dither_option dither_option; | |
500 | ||
9edba557 | 501 | enum view_3d_format view_format; |
ebf055f9 AK |
502 | |
503 | bool ignore_msa_timing_param; | |
ab2541b6 AC |
504 | /* TODO: custom INFO packets */ |
505 | /* TODO: ABM info (DMCU) */ | |
506 | /* TODO: PSR info */ | |
507 | /* TODO: CEA VIC */ | |
4fa086b9 LSL |
508 | |
509 | /* from core_stream struct */ | |
510 | struct dc_context *ctx; | |
511 | ||
512 | /* used by DCP and FMT */ | |
513 | struct bit_depth_reduction_params bit_depth_params; | |
514 | struct clamping_and_pixel_encoding_params clamping; | |
515 | ||
516 | int phy_pix_clk; | |
517 | enum signal_type signal; | |
518 | ||
519 | struct dc_stream_status status; | |
520 | ||
521 | /* from stream struct */ | |
522 | int ref_count; | |
ab2541b6 | 523 | }; |
4562236b | 524 | |
a783e7b5 | 525 | struct dc_stream_update { |
a783e7b5 | 526 | struct rect src; |
a783e7b5 | 527 | struct rect dst; |
f46661dd | 528 | struct dc_transfer_func *out_transfer_func; |
a783e7b5 LE |
529 | }; |
530 | ||
d54d29db | 531 | bool dc_is_stream_unchanged( |
0971c40e | 532 | struct dc_stream_state *old_stream, struct dc_stream_state *stream); |
a783e7b5 LE |
533 | |
534 | /* | |
535 | * Setup stream attributes if no stream updates are provided | |
536 | * there will be no impact on the stream parameters | |
537 | * | |
538 | * Set up surface attributes and associate to a stream | |
539 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
540 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
541 | * Any flip related attribute changes must be done through this interface. | |
542 | * | |
543 | * After this call: | |
544 | * Surfaces attributes are programmed and configured to be composed into stream. | |
545 | * This does not trigger a flip. No surface address is programmed. | |
546 | * | |
547 | */ | |
548 | ||
3be5262e | 549 | void dc_update_planes_and_stream(struct dc *dc, |
a783e7b5 | 550 | struct dc_surface_update *surface_updates, int surface_count, |
0971c40e | 551 | struct dc_stream_state *dc_stream, |
a783e7b5 LE |
552 | struct dc_stream_update *stream_update); |
553 | ||
4562236b | 554 | /* |
ab2541b6 | 555 | * Log the current stream state. |
4562236b | 556 | */ |
ab2541b6 | 557 | void dc_stream_log( |
0971c40e | 558 | const struct dc_stream_state *stream, |
4562236b HW |
559 | struct dal_logger *dc_logger, |
560 | enum dc_log_type log_type); | |
561 | ||
ab2541b6 | 562 | uint8_t dc_get_current_stream_count(const struct dc *dc); |
0971c40e | 563 | struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); |
4562236b | 564 | |
ab2541b6 AC |
565 | /* |
566 | * Return the current frame counter. | |
567 | */ | |
0971c40e | 568 | uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); |
4562236b HW |
569 | |
570 | /* TODO: Return parsed values rather than direct register read | |
571 | * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) | |
572 | * being refactored properly to be dce-specific | |
573 | */ | |
0971c40e | 574 | bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, |
81c50963 ST |
575 | uint32_t *v_blank_start, |
576 | uint32_t *v_blank_end, | |
577 | uint32_t *h_position, | |
578 | uint32_t *v_position); | |
4562236b HW |
579 | |
580 | /* | |
ab2541b6 | 581 | * Structure to store surface/stream associations for validation |
4562236b HW |
582 | */ |
583 | struct dc_validation_set { | |
0971c40e | 584 | struct dc_stream_state *stream; |
3be5262e HW |
585 | struct dc_plane_state *plane_states[MAX_SURFACES]; |
586 | uint8_t plane_count; | |
4562236b HW |
587 | }; |
588 | ||
0971c40e | 589 | bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); |
9345d987 | 590 | |
c9614aeb | 591 | bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); |
4562236b HW |
592 | /* |
593 | * This function takes a set of resources and checks that they are cofunctional. | |
594 | * | |
595 | * After this call: | |
596 | * No hardware is programmed for call. Only validation is done. | |
597 | */ | |
07d72b39 HW |
598 | struct validate_context *dc_get_validate_context( |
599 | const struct dc *dc, | |
600 | const struct dc_validation_set set[], | |
601 | uint8_t set_count); | |
602 | ||
4562236b HW |
603 | bool dc_validate_resources( |
604 | const struct dc *dc, | |
605 | const struct dc_validation_set set[], | |
606 | uint8_t set_count); | |
607 | ||
608 | /* | |
ab2541b6 AC |
609 | * This function takes a stream and checks if it is guaranteed to be supported. |
610 | * Guaranteed means that MAX_COFUNC similar streams are supported. | |
4562236b HW |
611 | * |
612 | * After this call: | |
613 | * No hardware is programmed for call. Only validation is done. | |
614 | */ | |
615 | ||
616 | bool dc_validate_guaranteed( | |
617 | const struct dc *dc, | |
0971c40e | 618 | struct dc_stream_state *stream); |
4562236b | 619 | |
8122a253 HW |
620 | void dc_resource_validate_ctx_copy_construct( |
621 | const struct validate_context *src_ctx, | |
622 | struct validate_context *dst_ctx); | |
623 | ||
624 | void dc_resource_validate_ctx_destruct(struct validate_context *context); | |
625 | ||
7cf2c840 HW |
626 | /* |
627 | * TODO update to make it about validation sets | |
628 | * Set up streams and links associated to drive sinks | |
629 | * The streams parameter is an absolute set of all active streams. | |
630 | * | |
631 | * After this call: | |
632 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
633 | * New streams are enabled with blank stream; no memory read. | |
634 | */ | |
e2c7bb12 | 635 | bool dc_commit_context(struct dc *dc, struct validate_context *context); |
7cf2c840 | 636 | |
4562236b | 637 | /* |
ab2541b6 AC |
638 | * Set up streams and links associated to drive sinks |
639 | * The streams parameter is an absolute set of all active streams. | |
4562236b HW |
640 | * |
641 | * After this call: | |
642 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
ab2541b6 | 643 | * New streams are enabled with blank stream; no memory read. |
4562236b | 644 | */ |
ab2541b6 | 645 | bool dc_commit_streams( |
4562236b | 646 | struct dc *dc, |
0971c40e | 647 | struct dc_stream_state *streams[], |
ab2541b6 | 648 | uint8_t stream_count); |
9edba557 VP |
649 | /* |
650 | * Enable stereo when commit_streams is not required, | |
651 | * for example, frame alternate. | |
652 | */ | |
653 | bool dc_enable_stereo( | |
654 | struct dc *dc, | |
655 | struct validate_context *context, | |
0971c40e | 656 | struct dc_stream_state *streams[], |
9edba557 | 657 | uint8_t stream_count); |
4562236b HW |
658 | |
659 | /** | |
660 | * Create a new default stream for the requested sink | |
661 | */ | |
0971c40e | 662 | struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); |
4562236b | 663 | |
0971c40e HW |
664 | void dc_stream_retain(struct dc_stream_state *dc_stream); |
665 | void dc_stream_release(struct dc_stream_state *dc_stream); | |
4562236b | 666 | |
e12cfcb1 | 667 | struct dc_stream_status *dc_stream_get_status( |
0971c40e | 668 | struct dc_stream_state *dc_stream); |
4562236b | 669 | |
5869b0f6 LE |
670 | enum surface_update_type dc_check_update_surfaces_for_stream( |
671 | struct dc *dc, | |
672 | struct dc_surface_update *updates, | |
673 | int surface_count, | |
ee8f63e1 | 674 | struct dc_stream_update *stream_update, |
5869b0f6 LE |
675 | const struct dc_stream_status *stream_status); |
676 | ||
8a76708e AG |
677 | |
678 | void dc_retain_validate_context(struct validate_context *context); | |
679 | void dc_release_validate_context(struct validate_context *context); | |
680 | ||
4562236b HW |
681 | /******************************************************************************* |
682 | * Link Interfaces | |
683 | ******************************************************************************/ | |
684 | ||
d0778ebf HW |
685 | struct dpcd_caps { |
686 | union dpcd_rev dpcd_rev; | |
687 | union max_lane_count max_ln_count; | |
688 | union max_down_spread max_down_spread; | |
689 | ||
690 | /* dongle type (DP converter, CV smart dongle) */ | |
691 | enum display_dongle_type dongle_type; | |
692 | /* Dongle's downstream count. */ | |
693 | union sink_count sink_count; | |
694 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, | |
695 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
696 | struct dc_dongle_caps dongle_caps; | |
697 | ||
698 | uint32_t sink_dev_id; | |
699 | uint32_t branch_dev_id; | |
700 | int8_t branch_dev_name[6]; | |
701 | int8_t branch_hw_revision; | |
702 | ||
703 | bool allow_invalid_MSA_timing_param; | |
704 | bool panel_mode_edp; | |
705 | }; | |
706 | ||
707 | struct dc_link_status { | |
708 | struct dpcd_caps *dpcd_caps; | |
709 | }; | |
710 | ||
711 | /* DP MST stream allocation (payload bandwidth number) */ | |
712 | struct link_mst_stream_allocation { | |
713 | /* DIG front */ | |
714 | const struct stream_encoder *stream_enc; | |
715 | /* associate DRM payload table with DC stream encoder */ | |
716 | uint8_t vcp_id; | |
717 | /* number of slots required for the DP stream in transport packet */ | |
718 | uint8_t slot_count; | |
719 | }; | |
720 | ||
721 | /* DP MST stream allocation table */ | |
722 | struct link_mst_stream_allocation_table { | |
723 | /* number of DP video streams */ | |
724 | int stream_count; | |
725 | /* array of stream allocations */ | |
726 | struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; | |
727 | }; | |
728 | ||
4562236b HW |
729 | /* |
730 | * A link contains one or more sinks and their connected status. | |
731 | * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. | |
732 | */ | |
733 | struct dc_link { | |
b73a22d3 | 734 | struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; |
4562236b | 735 | unsigned int sink_count; |
b73a22d3 | 736 | struct dc_sink *local_sink; |
4562236b HW |
737 | unsigned int link_index; |
738 | enum dc_connection_type type; | |
739 | enum signal_type connector_signal; | |
740 | enum dc_irq_source irq_source_hpd; | |
741 | enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ | |
742 | /* caps is the same as reported_link_cap. link_traing use | |
743 | * reported_link_cap. Will clean up. TODO | |
744 | */ | |
745 | struct dc_link_settings reported_link_cap; | |
746 | struct dc_link_settings verified_link_cap; | |
4562236b HW |
747 | struct dc_link_settings cur_link_settings; |
748 | struct dc_lane_settings cur_lane_setting; | |
8c4abe0b | 749 | struct dc_link_settings preferred_link_setting; |
4562236b HW |
750 | |
751 | uint8_t ddc_hw_inst; | |
7a096334 ZF |
752 | |
753 | uint8_t hpd_src; | |
754 | ||
4562236b HW |
755 | uint8_t link_enc_hw_inst; |
756 | ||
4562236b HW |
757 | bool test_pattern_enabled; |
758 | union compliance_test_state compliance_test_state; | |
9fb8de78 AG |
759 | |
760 | void *priv; | |
46df790c AG |
761 | |
762 | struct ddc_service *ddc; | |
ebf055f9 AK |
763 | |
764 | bool aux_mode; | |
4562236b | 765 | |
d0778ebf | 766 | /* Private to DC core */ |
4562236b | 767 | |
d0778ebf | 768 | const struct core_dc *dc; |
4562236b | 769 | |
d0778ebf | 770 | struct dc_context *ctx; |
ebf055f9 | 771 | |
d0778ebf HW |
772 | struct link_encoder *link_enc; |
773 | struct graphics_object_id link_id; | |
774 | union ddi_channel_mapping ddi_channel_mapping; | |
775 | struct connector_device_tag_info device_tag; | |
776 | struct dpcd_caps dpcd_caps; | |
777 | unsigned int dpcd_sink_count; | |
778 | ||
779 | enum edp_revision edp_revision; | |
780 | bool psr_enabled; | |
781 | ||
782 | /* MST record stream using this link */ | |
783 | struct link_flags { | |
784 | bool dp_keep_receiver_powered; | |
785 | } wa_flags; | |
786 | struct link_mst_stream_allocation_table mst_stream_alloc_table; | |
787 | ||
788 | struct dc_link_status link_status; | |
4562236b | 789 | |
4562236b HW |
790 | }; |
791 | ||
792 | const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); | |
793 | ||
794 | /* | |
795 | * Return an enumerated dc_link. dc_link order is constant and determined at | |
796 | * boot time. They cannot be created or destroyed. | |
797 | * Use dc_get_caps() to get number of links. | |
798 | */ | |
d0778ebf | 799 | struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); |
4562236b HW |
800 | |
801 | /* Return id of physical connector represented by a dc_link at link_index.*/ | |
802 | const struct graphics_object_id dc_get_link_id_at_index( | |
803 | struct dc *dc, uint32_t link_index); | |
804 | ||
805 | /* Set backlight level of an embedded panel (eDP, LVDS). */ | |
806 | bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, | |
0971c40e | 807 | uint32_t frame_ramp, const struct dc_stream_state *stream); |
4562236b | 808 | |
aa7397df AZ |
809 | bool dc_link_set_abm_disable(const struct dc_link *dc_link); |
810 | ||
4562236b HW |
811 | bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); |
812 | ||
7db4dede AZ |
813 | bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); |
814 | ||
d0778ebf | 815 | bool dc_link_setup_psr(struct dc_link *dc_link, |
0971c40e | 816 | const struct dc_stream_state *stream, struct psr_config *psr_config, |
9f72f51d | 817 | struct psr_context *psr_context); |
4562236b HW |
818 | |
819 | /* Request DC to detect if there is a Panel connected. | |
820 | * boot - If this call is during initial boot. | |
821 | * Return false for any type of detection failure or MST detection | |
822 | * true otherwise. True meaning further action is required (status update | |
823 | * and OS notification). | |
824 | */ | |
d0778ebf | 825 | bool dc_link_detect(struct dc_link *dc_link, bool boot); |
4562236b HW |
826 | |
827 | /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). | |
828 | * Return: | |
829 | * true - Downstream port status changed. DM should call DC to do the | |
830 | * detection. | |
831 | * false - no change in Downstream port status. No further action required | |
832 | * from DM. */ | |
d0778ebf | 833 | bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, |
8ee65d7c | 834 | union hpd_irq_data *hpd_irq_dpcd_data); |
4562236b HW |
835 | |
836 | struct dc_sink_init_data; | |
837 | ||
838 | struct dc_sink *dc_link_add_remote_sink( | |
d0778ebf | 839 | struct dc_link *dc_link, |
4562236b HW |
840 | const uint8_t *edid, |
841 | int len, | |
842 | struct dc_sink_init_data *init_data); | |
843 | ||
844 | void dc_link_remove_remote_sink( | |
d0778ebf | 845 | struct dc_link *link, |
b73a22d3 | 846 | struct dc_sink *sink); |
4562236b HW |
847 | |
848 | /* Used by diagnostics for virtual link at the moment */ | |
d0778ebf | 849 | void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink); |
4562236b HW |
850 | |
851 | void dc_link_dp_set_drive_settings( | |
d0778ebf | 852 | struct dc_link *link, |
4562236b HW |
853 | struct link_training_settings *lt_settings); |
854 | ||
820e3935 | 855 | enum link_training_result dc_link_dp_perform_link_training( |
4562236b HW |
856 | struct dc_link *link, |
857 | const struct dc_link_settings *link_setting, | |
858 | bool skip_video_pattern); | |
859 | ||
860 | void dc_link_dp_enable_hpd(const struct dc_link *link); | |
861 | ||
862 | void dc_link_dp_disable_hpd(const struct dc_link *link); | |
863 | ||
864 | bool dc_link_dp_set_test_pattern( | |
d0778ebf | 865 | struct dc_link *link, |
4562236b HW |
866 | enum dp_test_pattern test_pattern, |
867 | const struct link_training_settings *p_link_settings, | |
868 | const unsigned char *p_custom_pattern, | |
869 | unsigned int cust_pattern_size); | |
870 | ||
871 | /******************************************************************************* | |
872 | * Sink Interfaces - A sink corresponds to a display output device | |
873 | ******************************************************************************/ | |
874 | ||
8c895313 | 875 | struct dc_container_id { |
876 | // 128bit GUID in binary form | |
877 | unsigned char guid[16]; | |
878 | // 8 byte port ID -> ELD.PortID | |
879 | unsigned int portId[2]; | |
880 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName | |
881 | unsigned short manufacturerName; | |
882 | // 2 byte product code -> ELD.ProductCode | |
883 | unsigned short productCode; | |
884 | }; | |
885 | ||
b6d6103b | 886 | |
9edba557 | 887 | |
4562236b HW |
888 | /* |
889 | * The sink structure contains EDID and other display device properties | |
890 | */ | |
891 | struct dc_sink { | |
892 | enum signal_type sink_signal; | |
893 | struct dc_edid dc_edid; /* raw edid */ | |
894 | struct dc_edid_caps edid_caps; /* parse display caps */ | |
8c895313 | 895 | struct dc_container_id *dc_container_id; |
4a9a5d62 | 896 | uint32_t dongle_max_pix_clk; |
5c4e9806 | 897 | void *priv; |
9edba557 | 898 | struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; |
ebf055f9 | 899 | bool converter_disable_audio; |
b73a22d3 HW |
900 | |
901 | /* private to DC core */ | |
902 | struct dc_link *link; | |
903 | struct dc_context *ctx; | |
904 | ||
905 | /* private to dc_sink.c */ | |
906 | int ref_count; | |
4562236b HW |
907 | }; |
908 | ||
b73a22d3 HW |
909 | void dc_sink_retain(struct dc_sink *sink); |
910 | void dc_sink_release(struct dc_sink *sink); | |
4562236b HW |
911 | |
912 | const struct audio **dc_get_audios(struct dc *dc); | |
913 | ||
914 | struct dc_sink_init_data { | |
915 | enum signal_type sink_signal; | |
d0778ebf | 916 | struct dc_link *link; |
4562236b HW |
917 | uint32_t dongle_max_pix_clk; |
918 | bool converter_disable_audio; | |
919 | }; | |
920 | ||
921 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); | |
8c895313 | 922 | bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id); |
923 | bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id); | |
4562236b HW |
924 | |
925 | /******************************************************************************* | |
ab2541b6 | 926 | * Cursor interfaces - To manages the cursor within a stream |
4562236b HW |
927 | ******************************************************************************/ |
928 | /* TODO: Deprecated once we switch to dc_set_cursor_position */ | |
ab2541b6 | 929 | bool dc_stream_set_cursor_attributes( |
0971c40e | 930 | const struct dc_stream_state *stream, |
4562236b HW |
931 | const struct dc_cursor_attributes *attributes); |
932 | ||
ab2541b6 | 933 | bool dc_stream_set_cursor_position( |
0971c40e | 934 | struct dc_stream_state *stream, |
beb16b6a | 935 | const struct dc_cursor_position *position); |
4562236b HW |
936 | |
937 | /* Newer interfaces */ | |
938 | struct dc_cursor { | |
939 | struct dc_plane_address address; | |
940 | struct dc_cursor_attributes attributes; | |
941 | }; | |
942 | ||
4562236b HW |
943 | /******************************************************************************* |
944 | * Interrupt interfaces | |
945 | ******************************************************************************/ | |
946 | enum dc_irq_source dc_interrupt_to_irq_source( | |
947 | struct dc *dc, | |
948 | uint32_t src_id, | |
949 | uint32_t ext_id); | |
950 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); | |
951 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); | |
952 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
953 | struct dc *dc, uint32_t link_index); | |
954 | ||
955 | /******************************************************************************* | |
956 | * Power Interfaces | |
957 | ******************************************************************************/ | |
958 | ||
959 | void dc_set_power_state( | |
960 | struct dc *dc, | |
a3621485 | 961 | enum dc_acpi_cm_power_state power_state); |
4562236b HW |
962 | void dc_resume(const struct dc *dc); |
963 | ||
4562236b HW |
964 | /* |
965 | * DPCD access interfaces | |
966 | */ | |
967 | ||
7c7f5b15 | 968 | bool dc_read_aux_dpcd( |
4562236b HW |
969 | struct dc *dc, |
970 | uint32_t link_index, | |
971 | uint32_t address, | |
972 | uint8_t *data, | |
973 | uint32_t size); | |
974 | ||
7c7f5b15 | 975 | bool dc_write_aux_dpcd( |
4562236b HW |
976 | struct dc *dc, |
977 | uint32_t link_index, | |
978 | uint32_t address, | |
979 | const uint8_t *data, | |
2b230ea3 ZF |
980 | uint32_t size); |
981 | ||
7c7f5b15 AG |
982 | bool dc_read_aux_i2c( |
983 | struct dc *dc, | |
984 | uint32_t link_index, | |
985 | enum i2c_mot_mode mot, | |
986 | uint32_t address, | |
987 | uint8_t *data, | |
988 | uint32_t size); | |
989 | ||
990 | bool dc_write_aux_i2c( | |
991 | struct dc *dc, | |
992 | uint32_t link_index, | |
993 | enum i2c_mot_mode mot, | |
994 | uint32_t address, | |
995 | const uint8_t *data, | |
996 | uint32_t size); | |
997 | ||
2b230ea3 ZF |
998 | bool dc_query_ddc_data( |
999 | struct dc *dc, | |
1000 | uint32_t link_index, | |
1001 | uint32_t address, | |
1002 | uint8_t *write_buf, | |
1003 | uint32_t write_size, | |
1004 | uint8_t *read_buf, | |
1005 | uint32_t read_size); | |
4562236b HW |
1006 | |
1007 | bool dc_submit_i2c( | |
1008 | struct dc *dc, | |
1009 | uint32_t link_index, | |
1010 | struct i2c_command *cmd); | |
1011 | ||
5e7773a2 | 1012 | |
4562236b | 1013 | #endif /* DC_INTERFACE_H_ */ |