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4562236b HW |
1 | /* |
2 | * Copyright 2012-14 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef DC_INTERFACE_H_ | |
27 | #define DC_INTERFACE_H_ | |
28 | ||
29 | #include "dc_types.h" | |
4562236b HW |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" | |
32 | #include "gpio_types.h" | |
33 | #include "link_service_types.h" | |
34 | ||
091a97e5 | 35 | #define MAX_SURFACES 3 |
ab2541b6 | 36 | #define MAX_STREAMS 6 |
4562236b HW |
37 | #define MAX_SINKS_PER_LINK 4 |
38 | ||
39 | /******************************************************************************* | |
40 | * Display Core Interfaces | |
41 | ******************************************************************************/ | |
42 | ||
43 | struct dc_caps { | |
ab2541b6 | 44 | uint32_t max_streams; |
4562236b HW |
45 | uint32_t max_links; |
46 | uint32_t max_audios; | |
47 | uint32_t max_slave_planes; | |
d4e13b0d | 48 | uint32_t max_surfaces; |
4562236b HW |
49 | uint32_t max_downscale_ratio; |
50 | uint32_t i2c_speed_in_khz; | |
a37656b9 TC |
51 | |
52 | unsigned int max_cursor_size; | |
4562236b HW |
53 | }; |
54 | ||
55 | ||
56 | struct dc_dcc_surface_param { | |
57 | enum surface_pixel_format format; | |
58 | struct dc_size surface_size; | |
2c8ad2d5 | 59 | enum swizzle_mode_values swizzle_mode; |
4562236b HW |
60 | enum dc_scan_direction scan; |
61 | }; | |
62 | ||
63 | struct dc_dcc_setting { | |
64 | unsigned int max_compressed_blk_size; | |
65 | unsigned int max_uncompressed_blk_size; | |
66 | bool independent_64b_blks; | |
67 | }; | |
68 | ||
69 | struct dc_surface_dcc_cap { | |
70 | bool capable; | |
71 | bool const_color_support; | |
72 | ||
73 | union { | |
74 | struct { | |
75 | struct dc_dcc_setting rgb; | |
76 | } grph; | |
77 | ||
78 | struct { | |
79 | struct dc_dcc_setting luma; | |
80 | struct dc_dcc_setting chroma; | |
81 | } video; | |
82 | }; | |
83 | }; | |
84 | ||
85 | /* Forward declaration*/ | |
86 | struct dc; | |
87 | struct dc_surface; | |
88 | struct validate_context; | |
89 | ||
90 | struct dc_cap_funcs { | |
91 | int i; | |
92 | }; | |
93 | ||
94 | struct dc_stream_funcs { | |
95 | bool (*adjust_vmin_vmax)(struct dc *dc, | |
96 | const struct dc_stream **stream, | |
97 | int num_streams, | |
98 | int vmin, | |
99 | int vmax); | |
100 | ||
101 | void (*stream_update_scaling)(const struct dc *dc, | |
102 | const struct dc_stream *dc_stream, | |
103 | const struct rect *src, | |
104 | const struct rect *dst); | |
105 | bool (*set_gamut_remap)(struct dc *dc, | |
106 | const struct dc_stream **stream, int num_streams); | |
4562236b HW |
107 | bool (*set_psr_enable)(struct dc *dc, bool enable); |
108 | bool (*setup_psr)(struct dc *dc, const struct dc_stream *stream); | |
109 | }; | |
110 | ||
111 | struct link_training_settings; | |
112 | ||
113 | struct dc_link_funcs { | |
114 | void (*set_drive_settings)(struct dc *dc, | |
bf5cda33 HW |
115 | struct link_training_settings *lt_settings, |
116 | const struct dc_link *link); | |
4562236b HW |
117 | void (*perform_link_training)(struct dc *dc, |
118 | struct dc_link_settings *link_setting, | |
119 | bool skip_video_pattern); | |
120 | void (*set_preferred_link_settings)(struct dc *dc, | |
88639168 ZF |
121 | struct dc_link_settings *link_setting, |
122 | const struct dc_link *link); | |
4562236b HW |
123 | void (*enable_hpd)(const struct dc_link *link); |
124 | void (*disable_hpd)(const struct dc_link *link); | |
125 | void (*set_test_pattern)( | |
126 | const struct dc_link *link, | |
127 | enum dp_test_pattern test_pattern, | |
128 | const struct link_training_settings *p_link_settings, | |
129 | const unsigned char *p_custom_pattern, | |
130 | unsigned int cust_pattern_size); | |
131 | }; | |
132 | ||
133 | /* Structure to hold configuration flags set by dm at dc creation. */ | |
134 | struct dc_config { | |
135 | bool gpu_vm_support; | |
136 | bool disable_disp_pll_sharing; | |
137 | }; | |
138 | ||
139 | struct dc_debug { | |
140 | bool surface_visual_confirm; | |
141 | bool max_disp_clk; | |
4562236b | 142 | bool surface_trace; |
9474980a | 143 | bool timing_trace; |
4562236b HW |
144 | bool validation_trace; |
145 | bool disable_stutter; | |
146 | bool disable_dcc; | |
147 | bool disable_dfs_bypass; | |
2c8ad2d5 | 148 | bool disable_pplib_clock_request; |
4562236b | 149 | bool disable_clock_gate; |
aa66df58 | 150 | bool disable_dmcu; |
70814f6f | 151 | bool force_abm_enable; |
4562236b HW |
152 | }; |
153 | ||
154 | struct dc { | |
155 | struct dc_caps caps; | |
156 | struct dc_cap_funcs cap_funcs; | |
157 | struct dc_stream_funcs stream_funcs; | |
158 | struct dc_link_funcs link_funcs; | |
159 | struct dc_config config; | |
160 | struct dc_debug debug; | |
161 | }; | |
162 | ||
2c8ad2d5 AD |
163 | enum frame_buffer_mode { |
164 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, | |
165 | FRAME_BUFFER_MODE_ZFB_ONLY, | |
166 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, | |
167 | } ; | |
168 | ||
169 | struct dchub_init_data { | |
170 | bool dchub_initialzied; | |
171 | bool dchub_info_valid; | |
172 | int64_t zfb_phys_addr_base; | |
173 | int64_t zfb_mc_base_addr; | |
174 | uint64_t zfb_size_in_byte; | |
175 | enum frame_buffer_mode fb_mode; | |
176 | }; | |
2c8ad2d5 | 177 | |
4562236b HW |
178 | struct dc_init_data { |
179 | struct hw_asic_id asic_id; | |
180 | void *driver; /* ctx */ | |
181 | struct cgs_device *cgs_device; | |
182 | ||
183 | int num_virtual_links; | |
184 | /* | |
185 | * If 'vbios_override' not NULL, it will be called instead | |
186 | * of the real VBIOS. Intended use is Diagnostics on FPGA. | |
187 | */ | |
188 | struct dc_bios *vbios_override; | |
189 | enum dce_environment dce_environment; | |
190 | ||
191 | struct dc_config flags; | |
192 | }; | |
193 | ||
194 | struct dc *dc_create(const struct dc_init_data *init_params); | |
195 | ||
196 | void dc_destroy(struct dc **dc); | |
197 | ||
2c8ad2d5 | 198 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); |
2c8ad2d5 | 199 | |
4562236b HW |
200 | /******************************************************************************* |
201 | * Surface Interfaces | |
202 | ******************************************************************************/ | |
203 | ||
204 | enum { | |
fb735a9f | 205 | TRANSFER_FUNC_POINTS = 1025 |
4562236b HW |
206 | }; |
207 | ||
1646a6fe | 208 | struct dc_hdr_static_metadata { |
70063a59 | 209 | bool hdr_supported; |
1646a6fe AW |
210 | bool is_hdr; |
211 | ||
212 | /* display chromaticities and white point in units of 0.00001 */ | |
213 | unsigned int chromaticity_green_x; | |
214 | unsigned int chromaticity_green_y; | |
215 | unsigned int chromaticity_blue_x; | |
216 | unsigned int chromaticity_blue_y; | |
217 | unsigned int chromaticity_red_x; | |
218 | unsigned int chromaticity_red_y; | |
219 | unsigned int chromaticity_white_point_x; | |
220 | unsigned int chromaticity_white_point_y; | |
221 | ||
222 | uint32_t min_luminance; | |
223 | uint32_t max_luminance; | |
224 | uint32_t maximum_content_light_level; | |
225 | uint32_t maximum_frame_average_light_level; | |
226 | }; | |
227 | ||
fb735a9f AK |
228 | enum dc_transfer_func_type { |
229 | TF_TYPE_PREDEFINED, | |
230 | TF_TYPE_DISTRIBUTED_POINTS, | |
70063a59 | 231 | TF_TYPE_BYPASS |
fb735a9f AK |
232 | }; |
233 | ||
234 | struct dc_transfer_func_distributed_points { | |
fcd2f4bf AZ |
235 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
236 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; | |
237 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; | |
238 | ||
fb735a9f | 239 | uint16_t end_exponent; |
fcd2f4bf AZ |
240 | uint16_t x_point_at_y1_red; |
241 | uint16_t x_point_at_y1_green; | |
242 | uint16_t x_point_at_y1_blue; | |
fb735a9f AK |
243 | }; |
244 | ||
245 | enum dc_transfer_func_predefined { | |
246 | TRANSFER_FUNCTION_SRGB, | |
247 | TRANSFER_FUNCTION_BT709, | |
90e508ba | 248 | TRANSFER_FUNCTION_PQ, |
fb735a9f AK |
249 | TRANSFER_FUNCTION_LINEAR, |
250 | }; | |
251 | ||
252 | struct dc_transfer_func { | |
253 | enum dc_transfer_func_type type; | |
254 | enum dc_transfer_func_predefined tf; | |
255 | struct dc_transfer_func_distributed_points tf_pts; | |
256 | }; | |
257 | ||
4562236b HW |
258 | struct dc_surface { |
259 | bool visible; | |
260 | bool flip_immediate; | |
261 | struct dc_plane_address address; | |
262 | ||
263 | struct scaling_taps scaling_quality; | |
264 | struct rect src_rect; | |
265 | struct rect dst_rect; | |
266 | struct rect clip_rect; | |
267 | ||
268 | union plane_size plane_size; | |
269 | union dc_tiling_info tiling_info; | |
270 | struct dc_plane_dcc_param dcc; | |
271 | enum dc_color_space color_space; | |
272 | ||
273 | enum surface_pixel_format format; | |
274 | enum dc_rotation_angle rotation; | |
275 | bool horizontal_mirror; | |
276 | enum plane_stereo_format stereo_format; | |
277 | ||
1646a6fe AW |
278 | struct dc_hdr_static_metadata hdr_static_ctx; |
279 | ||
4562236b | 280 | const struct dc_gamma *gamma_correction; |
fb735a9f | 281 | const struct dc_transfer_func *in_transfer_func; |
4562236b HW |
282 | }; |
283 | ||
284 | struct dc_plane_info { | |
285 | union plane_size plane_size; | |
286 | union dc_tiling_info tiling_info; | |
9cd09bfe | 287 | struct dc_plane_dcc_param dcc; |
4562236b HW |
288 | enum surface_pixel_format format; |
289 | enum dc_rotation_angle rotation; | |
290 | bool horizontal_mirror; | |
291 | enum plane_stereo_format stereo_format; | |
292 | enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ | |
293 | bool visible; | |
294 | }; | |
295 | ||
296 | struct dc_scaling_info { | |
297 | struct rect src_rect; | |
298 | struct rect dst_rect; | |
299 | struct rect clip_rect; | |
300 | struct scaling_taps scaling_quality; | |
301 | }; | |
302 | ||
303 | struct dc_surface_update { | |
304 | const struct dc_surface *surface; | |
305 | ||
306 | /* isr safe update parameters. null means no updates */ | |
307 | struct dc_flip_addrs *flip_addr; | |
308 | struct dc_plane_info *plane_info; | |
309 | struct dc_scaling_info *scaling_info; | |
310 | /* following updates require alloc/sleep/spin that is not isr safe, | |
311 | * null means no updates | |
312 | */ | |
fb735a9f | 313 | /* gamma TO BE REMOVED */ |
4562236b | 314 | struct dc_gamma *gamma; |
1646a6fe | 315 | struct dc_hdr_static_metadata *hdr_static_metadata; |
fb735a9f AK |
316 | struct dc_transfer_func *in_transfer_func; |
317 | struct dc_transfer_func *out_transfer_func; | |
318 | ||
4562236b HW |
319 | |
320 | }; | |
321 | /* | |
322 | * This structure is filled in by dc_surface_get_status and contains | |
323 | * the last requested address and the currently active address so the called | |
324 | * can determine if there are any outstanding flips | |
325 | */ | |
326 | struct dc_surface_status { | |
327 | struct dc_plane_address requested_address; | |
328 | struct dc_plane_address current_address; | |
329 | bool is_flip_pending; | |
330 | }; | |
331 | ||
332 | /* | |
333 | * Create a new surface with default parameters; | |
334 | */ | |
335 | struct dc_surface *dc_create_surface(const struct dc *dc); | |
336 | const struct dc_surface_status *dc_surface_get_status( | |
337 | const struct dc_surface *dc_surface); | |
338 | ||
339 | void dc_surface_retain(const struct dc_surface *dc_surface); | |
340 | void dc_surface_release(const struct dc_surface *dc_surface); | |
341 | ||
89e89630 | 342 | void dc_gamma_retain(const struct dc_gamma *dc_gamma); |
aff20230 | 343 | void dc_gamma_release(const struct dc_gamma **dc_gamma); |
4562236b HW |
344 | struct dc_gamma *dc_create_gamma(void); |
345 | ||
fb735a9f AK |
346 | void dc_transfer_func_retain(const struct dc_transfer_func *dc_tf); |
347 | void dc_transfer_func_release(const struct dc_transfer_func *dc_tf); | |
90e508ba | 348 | struct dc_transfer_func *dc_create_transfer_func(void); |
fb735a9f | 349 | |
4562236b HW |
350 | /* |
351 | * This structure holds a surface address. There could be multiple addresses | |
352 | * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such | |
353 | * as frame durations and DCC format can also be set. | |
354 | */ | |
355 | struct dc_flip_addrs { | |
356 | struct dc_plane_address address; | |
357 | bool flip_immediate; | |
4562236b HW |
358 | /* TODO: add flip duration for FreeSync */ |
359 | }; | |
360 | ||
361 | /* | |
362 | * Optimized flip address update function. | |
363 | * | |
364 | * After this call: | |
365 | * Surface addresses and flip attributes are programmed. | |
366 | * Surface flip occur at next configured time (h_sync or v_sync flip) | |
367 | */ | |
368 | void dc_flip_surface_addrs(struct dc *dc, | |
369 | const struct dc_surface *const surfaces[], | |
370 | struct dc_flip_addrs flip_addrs[], | |
371 | uint32_t count); | |
372 | ||
373 | /* | |
ab2541b6 AC |
374 | * Set up surface attributes and associate to a stream |
375 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
376 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
4562236b HW |
377 | * Any flip related attribute changes must be done through this interface. |
378 | * | |
379 | * After this call: | |
ab2541b6 | 380 | * Surfaces attributes are programmed and configured to be composed into stream. |
4562236b HW |
381 | * This does not trigger a flip. No surface address is programmed. |
382 | */ | |
383 | ||
ab2541b6 | 384 | bool dc_commit_surfaces_to_stream( |
4562236b HW |
385 | struct dc *dc, |
386 | const struct dc_surface **dc_surfaces, | |
387 | uint8_t surface_count, | |
ab2541b6 | 388 | const struct dc_stream *stream); |
4562236b | 389 | |
ab2541b6 | 390 | bool dc_pre_update_surfaces_to_stream( |
4562236b HW |
391 | struct dc *dc, |
392 | const struct dc_surface *const *new_surfaces, | |
393 | uint8_t new_surface_count, | |
ab2541b6 | 394 | const struct dc_stream *stream); |
4562236b | 395 | |
ab2541b6 | 396 | bool dc_post_update_surfaces_to_stream( |
4562236b HW |
397 | struct dc *dc); |
398 | ||
ab2541b6 AC |
399 | void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, |
400 | int surface_count, const struct dc_stream *stream); | |
4562236b | 401 | |
5869b0f6 LE |
402 | enum surface_update_type { |
403 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ | |
404 | UPDATE_TYPE_MED, /* a lot of programming needed. may need to alloc */ | |
405 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ | |
406 | }; | |
407 | ||
4562236b | 408 | /******************************************************************************* |
ab2541b6 | 409 | * Stream Interfaces |
4562236b | 410 | ******************************************************************************/ |
ab2541b6 AC |
411 | struct dc_stream { |
412 | const struct dc_sink *sink; | |
413 | struct dc_crtc_timing timing; | |
4562236b | 414 | |
ab2541b6 | 415 | enum dc_color_space output_color_space; |
4562236b | 416 | |
ab2541b6 AC |
417 | struct rect src; /* composition area */ |
418 | struct rect dst; /* stream addressable area */ | |
4562236b | 419 | |
ab2541b6 AC |
420 | struct audio_info audio_info; |
421 | ||
422 | bool ignore_msa_timing_param; | |
423 | ||
424 | struct freesync_context freesync_ctx; | |
425 | ||
426 | const struct dc_transfer_func *out_transfer_func; | |
427 | struct colorspace_transform gamut_remap_matrix; | |
428 | struct csc_transform csc_color_matrix; | |
429 | ||
430 | /* TODO: dithering */ | |
431 | /* TODO: custom INFO packets */ | |
432 | /* TODO: ABM info (DMCU) */ | |
433 | /* TODO: PSR info */ | |
434 | /* TODO: CEA VIC */ | |
435 | }; | |
4562236b | 436 | |
a783e7b5 LE |
437 | struct dc_stream_update { |
438 | ||
439 | struct rect src; | |
440 | ||
441 | struct rect dst; | |
442 | ||
443 | }; | |
444 | ||
445 | ||
446 | /* | |
447 | * Setup stream attributes if no stream updates are provided | |
448 | * there will be no impact on the stream parameters | |
449 | * | |
450 | * Set up surface attributes and associate to a stream | |
451 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
452 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
453 | * Any flip related attribute changes must be done through this interface. | |
454 | * | |
455 | * After this call: | |
456 | * Surfaces attributes are programmed and configured to be composed into stream. | |
457 | * This does not trigger a flip. No surface address is programmed. | |
458 | * | |
459 | */ | |
460 | ||
461 | void dc_update_surfaces_and_stream(struct dc *dc, | |
462 | struct dc_surface_update *surface_updates, int surface_count, | |
463 | const struct dc_stream *dc_stream, | |
464 | struct dc_stream_update *stream_update); | |
465 | ||
4562236b | 466 | /* |
ab2541b6 | 467 | * Log the current stream state. |
4562236b | 468 | */ |
ab2541b6 AC |
469 | void dc_stream_log( |
470 | const struct dc_stream *stream, | |
4562236b HW |
471 | struct dal_logger *dc_logger, |
472 | enum dc_log_type log_type); | |
473 | ||
ab2541b6 AC |
474 | uint8_t dc_get_current_stream_count(const struct dc *dc); |
475 | struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); | |
4562236b | 476 | |
ab2541b6 AC |
477 | /* |
478 | * Return the current frame counter. | |
479 | */ | |
480 | uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); | |
4562236b HW |
481 | |
482 | /* TODO: Return parsed values rather than direct register read | |
483 | * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) | |
484 | * being refactored properly to be dce-specific | |
485 | */ | |
ab2541b6 AC |
486 | uint32_t dc_stream_get_scanoutpos( |
487 | const struct dc_stream *stream, uint32_t *vbl, uint32_t *position); | |
4562236b HW |
488 | |
489 | /* | |
ab2541b6 | 490 | * Structure to store surface/stream associations for validation |
4562236b HW |
491 | */ |
492 | struct dc_validation_set { | |
ab2541b6 | 493 | const struct dc_stream *stream; |
4562236b HW |
494 | const struct dc_surface *surfaces[MAX_SURFACES]; |
495 | uint8_t surface_count; | |
496 | }; | |
497 | ||
498 | /* | |
499 | * This function takes a set of resources and checks that they are cofunctional. | |
500 | * | |
501 | * After this call: | |
502 | * No hardware is programmed for call. Only validation is done. | |
503 | */ | |
504 | bool dc_validate_resources( | |
505 | const struct dc *dc, | |
506 | const struct dc_validation_set set[], | |
507 | uint8_t set_count); | |
508 | ||
509 | /* | |
ab2541b6 AC |
510 | * This function takes a stream and checks if it is guaranteed to be supported. |
511 | * Guaranteed means that MAX_COFUNC similar streams are supported. | |
4562236b HW |
512 | * |
513 | * After this call: | |
514 | * No hardware is programmed for call. Only validation is done. | |
515 | */ | |
516 | ||
517 | bool dc_validate_guaranteed( | |
518 | const struct dc *dc, | |
ab2541b6 | 519 | const struct dc_stream *stream); |
4562236b HW |
520 | |
521 | /* | |
ab2541b6 AC |
522 | * Set up streams and links associated to drive sinks |
523 | * The streams parameter is an absolute set of all active streams. | |
4562236b HW |
524 | * |
525 | * After this call: | |
526 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
ab2541b6 | 527 | * New streams are enabled with blank stream; no memory read. |
4562236b | 528 | */ |
ab2541b6 | 529 | bool dc_commit_streams( |
4562236b | 530 | struct dc *dc, |
ab2541b6 AC |
531 | const struct dc_stream *streams[], |
532 | uint8_t stream_count); | |
4562236b HW |
533 | |
534 | /** | |
535 | * Create a new default stream for the requested sink | |
536 | */ | |
537 | struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink); | |
538 | ||
539 | void dc_stream_retain(const struct dc_stream *dc_stream); | |
540 | void dc_stream_release(const struct dc_stream *dc_stream); | |
541 | ||
542 | struct dc_stream_status { | |
ab2541b6 AC |
543 | int primary_otg_inst; |
544 | int surface_count; | |
545 | const struct dc_surface *surfaces[MAX_SURFACE_NUM]; | |
546 | ||
4562236b HW |
547 | /* |
548 | * link this stream passes through | |
549 | */ | |
550 | const struct dc_link *link; | |
551 | }; | |
552 | ||
553 | const struct dc_stream_status *dc_stream_get_status( | |
554 | const struct dc_stream *dc_stream); | |
555 | ||
5869b0f6 LE |
556 | enum surface_update_type dc_check_update_surfaces_for_stream( |
557 | struct dc *dc, | |
558 | struct dc_surface_update *updates, | |
559 | int surface_count, | |
ee8f63e1 | 560 | struct dc_stream_update *stream_update, |
5869b0f6 LE |
561 | const struct dc_stream_status *stream_status); |
562 | ||
4562236b HW |
563 | /******************************************************************************* |
564 | * Link Interfaces | |
565 | ******************************************************************************/ | |
566 | ||
567 | /* | |
568 | * A link contains one or more sinks and their connected status. | |
569 | * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. | |
570 | */ | |
571 | struct dc_link { | |
572 | const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; | |
573 | unsigned int sink_count; | |
574 | const struct dc_sink *local_sink; | |
575 | unsigned int link_index; | |
576 | enum dc_connection_type type; | |
577 | enum signal_type connector_signal; | |
578 | enum dc_irq_source irq_source_hpd; | |
579 | enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ | |
580 | /* caps is the same as reported_link_cap. link_traing use | |
581 | * reported_link_cap. Will clean up. TODO | |
582 | */ | |
583 | struct dc_link_settings reported_link_cap; | |
584 | struct dc_link_settings verified_link_cap; | |
585 | struct dc_link_settings max_link_setting; | |
586 | struct dc_link_settings cur_link_settings; | |
587 | struct dc_lane_settings cur_lane_setting; | |
588 | ||
589 | uint8_t ddc_hw_inst; | |
590 | uint8_t link_enc_hw_inst; | |
591 | ||
592 | struct psr_caps psr_caps; | |
593 | bool test_pattern_enabled; | |
594 | union compliance_test_state compliance_test_state; | |
9fb8de78 AG |
595 | |
596 | void *priv; | |
4562236b HW |
597 | }; |
598 | ||
599 | struct dpcd_caps { | |
600 | union dpcd_rev dpcd_rev; | |
601 | union max_lane_count max_ln_count; | |
602 | union max_down_spread max_down_spread; | |
603 | ||
604 | /* dongle type (DP converter, CV smart dongle) */ | |
605 | enum display_dongle_type dongle_type; | |
606 | /* Dongle's downstream count. */ | |
607 | union sink_count sink_count; | |
608 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, | |
609 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
610 | bool is_dp_hdmi_s3d_converter; | |
611 | ||
612 | bool allow_invalid_MSA_timing_param; | |
613 | bool panel_mode_edp; | |
614 | uint32_t sink_dev_id; | |
615 | uint32_t branch_dev_id; | |
616 | int8_t branch_dev_name[6]; | |
617 | int8_t branch_hw_revision; | |
618 | }; | |
619 | ||
620 | struct dc_link_status { | |
621 | struct dpcd_caps *dpcd_caps; | |
622 | }; | |
623 | ||
624 | const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); | |
625 | ||
626 | /* | |
627 | * Return an enumerated dc_link. dc_link order is constant and determined at | |
628 | * boot time. They cannot be created or destroyed. | |
629 | * Use dc_get_caps() to get number of links. | |
630 | */ | |
631 | const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); | |
632 | ||
633 | /* Return id of physical connector represented by a dc_link at link_index.*/ | |
634 | const struct graphics_object_id dc_get_link_id_at_index( | |
635 | struct dc *dc, uint32_t link_index); | |
636 | ||
637 | /* Set backlight level of an embedded panel (eDP, LVDS). */ | |
638 | bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, | |
639 | uint32_t frame_ramp, const struct dc_stream *stream); | |
640 | ||
4562236b HW |
641 | bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); |
642 | ||
643 | bool dc_link_setup_psr(const struct dc_link *dc_link, | |
644 | const struct dc_stream *stream); | |
645 | ||
646 | /* Request DC to detect if there is a Panel connected. | |
647 | * boot - If this call is during initial boot. | |
648 | * Return false for any type of detection failure or MST detection | |
649 | * true otherwise. True meaning further action is required (status update | |
650 | * and OS notification). | |
651 | */ | |
652 | bool dc_link_detect(const struct dc_link *dc_link, bool boot); | |
653 | ||
654 | /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). | |
655 | * Return: | |
656 | * true - Downstream port status changed. DM should call DC to do the | |
657 | * detection. | |
658 | * false - no change in Downstream port status. No further action required | |
659 | * from DM. */ | |
660 | bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link); | |
661 | ||
662 | struct dc_sink_init_data; | |
663 | ||
664 | struct dc_sink *dc_link_add_remote_sink( | |
665 | const struct dc_link *dc_link, | |
666 | const uint8_t *edid, | |
667 | int len, | |
668 | struct dc_sink_init_data *init_data); | |
669 | ||
670 | void dc_link_remove_remote_sink( | |
671 | const struct dc_link *link, | |
672 | const struct dc_sink *sink); | |
673 | ||
674 | /* Used by diagnostics for virtual link at the moment */ | |
675 | void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink); | |
676 | ||
677 | void dc_link_dp_set_drive_settings( | |
678 | struct dc_link *link, | |
679 | struct link_training_settings *lt_settings); | |
680 | ||
681 | bool dc_link_dp_perform_link_training( | |
682 | struct dc_link *link, | |
683 | const struct dc_link_settings *link_setting, | |
684 | bool skip_video_pattern); | |
685 | ||
686 | void dc_link_dp_enable_hpd(const struct dc_link *link); | |
687 | ||
688 | void dc_link_dp_disable_hpd(const struct dc_link *link); | |
689 | ||
690 | bool dc_link_dp_set_test_pattern( | |
691 | const struct dc_link *link, | |
692 | enum dp_test_pattern test_pattern, | |
693 | const struct link_training_settings *p_link_settings, | |
694 | const unsigned char *p_custom_pattern, | |
695 | unsigned int cust_pattern_size); | |
696 | ||
697 | /******************************************************************************* | |
698 | * Sink Interfaces - A sink corresponds to a display output device | |
699 | ******************************************************************************/ | |
700 | ||
8c895313 | 701 | struct dc_container_id { |
702 | // 128bit GUID in binary form | |
703 | unsigned char guid[16]; | |
704 | // 8 byte port ID -> ELD.PortID | |
705 | unsigned int portId[2]; | |
706 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName | |
707 | unsigned short manufacturerName; | |
708 | // 2 byte product code -> ELD.ProductCode | |
709 | unsigned short productCode; | |
710 | }; | |
711 | ||
4562236b HW |
712 | /* |
713 | * The sink structure contains EDID and other display device properties | |
714 | */ | |
715 | struct dc_sink { | |
716 | enum signal_type sink_signal; | |
717 | struct dc_edid dc_edid; /* raw edid */ | |
718 | struct dc_edid_caps edid_caps; /* parse display caps */ | |
8c895313 | 719 | struct dc_container_id *dc_container_id; |
4a9a5d62 ZF |
720 | uint32_t dongle_max_pix_clk; |
721 | bool converter_disable_audio; | |
4562236b HW |
722 | }; |
723 | ||
724 | void dc_sink_retain(const struct dc_sink *sink); | |
725 | void dc_sink_release(const struct dc_sink *sink); | |
726 | ||
727 | const struct audio **dc_get_audios(struct dc *dc); | |
728 | ||
729 | struct dc_sink_init_data { | |
730 | enum signal_type sink_signal; | |
731 | const struct dc_link *link; | |
732 | uint32_t dongle_max_pix_clk; | |
733 | bool converter_disable_audio; | |
734 | }; | |
735 | ||
736 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); | |
8c895313 | 737 | bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id); |
738 | bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id); | |
4562236b HW |
739 | |
740 | /******************************************************************************* | |
ab2541b6 | 741 | * Cursor interfaces - To manages the cursor within a stream |
4562236b HW |
742 | ******************************************************************************/ |
743 | /* TODO: Deprecated once we switch to dc_set_cursor_position */ | |
ab2541b6 AC |
744 | bool dc_stream_set_cursor_attributes( |
745 | const struct dc_stream *stream, | |
4562236b HW |
746 | const struct dc_cursor_attributes *attributes); |
747 | ||
ab2541b6 AC |
748 | bool dc_stream_set_cursor_position( |
749 | const struct dc_stream *stream, | |
dabb3979 | 750 | struct dc_cursor_position *position); |
4562236b HW |
751 | |
752 | /* Newer interfaces */ | |
753 | struct dc_cursor { | |
754 | struct dc_plane_address address; | |
755 | struct dc_cursor_attributes attributes; | |
756 | }; | |
757 | ||
4562236b HW |
758 | /******************************************************************************* |
759 | * Interrupt interfaces | |
760 | ******************************************************************************/ | |
761 | enum dc_irq_source dc_interrupt_to_irq_source( | |
762 | struct dc *dc, | |
763 | uint32_t src_id, | |
764 | uint32_t ext_id); | |
765 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); | |
766 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); | |
767 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
768 | struct dc *dc, uint32_t link_index); | |
769 | ||
770 | /******************************************************************************* | |
771 | * Power Interfaces | |
772 | ******************************************************************************/ | |
773 | ||
774 | void dc_set_power_state( | |
775 | struct dc *dc, | |
a3621485 | 776 | enum dc_acpi_cm_power_state power_state); |
4562236b HW |
777 | void dc_resume(const struct dc *dc); |
778 | ||
779 | /******************************************************************************* | |
780 | * DDC Interfaces | |
781 | ******************************************************************************/ | |
782 | ||
783 | const struct ddc_service *dc_get_ddc_at_index( | |
784 | struct dc *dc, uint32_t link_index); | |
785 | ||
786 | /* | |
787 | * DPCD access interfaces | |
788 | */ | |
789 | ||
790 | bool dc_read_dpcd( | |
791 | struct dc *dc, | |
792 | uint32_t link_index, | |
793 | uint32_t address, | |
794 | uint8_t *data, | |
795 | uint32_t size); | |
796 | ||
797 | bool dc_write_dpcd( | |
798 | struct dc *dc, | |
799 | uint32_t link_index, | |
800 | uint32_t address, | |
801 | const uint8_t *data, | |
2b230ea3 ZF |
802 | uint32_t size); |
803 | ||
804 | bool dc_query_ddc_data( | |
805 | struct dc *dc, | |
806 | uint32_t link_index, | |
807 | uint32_t address, | |
808 | uint8_t *write_buf, | |
809 | uint32_t write_size, | |
810 | uint8_t *read_buf, | |
811 | uint32_t read_size); | |
4562236b HW |
812 | |
813 | bool dc_submit_i2c( | |
814 | struct dc *dc, | |
815 | uint32_t link_index, | |
816 | struct i2c_command *cmd); | |
817 | ||
5e7773a2 | 818 | |
4562236b | 819 | #endif /* DC_INTERFACE_H_ */ |