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4562236b HW |
1 | /* |
2 | * Copyright 2012-14 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef DC_INTERFACE_H_ | |
27 | #define DC_INTERFACE_H_ | |
28 | ||
29 | #include "dc_types.h" | |
4562236b HW |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" | |
32 | #include "gpio_types.h" | |
33 | #include "link_service_types.h" | |
d0778ebf | 34 | #include "grph_object_ctrl_defs.h" |
4fa086b9 | 35 | #include <inc/hw/opp.h> |
4562236b | 36 | |
091a97e5 | 37 | #define MAX_SURFACES 3 |
ab2541b6 | 38 | #define MAX_STREAMS 6 |
4562236b HW |
39 | #define MAX_SINKS_PER_LINK 4 |
40 | ||
41 | /******************************************************************************* | |
42 | * Display Core Interfaces | |
43 | ******************************************************************************/ | |
44 | ||
45 | struct dc_caps { | |
ab2541b6 | 46 | uint32_t max_streams; |
4562236b HW |
47 | uint32_t max_links; |
48 | uint32_t max_audios; | |
49 | uint32_t max_slave_planes; | |
d4e13b0d | 50 | uint32_t max_surfaces; |
4562236b HW |
51 | uint32_t max_downscale_ratio; |
52 | uint32_t i2c_speed_in_khz; | |
a37656b9 TC |
53 | |
54 | unsigned int max_cursor_size; | |
4562236b HW |
55 | }; |
56 | ||
57 | ||
58 | struct dc_dcc_surface_param { | |
4562236b | 59 | struct dc_size surface_size; |
ebf055f9 | 60 | enum surface_pixel_format format; |
2c8ad2d5 | 61 | enum swizzle_mode_values swizzle_mode; |
4562236b HW |
62 | enum dc_scan_direction scan; |
63 | }; | |
64 | ||
65 | struct dc_dcc_setting { | |
66 | unsigned int max_compressed_blk_size; | |
67 | unsigned int max_uncompressed_blk_size; | |
68 | bool independent_64b_blks; | |
69 | }; | |
70 | ||
71 | struct dc_surface_dcc_cap { | |
4562236b HW |
72 | union { |
73 | struct { | |
74 | struct dc_dcc_setting rgb; | |
75 | } grph; | |
76 | ||
77 | struct { | |
78 | struct dc_dcc_setting luma; | |
79 | struct dc_dcc_setting chroma; | |
80 | } video; | |
81 | }; | |
ebf055f9 AK |
82 | |
83 | bool capable; | |
84 | bool const_color_support; | |
4562236b HW |
85 | }; |
86 | ||
94267b3d ST |
87 | struct dc_static_screen_events { |
88 | bool cursor_update; | |
89 | bool surface_update; | |
90 | bool overlay_update; | |
91 | }; | |
92 | ||
4562236b HW |
93 | /* Forward declaration*/ |
94 | struct dc; | |
95 | struct dc_surface; | |
96 | struct validate_context; | |
97 | ||
98 | struct dc_cap_funcs { | |
ff5ef992 AD |
99 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
100 | bool (*get_dcc_compression_cap)(const struct dc *dc, | |
101 | const struct dc_dcc_surface_param *input, | |
102 | struct dc_surface_dcc_cap *output); | |
103 | #else | |
4562236b | 104 | int i; |
ff5ef992 | 105 | #endif |
4562236b HW |
106 | }; |
107 | ||
108 | struct dc_stream_funcs { | |
109 | bool (*adjust_vmin_vmax)(struct dc *dc, | |
4fa086b9 | 110 | struct dc_stream **stream, |
4562236b HW |
111 | int num_streams, |
112 | int vmin, | |
113 | int vmax); | |
72ada5f7 | 114 | bool (*get_crtc_position)(struct dc *dc, |
4fa086b9 | 115 | struct dc_stream **stream, |
72ada5f7 EC |
116 | int num_streams, |
117 | unsigned int *v_pos, | |
118 | unsigned int *nom_v_pos); | |
119 | ||
4562236b | 120 | bool (*set_gamut_remap)(struct dc *dc, |
f46661dd | 121 | const struct dc_stream *stream); |
94267b3d | 122 | |
abe07e80 | 123 | bool (*program_csc_matrix)(struct dc *dc, |
4fa086b9 | 124 | struct dc_stream *stream); |
abe07e80 | 125 | |
94267b3d | 126 | void (*set_static_screen_events)(struct dc *dc, |
4fa086b9 | 127 | struct dc_stream **stream, |
94267b3d ST |
128 | int num_streams, |
129 | const struct dc_static_screen_events *events); | |
529cad0f | 130 | |
4fa086b9 | 131 | void (*set_dither_option)(struct dc_stream *stream, |
529cad0f | 132 | enum dc_dither_option option); |
4562236b HW |
133 | }; |
134 | ||
135 | struct link_training_settings; | |
136 | ||
137 | struct dc_link_funcs { | |
138 | void (*set_drive_settings)(struct dc *dc, | |
bf5cda33 HW |
139 | struct link_training_settings *lt_settings, |
140 | const struct dc_link *link); | |
4562236b HW |
141 | void (*perform_link_training)(struct dc *dc, |
142 | struct dc_link_settings *link_setting, | |
143 | bool skip_video_pattern); | |
144 | void (*set_preferred_link_settings)(struct dc *dc, | |
88639168 | 145 | struct dc_link_settings *link_setting, |
d0778ebf | 146 | struct dc_link *link); |
4562236b HW |
147 | void (*enable_hpd)(const struct dc_link *link); |
148 | void (*disable_hpd)(const struct dc_link *link); | |
149 | void (*set_test_pattern)( | |
d0778ebf | 150 | struct dc_link *link, |
4562236b HW |
151 | enum dp_test_pattern test_pattern, |
152 | const struct link_training_settings *p_link_settings, | |
153 | const unsigned char *p_custom_pattern, | |
154 | unsigned int cust_pattern_size); | |
155 | }; | |
156 | ||
157 | /* Structure to hold configuration flags set by dm at dc creation. */ | |
158 | struct dc_config { | |
159 | bool gpu_vm_support; | |
160 | bool disable_disp_pll_sharing; | |
161 | }; | |
162 | ||
163 | struct dc_debug { | |
164 | bool surface_visual_confirm; | |
2b13d7d3 | 165 | bool sanity_checks; |
4562236b | 166 | bool max_disp_clk; |
4562236b | 167 | bool surface_trace; |
9474980a | 168 | bool timing_trace; |
c9742685 | 169 | bool clock_trace; |
4562236b HW |
170 | bool validation_trace; |
171 | bool disable_stutter; | |
172 | bool disable_dcc; | |
173 | bool disable_dfs_bypass; | |
ff5ef992 AD |
174 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
175 | bool disable_dpp_power_gate; | |
176 | bool disable_hubp_power_gate; | |
177 | bool disable_pplib_wm_range; | |
178 | bool use_dml_wm; | |
90f095c1 | 179 | bool disable_pipe_split; |
139cb65c DL |
180 | int sr_exit_time_dpm0_ns; |
181 | int sr_enter_plus_exit_time_dpm0_ns; | |
ff5ef992 AD |
182 | int sr_exit_time_ns; |
183 | int sr_enter_plus_exit_time_ns; | |
184 | int urgent_latency_ns; | |
185 | int percent_of_ideal_drambw; | |
186 | int dram_clock_change_latency_ns; | |
e73b59b7 | 187 | int always_scale; |
ff5ef992 | 188 | #endif |
2c8ad2d5 | 189 | bool disable_pplib_clock_request; |
4562236b | 190 | bool disable_clock_gate; |
aa66df58 | 191 | bool disable_dmcu; |
29eba8e8 | 192 | bool disable_psr; |
70814f6f | 193 | bool force_abm_enable; |
4562236b HW |
194 | }; |
195 | ||
196 | struct dc { | |
197 | struct dc_caps caps; | |
198 | struct dc_cap_funcs cap_funcs; | |
199 | struct dc_stream_funcs stream_funcs; | |
200 | struct dc_link_funcs link_funcs; | |
201 | struct dc_config config; | |
202 | struct dc_debug debug; | |
203 | }; | |
204 | ||
2c8ad2d5 AD |
205 | enum frame_buffer_mode { |
206 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, | |
207 | FRAME_BUFFER_MODE_ZFB_ONLY, | |
208 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, | |
209 | } ; | |
210 | ||
211 | struct dchub_init_data { | |
2c8ad2d5 AD |
212 | int64_t zfb_phys_addr_base; |
213 | int64_t zfb_mc_base_addr; | |
214 | uint64_t zfb_size_in_byte; | |
215 | enum frame_buffer_mode fb_mode; | |
ebf055f9 AK |
216 | bool dchub_initialzied; |
217 | bool dchub_info_valid; | |
2c8ad2d5 | 218 | }; |
2c8ad2d5 | 219 | |
4562236b HW |
220 | struct dc_init_data { |
221 | struct hw_asic_id asic_id; | |
222 | void *driver; /* ctx */ | |
223 | struct cgs_device *cgs_device; | |
224 | ||
225 | int num_virtual_links; | |
226 | /* | |
227 | * If 'vbios_override' not NULL, it will be called instead | |
228 | * of the real VBIOS. Intended use is Diagnostics on FPGA. | |
229 | */ | |
230 | struct dc_bios *vbios_override; | |
231 | enum dce_environment dce_environment; | |
232 | ||
233 | struct dc_config flags; | |
690b5e39 RL |
234 | #ifdef ENABLE_FBC |
235 | uint64_t fbc_gpu_addr; | |
236 | #endif | |
4562236b HW |
237 | }; |
238 | ||
239 | struct dc *dc_create(const struct dc_init_data *init_params); | |
240 | ||
241 | void dc_destroy(struct dc **dc); | |
242 | ||
2c8ad2d5 | 243 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); |
2c8ad2d5 | 244 | |
6d244be8 TC |
245 | void dc_log_hw_state(struct dc *dc); |
246 | ||
4562236b HW |
247 | /******************************************************************************* |
248 | * Surface Interfaces | |
249 | ******************************************************************************/ | |
250 | ||
251 | enum { | |
fb735a9f | 252 | TRANSFER_FUNC_POINTS = 1025 |
4562236b HW |
253 | }; |
254 | ||
1646a6fe | 255 | struct dc_hdr_static_metadata { |
1646a6fe AW |
256 | /* display chromaticities and white point in units of 0.00001 */ |
257 | unsigned int chromaticity_green_x; | |
258 | unsigned int chromaticity_green_y; | |
259 | unsigned int chromaticity_blue_x; | |
260 | unsigned int chromaticity_blue_y; | |
261 | unsigned int chromaticity_red_x; | |
262 | unsigned int chromaticity_red_y; | |
263 | unsigned int chromaticity_white_point_x; | |
264 | unsigned int chromaticity_white_point_y; | |
265 | ||
266 | uint32_t min_luminance; | |
267 | uint32_t max_luminance; | |
268 | uint32_t maximum_content_light_level; | |
269 | uint32_t maximum_frame_average_light_level; | |
ebf055f9 AK |
270 | |
271 | bool hdr_supported; | |
272 | bool is_hdr; | |
1646a6fe AW |
273 | }; |
274 | ||
fb735a9f AK |
275 | enum dc_transfer_func_type { |
276 | TF_TYPE_PREDEFINED, | |
277 | TF_TYPE_DISTRIBUTED_POINTS, | |
7950f0f9 | 278 | TF_TYPE_BYPASS |
fb735a9f AK |
279 | }; |
280 | ||
281 | struct dc_transfer_func_distributed_points { | |
fcd2f4bf AZ |
282 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
283 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; | |
284 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; | |
285 | ||
fb735a9f | 286 | uint16_t end_exponent; |
fcd2f4bf AZ |
287 | uint16_t x_point_at_y1_red; |
288 | uint16_t x_point_at_y1_green; | |
289 | uint16_t x_point_at_y1_blue; | |
fb735a9f AK |
290 | }; |
291 | ||
292 | enum dc_transfer_func_predefined { | |
293 | TRANSFER_FUNCTION_SRGB, | |
294 | TRANSFER_FUNCTION_BT709, | |
90e508ba | 295 | TRANSFER_FUNCTION_PQ, |
fb735a9f AK |
296 | TRANSFER_FUNCTION_LINEAR, |
297 | }; | |
298 | ||
299 | struct dc_transfer_func { | |
ebf055f9 | 300 | struct dc_transfer_func_distributed_points tf_pts; |
fb735a9f AK |
301 | enum dc_transfer_func_type type; |
302 | enum dc_transfer_func_predefined tf; | |
7b0c470f LSL |
303 | struct dc_context *ctx; |
304 | int ref_count; | |
fb735a9f AK |
305 | }; |
306 | ||
e12cfcb1 HW |
307 | /* |
308 | * This structure is filled in by dc_surface_get_status and contains | |
309 | * the last requested address and the currently active address so the called | |
310 | * can determine if there are any outstanding flips | |
311 | */ | |
312 | struct dc_surface_status { | |
313 | struct dc_plane_address requested_address; | |
314 | struct dc_plane_address current_address; | |
315 | bool is_flip_pending; | |
316 | bool is_right_eye; | |
317 | }; | |
318 | ||
4562236b | 319 | struct dc_surface { |
4562236b HW |
320 | struct dc_plane_address address; |
321 | ||
322 | struct scaling_taps scaling_quality; | |
323 | struct rect src_rect; | |
324 | struct rect dst_rect; | |
325 | struct rect clip_rect; | |
326 | ||
327 | union plane_size plane_size; | |
328 | union dc_tiling_info tiling_info; | |
ebf055f9 | 329 | |
4562236b | 330 | struct dc_plane_dcc_param dcc; |
ebf055f9 AK |
331 | struct dc_hdr_static_metadata hdr_static_ctx; |
332 | ||
7a6c4af6 | 333 | struct dc_gamma *gamma_correction; |
7b0c470f | 334 | struct dc_transfer_func *in_transfer_func; |
4562236b | 335 | |
ebf055f9 | 336 | enum dc_color_space color_space; |
4562236b HW |
337 | enum surface_pixel_format format; |
338 | enum dc_rotation_angle rotation; | |
4562236b HW |
339 | enum plane_stereo_format stereo_format; |
340 | ||
ebf055f9 AK |
341 | bool per_pixel_alpha; |
342 | bool visible; | |
343 | bool flip_immediate; | |
344 | bool horizontal_mirror; | |
e12cfcb1 HW |
345 | |
346 | /* private to DC core */ | |
347 | struct dc_surface_status status; | |
348 | struct dc_context *ctx; | |
349 | ||
350 | /* private to dc_surface.c */ | |
351 | enum dc_irq_source irq_source; | |
352 | int ref_count; | |
4562236b HW |
353 | }; |
354 | ||
355 | struct dc_plane_info { | |
356 | union plane_size plane_size; | |
357 | union dc_tiling_info tiling_info; | |
9cd09bfe | 358 | struct dc_plane_dcc_param dcc; |
4562236b HW |
359 | enum surface_pixel_format format; |
360 | enum dc_rotation_angle rotation; | |
4562236b HW |
361 | enum plane_stereo_format stereo_format; |
362 | enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ | |
ebf055f9 | 363 | bool horizontal_mirror; |
4562236b | 364 | bool visible; |
ebf055f9 | 365 | bool per_pixel_alpha; |
4562236b HW |
366 | }; |
367 | ||
368 | struct dc_scaling_info { | |
ebf055f9 AK |
369 | struct rect src_rect; |
370 | struct rect dst_rect; | |
371 | struct rect clip_rect; | |
372 | struct scaling_taps scaling_quality; | |
4562236b HW |
373 | }; |
374 | ||
375 | struct dc_surface_update { | |
e12cfcb1 | 376 | struct dc_surface *surface; |
4562236b HW |
377 | |
378 | /* isr safe update parameters. null means no updates */ | |
379 | struct dc_flip_addrs *flip_addr; | |
380 | struct dc_plane_info *plane_info; | |
381 | struct dc_scaling_info *scaling_info; | |
382 | /* following updates require alloc/sleep/spin that is not isr safe, | |
383 | * null means no updates | |
384 | */ | |
fb735a9f | 385 | /* gamma TO BE REMOVED */ |
4562236b | 386 | struct dc_gamma *gamma; |
fb735a9f | 387 | struct dc_transfer_func *in_transfer_func; |
f46661dd | 388 | struct dc_hdr_static_metadata *hdr_static_metadata; |
4562236b | 389 | }; |
4562236b HW |
390 | |
391 | /* | |
392 | * Create a new surface with default parameters; | |
393 | */ | |
394 | struct dc_surface *dc_create_surface(const struct dc *dc); | |
395 | const struct dc_surface_status *dc_surface_get_status( | |
396 | const struct dc_surface *dc_surface); | |
397 | ||
e12cfcb1 HW |
398 | void dc_surface_retain(struct dc_surface *dc_surface); |
399 | void dc_surface_release(struct dc_surface *dc_surface); | |
4562236b | 400 | |
7a6c4af6 HW |
401 | void dc_gamma_retain(struct dc_gamma *dc_gamma); |
402 | void dc_gamma_release(struct dc_gamma **dc_gamma); | |
4562236b HW |
403 | struct dc_gamma *dc_create_gamma(void); |
404 | ||
7b0c470f LSL |
405 | void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); |
406 | void dc_transfer_func_release(struct dc_transfer_func *dc_tf); | |
90e508ba | 407 | struct dc_transfer_func *dc_create_transfer_func(void); |
fb735a9f | 408 | |
4562236b HW |
409 | /* |
410 | * This structure holds a surface address. There could be multiple addresses | |
411 | * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such | |
412 | * as frame durations and DCC format can also be set. | |
413 | */ | |
414 | struct dc_flip_addrs { | |
415 | struct dc_plane_address address; | |
416 | bool flip_immediate; | |
4562236b HW |
417 | /* TODO: add flip duration for FreeSync */ |
418 | }; | |
419 | ||
4562236b | 420 | /* |
ab2541b6 AC |
421 | * Set up surface attributes and associate to a stream |
422 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
423 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
4562236b HW |
424 | * Any flip related attribute changes must be done through this interface. |
425 | * | |
426 | * After this call: | |
ab2541b6 | 427 | * Surfaces attributes are programmed and configured to be composed into stream. |
4562236b HW |
428 | * This does not trigger a flip. No surface address is programmed. |
429 | */ | |
430 | ||
ab2541b6 | 431 | bool dc_commit_surfaces_to_stream( |
4562236b | 432 | struct dc *dc, |
e12cfcb1 | 433 | struct dc_surface **dc_surfaces, |
4562236b | 434 | uint8_t surface_count, |
4fa086b9 | 435 | struct dc_stream *stream); |
4562236b | 436 | |
ab2541b6 | 437 | bool dc_post_update_surfaces_to_stream( |
4562236b HW |
438 | struct dc *dc); |
439 | ||
81e2b2de DL |
440 | /* Surface update type is used by dc_update_surfaces_and_stream |
441 | * The update type is determined at the very beginning of the function based | |
442 | * on parameters passed in and decides how much programming (or updating) is | |
443 | * going to be done during the call. | |
444 | * | |
445 | * UPDATE_TYPE_FAST is used for really fast updates that do not require much | |
446 | * logical calculations or hardware register programming. This update MUST be | |
447 | * ISR safe on windows. Currently fast update will only be used to flip surface | |
448 | * address. | |
449 | * | |
450 | * UPDATE_TYPE_MED is used for slower updates which require significant hw | |
451 | * re-programming however do not affect bandwidth consumption or clock | |
452 | * requirements. At present, this is the level at which front end updates | |
453 | * that do not require us to run bw_calcs happen. These are in/out transfer func | |
454 | * updates, viewport offset changes, recout size changes and pixel depth changes. | |
455 | * This update can be done at ISR, but we want to minimize how often this happens. | |
456 | * | |
457 | * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our | |
458 | * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front | |
459 | * end related. Any time viewport dimensions, recout dimensions, scaling ratios or | |
460 | * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do | |
461 | * a full update. This cannot be done at ISR level and should be a rare event. | |
462 | * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting | |
463 | * underscan we don't expect to see this call at all. | |
464 | */ | |
465 | ||
5869b0f6 LE |
466 | enum surface_update_type { |
467 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ | |
81e2b2de | 468 | UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ |
5869b0f6 LE |
469 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ |
470 | }; | |
471 | ||
4562236b | 472 | /******************************************************************************* |
ab2541b6 | 473 | * Stream Interfaces |
4562236b | 474 | ******************************************************************************/ |
4fa086b9 LSL |
475 | |
476 | struct dc_stream_status { | |
477 | int primary_otg_inst; | |
478 | int surface_count; | |
479 | struct dc_surface *surfaces[MAX_SURFACE_NUM]; | |
480 | ||
481 | /* | |
482 | * link this stream passes through | |
483 | */ | |
484 | struct dc_link *link; | |
485 | }; | |
486 | ||
ab2541b6 | 487 | struct dc_stream { |
b3d6c3f0 | 488 | struct dc_sink *sink; |
ab2541b6 | 489 | struct dc_crtc_timing timing; |
4562236b | 490 | |
ab2541b6 AC |
491 | struct rect src; /* composition area */ |
492 | struct rect dst; /* stream addressable area */ | |
4562236b | 493 | |
ab2541b6 AC |
494 | struct audio_info audio_info; |
495 | ||
ab2541b6 AC |
496 | struct freesync_context freesync_ctx; |
497 | ||
7b0c470f | 498 | struct dc_transfer_func *out_transfer_func; |
ab2541b6 AC |
499 | struct colorspace_transform gamut_remap_matrix; |
500 | struct csc_transform csc_color_matrix; | |
ebf055f9 AK |
501 | |
502 | enum signal_type output_signal; | |
503 | ||
504 | enum dc_color_space output_color_space; | |
505 | enum dc_dither_option dither_option; | |
506 | ||
9edba557 | 507 | enum view_3d_format view_format; |
ebf055f9 AK |
508 | |
509 | bool ignore_msa_timing_param; | |
ab2541b6 AC |
510 | /* TODO: custom INFO packets */ |
511 | /* TODO: ABM info (DMCU) */ | |
512 | /* TODO: PSR info */ | |
513 | /* TODO: CEA VIC */ | |
4fa086b9 LSL |
514 | |
515 | /* from core_stream struct */ | |
516 | struct dc_context *ctx; | |
517 | ||
518 | /* used by DCP and FMT */ | |
519 | struct bit_depth_reduction_params bit_depth_params; | |
520 | struct clamping_and_pixel_encoding_params clamping; | |
521 | ||
522 | int phy_pix_clk; | |
523 | enum signal_type signal; | |
524 | ||
525 | struct dc_stream_status status; | |
526 | ||
527 | /* from stream struct */ | |
528 | int ref_count; | |
ab2541b6 | 529 | }; |
4562236b | 530 | |
a783e7b5 | 531 | struct dc_stream_update { |
a783e7b5 | 532 | struct rect src; |
a783e7b5 | 533 | struct rect dst; |
f46661dd | 534 | struct dc_transfer_func *out_transfer_func; |
a783e7b5 LE |
535 | }; |
536 | ||
537 | ||
538 | /* | |
539 | * Setup stream attributes if no stream updates are provided | |
540 | * there will be no impact on the stream parameters | |
541 | * | |
542 | * Set up surface attributes and associate to a stream | |
543 | * The surfaces parameter is an absolute set of all surface active for the stream. | |
544 | * If no surfaces are provided, the stream will be blanked; no memory read. | |
545 | * Any flip related attribute changes must be done through this interface. | |
546 | * | |
547 | * After this call: | |
548 | * Surfaces attributes are programmed and configured to be composed into stream. | |
549 | * This does not trigger a flip. No surface address is programmed. | |
550 | * | |
551 | */ | |
552 | ||
553 | void dc_update_surfaces_and_stream(struct dc *dc, | |
554 | struct dc_surface_update *surface_updates, int surface_count, | |
4fa086b9 | 555 | struct dc_stream *dc_stream, |
a783e7b5 LE |
556 | struct dc_stream_update *stream_update); |
557 | ||
4562236b | 558 | /* |
ab2541b6 | 559 | * Log the current stream state. |
4562236b | 560 | */ |
ab2541b6 AC |
561 | void dc_stream_log( |
562 | const struct dc_stream *stream, | |
4562236b HW |
563 | struct dal_logger *dc_logger, |
564 | enum dc_log_type log_type); | |
565 | ||
ab2541b6 AC |
566 | uint8_t dc_get_current_stream_count(const struct dc *dc); |
567 | struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); | |
4562236b | 568 | |
ab2541b6 AC |
569 | /* |
570 | * Return the current frame counter. | |
571 | */ | |
572 | uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); | |
4562236b HW |
573 | |
574 | /* TODO: Return parsed values rather than direct register read | |
575 | * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) | |
576 | * being refactored properly to be dce-specific | |
577 | */ | |
81c50963 ST |
578 | bool dc_stream_get_scanoutpos(const struct dc_stream *stream, |
579 | uint32_t *v_blank_start, | |
580 | uint32_t *v_blank_end, | |
581 | uint32_t *h_position, | |
582 | uint32_t *v_position); | |
4562236b HW |
583 | |
584 | /* | |
ab2541b6 | 585 | * Structure to store surface/stream associations for validation |
4562236b HW |
586 | */ |
587 | struct dc_validation_set { | |
4fa086b9 | 588 | struct dc_stream *stream; |
e12cfcb1 | 589 | struct dc_surface *surfaces[MAX_SURFACES]; |
4562236b HW |
590 | uint8_t surface_count; |
591 | }; | |
592 | ||
4fa086b9 | 593 | bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); |
9345d987 | 594 | |
792671d7 | 595 | bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface); |
4562236b HW |
596 | /* |
597 | * This function takes a set of resources and checks that they are cofunctional. | |
598 | * | |
599 | * After this call: | |
600 | * No hardware is programmed for call. Only validation is done. | |
601 | */ | |
07d72b39 HW |
602 | struct validate_context *dc_get_validate_context( |
603 | const struct dc *dc, | |
604 | const struct dc_validation_set set[], | |
605 | uint8_t set_count); | |
606 | ||
4562236b HW |
607 | bool dc_validate_resources( |
608 | const struct dc *dc, | |
609 | const struct dc_validation_set set[], | |
610 | uint8_t set_count); | |
611 | ||
612 | /* | |
ab2541b6 AC |
613 | * This function takes a stream and checks if it is guaranteed to be supported. |
614 | * Guaranteed means that MAX_COFUNC similar streams are supported. | |
4562236b HW |
615 | * |
616 | * After this call: | |
617 | * No hardware is programmed for call. Only validation is done. | |
618 | */ | |
619 | ||
620 | bool dc_validate_guaranteed( | |
621 | const struct dc *dc, | |
4fa086b9 | 622 | struct dc_stream *stream); |
4562236b | 623 | |
8122a253 HW |
624 | void dc_resource_validate_ctx_copy_construct( |
625 | const struct validate_context *src_ctx, | |
626 | struct validate_context *dst_ctx); | |
627 | ||
628 | void dc_resource_validate_ctx_destruct(struct validate_context *context); | |
629 | ||
7cf2c840 HW |
630 | /* |
631 | * TODO update to make it about validation sets | |
632 | * Set up streams and links associated to drive sinks | |
633 | * The streams parameter is an absolute set of all active streams. | |
634 | * | |
635 | * After this call: | |
636 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
637 | * New streams are enabled with blank stream; no memory read. | |
638 | */ | |
e2c7bb12 | 639 | bool dc_commit_context(struct dc *dc, struct validate_context *context); |
7cf2c840 | 640 | |
4562236b | 641 | /* |
ab2541b6 AC |
642 | * Set up streams and links associated to drive sinks |
643 | * The streams parameter is an absolute set of all active streams. | |
4562236b HW |
644 | * |
645 | * After this call: | |
646 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
ab2541b6 | 647 | * New streams are enabled with blank stream; no memory read. |
4562236b | 648 | */ |
ab2541b6 | 649 | bool dc_commit_streams( |
4562236b | 650 | struct dc *dc, |
4fa086b9 | 651 | struct dc_stream *streams[], |
ab2541b6 | 652 | uint8_t stream_count); |
9edba557 VP |
653 | /* |
654 | * Enable stereo when commit_streams is not required, | |
655 | * for example, frame alternate. | |
656 | */ | |
657 | bool dc_enable_stereo( | |
658 | struct dc *dc, | |
659 | struct validate_context *context, | |
4fa086b9 | 660 | struct dc_stream *streams[], |
9edba557 | 661 | uint8_t stream_count); |
4562236b HW |
662 | |
663 | /** | |
664 | * Create a new default stream for the requested sink | |
665 | */ | |
b73a22d3 | 666 | struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); |
4562236b | 667 | |
4fa086b9 LSL |
668 | void dc_stream_retain(struct dc_stream *dc_stream); |
669 | void dc_stream_release(struct dc_stream *dc_stream); | |
4562236b | 670 | |
e12cfcb1 | 671 | struct dc_stream_status *dc_stream_get_status( |
4fa086b9 | 672 | struct dc_stream *dc_stream); |
4562236b | 673 | |
5869b0f6 LE |
674 | enum surface_update_type dc_check_update_surfaces_for_stream( |
675 | struct dc *dc, | |
676 | struct dc_surface_update *updates, | |
677 | int surface_count, | |
ee8f63e1 | 678 | struct dc_stream_update *stream_update, |
5869b0f6 LE |
679 | const struct dc_stream_status *stream_status); |
680 | ||
8a76708e AG |
681 | |
682 | void dc_retain_validate_context(struct validate_context *context); | |
683 | void dc_release_validate_context(struct validate_context *context); | |
684 | ||
4562236b HW |
685 | /******************************************************************************* |
686 | * Link Interfaces | |
687 | ******************************************************************************/ | |
688 | ||
d0778ebf HW |
689 | struct dpcd_caps { |
690 | union dpcd_rev dpcd_rev; | |
691 | union max_lane_count max_ln_count; | |
692 | union max_down_spread max_down_spread; | |
693 | ||
694 | /* dongle type (DP converter, CV smart dongle) */ | |
695 | enum display_dongle_type dongle_type; | |
696 | /* Dongle's downstream count. */ | |
697 | union sink_count sink_count; | |
698 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, | |
699 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
700 | struct dc_dongle_caps dongle_caps; | |
701 | ||
702 | uint32_t sink_dev_id; | |
703 | uint32_t branch_dev_id; | |
704 | int8_t branch_dev_name[6]; | |
705 | int8_t branch_hw_revision; | |
706 | ||
707 | bool allow_invalid_MSA_timing_param; | |
708 | bool panel_mode_edp; | |
709 | }; | |
710 | ||
711 | struct dc_link_status { | |
712 | struct dpcd_caps *dpcd_caps; | |
713 | }; | |
714 | ||
715 | /* DP MST stream allocation (payload bandwidth number) */ | |
716 | struct link_mst_stream_allocation { | |
717 | /* DIG front */ | |
718 | const struct stream_encoder *stream_enc; | |
719 | /* associate DRM payload table with DC stream encoder */ | |
720 | uint8_t vcp_id; | |
721 | /* number of slots required for the DP stream in transport packet */ | |
722 | uint8_t slot_count; | |
723 | }; | |
724 | ||
725 | /* DP MST stream allocation table */ | |
726 | struct link_mst_stream_allocation_table { | |
727 | /* number of DP video streams */ | |
728 | int stream_count; | |
729 | /* array of stream allocations */ | |
730 | struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; | |
731 | }; | |
732 | ||
4562236b HW |
733 | /* |
734 | * A link contains one or more sinks and their connected status. | |
735 | * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. | |
736 | */ | |
737 | struct dc_link { | |
b73a22d3 | 738 | struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; |
4562236b | 739 | unsigned int sink_count; |
b73a22d3 | 740 | struct dc_sink *local_sink; |
4562236b HW |
741 | unsigned int link_index; |
742 | enum dc_connection_type type; | |
743 | enum signal_type connector_signal; | |
744 | enum dc_irq_source irq_source_hpd; | |
745 | enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ | |
746 | /* caps is the same as reported_link_cap. link_traing use | |
747 | * reported_link_cap. Will clean up. TODO | |
748 | */ | |
749 | struct dc_link_settings reported_link_cap; | |
750 | struct dc_link_settings verified_link_cap; | |
4562236b HW |
751 | struct dc_link_settings cur_link_settings; |
752 | struct dc_lane_settings cur_lane_setting; | |
8c4abe0b | 753 | struct dc_link_settings preferred_link_setting; |
4562236b HW |
754 | |
755 | uint8_t ddc_hw_inst; | |
7a096334 ZF |
756 | |
757 | uint8_t hpd_src; | |
758 | ||
4562236b HW |
759 | uint8_t link_enc_hw_inst; |
760 | ||
4562236b HW |
761 | bool test_pattern_enabled; |
762 | union compliance_test_state compliance_test_state; | |
9fb8de78 AG |
763 | |
764 | void *priv; | |
46df790c AG |
765 | |
766 | struct ddc_service *ddc; | |
ebf055f9 AK |
767 | |
768 | bool aux_mode; | |
4562236b | 769 | |
d0778ebf | 770 | /* Private to DC core */ |
4562236b | 771 | |
d0778ebf | 772 | const struct core_dc *dc; |
4562236b | 773 | |
d0778ebf | 774 | struct dc_context *ctx; |
ebf055f9 | 775 | |
d0778ebf HW |
776 | struct link_encoder *link_enc; |
777 | struct graphics_object_id link_id; | |
778 | union ddi_channel_mapping ddi_channel_mapping; | |
779 | struct connector_device_tag_info device_tag; | |
780 | struct dpcd_caps dpcd_caps; | |
781 | unsigned int dpcd_sink_count; | |
782 | ||
783 | enum edp_revision edp_revision; | |
784 | bool psr_enabled; | |
785 | ||
786 | /* MST record stream using this link */ | |
787 | struct link_flags { | |
788 | bool dp_keep_receiver_powered; | |
789 | } wa_flags; | |
790 | struct link_mst_stream_allocation_table mst_stream_alloc_table; | |
791 | ||
792 | struct dc_link_status link_status; | |
4562236b | 793 | |
4562236b HW |
794 | }; |
795 | ||
796 | const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); | |
797 | ||
798 | /* | |
799 | * Return an enumerated dc_link. dc_link order is constant and determined at | |
800 | * boot time. They cannot be created or destroyed. | |
801 | * Use dc_get_caps() to get number of links. | |
802 | */ | |
d0778ebf | 803 | struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); |
4562236b HW |
804 | |
805 | /* Return id of physical connector represented by a dc_link at link_index.*/ | |
806 | const struct graphics_object_id dc_get_link_id_at_index( | |
807 | struct dc *dc, uint32_t link_index); | |
808 | ||
809 | /* Set backlight level of an embedded panel (eDP, LVDS). */ | |
810 | bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, | |
811 | uint32_t frame_ramp, const struct dc_stream *stream); | |
812 | ||
aa7397df AZ |
813 | bool dc_link_set_abm_disable(const struct dc_link *dc_link); |
814 | ||
4562236b HW |
815 | bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); |
816 | ||
7db4dede AZ |
817 | bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); |
818 | ||
d0778ebf | 819 | bool dc_link_setup_psr(struct dc_link *dc_link, |
9f72f51d AZ |
820 | const struct dc_stream *stream, struct psr_config *psr_config, |
821 | struct psr_context *psr_context); | |
4562236b HW |
822 | |
823 | /* Request DC to detect if there is a Panel connected. | |
824 | * boot - If this call is during initial boot. | |
825 | * Return false for any type of detection failure or MST detection | |
826 | * true otherwise. True meaning further action is required (status update | |
827 | * and OS notification). | |
828 | */ | |
d0778ebf | 829 | bool dc_link_detect(struct dc_link *dc_link, bool boot); |
4562236b HW |
830 | |
831 | /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). | |
832 | * Return: | |
833 | * true - Downstream port status changed. DM should call DC to do the | |
834 | * detection. | |
835 | * false - no change in Downstream port status. No further action required | |
836 | * from DM. */ | |
d0778ebf | 837 | bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, |
8ee65d7c | 838 | union hpd_irq_data *hpd_irq_dpcd_data); |
4562236b HW |
839 | |
840 | struct dc_sink_init_data; | |
841 | ||
842 | struct dc_sink *dc_link_add_remote_sink( | |
d0778ebf | 843 | struct dc_link *dc_link, |
4562236b HW |
844 | const uint8_t *edid, |
845 | int len, | |
846 | struct dc_sink_init_data *init_data); | |
847 | ||
848 | void dc_link_remove_remote_sink( | |
d0778ebf | 849 | struct dc_link *link, |
b73a22d3 | 850 | struct dc_sink *sink); |
4562236b HW |
851 | |
852 | /* Used by diagnostics for virtual link at the moment */ | |
d0778ebf | 853 | void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink); |
4562236b HW |
854 | |
855 | void dc_link_dp_set_drive_settings( | |
d0778ebf | 856 | struct dc_link *link, |
4562236b HW |
857 | struct link_training_settings *lt_settings); |
858 | ||
820e3935 | 859 | enum link_training_result dc_link_dp_perform_link_training( |
4562236b HW |
860 | struct dc_link *link, |
861 | const struct dc_link_settings *link_setting, | |
862 | bool skip_video_pattern); | |
863 | ||
864 | void dc_link_dp_enable_hpd(const struct dc_link *link); | |
865 | ||
866 | void dc_link_dp_disable_hpd(const struct dc_link *link); | |
867 | ||
868 | bool dc_link_dp_set_test_pattern( | |
d0778ebf | 869 | struct dc_link *link, |
4562236b HW |
870 | enum dp_test_pattern test_pattern, |
871 | const struct link_training_settings *p_link_settings, | |
872 | const unsigned char *p_custom_pattern, | |
873 | unsigned int cust_pattern_size); | |
874 | ||
875 | /******************************************************************************* | |
876 | * Sink Interfaces - A sink corresponds to a display output device | |
877 | ******************************************************************************/ | |
878 | ||
8c895313 | 879 | struct dc_container_id { |
880 | // 128bit GUID in binary form | |
881 | unsigned char guid[16]; | |
882 | // 8 byte port ID -> ELD.PortID | |
883 | unsigned int portId[2]; | |
884 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName | |
885 | unsigned short manufacturerName; | |
886 | // 2 byte product code -> ELD.ProductCode | |
887 | unsigned short productCode; | |
888 | }; | |
889 | ||
b6d6103b | 890 | |
9edba557 | 891 | |
4562236b HW |
892 | /* |
893 | * The sink structure contains EDID and other display device properties | |
894 | */ | |
895 | struct dc_sink { | |
896 | enum signal_type sink_signal; | |
897 | struct dc_edid dc_edid; /* raw edid */ | |
898 | struct dc_edid_caps edid_caps; /* parse display caps */ | |
8c895313 | 899 | struct dc_container_id *dc_container_id; |
4a9a5d62 | 900 | uint32_t dongle_max_pix_clk; |
5c4e9806 | 901 | void *priv; |
9edba557 | 902 | struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; |
ebf055f9 | 903 | bool converter_disable_audio; |
b73a22d3 HW |
904 | |
905 | /* private to DC core */ | |
906 | struct dc_link *link; | |
907 | struct dc_context *ctx; | |
908 | ||
909 | /* private to dc_sink.c */ | |
910 | int ref_count; | |
4562236b HW |
911 | }; |
912 | ||
b73a22d3 HW |
913 | void dc_sink_retain(struct dc_sink *sink); |
914 | void dc_sink_release(struct dc_sink *sink); | |
4562236b HW |
915 | |
916 | const struct audio **dc_get_audios(struct dc *dc); | |
917 | ||
918 | struct dc_sink_init_data { | |
919 | enum signal_type sink_signal; | |
d0778ebf | 920 | struct dc_link *link; |
4562236b HW |
921 | uint32_t dongle_max_pix_clk; |
922 | bool converter_disable_audio; | |
923 | }; | |
924 | ||
925 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); | |
8c895313 | 926 | bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id); |
927 | bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id); | |
4562236b HW |
928 | |
929 | /******************************************************************************* | |
ab2541b6 | 930 | * Cursor interfaces - To manages the cursor within a stream |
4562236b HW |
931 | ******************************************************************************/ |
932 | /* TODO: Deprecated once we switch to dc_set_cursor_position */ | |
ab2541b6 AC |
933 | bool dc_stream_set_cursor_attributes( |
934 | const struct dc_stream *stream, | |
4562236b HW |
935 | const struct dc_cursor_attributes *attributes); |
936 | ||
ab2541b6 | 937 | bool dc_stream_set_cursor_position( |
4fa086b9 | 938 | struct dc_stream *stream, |
beb16b6a | 939 | const struct dc_cursor_position *position); |
4562236b HW |
940 | |
941 | /* Newer interfaces */ | |
942 | struct dc_cursor { | |
943 | struct dc_plane_address address; | |
944 | struct dc_cursor_attributes attributes; | |
945 | }; | |
946 | ||
4562236b HW |
947 | /******************************************************************************* |
948 | * Interrupt interfaces | |
949 | ******************************************************************************/ | |
950 | enum dc_irq_source dc_interrupt_to_irq_source( | |
951 | struct dc *dc, | |
952 | uint32_t src_id, | |
953 | uint32_t ext_id); | |
954 | void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); | |
955 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); | |
956 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
957 | struct dc *dc, uint32_t link_index); | |
958 | ||
959 | /******************************************************************************* | |
960 | * Power Interfaces | |
961 | ******************************************************************************/ | |
962 | ||
963 | void dc_set_power_state( | |
964 | struct dc *dc, | |
a3621485 | 965 | enum dc_acpi_cm_power_state power_state); |
4562236b HW |
966 | void dc_resume(const struct dc *dc); |
967 | ||
4562236b HW |
968 | /* |
969 | * DPCD access interfaces | |
970 | */ | |
971 | ||
7c7f5b15 | 972 | bool dc_read_aux_dpcd( |
4562236b HW |
973 | struct dc *dc, |
974 | uint32_t link_index, | |
975 | uint32_t address, | |
976 | uint8_t *data, | |
977 | uint32_t size); | |
978 | ||
7c7f5b15 | 979 | bool dc_write_aux_dpcd( |
4562236b HW |
980 | struct dc *dc, |
981 | uint32_t link_index, | |
982 | uint32_t address, | |
983 | const uint8_t *data, | |
2b230ea3 ZF |
984 | uint32_t size); |
985 | ||
7c7f5b15 AG |
986 | bool dc_read_aux_i2c( |
987 | struct dc *dc, | |
988 | uint32_t link_index, | |
989 | enum i2c_mot_mode mot, | |
990 | uint32_t address, | |
991 | uint8_t *data, | |
992 | uint32_t size); | |
993 | ||
994 | bool dc_write_aux_i2c( | |
995 | struct dc *dc, | |
996 | uint32_t link_index, | |
997 | enum i2c_mot_mode mot, | |
998 | uint32_t address, | |
999 | const uint8_t *data, | |
1000 | uint32_t size); | |
1001 | ||
2b230ea3 ZF |
1002 | bool dc_query_ddc_data( |
1003 | struct dc *dc, | |
1004 | uint32_t link_index, | |
1005 | uint32_t address, | |
1006 | uint8_t *write_buf, | |
1007 | uint32_t write_size, | |
1008 | uint8_t *read_buf, | |
1009 | uint32_t read_size); | |
4562236b HW |
1010 | |
1011 | bool dc_submit_i2c( | |
1012 | struct dc *dc, | |
1013 | uint32_t link_index, | |
1014 | struct i2c_command *cmd); | |
1015 | ||
5e7773a2 | 1016 | |
4562236b | 1017 | #endif /* DC_INTERFACE_H_ */ |