[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dc_dp_types.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef DC_DP_TYPES_H
#define DC_DP_TYPES_H

enum dc_lane_count {
	LANE_COUNT_UNKNOWN = 0,
	LANE_COUNT_ONE = 1,
	LANE_COUNT_TWO = 2,
	LANE_COUNT_FOUR = 4,
	LANE_COUNT_EIGHT = 8,
	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
};

/* This is actually a reference clock (27MHz) multiplier
 * 162MBps bandwidth for 1.62GHz like rate,
 * 270MBps for 2.70GHz,
 * 324MBps for 3.24Ghz,
 * 540MBps for 5.40GHz
 * 810MBps for 8.10GHz
 */
enum dc_link_rate {
	LINK_RATE_UNKNOWN = 0,
	LINK_RATE_LOW = 0x06,
	LINK_RATE_HIGH = 0x0A,
	LINK_RATE_RBR2 = 0x0C,
	LINK_RATE_HIGH2 = 0x14,
	LINK_RATE_HIGH3 = 0x1E
};

enum dc_link_spread {
	LINK_SPREAD_DISABLED = 0x00,
	/* 0.5 % downspread 30 kHz */
	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
	/* 0.5 % downspread 33 kHz */
	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
};

enum dc_voltage_swing {
	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
	VOLTAGE_SWING_LEVEL1,
	VOLTAGE_SWING_LEVEL2,
	VOLTAGE_SWING_LEVEL3,
	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
};

enum dc_pre_emphasis {
	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
	PRE_EMPHASIS_LEVEL1,
	PRE_EMPHASIS_LEVEL2,
	PRE_EMPHASIS_LEVEL3,
	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
};
/* Post Cursor 2 is optional for transmitter
 * and it applies only to the main link operating at HBR2
 */
enum dc_post_cursor2 {
	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
	POST_CURSOR2_LEVEL1,
	POST_CURSOR2_LEVEL2,
	POST_CURSOR2_LEVEL3,
	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
};

struct dc_link_settings {
	enum dc_lane_count lane_count;
	enum dc_link_rate link_rate;
	enum dc_link_spread link_spread;
};

struct dc_lane_settings {
	enum dc_voltage_swing VOLTAGE_SWING;
	enum dc_pre_emphasis PRE_EMPHASIS;
	enum dc_post_cursor2 POST_CURSOR2;
};

struct dc_link_training_settings {
	struct dc_link_settings link;
	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
};


union dpcd_rev {
	struct {
		uint8_t MINOR:4;
		uint8_t MAJOR:4;
	} bits;
	uint8_t raw;
};

union max_lane_count {
	struct {
		uint8_t MAX_LANE_COUNT:5;
		uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
		uint8_t TPS3_SUPPORTED:1;
		uint8_t ENHANCED_FRAME_CAP:1;
	} bits;
	uint8_t raw;
};

union max_down_spread {
	struct {
		uint8_t MAX_DOWN_SPREAD:1;
		uint8_t RESERVED:5;
		uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
		uint8_t TPS4_SUPPORTED:1;
	} bits;
	uint8_t raw;
};

union mstm_cap {
	struct {
		uint8_t MST_CAP:1;
		uint8_t RESERVED:7;
	} bits;
	uint8_t raw;
};

union lane_count_set {
	struct {
		uint8_t LANE_COUNT_SET:5;
		uint8_t POST_LT_ADJ_REQ_GRANTED:1;
		uint8_t RESERVED:1;
		uint8_t ENHANCED_FRAMING:1;
	} bits;
	uint8_t raw;
};

union lane_status {
	struct {
		uint8_t CR_DONE_0:1;
		uint8_t CHANNEL_EQ_DONE_0:1;
		uint8_t SYMBOL_LOCKED_0:1;
		uint8_t RESERVED0:1;
		uint8_t CR_DONE_1:1;
		uint8_t CHANNEL_EQ_DONE_1:1;
		uint8_t SYMBOL_LOCKED_1:1;
		uint8_t RESERVED_1:1;
	} bits;
	uint8_t raw;
};

union device_service_irq {
	struct {
		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
		uint8_t AUTOMATED_TEST:1;
		uint8_t CP_IRQ:1;
		uint8_t MCCS_IRQ:1;
		uint8_t DOWN_REP_MSG_RDY:1;
		uint8_t UP_REQ_MSG_RDY:1;
		uint8_t SINK_SPECIFIC:1;
		uint8_t reserved:1;
	} bits;
	uint8_t raw;
};

union sink_count {
	struct {
		uint8_t SINK_COUNT:6;
		uint8_t CPREADY:1;
		uint8_t RESERVED:1;
	} bits;
	uint8_t raw;
};

union lane_align_status_updated {
	struct {
		uint8_t INTERLANE_ALIGN_DONE:1;
		uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
		uint8_t RESERVED:4;
		uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
		uint8_t LINK_STATUS_UPDATED:1;
	} bits;
	uint8_t raw;
};

union lane_adjust {
	struct {
		uint8_t VOLTAGE_SWING_LANE:2;
		uint8_t PRE_EMPHASIS_LANE:2;
		uint8_t RESERVED:4;
	} bits;
	uint8_t raw;
};

union dpcd_training_pattern {
	struct {
		uint8_t TRAINING_PATTERN_SET:4;
		uint8_t RECOVERED_CLOCK_OUT_EN:1;
		uint8_t SCRAMBLING_DISABLE:1;
		uint8_t SYMBOL_ERROR_COUNT_SEL:2;
	} v1_4;
	struct {
		uint8_t TRAINING_PATTERN_SET:2;
		uint8_t LINK_QUAL_PATTERN_SET:2;
		uint8_t RESERVED:4;
	} v1_3;
	uint8_t raw;
};

/* Training Lane is used to configure downstream DP device's voltage swing
and pre-emphasis levels*/
/* The DPCD addresses are from 0x103 to 0x106*/
union dpcd_training_lane {
	struct {
		uint8_t VOLTAGE_SWING_SET:2;
		uint8_t MAX_SWING_REACHED:1;
		uint8_t PRE_EMPHASIS_SET:2;
		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
		uint8_t RESERVED:2;
	} bits;
	uint8_t raw;
};

/* TMDS-converter related */
union dwnstream_port_caps_byte0 {
	struct {
		uint8_t DWN_STRM_PORTX_TYPE:3;
		uint8_t DWN_STRM_PORTX_HPD:1;
		uint8_t RESERVERD:4;
	} bits;
	uint8_t raw;
};

/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
enum dpcd_downstream_port_detailed_type {
	DOWN_STREAM_DETAILED_DP = 0,
	DOWN_STREAM_DETAILED_VGA,
	DOWN_STREAM_DETAILED_DVI,
	DOWN_STREAM_DETAILED_HDMI,
	DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
};

union dwnstream_port_caps_byte1 {
	struct {
		uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
		uint8_t RESERVED:6;
	} bits;
	uint8_t raw;
};

union dp_downstream_port_present {
	uint8_t byte;
	struct {
		uint8_t PORT_PRESENT:1;
		uint8_t PORT_TYPE:2;
		uint8_t FMT_CONVERSION:1;
		uint8_t DETAILED_CAPS:1;
		uint8_t RESERVED:3;
	} fields;
};

union dwnstream_port_caps_byte3_dvi {
	struct {
		uint8_t RESERVED1:1;
		uint8_t DUAL_LINK:1;
		uint8_t HIGH_COLOR_DEPTH:1;
		uint8_t RESERVED2:5;
	} bits;
	uint8_t raw;
};

union dwnstream_port_caps_byte3_hdmi {
	struct {
		uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
		uint8_t YCrCr422_PASS_THROUGH:1;
		uint8_t YCrCr420_PASS_THROUGH:1;
		uint8_t YCrCr422_CONVERSION:1;
		uint8_t YCrCr420_CONVERSION:1;
		uint8_t RESERVED:3;
	} bits;
	uint8_t raw;
};

/*4-byte structure for detailed capabilities of a down-stream port
(DP-to-TMDS converter).*/

union sink_status {
	struct {
		uint8_t RX_PORT0_STATUS:1;
		uint8_t RX_PORT1_STATUS:1;
		uint8_t RESERVED:6;
	} bits;
	uint8_t raw;
};

/*6-byte structure corresponding to 6 registers (200h-205h)
read during handling of HPD-IRQ*/
union hpd_irq_data {
	struct {
		union sink_count sink_cnt;/* 200h */
		union device_service_irq device_service_irq;/* 201h */
		union lane_status lane01_status;/* 202h */
		union lane_status lane23_status;/* 203h */
		union lane_align_status_updated lane_status_updated;/* 204h */
		union sink_status sink_status;
	} bytes;
	uint8_t raw[6];
};

union down_stream_port_count {
	struct {
		uint8_t DOWN_STR_PORT_COUNT:4;
		uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
		/*Bit 6 = MSA_TIMING_PAR_IGNORED
		0 = Sink device requires the MSA timing parameters
		1 = Sink device is capable of rendering incoming video
		 stream without MSA timing parameters*/
		uint8_t IGNORE_MSA_TIMING_PARAM:1;
		/*Bit 7 = OUI Support
		0 = OUI not supported
		1 = OUI supported
		(OUI and Device Identification mandatory for DP 1.2)*/
		uint8_t OUI_SUPPORT:1;
	} bits;
	uint8_t raw;
};

union down_spread_ctrl {
	struct {
		uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
	/* Bits 4 = SPREAD_AMP. Spreading amplitude
	0 = Main link signal is not downspread
	1 = Main link signal is downspread <= 0.5%
	with frequency in the range of 30kHz ~ 33kHz*/
		uint8_t SPREAD_AMP:1;
		uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
	0 = Source device will send valid data for the MSA Timing Params
	1 = Source device may send invalid data for these MSA Timing Params*/
		uint8_t IGNORE_MSA_TIMING_PARAM:1;
	} bits;
	uint8_t raw;
};

union dpcd_edp_config {
	struct {
		uint8_t PANEL_MODE_EDP:1;
		uint8_t FRAMING_CHANGE_ENABLE:1;
		uint8_t RESERVED:5;
		uint8_t PANEL_SELF_TEST_ENABLE:1;
	} bits;
	uint8_t raw;
};

struct dp_device_vendor_id {
	uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
	uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
};

struct dp_sink_hw_fw_revision {
	uint8_t ieee_hw_rev;
	uint8_t ieee_fw_rev[2];
};

/*DPCD register of DP receiver capability field bits-*/
union edp_configuration_cap {
	struct {
		uint8_t ALT_SCRAMBLER_RESET:1;
		uint8_t FRAMING_CHANGE:1;
		uint8_t RESERVED:1;
		uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
		uint8_t RESERVED2:4;
	} bits;
	uint8_t raw;
};

union training_aux_rd_interval {
	struct {
		uint8_t TRAINIG_AUX_RD_INTERVAL:7;
		uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
	} bits;
	uint8_t raw;
};

/* Automated test structures */
union test_request {
	struct {
	uint8_t LINK_TRAINING         :1;
	uint8_t LINK_TEST_PATTRN      :1;
	uint8_t EDID_REAT             :1;
	uint8_t PHY_TEST_PATTERN      :1;
	uint8_t AUDIO_TEST_PATTERN    :1;
	uint8_t RESERVED              :1;
	uint8_t TEST_STEREO_3D        :1;
	} bits;
	uint8_t raw;
};

union test_response {
	struct {
		uint8_t ACK         :1;
		uint8_t NO_ACK      :1;
		uint8_t RESERVED    :6;
	} bits;
	uint8_t raw;
};

union phy_test_pattern {
	struct {
		/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
		 * and 3 bits for DP1.2.
		 */
		uint8_t PATTERN     :3;
		/* BY speci, bit7:2 is 0 for DP1.1. */
		uint8_t RESERVED    :5;
	} bits;
	uint8_t raw;
};

/* States of Compliance Test Specification (CTS DP1.2). */
union compliance_test_state {
	struct {
		unsigned char STEREO_3D_RUNNING        : 1;
		unsigned char RESERVED                 : 7;
	} bits;
	unsigned char raw;
};

union link_test_pattern {
	struct {
		/* dpcd_link_test_patterns */
		unsigned char PATTERN :2;
		unsigned char RESERVED:6;
	} bits;
	unsigned char raw;
};

union test_misc {
	struct dpcd_test_misc_bits {
		unsigned char SYNC_CLOCK :1;
		/* dpcd_test_color_format */
		unsigned char CLR_FORMAT :2;
		/* dpcd_test_dyn_range */
		unsigned char DYN_RANGE  :1;
		unsigned char YCBCR      :1;
		/* dpcd_test_bit_depth */
		unsigned char BPC        :3;
	} bits;
	unsigned char raw;
};

#endif /* DC_DP_TYPES_H */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef DC_DP_TYPES_H
	27	#define DC_DP_TYPES_H
	28
	29	enum dc_lane_count {
	30	LANE_COUNT_UNKNOWN = 0,
	31	LANE_COUNT_ONE = 1,
	32	LANE_COUNT_TWO = 2,
	33	LANE_COUNT_FOUR = 4,
	34	LANE_COUNT_EIGHT = 8,
	35	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
	36	};
	37
	38	/* This is actually a reference clock (27MHz) multiplier
	39	* 162MBps bandwidth for 1.62GHz like rate,
	40	* 270MBps for 2.70GHz,
	41	* 324MBps for 3.24Ghz,
	42	* 540MBps for 5.40GHz
	43	* 810MBps for 8.10GHz
	44	*/
	45	enum dc_link_rate {
	46	LINK_RATE_UNKNOWN = 0,
	47	LINK_RATE_LOW = 0x06,
	48	LINK_RATE_HIGH = 0x0A,
	49	LINK_RATE_RBR2 = 0x0C,
	50	LINK_RATE_HIGH2 = 0x14,
	51	LINK_RATE_HIGH3 = 0x1E
	52	};
	53
	54	enum dc_link_spread {
	55	LINK_SPREAD_DISABLED = 0x00,
	56	/* 0.5 % downspread 30 kHz */
	57	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
	58	/* 0.5 % downspread 33 kHz */
	59	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
	60	};
	61
	62	enum dc_voltage_swing {
	63	VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */
	64	VOLTAGE_SWING_LEVEL1,
65	VOLTAGE_SWING_LEVEL2,
66	VOLTAGE_SWING_LEVEL3,
67	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
68	};
69
70	enum dc_pre_emphasis {
71	PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */
72	PRE_EMPHASIS_LEVEL1,
73	PRE_EMPHASIS_LEVEL2,
74	PRE_EMPHASIS_LEVEL3,
75	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
76	};
77	/* Post Cursor 2 is optional for transmitter
78	* and it applies only to the main link operating at HBR2
79	*/
80	enum dc_post_cursor2 {
81	POST_CURSOR2_DISABLED = 0, /* direct HW translation! */
82	POST_CURSOR2_LEVEL1,
83	POST_CURSOR2_LEVEL2,
84	POST_CURSOR2_LEVEL3,
85	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
86	};
87
88	struct dc_link_settings {
89	enum dc_lane_count lane_count;
90	enum dc_link_rate link_rate;
91	enum dc_link_spread link_spread;
92	};
93
94	struct dc_lane_settings {
95	enum dc_voltage_swing VOLTAGE_SWING;
96	enum dc_pre_emphasis PRE_EMPHASIS;
97	enum dc_post_cursor2 POST_CURSOR2;
98	};
99
100	struct dc_link_training_settings {
101	struct dc_link_settings link;
102	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
103	};
104
eaca91ee HW	105
	106	union dpcd_rev {
	107	struct {
	108	uint8_t MINOR:4;
	109	uint8_t MAJOR:4;
	110	} bits;
	111	uint8_t raw;
	112	};
	113
	114	union max_lane_count {
	115	struct {
	116	uint8_t MAX_LANE_COUNT:5;
	117	uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
	118	uint8_t TPS3_SUPPORTED:1;
	119	uint8_t ENHANCED_FRAME_CAP:1;
	120	} bits;
	121	uint8_t raw;
	122	};
	123
	124	union max_down_spread {
	125	struct {
	126	uint8_t MAX_DOWN_SPREAD:1;
	127	uint8_t RESERVED:5;
	128	uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
	129	uint8_t TPS4_SUPPORTED:1;
	130	} bits;
	131	uint8_t raw;
	132	};
	133
	134	union mstm_cap {
	135	struct {
	136	uint8_t MST_CAP:1;
	137	uint8_t RESERVED:7;
	138	} bits;
	139	uint8_t raw;
	140	};
	141
	142	union lane_count_set {
	143	struct {
	144	uint8_t LANE_COUNT_SET:5;
	145	uint8_t POST_LT_ADJ_REQ_GRANTED:1;
	146	uint8_t RESERVED:1;
	147	uint8_t ENHANCED_FRAMING:1;
	148	} bits;
	149	uint8_t raw;
	150	};
	151
	152	union lane_status {
	153	struct {
	154	uint8_t CR_DONE_0:1;
	155	uint8_t CHANNEL_EQ_DONE_0:1;
	156	uint8_t SYMBOL_LOCKED_0:1;
	157	uint8_t RESERVED0:1;
	158	uint8_t CR_DONE_1:1;
	159	uint8_t CHANNEL_EQ_DONE_1:1;
	160	uint8_t SYMBOL_LOCKED_1:1;
	161	uint8_t RESERVED_1:1;
	162	} bits;
	163	uint8_t raw;
	164	};
	165
	166	union device_service_irq {
	167	struct {
	168	uint8_t REMOTE_CONTROL_CMD_PENDING:1;
169	uint8_t AUTOMATED_TEST:1;
170	uint8_t CP_IRQ:1;
171	uint8_t MCCS_IRQ:1;
172	uint8_t DOWN_REP_MSG_RDY:1;
173	uint8_t UP_REQ_MSG_RDY:1;
174	uint8_t SINK_SPECIFIC:1;
175	uint8_t reserved:1;
176	} bits;
177	uint8_t raw;
178	};
179
180	union sink_count {
181	struct {
182	uint8_t SINK_COUNT:6;
183	uint8_t CPREADY:1;
184	uint8_t RESERVED:1;
185	} bits;
186	uint8_t raw;
187	};
188
189	union lane_align_status_updated {
190	struct {
191	uint8_t INTERLANE_ALIGN_DONE:1;
192	uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
193	uint8_t RESERVED:4;
194	uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
195	uint8_t LINK_STATUS_UPDATED:1;
196	} bits;
197	uint8_t raw;
198	};
199
200	union lane_adjust {
201	struct {
202	uint8_t VOLTAGE_SWING_LANE:2;
203	uint8_t PRE_EMPHASIS_LANE:2;
204	uint8_t RESERVED:4;
205	} bits;
206	uint8_t raw;
207	};
208
209	union dpcd_training_pattern {
210	struct {
211	uint8_t TRAINING_PATTERN_SET:4;
212	uint8_t RECOVERED_CLOCK_OUT_EN:1;
213	uint8_t SCRAMBLING_DISABLE:1;
214	uint8_t SYMBOL_ERROR_COUNT_SEL:2;
215	} v1_4;
216	struct {
217	uint8_t TRAINING_PATTERN_SET:2;
218	uint8_t LINK_QUAL_PATTERN_SET:2;
219	uint8_t RESERVED:4;
220	} v1_3;
221	uint8_t raw;
222	};
223
224	/* Training Lane is used to configure downstream DP device's voltage swing
225	and pre-emphasis levels*/
226	/* The DPCD addresses are from 0x103 to 0x106*/
227	union dpcd_training_lane {
228	struct {
229	uint8_t VOLTAGE_SWING_SET:2;
230	uint8_t MAX_SWING_REACHED:1;
231	uint8_t PRE_EMPHASIS_SET:2;
232	uint8_t MAX_PRE_EMPHASIS_REACHED:1;
233	uint8_t RESERVED:2;
234	} bits;
235	uint8_t raw;
236	};
237
238	/* TMDS-converter related */
239	union dwnstream_port_caps_byte0 {
240	struct {
241	uint8_t DWN_STRM_PORTX_TYPE:3;
242	uint8_t DWN_STRM_PORTX_HPD:1;
243	uint8_t RESERVERD:4;
244	} bits;
245	uint8_t raw;
246	};
247
248	/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
249	enum dpcd_downstream_port_detailed_type {
250	DOWN_STREAM_DETAILED_DP = 0,
251	DOWN_STREAM_DETAILED_VGA,
252	DOWN_STREAM_DETAILED_DVI,
253	DOWN_STREAM_DETAILED_HDMI,
254	DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
255	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
256	};
257
03f5c686	258	union dwnstream_port_caps_byte1 {
eaca91ee HW	259	struct {
	260	uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
	261	uint8_t RESERVED:6;
	262	} bits;
	263	uint8_t raw;
	264	};
	265
	266	union dp_downstream_port_present {
	267	uint8_t byte;
	268	struct {
	269	uint8_t PORT_PRESENT:1;
	270	uint8_t PORT_TYPE:2;
	271	uint8_t FMT_CONVERSION:1;
	272	uint8_t DETAILED_CAPS:1;
	273	uint8_t RESERVED:3;
	274	} fields;
	275	};
	276
	277	union dwnstream_port_caps_byte3_dvi {
	278	struct {
	279	uint8_t RESERVED1:1;
	280	uint8_t DUAL_LINK:1;
	281	uint8_t HIGH_COLOR_DEPTH:1;
	282	uint8_t RESERVED2:5;
	283	} bits;
	284	uint8_t raw;
	285	};
	286
	287	union dwnstream_port_caps_byte3_hdmi {
	288	struct {
	289	uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
03f5c686 CL	290	uint8_t YCrCr422_PASS_THROUGH:1;
	291	uint8_t YCrCr420_PASS_THROUGH:1;
	292	uint8_t YCrCr422_CONVERSION:1;
	293	uint8_t YCrCr420_CONVERSION:1;
	294	uint8_t RESERVED:3;
eaca91ee HW	295	} bits;
	296	uint8_t raw;
	297	};
	298
	299	/*4-byte structure for detailed capabilities of a down-stream port
	300	(DP-to-TMDS converter).*/
	301
	302	union sink_status {
	303	struct {
	304	uint8_t RX_PORT0_STATUS:1;
	305	uint8_t RX_PORT1_STATUS:1;
	306	uint8_t RESERVED:6;
	307	} bits;
	308	uint8_t raw;
	309	};
	310
	311	/*6-byte structure corresponding to 6 registers (200h-205h)
	312	read during handling of HPD-IRQ*/
	313	union hpd_irq_data {
	314	struct {
	315	union sink_count sink_cnt;/* 200h */
	316	union device_service_irq device_service_irq;/* 201h */
	317	union lane_status lane01_status;/* 202h */
	318	union lane_status lane23_status;/* 203h */
	319	union lane_align_status_updated lane_status_updated;/* 204h */
	320	union sink_status sink_status;
	321	} bytes;
	322	uint8_t raw[6];
	323	};
	324
	325	union down_stream_port_count {
	326	struct {
	327	uint8_t DOWN_STR_PORT_COUNT:4;
	328	uint8_t RESERVED:2; /Bits 5:4 = RESERVED. Read all 0s./
	329	/*Bit 6 = MSA_TIMING_PAR_IGNORED
	330	0 = Sink device requires the MSA timing parameters
	331	1 = Sink device is capable of rendering incoming video
	332	stream without MSA timing parameters*/
	333	uint8_t IGNORE_MSA_TIMING_PARAM:1;
	334	/*Bit 7 = OUI Support
	335	0 = OUI not supported
	336	1 = OUI supported
	337	(OUI and Device Identification mandatory for DP 1.2)*/
	338	uint8_t OUI_SUPPORT:1;
	339	} bits;
	340	uint8_t raw;
	341	};
	342
	343	union down_spread_ctrl {
	344	struct {
	345	uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
	346	/* Bits 4 = SPREAD_AMP. Spreading amplitude
	347	0 = Main link signal is not downspread
	348	1 = Main link signal is downspread <= 0.5%
	349	with frequency in the range of 30kHz ~ 33kHz*/
	350	uint8_t SPREAD_AMP:1;
	351	uint8_t RESERVED2:2;/Bit 6:5 = RESERVED. Read all 0s/
	352	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
	353	0 = Source device will send valid data for the MSA Timing Params
	354	1 = Source device may send invalid data for these MSA Timing Params*/
	355	uint8_t IGNORE_MSA_TIMING_PARAM:1;
	356	} bits;
	357	uint8_t raw;
	358	};
359
360	union dpcd_edp_config {
361	struct {
362	uint8_t PANEL_MODE_EDP:1;
363	uint8_t FRAMING_CHANGE_ENABLE:1;
364	uint8_t RESERVED:5;
365	uint8_t PANEL_SELF_TEST_ENABLE:1;
366	} bits;
367	uint8_t raw;
368	};
369
370	struct dp_device_vendor_id {
371	uint8_t ieee_oui[3];/24-bit IEEE OUI/
372	uint8_t ieee_device_id[6];/usually 6-byte ASCII name/
373	};
374
375	struct dp_sink_hw_fw_revision {
376	uint8_t ieee_hw_rev;
377	uint8_t ieee_fw_rev[2];
378	};
379
380	/DPCD register of DP receiver capability field bits-/
381	union edp_configuration_cap {
382	struct {
383	uint8_t ALT_SCRAMBLER_RESET:1;
384	uint8_t FRAMING_CHANGE:1;
385	uint8_t RESERVED:1;
386	uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
387	uint8_t RESERVED2:4;
388	} bits;
389	uint8_t raw;
390	};
391
392	union training_aux_rd_interval {
393	struct {
394	uint8_t TRAINIG_AUX_RD_INTERVAL:7;
395	uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
396	} bits;
397	uint8_t raw;
398	};
399
400	/* Automated test structures */
401	union test_request {
402	struct {
403	uint8_t LINK_TRAINING :1;
404	uint8_t LINK_TEST_PATTRN :1;
405	uint8_t EDID_REAT :1;
406	uint8_t PHY_TEST_PATTERN :1;
407	uint8_t AUDIO_TEST_PATTERN :1;
408	uint8_t RESERVED :1;
409	uint8_t TEST_STEREO_3D :1;
410	} bits;
411	uint8_t raw;
412	};
413
414	union test_response {
415	struct {
416	uint8_t ACK :1;
417	uint8_t NO_ACK :1;
418	uint8_t RESERVED :6;
419	} bits;
420	uint8_t raw;
421	};
422
423	union phy_test_pattern {
424	struct {
425	/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
426	* and 3 bits for DP1.2.
427	*/
428	uint8_t PATTERN :3;
429	/* BY speci, bit7:2 is 0 for DP1.1. */
430	uint8_t RESERVED :5;
431	} bits;
432	uint8_t raw;
433	};
434
435	/* States of Compliance Test Specification (CTS DP1.2). */
436	union compliance_test_state {
437	struct {
438	unsigned char STEREO_3D_RUNNING : 1;
75a74755	439	unsigned char RESERVED : 7;
eaca91ee HW	440	} bits;
	441	unsigned char raw;
	442	};
	443
	444	union link_test_pattern {
	445	struct {
	446	/* dpcd_link_test_patterns */
	447	unsigned char PATTERN :2;
	448	unsigned char RESERVED:6;
	449	} bits;
	450	unsigned char raw;
	451	};
	452
	453	union test_misc {
	454	struct dpcd_test_misc_bits {
	455	unsigned char SYNC_CLOCK :1;
	456	/* dpcd_test_color_format */
	457	unsigned char CLR_FORMAT :2;
	458	/* dpcd_test_dyn_range */
	459	unsigned char DYN_RANGE :1;
	460	unsigned char YCBCR :1;
	461	/* dpcd_test_bit_depth */
	462	unsigned char BPC :3;
	463	} bits;
	464	unsigned char raw;
	465	};
	466
4562236b	467	#endif /* DC_DP_TYPES_H */