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4562236b HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | #include "dm_services.h" | |
26 | ||
27 | #include "link_encoder.h" | |
28 | #include "stream_encoder.h" | |
29 | ||
30 | #include "resource.h" | |
31 | #include "include/irq_service_interface.h" | |
32 | #include "../virtual/virtual_stream_encoder.h" | |
33 | #include "dce110/dce110_resource.h" | |
34 | #include "dce110/dce110_timing_generator.h" | |
35 | #include "irq/dce110/irq_service_dce110.h" | |
36 | #include "dce/dce_link_encoder.h" | |
37 | #include "dce/dce_stream_encoder.h" | |
c3489214 DL |
38 | |
39 | #include "dce/dce_mem_input.h" | |
e6303950 | 40 | #include "dce/dce_ipp.h" |
4562236b | 41 | #include "dce/dce_transform.h" |
ab3ee7a5 | 42 | #include "dce/dce_opp.h" |
9a70eba7 | 43 | #include "dce/dce_clocks.h" |
4562236b HW |
44 | #include "dce/dce_clock_source.h" |
45 | #include "dce/dce_audio.h" | |
46 | #include "dce/dce_hwseq.h" | |
47 | #include "dce100/dce100_hw_sequencer.h" | |
48 | ||
49 | #include "reg_helper.h" | |
50 | ||
51 | #include "dce/dce_10_0_d.h" | |
52 | #include "dce/dce_10_0_sh_mask.h" | |
53 | ||
54 | #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT | |
55 | #include "gmc/gmc_8_2_d.h" | |
56 | #include "gmc/gmc_8_2_sh_mask.h" | |
57 | #endif | |
58 | ||
59 | #ifndef mmDP_DPHY_INTERNAL_CTRL | |
60 | #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 | |
61 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 | |
62 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 | |
63 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 | |
64 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 | |
65 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 | |
66 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 | |
67 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 | |
68 | #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 | |
69 | #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 | |
70 | #endif | |
71 | ||
72 | #ifndef mmBIOS_SCRATCH_2 | |
73 | #define mmBIOS_SCRATCH_2 0x05CB | |
74 | #define mmBIOS_SCRATCH_6 0x05CF | |
75 | #endif | |
76 | ||
77 | #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL | |
78 | #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC | |
79 | #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC | |
80 | #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC | |
81 | #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC | |
82 | #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC | |
83 | #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC | |
84 | #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC | |
85 | #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC | |
86 | #endif | |
87 | ||
88 | #ifndef mmDP_DPHY_FAST_TRAINING | |
89 | #define mmDP_DPHY_FAST_TRAINING 0x4ABC | |
90 | #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC | |
91 | #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC | |
92 | #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC | |
93 | #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC | |
94 | #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC | |
95 | #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC | |
96 | #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC | |
97 | #endif | |
98 | ||
99 | static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { | |
100 | { | |
101 | .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), | |
102 | .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), | |
103 | }, | |
104 | { | |
105 | .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), | |
106 | .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), | |
107 | }, | |
108 | { | |
109 | .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), | |
110 | .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), | |
111 | }, | |
112 | { | |
113 | .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), | |
114 | .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), | |
115 | }, | |
116 | { | |
117 | .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), | |
118 | .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), | |
119 | }, | |
120 | { | |
121 | .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), | |
122 | .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), | |
123 | } | |
124 | }; | |
125 | ||
4562236b HW |
126 | /* set register offset */ |
127 | #define SR(reg_name)\ | |
128 | .reg_name = mm ## reg_name | |
129 | ||
130 | /* set register offset with instance */ | |
131 | #define SRI(reg_name, block, id)\ | |
132 | .reg_name = mm ## block ## id ## _ ## reg_name | |
133 | ||
134 | ||
9a70eba7 DL |
135 | static const struct dce_disp_clk_registers disp_clk_regs = { |
136 | CLK_COMMON_REG_LIST_DCE_BASE() | |
137 | }; | |
138 | ||
139 | static const struct dce_disp_clk_shift disp_clk_shift = { | |
140 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) | |
141 | }; | |
142 | ||
143 | static const struct dce_disp_clk_mask disp_clk_mask = { | |
144 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) | |
145 | }; | |
146 | ||
e6303950 DL |
147 | #define ipp_regs(id)\ |
148 | [id] = {\ | |
149 | IPP_DCE100_REG_LIST_DCE_BASE(id)\ | |
150 | } | |
151 | ||
152 | static const struct dce_ipp_registers ipp_regs[] = { | |
153 | ipp_regs(0), | |
154 | ipp_regs(1), | |
155 | ipp_regs(2), | |
156 | ipp_regs(3), | |
157 | ipp_regs(4), | |
158 | ipp_regs(5) | |
159 | }; | |
160 | ||
161 | static const struct dce_ipp_shift ipp_shift = { | |
162 | IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) | |
163 | }; | |
164 | ||
165 | static const struct dce_ipp_mask ipp_mask = { | |
166 | IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) | |
167 | }; | |
168 | ||
4562236b HW |
169 | #define transform_regs(id)\ |
170 | [id] = {\ | |
171 | XFM_COMMON_REG_LIST_DCE100(id)\ | |
172 | } | |
173 | ||
174 | static const struct dce_transform_registers xfm_regs[] = { | |
175 | transform_regs(0), | |
176 | transform_regs(1), | |
177 | transform_regs(2), | |
178 | transform_regs(3), | |
179 | transform_regs(4), | |
180 | transform_regs(5) | |
181 | }; | |
182 | ||
183 | static const struct dce_transform_shift xfm_shift = { | |
184 | XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) | |
185 | }; | |
186 | ||
187 | static const struct dce_transform_mask xfm_mask = { | |
188 | XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) | |
189 | }; | |
190 | ||
191 | #define aux_regs(id)\ | |
192 | [id] = {\ | |
193 | AUX_REG_LIST(id)\ | |
194 | } | |
195 | ||
196 | static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { | |
197 | aux_regs(0), | |
198 | aux_regs(1), | |
199 | aux_regs(2), | |
200 | aux_regs(3), | |
201 | aux_regs(4), | |
202 | aux_regs(5) | |
203 | }; | |
204 | ||
205 | #define hpd_regs(id)\ | |
206 | [id] = {\ | |
207 | HPD_REG_LIST(id)\ | |
208 | } | |
209 | ||
210 | static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
211 | hpd_regs(0), | |
212 | hpd_regs(1), | |
213 | hpd_regs(2), | |
214 | hpd_regs(3), | |
215 | hpd_regs(4), | |
216 | hpd_regs(5) | |
217 | }; | |
218 | ||
219 | #define link_regs(id)\ | |
220 | [id] = {\ | |
3f8a9440 | 221 | LE_DCE100_REG_LIST(id)\ |
4562236b HW |
222 | } |
223 | ||
224 | static const struct dce110_link_enc_registers link_enc_regs[] = { | |
225 | link_regs(0), | |
226 | link_regs(1), | |
227 | link_regs(2), | |
228 | link_regs(3), | |
229 | link_regs(4), | |
230 | link_regs(5), | |
231 | link_regs(6), | |
232 | }; | |
233 | ||
234 | #define stream_enc_regs(id)\ | |
235 | [id] = {\ | |
236 | SE_COMMON_REG_LIST_DCE_BASE(id),\ | |
237 | .AFMT_CNTL = 0,\ | |
238 | } | |
239 | ||
240 | static const struct dce110_stream_enc_registers stream_enc_regs[] = { | |
241 | stream_enc_regs(0), | |
242 | stream_enc_regs(1), | |
243 | stream_enc_regs(2), | |
244 | stream_enc_regs(3), | |
245 | stream_enc_regs(4), | |
246 | stream_enc_regs(5), | |
247 | stream_enc_regs(6) | |
248 | }; | |
249 | ||
250 | static const struct dce_stream_encoder_shift se_shift = { | |
251 | SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) | |
252 | }; | |
253 | ||
254 | static const struct dce_stream_encoder_mask se_mask = { | |
255 | SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) | |
256 | }; | |
257 | ||
ab3ee7a5 ZF |
258 | #define opp_regs(id)\ |
259 | [id] = {\ | |
260 | OPP_DCE_100_REG_LIST(id),\ | |
261 | } | |
262 | ||
263 | static const struct dce_opp_registers opp_regs[] = { | |
264 | opp_regs(0), | |
265 | opp_regs(1), | |
266 | opp_regs(2), | |
267 | opp_regs(3), | |
268 | opp_regs(4), | |
269 | opp_regs(5) | |
270 | }; | |
271 | ||
272 | static const struct dce_opp_shift opp_shift = { | |
273 | OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) | |
274 | }; | |
275 | ||
276 | static const struct dce_opp_mask opp_mask = { | |
277 | OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) | |
278 | }; | |
279 | ||
280 | ||
4562236b HW |
281 | #define audio_regs(id)\ |
282 | [id] = {\ | |
283 | AUD_COMMON_REG_LIST(id)\ | |
284 | } | |
285 | ||
286 | static const struct dce_audio_registers audio_regs[] = { | |
287 | audio_regs(0), | |
288 | audio_regs(1), | |
289 | audio_regs(2), | |
290 | audio_regs(3), | |
291 | audio_regs(4), | |
292 | audio_regs(5), | |
293 | audio_regs(6), | |
294 | }; | |
295 | ||
296 | static const struct dce_audio_shift audio_shift = { | |
297 | AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
298 | }; | |
299 | ||
300 | static const struct dce_aduio_mask audio_mask = { | |
301 | AUD_COMMON_MASK_SH_LIST(_MASK) | |
302 | }; | |
303 | ||
304 | #define clk_src_regs(id)\ | |
305 | [id] = {\ | |
306 | CS_COMMON_REG_LIST_DCE_100_110(id),\ | |
307 | } | |
308 | ||
309 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
310 | clk_src_regs(0), | |
311 | clk_src_regs(1), | |
312 | clk_src_regs(2) | |
313 | }; | |
314 | ||
315 | static const struct dce110_clk_src_shift cs_shift = { | |
316 | CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) | |
317 | }; | |
318 | ||
319 | static const struct dce110_clk_src_mask cs_mask = { | |
320 | CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) | |
321 | }; | |
322 | ||
323 | ||
324 | ||
325 | #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 | |
326 | ||
4562236b HW |
327 | static const struct bios_registers bios_regs = { |
328 | .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 | |
329 | }; | |
330 | ||
331 | static const struct resource_caps res_cap = { | |
332 | .num_timing_generator = 6, | |
333 | .num_audio = 6, | |
334 | .num_stream_encoder = 6, | |
335 | .num_pll = 3 | |
336 | }; | |
337 | ||
338 | #define CTX ctx | |
339 | #define REG(reg) mm ## reg | |
340 | ||
341 | #ifndef mmCC_DC_HDMI_STRAPS | |
342 | #define mmCC_DC_HDMI_STRAPS 0x1918 | |
343 | #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 | |
344 | #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 | |
345 | #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 | |
346 | #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 | |
347 | #endif | |
348 | ||
349 | static void read_dce_straps( | |
350 | struct dc_context *ctx, | |
351 | struct resource_straps *straps) | |
352 | { | |
353 | REG_GET_2(CC_DC_HDMI_STRAPS, | |
354 | HDMI_DISABLE, &straps->hdmi_disable, | |
355 | AUDIO_STREAM_NUMBER, &straps->audio_stream_number); | |
356 | ||
357 | REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); | |
358 | } | |
359 | ||
360 | static struct audio *create_audio( | |
361 | struct dc_context *ctx, unsigned int inst) | |
362 | { | |
363 | return dce_audio_create(ctx, inst, | |
364 | &audio_regs[inst], &audio_shift, &audio_mask); | |
365 | } | |
366 | ||
367 | static struct timing_generator *dce100_timing_generator_create( | |
368 | struct dc_context *ctx, | |
369 | uint32_t instance, | |
370 | const struct dce110_timing_generator_offsets *offsets) | |
371 | { | |
372 | struct dce110_timing_generator *tg110 = | |
373 | dm_alloc(sizeof(struct dce110_timing_generator)); | |
374 | ||
375 | if (!tg110) | |
376 | return NULL; | |
377 | ||
378 | if (dce110_timing_generator_construct(tg110, ctx, instance, | |
379 | offsets)) | |
380 | return &tg110->base; | |
381 | ||
382 | BREAK_TO_DEBUGGER(); | |
383 | dm_free(tg110); | |
384 | return NULL; | |
385 | } | |
386 | ||
387 | static struct stream_encoder *dce100_stream_encoder_create( | |
388 | enum engine_id eng_id, | |
389 | struct dc_context *ctx) | |
390 | { | |
391 | struct dce110_stream_encoder *enc110 = | |
392 | dm_alloc(sizeof(struct dce110_stream_encoder)); | |
393 | ||
394 | if (!enc110) | |
395 | return NULL; | |
396 | ||
397 | if (dce110_stream_encoder_construct( | |
398 | enc110, ctx, ctx->dc_bios, eng_id, | |
399 | &stream_enc_regs[eng_id], &se_shift, &se_mask)) | |
400 | return &enc110->base; | |
401 | ||
402 | BREAK_TO_DEBUGGER(); | |
403 | dm_free(enc110); | |
404 | return NULL; | |
405 | } | |
406 | ||
407 | #define SRII(reg_name, block, id)\ | |
408 | .reg_name[id] = mm ## block ## id ## _ ## reg_name | |
409 | ||
410 | static const struct dce_hwseq_registers hwseq_reg = { | |
411 | HWSEQ_DCE10_REG_LIST() | |
412 | }; | |
413 | ||
414 | static const struct dce_hwseq_shift hwseq_shift = { | |
415 | HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) | |
416 | }; | |
417 | ||
418 | static const struct dce_hwseq_mask hwseq_mask = { | |
419 | HWSEQ_DCE10_MASK_SH_LIST(_MASK) | |
420 | }; | |
421 | ||
422 | static struct dce_hwseq *dce100_hwseq_create( | |
423 | struct dc_context *ctx) | |
424 | { | |
425 | struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); | |
426 | ||
427 | if (hws) { | |
428 | hws->ctx = ctx; | |
429 | hws->regs = &hwseq_reg; | |
430 | hws->shifts = &hwseq_shift; | |
431 | hws->masks = &hwseq_mask; | |
432 | } | |
433 | return hws; | |
434 | } | |
435 | ||
436 | static const struct resource_create_funcs res_create_funcs = { | |
437 | .read_dce_straps = read_dce_straps, | |
438 | .create_audio = create_audio, | |
439 | .create_stream_encoder = dce100_stream_encoder_create, | |
440 | .create_hwseq = dce100_hwseq_create, | |
441 | }; | |
442 | ||
443 | #define mi_inst_regs(id) { \ | |
197062bf | 444 | MI_DCE8_REG_LIST(id), \ |
4562236b HW |
445 | .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ |
446 | } | |
447 | static const struct dce_mem_input_registers mi_regs[] = { | |
448 | mi_inst_regs(0), | |
449 | mi_inst_regs(1), | |
450 | mi_inst_regs(2), | |
451 | mi_inst_regs(3), | |
452 | mi_inst_regs(4), | |
453 | mi_inst_regs(5), | |
454 | }; | |
455 | ||
456 | static const struct dce_mem_input_shift mi_shifts = { | |
197062bf | 457 | MI_DCE8_MASK_SH_LIST(__SHIFT), |
4562236b HW |
458 | .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT |
459 | }; | |
460 | ||
461 | static const struct dce_mem_input_mask mi_masks = { | |
197062bf | 462 | MI_DCE8_MASK_SH_LIST(_MASK), |
4562236b HW |
463 | .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK |
464 | }; | |
465 | ||
466 | static struct mem_input *dce100_mem_input_create( | |
467 | struct dc_context *ctx, | |
c3489214 | 468 | uint32_t inst) |
4562236b | 469 | { |
c3489214 | 470 | struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); |
4562236b | 471 | |
c3489214 DL |
472 | if (!dce_mi) { |
473 | BREAK_TO_DEBUGGER(); | |
4562236b | 474 | return NULL; |
4562236b HW |
475 | } |
476 | ||
c3489214 DL |
477 | dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); |
478 | dce_mi->wa.single_head_rdreq_dmif_limit = 2; | |
479 | return &dce_mi->base; | |
4562236b HW |
480 | } |
481 | ||
482 | static void dce100_transform_destroy(struct transform **xfm) | |
483 | { | |
484 | dm_free(TO_DCE_TRANSFORM(*xfm)); | |
485 | *xfm = NULL; | |
486 | } | |
487 | ||
488 | static struct transform *dce100_transform_create( | |
489 | struct dc_context *ctx, | |
490 | uint32_t inst) | |
491 | { | |
492 | struct dce_transform *transform = | |
493 | dm_alloc(sizeof(struct dce_transform)); | |
494 | ||
495 | if (!transform) | |
496 | return NULL; | |
497 | ||
498 | if (dce_transform_construct(transform, ctx, inst, | |
499 | &xfm_regs[inst], &xfm_shift, &xfm_mask)) { | |
500 | return &transform->base; | |
501 | } | |
502 | ||
503 | BREAK_TO_DEBUGGER(); | |
504 | dm_free(transform); | |
505 | return NULL; | |
506 | } | |
507 | ||
508 | static struct input_pixel_processor *dce100_ipp_create( | |
e6303950 | 509 | struct dc_context *ctx, uint32_t inst) |
4562236b | 510 | { |
e6303950 | 511 | struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); |
4562236b | 512 | |
e6303950 DL |
513 | if (!ipp) { |
514 | BREAK_TO_DEBUGGER(); | |
4562236b | 515 | return NULL; |
e6303950 | 516 | } |
4562236b | 517 | |
e6303950 DL |
518 | dce_ipp_construct(ipp, ctx, inst, |
519 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
520 | return &ipp->base; | |
4562236b HW |
521 | } |
522 | ||
7fc698a0 TC |
523 | static const struct encoder_feature_support link_enc_feature = { |
524 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
525 | .max_hdmi_pixel_clock = 300000, | |
526 | .flags.bits.IS_HBR2_CAPABLE = true, | |
527 | .flags.bits.IS_TPS3_CAPABLE = true, | |
528 | .flags.bits.IS_YCBCR_CAPABLE = true | |
529 | }; | |
530 | ||
4562236b HW |
531 | struct link_encoder *dce100_link_encoder_create( |
532 | const struct encoder_init_data *enc_init_data) | |
533 | { | |
534 | struct dce110_link_encoder *enc110 = | |
535 | dm_alloc(sizeof(struct dce110_link_encoder)); | |
536 | ||
537 | if (!enc110) | |
538 | return NULL; | |
539 | ||
540 | if (dce110_link_encoder_construct( | |
541 | enc110, | |
542 | enc_init_data, | |
7fc698a0 | 543 | &link_enc_feature, |
4562236b HW |
544 | &link_enc_regs[enc_init_data->transmitter], |
545 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
546 | &link_enc_hpd_regs[enc_init_data->hpd_source])) { | |
547 | ||
4562236b HW |
548 | return &enc110->base; |
549 | } | |
550 | ||
551 | BREAK_TO_DEBUGGER(); | |
552 | dm_free(enc110); | |
553 | return NULL; | |
554 | } | |
555 | ||
556 | struct output_pixel_processor *dce100_opp_create( | |
557 | struct dc_context *ctx, | |
ab3ee7a5 | 558 | uint32_t inst) |
4562236b HW |
559 | { |
560 | struct dce110_opp *opp = | |
561 | dm_alloc(sizeof(struct dce110_opp)); | |
562 | ||
563 | if (!opp) | |
564 | return NULL; | |
565 | ||
566 | if (dce110_opp_construct(opp, | |
ab3ee7a5 | 567 | ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) |
4562236b HW |
568 | return &opp->base; |
569 | ||
570 | BREAK_TO_DEBUGGER(); | |
571 | dm_free(opp); | |
572 | return NULL; | |
573 | } | |
574 | ||
4562236b HW |
575 | struct clock_source *dce100_clock_source_create( |
576 | struct dc_context *ctx, | |
577 | struct dc_bios *bios, | |
578 | enum clock_source_id id, | |
579 | const struct dce110_clk_src_regs *regs, | |
580 | bool dp_clk_src) | |
581 | { | |
582 | struct dce110_clk_src *clk_src = | |
583 | dm_alloc(sizeof(struct dce110_clk_src)); | |
584 | ||
585 | if (!clk_src) | |
586 | return NULL; | |
587 | ||
588 | if (dce110_clk_src_construct(clk_src, ctx, bios, id, | |
589 | regs, &cs_shift, &cs_mask)) { | |
590 | clk_src->base.dp_clk_src = dp_clk_src; | |
591 | return &clk_src->base; | |
592 | } | |
593 | ||
594 | BREAK_TO_DEBUGGER(); | |
595 | return NULL; | |
596 | } | |
597 | ||
598 | void dce100_clock_source_destroy(struct clock_source **clk_src) | |
599 | { | |
600 | dm_free(TO_DCE110_CLK_SRC(*clk_src)); | |
601 | *clk_src = NULL; | |
602 | } | |
603 | ||
604 | static void destruct(struct dce110_resource_pool *pool) | |
605 | { | |
606 | unsigned int i; | |
607 | ||
608 | for (i = 0; i < pool->base.pipe_count; i++) { | |
609 | if (pool->base.opps[i] != NULL) | |
4d35b093 | 610 | dce110_opp_destroy(&pool->base.opps[i]); |
4562236b HW |
611 | |
612 | if (pool->base.transforms[i] != NULL) | |
613 | dce100_transform_destroy(&pool->base.transforms[i]); | |
614 | ||
615 | if (pool->base.ipps[i] != NULL) | |
e6303950 | 616 | dce_ipp_destroy(&pool->base.ipps[i]); |
4562236b HW |
617 | |
618 | if (pool->base.mis[i] != NULL) { | |
c3489214 | 619 | dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); |
4562236b HW |
620 | pool->base.mis[i] = NULL; |
621 | } | |
622 | ||
623 | if (pool->base.timing_generators[i] != NULL) { | |
624 | dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); | |
625 | pool->base.timing_generators[i] = NULL; | |
626 | } | |
627 | } | |
628 | ||
629 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
630 | if (pool->base.stream_enc[i] != NULL) | |
631 | dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); | |
632 | } | |
633 | ||
634 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
635 | if (pool->base.clock_sources[i] != NULL) | |
636 | dce100_clock_source_destroy(&pool->base.clock_sources[i]); | |
637 | } | |
638 | ||
639 | if (pool->base.dp_clock_source != NULL) | |
640 | dce100_clock_source_destroy(&pool->base.dp_clock_source); | |
641 | ||
642 | for (i = 0; i < pool->base.audio_count; i++) { | |
643 | if (pool->base.audios[i] != NULL) | |
644 | dce_aud_destroy(&pool->base.audios[i]); | |
645 | } | |
646 | ||
647 | if (pool->base.display_clock != NULL) | |
9a70eba7 | 648 | dce_disp_clk_destroy(&pool->base.display_clock); |
4562236b HW |
649 | |
650 | if (pool->base.irqs != NULL) | |
651 | dal_irq_service_destroy(&pool->base.irqs); | |
652 | } | |
653 | ||
9345d987 | 654 | static enum dc_status build_mapped_resource( |
4562236b | 655 | const struct core_dc *dc, |
430ef426 DL |
656 | struct validate_context *context, |
657 | struct validate_context *old_context) | |
4562236b HW |
658 | { |
659 | enum dc_status status = DC_OK; | |
ab2541b6 | 660 | uint8_t i, j; |
4562236b | 661 | |
ab2541b6 | 662 | for (i = 0; i < context->stream_count; i++) { |
0971c40e | 663 | struct dc_stream_state *stream = context->streams[i]; |
4562236b | 664 | |
430ef426 | 665 | if (old_context && resource_is_stream_unchanged(old_context, stream)) |
ab2541b6 | 666 | continue; |
4562236b | 667 | |
ab2541b6 AC |
668 | for (j = 0; j < MAX_PIPES; j++) { |
669 | struct pipe_ctx *pipe_ctx = | |
670 | &context->res_ctx.pipe_ctx[j]; | |
4562236b | 671 | |
ab2541b6 AC |
672 | if (context->res_ctx.pipe_ctx[j].stream != stream) |
673 | continue; | |
4562236b | 674 | |
ab2541b6 | 675 | status = dce110_resource_build_pipe_hw_param(pipe_ctx); |
4562236b | 676 | |
ab2541b6 AC |
677 | if (status != DC_OK) |
678 | return status; | |
4562236b | 679 | |
ab2541b6 | 680 | resource_build_info_frame(pipe_ctx); |
4562236b | 681 | |
ab2541b6 AC |
682 | /* do not need to validate non root pipes */ |
683 | break; | |
4562236b HW |
684 | } |
685 | } | |
686 | ||
687 | return DC_OK; | |
688 | } | |
689 | ||
45209ef7 | 690 | bool dce100_validate_bandwidth( |
4562236b HW |
691 | const struct core_dc *dc, |
692 | struct validate_context *context) | |
693 | { | |
694 | /* TODO implement when needed but for now hardcode max value*/ | |
9037d802 DL |
695 | context->bw.dce.dispclk_khz = 681000; |
696 | context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; | |
4562236b | 697 | |
3853c184 | 698 | return true; |
4562236b HW |
699 | } |
700 | ||
701 | static bool dce100_validate_surface_sets( | |
702 | const struct dc_validation_set set[], | |
703 | int set_count) | |
704 | { | |
705 | int i; | |
706 | ||
707 | for (i = 0; i < set_count; i++) { | |
3be5262e | 708 | if (set[i].plane_count == 0) |
4562236b HW |
709 | continue; |
710 | ||
3be5262e | 711 | if (set[i].plane_count > 1) |
4562236b HW |
712 | return false; |
713 | ||
3be5262e | 714 | if (set[i].plane_states[0]->format |
4562236b HW |
715 | >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
716 | return false; | |
717 | } | |
718 | ||
719 | return true; | |
720 | } | |
721 | ||
722 | enum dc_status dce100_validate_with_context( | |
723 | const struct core_dc *dc, | |
724 | const struct dc_validation_set set[], | |
725 | int set_count, | |
430ef426 DL |
726 | struct validate_context *context, |
727 | struct validate_context *old_context) | |
4562236b HW |
728 | { |
729 | struct dc_context *dc_ctx = dc->ctx; | |
730 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
731 | int i; | |
732 | ||
733 | if (!dce100_validate_surface_sets(set, set_count)) | |
734 | return DC_FAIL_SURFACE_VALIDATE; | |
735 | ||
4562236b | 736 | for (i = 0; i < set_count; i++) { |
4fa086b9 LSL |
737 | context->streams[i] = set[i].stream; |
738 | dc_stream_retain(context->streams[i]); | |
ab2541b6 | 739 | context->stream_count++; |
4562236b HW |
740 | } |
741 | ||
430ef426 | 742 | result = resource_map_pool_resources(dc, context, old_context); |
4562236b HW |
743 | |
744 | if (result == DC_OK) | |
430ef426 | 745 | result = resource_map_clock_resources(dc, context, old_context); |
4562236b | 746 | |
a2b8659d | 747 | if (!resource_validate_attach_surfaces(set, set_count, |
430ef426 | 748 | old_context, context, dc->res_pool)) { |
ab2541b6 | 749 | DC_ERROR("Failed to attach surface to stream!\n"); |
4562236b HW |
750 | return DC_FAIL_ATTACH_SURFACES; |
751 | } | |
752 | ||
753 | if (result == DC_OK) | |
9345d987 | 754 | result = build_mapped_resource(dc, context, old_context); |
4562236b HW |
755 | |
756 | if (result == DC_OK) | |
757 | result = resource_build_scaling_params_for_context(dc, context); | |
758 | ||
759 | if (result == DC_OK) | |
45209ef7 DL |
760 | if (!dce100_validate_bandwidth(dc, context)) |
761 | result = DC_FAIL_BANDWIDTH_VALIDATE; | |
4562236b HW |
762 | |
763 | return result; | |
764 | } | |
765 | ||
766 | enum dc_status dce100_validate_guaranteed( | |
767 | const struct core_dc *dc, | |
0971c40e | 768 | struct dc_stream_state *dc_stream, |
4562236b HW |
769 | struct validate_context *context) |
770 | { | |
771 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
772 | ||
4fa086b9 LSL |
773 | context->streams[0] = dc_stream; |
774 | dc_stream_retain(context->streams[0]); | |
ab2541b6 | 775 | context->stream_count++; |
4562236b | 776 | |
430ef426 | 777 | result = resource_map_pool_resources(dc, context, NULL); |
4562236b HW |
778 | |
779 | if (result == DC_OK) | |
430ef426 | 780 | result = resource_map_clock_resources(dc, context, NULL); |
4562236b HW |
781 | |
782 | if (result == DC_OK) | |
9345d987 | 783 | result = build_mapped_resource(dc, context, NULL); |
4562236b HW |
784 | |
785 | if (result == DC_OK) { | |
ab2541b6 AC |
786 | validate_guaranteed_copy_streams( |
787 | context, dc->public.caps.max_streams); | |
4562236b HW |
788 | result = resource_build_scaling_params_for_context(dc, context); |
789 | } | |
790 | ||
791 | if (result == DC_OK) | |
45209ef7 DL |
792 | if (!dce100_validate_bandwidth(dc, context)) |
793 | result = DC_FAIL_BANDWIDTH_VALIDATE; | |
4562236b HW |
794 | |
795 | return result; | |
796 | } | |
797 | ||
798 | static void dce100_destroy_resource_pool(struct resource_pool **pool) | |
799 | { | |
800 | struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); | |
801 | ||
802 | destruct(dce110_pool); | |
803 | dm_free(dce110_pool); | |
804 | *pool = NULL; | |
805 | } | |
806 | ||
c9614aeb | 807 | enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state) |
792671d7 AG |
808 | { |
809 | ||
c9614aeb | 810 | if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
792671d7 AG |
811 | return DC_OK; |
812 | ||
813 | return DC_FAIL_SURFACE_VALIDATE; | |
814 | } | |
815 | ||
4562236b HW |
816 | static const struct resource_funcs dce100_res_pool_funcs = { |
817 | .destroy = dce100_destroy_resource_pool, | |
818 | .link_enc_create = dce100_link_encoder_create, | |
819 | .validate_with_context = dce100_validate_with_context, | |
820 | .validate_guaranteed = dce100_validate_guaranteed, | |
792671d7 | 821 | .validate_bandwidth = dce100_validate_bandwidth, |
c9614aeb | 822 | .validate_plane = dce100_validate_plane, |
4562236b HW |
823 | }; |
824 | ||
825 | static bool construct( | |
826 | uint8_t num_virtual_links, | |
827 | struct core_dc *dc, | |
828 | struct dce110_resource_pool *pool) | |
829 | { | |
830 | unsigned int i; | |
831 | struct dc_context *ctx = dc->ctx; | |
1515a47b | 832 | struct dc_firmware_info info; |
4562236b HW |
833 | struct dc_bios *bp; |
834 | struct dm_pp_static_clock_info static_clk_info = {0}; | |
835 | ||
836 | ctx->dc_bios->regs = &bios_regs; | |
837 | ||
838 | pool->base.res_cap = &res_cap; | |
839 | pool->base.funcs = &dce100_res_pool_funcs; | |
f0e3db90 | 840 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
4562236b HW |
841 | |
842 | bp = ctx->dc_bios; | |
843 | ||
844 | if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && | |
845 | info.external_clock_source_frequency_for_dp != 0) { | |
846 | pool->base.dp_clock_source = | |
847 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); | |
848 | ||
849 | pool->base.clock_sources[0] = | |
850 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); | |
851 | pool->base.clock_sources[1] = | |
852 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); | |
853 | pool->base.clock_sources[2] = | |
854 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); | |
855 | pool->base.clk_src_count = 3; | |
856 | ||
857 | } else { | |
858 | pool->base.dp_clock_source = | |
859 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); | |
860 | ||
861 | pool->base.clock_sources[0] = | |
862 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); | |
863 | pool->base.clock_sources[1] = | |
864 | dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); | |
865 | pool->base.clk_src_count = 2; | |
866 | } | |
867 | ||
868 | if (pool->base.dp_clock_source == NULL) { | |
869 | dm_error("DC: failed to create dp clock source!\n"); | |
870 | BREAK_TO_DEBUGGER(); | |
871 | goto res_create_fail; | |
872 | } | |
873 | ||
874 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
875 | if (pool->base.clock_sources[i] == NULL) { | |
876 | dm_error("DC: failed to create clock sources!\n"); | |
877 | BREAK_TO_DEBUGGER(); | |
878 | goto res_create_fail; | |
879 | } | |
880 | } | |
881 | ||
9a70eba7 DL |
882 | pool->base.display_clock = dce_disp_clk_create(ctx, |
883 | &disp_clk_regs, | |
884 | &disp_clk_shift, | |
885 | &disp_clk_mask); | |
4562236b HW |
886 | if (pool->base.display_clock == NULL) { |
887 | dm_error("DC: failed to create display clock!\n"); | |
888 | BREAK_TO_DEBUGGER(); | |
889 | goto res_create_fail; | |
890 | } | |
891 | ||
892 | ||
893 | /* get static clock information for PPLIB or firmware, save | |
894 | * max_clock_state | |
895 | */ | |
3bad7c5c DL |
896 | if (dm_pp_get_static_clocks(ctx, &static_clk_info)) |
897 | pool->base.display_clock->max_clks_state = | |
e9c58bb4 | 898 | static_clk_info.max_clocks_state; |
4562236b HW |
899 | { |
900 | struct irq_service_init_data init_data; | |
901 | init_data.ctx = dc->ctx; | |
902 | pool->base.irqs = dal_irq_service_dce110_create(&init_data); | |
903 | if (!pool->base.irqs) | |
904 | goto res_create_fail; | |
905 | } | |
906 | ||
907 | /************************************************* | |
908 | * Resource + asic cap harcoding * | |
909 | *************************************************/ | |
f0e3db90 | 910 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
4562236b HW |
911 | pool->base.pipe_count = res_cap.num_timing_generator; |
912 | dc->public.caps.max_downscale_ratio = 200; | |
913 | dc->public.caps.i2c_speed_in_khz = 40; | |
a37656b9 | 914 | dc->public.caps.max_cursor_size = 128; |
4562236b HW |
915 | |
916 | for (i = 0; i < pool->base.pipe_count; i++) { | |
917 | pool->base.timing_generators[i] = | |
918 | dce100_timing_generator_create( | |
919 | ctx, | |
920 | i, | |
921 | &dce100_tg_offsets[i]); | |
922 | if (pool->base.timing_generators[i] == NULL) { | |
923 | BREAK_TO_DEBUGGER(); | |
924 | dm_error("DC: failed to create tg!\n"); | |
925 | goto res_create_fail; | |
926 | } | |
927 | ||
c3489214 | 928 | pool->base.mis[i] = dce100_mem_input_create(ctx, i); |
4562236b HW |
929 | if (pool->base.mis[i] == NULL) { |
930 | BREAK_TO_DEBUGGER(); | |
931 | dm_error( | |
932 | "DC: failed to create memory input!\n"); | |
933 | goto res_create_fail; | |
934 | } | |
935 | ||
e6303950 | 936 | pool->base.ipps[i] = dce100_ipp_create(ctx, i); |
4562236b HW |
937 | if (pool->base.ipps[i] == NULL) { |
938 | BREAK_TO_DEBUGGER(); | |
939 | dm_error( | |
940 | "DC: failed to create input pixel processor!\n"); | |
941 | goto res_create_fail; | |
942 | } | |
943 | ||
944 | pool->base.transforms[i] = dce100_transform_create(ctx, i); | |
945 | if (pool->base.transforms[i] == NULL) { | |
946 | BREAK_TO_DEBUGGER(); | |
947 | dm_error( | |
948 | "DC: failed to create transform!\n"); | |
949 | goto res_create_fail; | |
950 | } | |
951 | ||
ab3ee7a5 | 952 | pool->base.opps[i] = dce100_opp_create(ctx, i); |
4562236b HW |
953 | if (pool->base.opps[i] == NULL) { |
954 | BREAK_TO_DEBUGGER(); | |
955 | dm_error( | |
956 | "DC: failed to create output pixel processor!\n"); | |
957 | goto res_create_fail; | |
958 | } | |
959 | } | |
960 | ||
3be5262e | 961 | dc->public.caps.max_planes = pool->base.pipe_count; |
d4e13b0d | 962 | |
4562236b HW |
963 | if (!resource_construct(num_virtual_links, dc, &pool->base, |
964 | &res_create_funcs)) | |
965 | goto res_create_fail; | |
966 | ||
967 | /* Create hardware sequencer */ | |
968 | if (!dce100_hw_sequencer_construct(dc)) | |
969 | goto res_create_fail; | |
970 | ||
971 | return true; | |
972 | ||
973 | res_create_fail: | |
974 | destruct(pool); | |
975 | ||
976 | return false; | |
977 | } | |
978 | ||
979 | struct resource_pool *dce100_create_resource_pool( | |
980 | uint8_t num_virtual_links, | |
981 | struct core_dc *dc) | |
982 | { | |
983 | struct dce110_resource_pool *pool = | |
984 | dm_alloc(sizeof(struct dce110_resource_pool)); | |
985 | ||
986 | if (!pool) | |
987 | return NULL; | |
988 | ||
989 | if (construct(num_virtual_links, dc, pool)) | |
990 | return &pool->base; | |
991 | ||
992 | BREAK_TO_DEBUGGER(); | |
993 | return NULL; | |
994 | } | |
995 |