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drm/amd/display: Enable DCE12 support
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26#include "dc.h"
27#include "dc_bios_types.h"
28#include "core_types.h"
29#include "core_status.h"
30#include "resource.h"
31#include "hw_sequencer.h"
32#include "dm_helpers.h"
33#include "dce110_hw_sequencer.h"
34#include "dce110_timing_generator.h"
35
36#include "bios/bios_parser_helper.h"
37#include "timing_generator.h"
38#include "mem_input.h"
39#include "opp.h"
40#include "ipp.h"
41#include "transform.h"
42#include "stream_encoder.h"
43#include "link_encoder.h"
44#include "clock_source.h"
5e7773a2 45#include "abm.h"
4562236b
HW		 46#include "audio.h"
47#include "dce/dce_hwseq.h"
48
49/* include DCE11 register header files */
50#include "dce/dce_11_0_d.h"
51#include "dce/dce_11_0_sh_mask.h"
e266fdf6 52#include "custom_float.h"
4562236b
HW		 53
54struct dce110_hw_seq_reg_offsets {
55 uint32_t crtc;
56};
57
58static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
59{
60 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
61},
62{
63 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
64},
65{
66 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
67},
68{
69 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
70}
71};
72
73#define HW_REG_BLND(reg, id)\
74 (reg + reg_offsets[id].blnd)
75
76#define HW_REG_CRTC(reg, id)\
77 (reg + reg_offsets[id].crtc)
78
79#define MAX_WATERMARK 0xFFFF
80#define SAFE_NBP_MARK 0x7FFF
81
82/*******************************************************************************
83 * Private definitions
84 ******************************************************************************/
85/***************************PIPE_CONTROL***********************************/
86static void dce110_init_pte(struct dc_context *ctx)
87{
88 uint32_t addr;
89 uint32_t value = 0;
90 uint32_t chunk_int = 0;
91 uint32_t chunk_mul = 0;
92
93 addr = mmUNP_DVMM_PTE_CONTROL;
94 value = dm_read_reg(ctx, addr);
95
96 set_reg_field_value(
97 value,
98 0,
99 DVMM_PTE_CONTROL,
100 DVMM_USE_SINGLE_PTE);
101
102 set_reg_field_value(
103 value,
104 1,
105 DVMM_PTE_CONTROL,
106 DVMM_PTE_BUFFER_MODE0);
107
108 set_reg_field_value(
109 value,
110 1,
111 DVMM_PTE_CONTROL,
112 DVMM_PTE_BUFFER_MODE1);
113
114 dm_write_reg(ctx, addr, value);
115
116 addr = mmDVMM_PTE_REQ;
117 value = dm_read_reg(ctx, addr);
118
119 chunk_int = get_reg_field_value(
120 value,
121 DVMM_PTE_REQ,
122 HFLIP_PTEREQ_PER_CHUNK_INT);
123
124 chunk_mul = get_reg_field_value(
125 value,
126 DVMM_PTE_REQ,
127 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
128
129 if (chunk_int != 0x4 || chunk_mul != 0x4) {
130
131 set_reg_field_value(
132 value,
133 255,
134 DVMM_PTE_REQ,
135 MAX_PTEREQ_TO_ISSUE);
136
137 set_reg_field_value(
138 value,
139 4,
140 DVMM_PTE_REQ,
141 HFLIP_PTEREQ_PER_CHUNK_INT);
142
143 set_reg_field_value(
144 value,
145 4,
146 DVMM_PTE_REQ,
147 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
148
149 dm_write_reg(ctx, addr, value);
150 }
151}
152/**************************************************************************/
153
154static void enable_display_pipe_clock_gating(
155 struct dc_context *ctx,
156 bool clock_gating)
157{
158 /*TODO*/
159}
160
161static bool dce110_enable_display_power_gating(
162 struct core_dc *dc,
163 uint8_t controller_id,
164 struct dc_bios *dcb,
165 enum pipe_gating_control power_gating)
166{
167 enum bp_result bp_result = BP_RESULT_OK;
168 enum bp_pipe_control_action cntl;
169 struct dc_context *ctx = dc->ctx;
170 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
171
172 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
173 return true;
174
175 if (power_gating == PIPE_GATING_CONTROL_INIT)
176 cntl = ASIC_PIPE_INIT;
177 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
178 cntl = ASIC_PIPE_ENABLE;
179 else
180 cntl = ASIC_PIPE_DISABLE;
181
182 if (controller_id == underlay_idx)
183 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
184
185 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
186
187 bp_result = dcb->funcs->enable_disp_power_gating(
188 dcb, controller_id + 1, cntl);
189
190 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
191 * by default when command table is called
192 *
193 * Bios parser accepts controller_id = 6 as indicative of
194 * underlay pipe in dce110. But we do not support more
195 * than 3.
196 */
197 if (controller_id < CONTROLLER_ID_MAX - 1)
198 dm_write_reg(ctx,
199 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
200 0);
201 }
202
203 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
204 dce110_init_pte(ctx);
205
206 if (bp_result == BP_RESULT_OK)
207 return true;
208 else
209 return false;
210}
211
212static void build_prescale_params(struct ipp_prescale_params *prescale_params,
213 const struct core_surface *surface)
214{
215 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
216
217 switch (surface->public.format) {
218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
8693049a 219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4562236b
HW		 220 prescale_params->scale = 0x2020;
221 break;
222 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
223 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
224 prescale_params->scale = 0x2008;
225 break;
226 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
227 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
228 prescale_params->scale = 0x2000;
229 break;
230 default:
231 ASSERT(false);
d7194cf6 232 break;
4562236b
HW		 233 }
234}
235
5936223f
JL		 236
237/* Only use LUT for 8 bit formats */
238static bool use_lut(const struct core_surface *surface)
239{
240 switch (surface->public.format) {
241 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
242 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
243 return true;
244 default:
245 return false;
246 }
247}
248
d7194cf6 249static bool dce110_set_input_transfer_func(
fb735a9f 250 struct pipe_ctx *pipe_ctx,
4562236b
HW		 251 const struct core_surface *surface)
252{
fb735a9f 253 struct input_pixel_processor *ipp = pipe_ctx->ipp;
90e508ba
AK		 254 const struct core_transfer_func *tf = NULL;
255 struct ipp_prescale_params prescale_params = { 0 };
256 bool result = true;
257
258 if (ipp == NULL)
259 return false;
260
261 if (surface->public.in_transfer_func)
262 tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func);
263
264 build_prescale_params(&prescale_params, surface);
265 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
266
5936223f 267 if (surface->public.gamma_correction && use_lut(surface))
d7194cf6
AC		 268 ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
269
90e508ba
AK		 270 if (tf == NULL) {
271 /* Default case if no input transfer function specified */
272 ipp->funcs->ipp_set_degamma(ipp,
306dadf0 273 IPP_DEGAMMA_MODE_HW_sRGB);
90e508ba
AK		 274 } else if (tf->public.type == TF_TYPE_PREDEFINED) {
275 switch (tf->public.tf) {
276 case TRANSFER_FUNCTION_SRGB:
277 ipp->funcs->ipp_set_degamma(ipp,
278 IPP_DEGAMMA_MODE_HW_sRGB);
279 break;
280 case TRANSFER_FUNCTION_BT709:
281 ipp->funcs->ipp_set_degamma(ipp,
282 IPP_DEGAMMA_MODE_HW_xvYCC);
283 break;
284 case TRANSFER_FUNCTION_LINEAR:
285 ipp->funcs->ipp_set_degamma(ipp,
286 IPP_DEGAMMA_MODE_BYPASS);
287 break;
288 case TRANSFER_FUNCTION_PQ:
289 result = false;
290 break;
291 default:
292 result = false;
d7194cf6 293 break;
90e508ba 294 }
70063a59
AZ		 295 } else if (tf->public.type == TF_TYPE_BYPASS) {
296 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
90e508ba
AK		 297 } else {
298 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
299 result = false;
300 }
301
302 return result;
303}
304
fcd2f4bf
AZ		 305static bool convert_to_custom_float(
306 struct pwl_result_data *rgb_resulted,
307 struct curve_points *arr_points,
308 uint32_t hw_points_num)
309{
310 struct custom_float_format fmt;
311
312 struct pwl_result_data *rgb = rgb_resulted;
313
314 uint32_t i = 0;
315
316 fmt.exponenta_bits = 6;
317 fmt.mantissa_bits = 12;
318 fmt.sign = true;
319
320 if (!convert_to_custom_float_format(
321 arr_points[0].x,
322 &fmt,
323 &arr_points[0].custom_float_x)) {
324 BREAK_TO_DEBUGGER();
325 return false;
326 }
327
328 if (!convert_to_custom_float_format(
329 arr_points[0].offset,
330 &fmt,
331 &arr_points[0].custom_float_offset)) {
332 BREAK_TO_DEBUGGER();
333 return false;
334 }
335
336 if (!convert_to_custom_float_format(
337 arr_points[0].slope,
338 &fmt,
339 &arr_points[0].custom_float_slope)) {
340 BREAK_TO_DEBUGGER();
341 return false;
342 }
343
344 fmt.mantissa_bits = 10;
345 fmt.sign = false;
346
347 if (!convert_to_custom_float_format(
348 arr_points[1].x,
349 &fmt,
350 &arr_points[1].custom_float_x)) {
351 BREAK_TO_DEBUGGER();
352 return false;
353 }
354
355 if (!convert_to_custom_float_format(
356 arr_points[1].y,
357 &fmt,
358 &arr_points[1].custom_float_y)) {
359 BREAK_TO_DEBUGGER();
360 return false;
361 }
362
363 if (!convert_to_custom_float_format(
364 arr_points[2].slope,
365 &fmt,
366 &arr_points[2].custom_float_slope)) {
367 BREAK_TO_DEBUGGER();
368 return false;
369 }
370
371 fmt.mantissa_bits = 12;
372 fmt.sign = true;
373
374 while (i != hw_points_num) {
375 if (!convert_to_custom_float_format(
376 rgb->red,
377 &fmt,
378 &rgb->red_reg)) {
379 BREAK_TO_DEBUGGER();
380 return false;
381 }
382
383 if (!convert_to_custom_float_format(
384 rgb->green,
385 &fmt,
386 &rgb->green_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(
392 rgb->blue,
393 &fmt,
394 &rgb->blue_reg)) {
395 BREAK_TO_DEBUGGER();
396 return false;
397 }
398
399 if (!convert_to_custom_float_format(
400 rgb->delta_red,
401 &fmt,
402 &rgb->delta_red_reg)) {
403 BREAK_TO_DEBUGGER();
404 return false;
405 }
406
407 if (!convert_to_custom_float_format(
408 rgb->delta_green,
409 &fmt,
410 &rgb->delta_green_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 if (!convert_to_custom_float_format(
416 rgb->delta_blue,
417 &fmt,
418 &rgb->delta_blue_reg)) {
419 BREAK_TO_DEBUGGER();
420 return false;
421 }
422
423 ++rgb;
424 ++i;
425 }
426
427 return true;
428}
429
e266fdf6 430static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
fcd2f4bf
AZ		 431 *output_tf, struct pwl_params *regamma_params)
432{
23ae4f8e
AZ		 433 struct curve_points *arr_points;
434 struct pwl_result_data *rgb_resulted;
435 struct pwl_result_data *rgb;
436 struct pwl_result_data *rgb_plus_1;
fcd2f4bf
AZ		 437 struct fixed31_32 y_r;
438 struct fixed31_32 y_g;
439 struct fixed31_32 y_b;
440 struct fixed31_32 y1_min;
441 struct fixed31_32 y3_max;
442
443 int32_t segment_start, segment_end;
23ae4f8e
AZ		 444 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
445
70063a59
AZ		 446 if (output_tf == NULL || regamma_params == NULL ||
447 output_tf->type == TF_TYPE_BYPASS)
23ae4f8e
AZ		 448 return false;
449
450 arr_points = regamma_params->arr_points;
451 rgb_resulted = regamma_params->rgb_resulted;
452 hw_points = 0;
fcd2f4bf
AZ		 453
454 memset(regamma_params, 0, sizeof(struct pwl_params));
455
456 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
534db198 457 /* 16 segments
fcd2f4bf
AZ		 458 * segments are from 2^-11 to 2^5
459 */
460 segment_start = -11;
461 segment_end = 5;
462
534db198
AZ		 463 seg_distr[0] = 2;
464 seg_distr[1] = 2;
465 seg_distr[2] = 2;
466 seg_distr[3] = 2;
467 seg_distr[4] = 2;
468 seg_distr[5] = 2;
469 seg_distr[6] = 3;
470 seg_distr[7] = 4;
471 seg_distr[8] = 4;
472 seg_distr[9] = 4;
473 seg_distr[10] = 4;
474 seg_distr[11] = 5;
475 seg_distr[12] = 5;
476 seg_distr[13] = 5;
477 seg_distr[14] = 5;
478 seg_distr[15] = 5;
479
fcd2f4bf 480 } else {
534db198 481 /* 10 segments
fcd2f4bf
AZ		 482 * segment is from 2^-10 to 2^0
483 */
484 segment_start = -10;
485 segment_end = 0;
534db198
AZ		 486
487 seg_distr[0] = 3;
488 seg_distr[1] = 4;
489 seg_distr[2] = 4;
490 seg_distr[3] = 4;
491 seg_distr[4] = 4;
492 seg_distr[5] = 4;
493 seg_distr[6] = 4;
494 seg_distr[7] = 4;
495 seg_distr[8] = 5;
496 seg_distr[9] = 5;
497 seg_distr[10] = -1;
498 seg_distr[11] = -1;
499 seg_distr[12] = -1;
500 seg_distr[13] = -1;
501 seg_distr[14] = -1;
502 seg_distr[15] = -1;
503 }
504
505 for (k = 0; k < 16; k++) {
506 if (seg_distr[k] != -1)
507 hw_points += (1 << seg_distr[k]);
fcd2f4bf
AZ		 508 }
509
fcd2f4bf 510 j = 0;
534db198
AZ		 511 for (k = 0; k < (segment_end - segment_start); k++) {
512 increment = 32 / (1 << seg_distr[k]);
513 start_index = (segment_start + k + 25) * 32;
514 for (i = start_index; i < start_index + 32; i += increment) {
515 if (j == hw_points - 1)
516 break;
517 rgb_resulted[j].red = output_tf->tf_pts.red[i];
518 rgb_resulted[j].green = output_tf->tf_pts.green[i];
519 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
520 j++;
521 }
fcd2f4bf
AZ		 522 }
523
534db198
AZ		 524 /* last point */
525 start_index = (segment_end + 25) * 32;
526 rgb_resulted[hw_points - 1].red =
527 output_tf->tf_pts.red[start_index];
528 rgb_resulted[hw_points - 1].green =
529 output_tf->tf_pts.green[start_index];
530 rgb_resulted[hw_points - 1].blue =
531 output_tf->tf_pts.blue[start_index];
532
fcd2f4bf
AZ		 533 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
534 dal_fixed31_32_from_int(segment_start));
535 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
536 dal_fixed31_32_from_int(segment_end));
537 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
538 dal_fixed31_32_from_int(segment_end));
539
540 y_r = rgb_resulted[0].red;
541 y_g = rgb_resulted[0].green;
542 y_b = rgb_resulted[0].blue;
543
544 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
545
546 arr_points[0].y = y1_min;
547 arr_points[0].slope = dal_fixed31_32_div(
548 arr_points[0].y,
549 arr_points[0].x);
550
551 y_r = rgb_resulted[hw_points - 1].red;
552 y_g = rgb_resulted[hw_points - 1].green;
553 y_b = rgb_resulted[hw_points - 1].blue;
554
555 /* see comment above, m_arrPoints[1].y should be the Y value for the
556 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
557 */
558 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
559
560 arr_points[1].y = y3_max;
561 arr_points[2].y = y3_max;
562
563 arr_points[1].slope = dal_fixed31_32_zero;
564 arr_points[2].slope = dal_fixed31_32_zero;
565
566 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
567 /* for PQ, we want to have a straight line from last HW X point,
568 * and the slope to be such that we hit 1.0 at 10000 nits.
569 */
570 const struct fixed31_32 end_value =
571 dal_fixed31_32_from_int(125);
572
573 arr_points[1].slope = dal_fixed31_32_div(
574 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
575 dal_fixed31_32_sub(end_value, arr_points[1].x));
576 arr_points[2].slope = dal_fixed31_32_div(
577 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
578 dal_fixed31_32_sub(end_value, arr_points[1].x));
579 }
580
581 regamma_params->hw_points_num = hw_points;
582
534db198
AZ		 583 i = 1;
584 for (k = 0; k < 16 && i < 16; k++) {
585 if (seg_distr[k] != -1) {
586 regamma_params->arr_curve_points[k].segments_num =
587 seg_distr[k];
588 regamma_params->arr_curve_points[i].offset =
589 regamma_params->arr_curve_points[k].
590 offset + (1 << seg_distr[k]);
591 }
592 i++;
fcd2f4bf
AZ		 593 }
594
534db198
AZ		 595 if (seg_distr[k] != -1)
596 regamma_params->arr_curve_points[k].segments_num =
597 seg_distr[k];
598
23ae4f8e
AZ		 599 rgb = rgb_resulted;
600 rgb_plus_1 = rgb_resulted + 1;
fcd2f4bf
AZ		 601
602 i = 1;
603
604 while (i != hw_points + 1) {
605 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
606 rgb_plus_1->red = rgb->red;
607 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
608 rgb_plus_1->green = rgb->green;
609 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
610 rgb_plus_1->blue = rgb->blue;
611
612 rgb->delta_red = dal_fixed31_32_sub(
613 rgb_plus_1->red,
614 rgb->red);
615 rgb->delta_green = dal_fixed31_32_sub(
616 rgb_plus_1->green,
617 rgb->green);
618 rgb->delta_blue = dal_fixed31_32_sub(
619 rgb_plus_1->blue,
620 rgb->blue);
621
622 ++rgb_plus_1;
623 ++rgb;
624 ++i;
625 }
626
627 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
628
629 return true;
630}
631
90e508ba
AK		 632static bool dce110_set_output_transfer_func(
633 struct pipe_ctx *pipe_ctx,
634 const struct core_surface *surface, /* Surface - To be removed */
635 const struct core_stream *stream)
636{
fb735a9f 637 struct output_pixel_processor *opp = pipe_ctx->opp;
4562236b
HW		 638
639 opp->funcs->opp_power_on_regamma_lut(opp, true);
cc0cb445 640 opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM;
4562236b 641
d7194cf6 642 if (stream->public.out_transfer_func &&
cc0cb445 643 stream->public.out_transfer_func->type ==
fcd2f4bf 644 TF_TYPE_PREDEFINED &&
cc0cb445 645 stream->public.out_transfer_func->tf ==
fcd2f4bf 646 TRANSFER_FUNCTION_SRGB) {
d7194cf6 647 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
fcd2f4bf 648 } else if (dce110_translate_regamma_to_hw_format(
cc0cb445
LE		 649 stream->public.out_transfer_func, opp->regamma_params)) {
650 opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params);
651 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
4562236b 652 } else {
4562236b
HW		 653 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
654 }
655
656 opp->funcs->opp_power_on_regamma_lut(opp, false);
657
cc0cb445 658 return true;
4562236b
HW		 659}
660
661static enum dc_status bios_parser_crtc_source_select(
662 struct pipe_ctx *pipe_ctx)
663{
664 struct dc_bios *dcb;
665 /* call VBIOS table to set CRTC source for the HW
666 * encoder block
667 * note: video bios clears all FMT setting here. */
668 struct bp_crtc_source_select crtc_source_select = {0};
669 const struct core_sink *sink = pipe_ctx->stream->sink;
670
671 crtc_source_select.engine_id = pipe_ctx->stream_enc->id;
672 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
673 /*TODO: Need to un-hardcode color depth, dp_audio and account for
674 * the case where signal and sink signal is different (translator
675 * encoder)*/
676 crtc_source_select.signal = pipe_ctx->stream->signal;
677 crtc_source_select.enable_dp_audio = false;
678 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
679 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
680
681 dcb = sink->ctx->dc_bios;
682
683 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
684 dcb,
685 &crtc_source_select)) {
686 return DC_ERROR_UNEXPECTED;
687 }
688
689 return DC_OK;
690}
691
692void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
693{
86e2e1be
HW		 694 ASSERT(pipe_ctx->stream);
695
696 if (pipe_ctx->stream_enc == NULL)
697 return; /* this is not root pipe */
698
4562236b
HW		 699 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
700 pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
701 pipe_ctx->stream_enc,
702 &pipe_ctx->encoder_info_frame);
703 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
704 pipe_ctx->stream_enc->funcs->update_dp_info_packets(
705 pipe_ctx->stream_enc,
706 &pipe_ctx->encoder_info_frame);
707}
708
709void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
710{
711 enum dc_lane_count lane_count =
712 pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count;
713
714 struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
715 struct core_link *link = pipe_ctx->stream->sink->link;
716
717 /* 1. update AVI info frame (HDMI, DP)
718 * we always need to update info frame
719 */
720 uint32_t active_total_with_borders;
721 uint32_t early_control = 0;
722 struct timing_generator *tg = pipe_ctx->tg;
723
724 /* TODOFPGA may change to hwss.update_info_frame */
725 dce110_update_info_frame(pipe_ctx);
726 /* enable early control to avoid corruption on DP monitor*/
727 active_total_with_borders =
728 timing->h_addressable
729 + timing->h_border_left
730 + timing->h_border_right;
731
732 if (lane_count != 0)
733 early_control = active_total_with_borders % lane_count;
734
735 if (early_control == 0)
736 early_control = lane_count;
737
738 tg->funcs->set_early_control(tg, early_control);
739
740 /* enable audio only within mode set */
741 if (pipe_ctx->audio != NULL) {
742 if (dc_is_dp_signal(pipe_ctx->stream->signal))
743 pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc);
744 }
745
746 /* For MST, there are multiply stream go to only one link.
747 * connect DIG back_end to front_end while enable_stream and
748 * disconnect them during disable_stream
749 * BY this, it is logic clean to separate stream and link */
750 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
751 pipe_ctx->stream_enc->id, true);
752
753}
754
755void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
756{
757 struct core_stream *stream = pipe_ctx->stream;
758 struct core_link *link = stream->sink->link;
759
760 if (pipe_ctx->audio) {
761 pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio);
762
763 if (dc_is_dp_signal(pipe_ctx->stream->signal))
764 pipe_ctx->stream_enc->funcs->dp_audio_disable(
765 pipe_ctx->stream_enc);
766 else
767 pipe_ctx->stream_enc->funcs->hdmi_audio_disable(
768 pipe_ctx->stream_enc);
769
770 pipe_ctx->audio = NULL;
771
772 /* TODO: notify audio driver for if audio modes list changed
773 * add audio mode list change flag */
774 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
775 * stream->stream_engine_id);
776 */
777 }
778
779 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
780 pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets(
781 pipe_ctx->stream_enc);
782
783 if (dc_is_dp_signal(pipe_ctx->stream->signal))
784 pipe_ctx->stream_enc->funcs->stop_dp_info_packets(
785 pipe_ctx->stream_enc);
786
787 pipe_ctx->stream_enc->funcs->audio_mute_control(
788 pipe_ctx->stream_enc, true);
789
790
791 /* blank at encoder level */
792 if (dc_is_dp_signal(pipe_ctx->stream->signal))
793 pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc);
794
795 link->link_enc->funcs->connect_dig_be_to_fe(
796 link->link_enc,
797 pipe_ctx->stream_enc->id,
798 false);
799
800}
801
802void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
803 struct dc_link_settings *link_settings)
804{
805 struct encoder_unblank_param params = { { 0 } };
806
807 /* only 3 items below are used by unblank */
6235b23c 808 params.pixel_clk_khz =
4562236b
HW		 809 pipe_ctx->stream->public.timing.pix_clk_khz;
810 params.link_settings.link_rate = link_settings->link_rate;
811 pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, &params);
812}
813
814static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
815{
816 switch (crtc_id) {
817 case CONTROLLER_ID_D0:
818 return DTO_SOURCE_ID0;
819 case CONTROLLER_ID_D1:
820 return DTO_SOURCE_ID1;
821 case CONTROLLER_ID_D2:
822 return DTO_SOURCE_ID2;
823 case CONTROLLER_ID_D3:
824 return DTO_SOURCE_ID3;
825 case CONTROLLER_ID_D4:
826 return DTO_SOURCE_ID4;
827 case CONTROLLER_ID_D5:
828 return DTO_SOURCE_ID5;
829 default:
830 return DTO_SOURCE_UNKNOWN;
831 }
832}
833
834static void build_audio_output(
835 const struct pipe_ctx *pipe_ctx,
836 struct audio_output *audio_output)
837{
838 const struct core_stream *stream = pipe_ctx->stream;
839 audio_output->engine_id = pipe_ctx->stream_enc->id;
840
841 audio_output->signal = pipe_ctx->stream->signal;
842
843 /* audio_crtc_info */
844
845 audio_output->crtc_info.h_total =
846 stream->public.timing.h_total;
847
848 /*
849 * Audio packets are sent during actual CRTC blank physical signal, we
850 * need to specify actual active signal portion
851 */
852 audio_output->crtc_info.h_active =
853 stream->public.timing.h_addressable
854 + stream->public.timing.h_border_left
855 + stream->public.timing.h_border_right;
856
857 audio_output->crtc_info.v_active =
858 stream->public.timing.v_addressable
859 + stream->public.timing.v_border_top
860 + stream->public.timing.v_border_bottom;
861
862 audio_output->crtc_info.pixel_repetition = 1;
863
864 audio_output->crtc_info.interlaced =
865 stream->public.timing.flags.INTERLACE;
866
867 audio_output->crtc_info.refresh_rate =
868 (stream->public.timing.pix_clk_khz*1000)/
869 (stream->public.timing.h_total*stream->public.timing.v_total);
870
871 audio_output->crtc_info.color_depth =
872 stream->public.timing.display_color_depth;
873
874 audio_output->crtc_info.requested_pixel_clock =
875 pipe_ctx->pix_clk_params.requested_pix_clk;
876
4562236b
HW		 877 audio_output->crtc_info.calculated_pixel_clock =
878 pipe_ctx->pix_clk_params.requested_pix_clk;
879
87b58768
CL		 880/*for HDMI, audio ACR is with deep color ratio factor*/
881 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
882 audio_output->crtc_info.requested_pixel_clock ==
883 stream->public.timing.pix_clk_khz) {
884 if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
885 audio_output->crtc_info.requested_pixel_clock =
886 audio_output->crtc_info.requested_pixel_clock/2;
887 audio_output->crtc_info.calculated_pixel_clock =
888 pipe_ctx->pix_clk_params.requested_pix_clk/2;
87b58768 889
87b58768
CL		 890 }
891 }
892
4562236b
HW		 893 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
894 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
895 audio_output->pll_info.dp_dto_source_clock_in_khz =
1a687574
DL		 896 pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
897 pipe_ctx->dis_clk);
4562236b
HW		 898 }
899
900 audio_output->pll_info.feed_back_divider =
901 pipe_ctx->pll_settings.feedback_divider;
902
903 audio_output->pll_info.dto_source =
904 translate_to_dto_source(
905 pipe_ctx->pipe_idx + 1);
906
907 /* TODO hard code to enable for now. Need get from stream */
908 audio_output->pll_info.ss_enabled = true;
909
910 audio_output->pll_info.ss_percentage =
911 pipe_ctx->pll_settings.ss_percentage;
912}
913
914static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
915 struct tg_color *color)
916{
917 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
918
919 switch (pipe_ctx->scl_data.format) {
920 case PIXEL_FORMAT_ARGB8888:
921 /* set boarder color to red */
922 color->color_r_cr = color_value;
923 break;
924
925 case PIXEL_FORMAT_ARGB2101010:
926 /* set boarder color to blue */
927 color->color_b_cb = color_value;
928 break;
929 case PIXEL_FORMAT_420BPP12:
b2d0a103 930 case PIXEL_FORMAT_420BPP15:
4562236b
HW		 931 /* set boarder color to green */
932 color->color_g_y = color_value;
933 break;
934 case PIXEL_FORMAT_FP16:
935 /* set boarder color to white */
936 color->color_r_cr = color_value;
937 color->color_b_cb = color_value;
938 color->color_g_y = color_value;
939 break;
940 default:
941 break;
942 }
943}
944
945static void program_scaler(const struct core_dc *dc,
946 const struct pipe_ctx *pipe_ctx)
947{
948 struct tg_color color = {0};
949
950 if (dc->public.debug.surface_visual_confirm)
951 get_surface_visual_confirm_color(pipe_ctx, &color);
952 else
953 color_space_to_black_color(dc,
954 pipe_ctx->stream->public.output_color_space,
955 &color);
956
957 pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth(
958 pipe_ctx->xfm,
959 pipe_ctx->scl_data.lb_params.depth,
960 &pipe_ctx->stream->bit_depth_params);
961
962 if (pipe_ctx->tg->funcs->set_overscan_blank_color)
963 pipe_ctx->tg->funcs->set_overscan_blank_color(
964 pipe_ctx->tg,
965 &color);
966
967 pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm,
968 &pipe_ctx->scl_data);
969}
970
4b5e7d62 971static enum dc_status dce110_prog_pixclk_crtc_otg(
4562236b
HW		 972 struct pipe_ctx *pipe_ctx,
973 struct validate_context *context,
974 struct core_dc *dc)
975{
976 struct core_stream *stream = pipe_ctx->stream;
977 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
978 pipe_ctx[pipe_ctx->pipe_idx];
979 struct tg_color black_color = {0};
980
981 if (!pipe_ctx_old->stream) {
982
983 /* program blank color */
984 color_space_to_black_color(dc,
985 stream->public.output_color_space, &black_color);
986 pipe_ctx->tg->funcs->set_blank_color(
987 pipe_ctx->tg,
988 &black_color);
4b5e7d62 989
4562236b
HW		 990 /*
991 * Must blank CRTC after disabling power gating and before any
992 * programming, otherwise CRTC will be hung in bad state
993 */
994 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
995
996 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
997 pipe_ctx->clock_source,
998 &pipe_ctx->pix_clk_params,
999 &pipe_ctx->pll_settings)) {
1000 BREAK_TO_DEBUGGER();
1001 return DC_ERROR_UNEXPECTED;
1002 }
1003
1004 pipe_ctx->tg->funcs->program_timing(
1005 pipe_ctx->tg,
1006 &stream->public.timing,
1007 true);
1008 }
1009
1010 if (!pipe_ctx_old->stream) {
1011 if (false == pipe_ctx->tg->funcs->enable_crtc(
1012 pipe_ctx->tg)) {
1013 BREAK_TO_DEBUGGER();
1014 return DC_ERROR_UNEXPECTED;
1015 }
1016 }
1017
1018 return DC_OK;
1019}
1020
1021static enum dc_status apply_single_controller_ctx_to_hw(
1022 struct pipe_ctx *pipe_ctx,
1023 struct validate_context *context,
1024 struct core_dc *dc)
1025{
1026 struct core_stream *stream = pipe_ctx->stream;
1027 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
1028 pipe_ctx[pipe_ctx->pipe_idx];
1029
1030 /* */
1031 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1032
1033 pipe_ctx->opp->funcs->opp_set_dyn_expansion(
1034 pipe_ctx->opp,
1035 COLOR_SPACE_YCBCR601,
1036 stream->public.timing.display_color_depth,
1037 pipe_ctx->stream->signal);
1038
181a888f
CL		 1039 /* FPGA does not program backend */
1040 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4562236b
HW		 1041 pipe_ctx->opp->funcs->opp_program_fmt(
1042 pipe_ctx->opp,
1043 &stream->bit_depth_params,
1044 &stream->clamping);
4562236b 1045 return DC_OK;
181a888f 1046 }
4562236b
HW		 1047 /* TODO: move to stream encoder */
1048 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1049 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1050 BREAK_TO_DEBUGGER();
1051 return DC_ERROR_UNEXPECTED;
1052 }
1053
1054 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1055 stream->sink->link->link_enc->funcs->setup(
1056 stream->sink->link->link_enc,
1057 pipe_ctx->stream->signal);
1058
181a888f
CL		 1059/*vbios crtc_source_selection and encoder_setup will override fmt_C*/
1060 pipe_ctx->opp->funcs->opp_program_fmt(
1061 pipe_ctx->opp,
1062 &stream->bit_depth_params,
1063 &stream->clamping);
1064
4562236b
HW		 1065 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1066 pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
1067 pipe_ctx->stream_enc,
1068 &stream->public.timing,
1069 stream->public.output_color_space);
1070
1071 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1072 pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute(
1073 pipe_ctx->stream_enc,
1074 &stream->public.timing,
1075 stream->phy_pix_clk,
1076 pipe_ctx->audio != NULL);
1077
1078 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1079 pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute(
1080 pipe_ctx->stream_enc,
1081 &stream->public.timing,
1082 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1083 true : false);
1084
1085 if (!pipe_ctx_old->stream) {
1086 core_link_enable_stream(pipe_ctx);
1087
b3c64dff
CL		 1088 resource_build_info_frame(pipe_ctx);
1089 dce110_update_info_frame(pipe_ctx);
4562236b
HW		 1090 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1091 dce110_unblank_stream(pipe_ctx,
1092 &stream->sink->link->public.cur_link_settings);
1093 }
1094
1095 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1096 /* program_scaler and allocate_mem_input are not new asic */
1097 if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data,
1098 &pipe_ctx->scl_data,
1099 sizeof(struct scaler_data)) != 0)
1100 program_scaler(dc, pipe_ctx);
1101
1102 /* mst support - use total stream count */
1103 pipe_ctx->mi->funcs->allocate_mem_input(
1104 pipe_ctx->mi,
1105 stream->public.timing.h_total,
1106 stream->public.timing.v_total,
1107 stream->public.timing.pix_clk_khz,
ab2541b6 1108 context->stream_count);
4562236b
HW		 1109
1110 return DC_OK;
1111}
1112
1113/******************************************************************************/
1114
1115static void power_down_encoders(struct core_dc *dc)
1116{
1117 int i;
1118
1119 for (i = 0; i < dc->link_count; i++) {
1120 dc->links[i]->link_enc->funcs->disable_output(
1121 dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
1122 }
1123}
1124
1125static void power_down_controllers(struct core_dc *dc)
1126{
1127 int i;
1128
1129 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1130 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1131 dc->res_pool->timing_generators[i]);
1132 }
1133}
1134
1135static void power_down_clock_sources(struct core_dc *dc)
1136{
1137 int i;
1138
1139 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1140 dc->res_pool->dp_clock_source) == false)
1141 dm_error("Failed to power down pll! (dp clk src)\n");
1142
1143 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1144 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1145 dc->res_pool->clock_sources[i]) == false)
1146 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1147 }
1148}
1149
1150static void power_down_all_hw_blocks(struct core_dc *dc)
1151{
1152 power_down_encoders(dc);
1153
1154 power_down_controllers(dc);
1155
1156 power_down_clock_sources(dc);
1157}
1158
1159static void disable_vga_and_power_gate_all_controllers(
1160 struct core_dc *dc)
1161{
1162 int i;
1163 struct timing_generator *tg;
1164 struct dc_context *ctx = dc->ctx;
1165
1166 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1167 tg = dc->res_pool->timing_generators[i];
1168
1169 tg->funcs->disable_vga(tg);
1170
1171 /* Enable CLOCK gating for each pipe BEFORE controller
1172 * powergating. */
1173 enable_display_pipe_clock_gating(ctx,
1174 true);
1175
1176 dc->hwss.power_down_front_end(
1177 dc, &dc->current_context->res_ctx.pipe_ctx[i]);
1178 }
1179}
1180
1181/**
1182 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1183 * 1. Power down all DC HW blocks
1184 * 2. Disable VGA engine on all controllers
1185 * 3. Enable power gating for controller
1186 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1187 */
1188void dce110_enable_accelerated_mode(struct core_dc *dc)
1189{
1190 power_down_all_hw_blocks(dc);
1191
1192 disable_vga_and_power_gate_all_controllers(dc);
1193 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1194}
1195
4562236b
HW		 1196static uint32_t compute_pstate_blackout_duration(
1197 struct bw_fixed blackout_duration,
1198 const struct core_stream *stream)
1199{
1200 uint32_t total_dest_line_time_ns;
1201 uint32_t pstate_blackout_duration_ns;
1202
1203 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1204
1205 total_dest_line_time_ns = 1000000UL *
1206 stream->public.timing.h_total /
1207 stream->public.timing.pix_clk_khz +
1208 pstate_blackout_duration_ns;
1209
1210 return total_dest_line_time_ns;
1211}
1212
4562236b
HW		 1213void dce110_set_displaymarks(
1214 const struct core_dc *dc,
1215 struct validate_context *context)
1216{
1217 uint8_t i, num_pipes;
1218 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1219
1220 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1221 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1222 uint32_t total_dest_line_time_ns;
1223
1224 if (pipe_ctx->stream == NULL)
1225 continue;
1226
1227 total_dest_line_time_ns = compute_pstate_blackout_duration(
1228 dc->bw_vbios.blackout_duration, pipe_ctx->stream);
1229 pipe_ctx->mi->funcs->mem_input_program_display_marks(
1230 pipe_ctx->mi,
1231 context->bw_results.nbp_state_change_wm_ns[num_pipes],
1232 context->bw_results.stutter_exit_wm_ns[num_pipes],
1233 context->bw_results.urgent_wm_ns[num_pipes],
1234 total_dest_line_time_ns);
1235 if (i == underlay_idx) {
1236 num_pipes++;
1237 pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks(
1238 pipe_ctx->mi,
1239 context->bw_results.nbp_state_change_wm_ns[num_pipes],
1240 context->bw_results.stutter_exit_wm_ns[num_pipes],
1241 context->bw_results.urgent_wm_ns[num_pipes],
1242 total_dest_line_time_ns);
1243 }
1244 num_pipes++;
1245 }
1246}
1247
1248static void set_safe_displaymarks(struct resource_context *res_ctx)
1249{
1250 int i;
1251 int underlay_idx = res_ctx->pool->underlay_pipe_index;
1252 struct bw_watermarks max_marks = {
1253 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1254 struct bw_watermarks nbp_marks = {
1255 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1256
1257 for (i = 0; i < MAX_PIPES; i++) {
1258 if (res_ctx->pipe_ctx[i].stream == NULL)
1259 continue;
1260
1261 res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks(
1262 res_ctx->pipe_ctx[i].mi,
1263 nbp_marks,
1264 max_marks,
1265 max_marks,
1266 MAX_WATERMARK);
1267 if (i == underlay_idx)
1268 res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks(
1269 res_ctx->pipe_ctx[i].mi,
1270 nbp_marks,
1271 max_marks,
1272 max_marks,
1273 MAX_WATERMARK);
1274 }
1275}
1276
1277static void switch_dp_clock_sources(
1278 const struct core_dc *dc,
1279 struct resource_context *res_ctx)
1280{
1281 uint8_t i;
1282 for (i = 0; i < MAX_PIPES; i++) {
1283 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1284
1285 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1286 continue;
1287
1288 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1289 struct clock_source *clk_src =
1290 resource_find_used_clk_src_for_sharing(
1291 res_ctx, pipe_ctx);
1292
1293 if (clk_src &&
1294 clk_src != pipe_ctx->clock_source) {
1295 resource_unreference_clock_source(
8c737fcc 1296 res_ctx, &pipe_ctx->clock_source);
4562236b
HW		 1297 pipe_ctx->clock_source = clk_src;
1298 resource_reference_clock_source(res_ctx, clk_src);
1299
1300 dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
1301 }
1302 }
1303 }
1304}
1305
1306/*******************************************************************************
1307 * Public functions
1308 ******************************************************************************/
1309
1310static void reset_single_pipe_hw_ctx(
1311 const struct core_dc *dc,
1312 struct pipe_ctx *pipe_ctx,
1313 struct validate_context *context)
1314{
1315 core_link_disable_stream(pipe_ctx);
4b5e7d62
HW		 1316 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
1317 if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) {
4562236b
HW		 1318 dm_error("DC: failed to blank crtc!\n");
1319 BREAK_TO_DEBUGGER();
1320 }
1321 pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
1322 pipe_ctx->mi->funcs->free_mem_input(
ab2541b6 1323 pipe_ctx->mi, context->stream_count);
4562236b 1324 resource_unreference_clock_source(
8c737fcc 1325 &context->res_ctx, &pipe_ctx->clock_source);
4562236b
HW		 1326
1327 dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx);
1328
1329 pipe_ctx->stream = NULL;
1330}
1331
1332static void set_drr(struct pipe_ctx **pipe_ctx,
1333 int num_pipes, int vmin, int vmax)
1334{
1335 int i = 0;
1336 struct drr_params params = {0};
1337
1338 params.vertical_total_max = vmax;
1339 params.vertical_total_min = vmin;
1340
1341 /* TODO: If multiple pipes are to be supported, you need
1342 * some GSL stuff
1343 */
1344
1345 for (i = 0; i < num_pipes; i++) {
1346 pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
1347 }
1348}
1349
1350static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1351 int num_pipes, int value)
1352{
1353 unsigned int i;
1354
1355 for (i = 0; i < num_pipes; i++)
1356 pipe_ctx[i]->tg->funcs->
1357 set_static_screen_control(pipe_ctx[i]->tg, value);
1358}
1359
1360/* unit: in_khz before mode set, get pixel clock from context. ASIC register
1361 * may not be programmed yet.
1362 * TODO: after mode set, pre_mode_set = false,
1363 * may read PLL register to get pixel clock
1364 */
1365static uint32_t get_max_pixel_clock_for_all_paths(
1366 struct core_dc *dc,
1367 struct validate_context *context,
1368 bool pre_mode_set)
1369{
1370 uint32_t max_pix_clk = 0;
1371 int i;
1372
1373 if (!pre_mode_set) {
1374 /* TODO: read ASIC register to get pixel clock */
1375 ASSERT(0);
1376 }
1377
1378 for (i = 0; i < MAX_PIPES; i++) {
1379 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1380
1381 if (pipe_ctx->stream == NULL)
1382 continue;
1383
1384 /* do not check under lay */
1385 if (pipe_ctx->top_pipe)
1386 continue;
1387
1388 if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk)
1389 max_pix_clk =
1390 pipe_ctx->pix_clk_params.requested_pix_clk;
1391 }
1392
1393 if (max_pix_clk == 0)
1394 ASSERT(0);
1395
1396 return max_pix_clk;
1397}
1398
2c8ad2d5 1399/* Find clock state based on clock requested. if clock value is 0, simply
4562236b 1400 * set clock state as requested without finding clock state by clock value
2c8ad2d5
AD		 1401 *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock.
1402 *
1403 * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value
1404 * etc support for dcn1.0
4562236b
HW		 1405 */
1406static void apply_min_clocks(
1407 struct core_dc *dc,
1408 struct validate_context *context,
e9c58bb4 1409 enum dm_pp_clocks_state *clocks_state,
4562236b
HW		 1410 bool pre_mode_set)
1411{
1412 struct state_dependent_clocks req_clocks = {0};
1413 struct pipe_ctx *pipe_ctx;
1414 int i;
1415
1416 for (i = 0; i < MAX_PIPES; i++) {
1417 pipe_ctx = &context->res_ctx.pipe_ctx[i];
1418 if (pipe_ctx->dis_clk != NULL)
1419 break;
1420 }
1421
1422 if (!pre_mode_set) {
1423 /* set clock_state without verification */
5d6d185f
DL		 1424 if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
1425 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
1426 pipe_ctx->dis_clk, *clocks_state);
4562236b 1427 return;
5d6d185f 1428 }
4562236b
HW		 1429
1430 /* TODOFPGA */
2c8ad2d5
AD		 1431#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
1432 /* TODO: This is incorrect. Figure out how to fix. */
1433 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1434 pipe_ctx->dis_clk,
1435 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1436 pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz,
1437 pre_mode_set,
1438 false);
1439
1440 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1441 pipe_ctx->dis_clk,
1442 DM_PP_CLOCK_TYPE_PIXELCLK,
1443 pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1444 pre_mode_set,
1445 false);
1446
1447 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1448 pipe_ctx->dis_clk,
1449 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1450 pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1451 pre_mode_set,
1452 false);
1453 return;
1454#endif
4562236b
HW		 1455 }
1456
1457 /* get the required state based on state dependent clocks:
1458 * display clock and pixel clock
1459 */
a99240d5 1460 req_clocks.display_clk_khz = context->dispclk_khz;
4562236b
HW		 1461
1462 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1463 dc, context, true);
1464
5d6d185f
DL		 1465 if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) {
1466 *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state(
1467 pipe_ctx->dis_clk, &req_clocks);
1468 pipe_ctx->dis_clk->funcs->set_min_clocks_state(
4562236b
HW		 1469 pipe_ctx->dis_clk, *clocks_state);
1470 } else {
2c8ad2d5
AD		 1471#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
1472 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1473 pipe_ctx->dis_clk,
1474 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1475 req_clocks.display_clk_khz,
1476 pre_mode_set,
1477 false);
1478
1479 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1480 pipe_ctx->dis_clk,
1481 DM_PP_CLOCK_TYPE_PIXELCLK,
1482 req_clocks.pixel_clk_khz,
1483 pre_mode_set,
1484 false);
1485
1486 pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
1487 pipe_ctx->dis_clk,
1488 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1489 req_clocks.pixel_clk_khz,
1490 pre_mode_set,
1491 false);
1492#endif
4562236b
HW		 1493 }
1494}
1495
1496static enum dc_status apply_ctx_to_hw_fpga(
1497 struct core_dc *dc,
1498 struct validate_context *context)
1499{
1500 enum dc_status status = DC_ERROR_UNEXPECTED;
1501 int i;
1502
1503 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1504 struct pipe_ctx *pipe_ctx_old =
1505 &dc->current_context->res_ctx.pipe_ctx[i];
1506 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1507
1508 if (pipe_ctx->stream == NULL)
1509 continue;
1510
1511 if (pipe_ctx->stream == pipe_ctx_old->stream)
1512 continue;
1513
1514 status = apply_single_controller_ctx_to_hw(
1515 pipe_ctx,
1516 context,
1517 dc);
1518
1519 if (status != DC_OK)
1520 return status;
1521 }
1522
1523 return DC_OK;
1524}
1525
1526static void reset_hw_ctx_wrap(
1527 struct core_dc *dc,
1528 struct validate_context *context)
1529{
1530 int i;
1531
1532 /* Reset old context */
1533 /* look up the targets that have been removed since last commit */
1534 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1535 struct pipe_ctx *pipe_ctx_old =
1536 &dc->current_context->res_ctx.pipe_ctx[i];
1537 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1538
1539 /* Note: We need to disable output if clock sources change,
1540 * since bios does optimization and doesn't apply if changing
1541 * PHY when not already disabled.
1542 */
1543
1544 /* Skip underlay pipe since it will be handled in commit surface*/
1545 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1546 continue;
1547
1548 if (!pipe_ctx->stream ||
1549 pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1550 reset_single_pipe_hw_ctx(
1551 dc, pipe_ctx_old, dc->current_context);
1552 }
1553}
1554
cf437593 1555
4562236b
HW		 1556enum dc_status dce110_apply_ctx_to_hw(
1557 struct core_dc *dc,
1558 struct validate_context *context)
1559{
1560 struct dc_bios *dcb = dc->ctx->dc_bios;
1561 enum dc_status status;
1562 int i;
e9c58bb4 1563 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
4562236b
HW		 1564
1565 /* Reset old context */
1566 /* look up the targets that have been removed since last commit */
1567 dc->hwss.reset_hw_ctx_wrap(dc, context);
1568
1569 /* Skip applying if no targets */
ab2541b6 1570 if (context->stream_count <= 0)
4562236b
HW		 1571 return DC_OK;
1572
1573 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1574 apply_ctx_to_hw_fpga(dc, context);
1575 return DC_OK;
1576 }
1577
1578 /* Apply new context */
1579 dcb->funcs->set_scratch_critical_state(dcb, true);
1580
1581 /* below is for real asic only */
1582 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1583 struct pipe_ctx *pipe_ctx_old =
1584 &dc->current_context->res_ctx.pipe_ctx[i];
1585 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1586
1587 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1588 continue;
1589
1590 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1591 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1592 dce_crtc_switch_to_clk_src(dc->hwseq,
1593 pipe_ctx->clock_source, i);
1594 continue;
1595 }
1596
1597 dc->hwss.enable_display_power_gating(
1598 dc, i, dc->ctx->dc_bios,
1599 PIPE_GATING_CONTROL_DISABLE);
1600 }
1601
1602 set_safe_displaymarks(&context->res_ctx);
1603 /*TODO: when pplib works*/
1604 apply_min_clocks(dc, context, &clocks_state, true);
1605
a99240d5
DL		 1606 if (context->dispclk_khz
1607 > dc->current_context->dispclk_khz)
1a687574
DL		 1608 context->res_ctx.pool->display_clock->funcs->set_clock(
1609 context->res_ctx.pool->display_clock,
a99240d5 1610 context->dispclk_khz * 115 / 100);
4562236b 1611
ab8812a3
HW		 1612 /* program audio wall clock. use HDMI as clock source if HDMI
1613 * audio active. Otherwise, use DP as clock source
1614 * first, loop to find any HDMI audio, if not, loop find DP audio
1615 */
1616 /* Setup audio rate clock source */
1617 /* Issue:
1618 * Audio lag happened on DP monitor when unplug a HDMI monitor
1619 *
1620 * Cause:
1621 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1622 * is set to either dto0 or dto1, audio should work fine.
1623 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1624 * set to dto0 will cause audio lag.
1625 *
1626 * Solution:
1627 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1628 * find first available pipe with audio, setup audio wall DTO per topology
1629 * instead of per pipe.
1630 */
1631 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1632 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1633
1634 if (pipe_ctx->stream == NULL)
1635 continue;
1636
1637 if (pipe_ctx->top_pipe)
1638 continue;
1639
1640 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1641 continue;
1642
1643 if (pipe_ctx->audio != NULL) {
1644 struct audio_output audio_output;
1645
1646 build_audio_output(pipe_ctx, &audio_output);
1647
1648 pipe_ctx->audio->funcs->wall_dto_setup(
1649 pipe_ctx->audio,
1650 pipe_ctx->stream->signal,
1651 &audio_output.crtc_info,
1652 &audio_output.pll_info);
1653 break;
1654 }
1655 }
1656
1657 /* no HDMI audio is found, try DP audio */
1658 if (i == context->res_ctx.pool->pipe_count) {
1659 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1660 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1661
1662 if (pipe_ctx->stream == NULL)
1663 continue;
1664
1665 if (pipe_ctx->top_pipe)
1666 continue;
1667
1668 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1669 continue;
1670
1671 if (pipe_ctx->audio != NULL) {
1672 struct audio_output audio_output;
1673
1674 build_audio_output(pipe_ctx, &audio_output);
1675
1676 pipe_ctx->audio->funcs->wall_dto_setup(
1677 pipe_ctx->audio,
1678 pipe_ctx->stream->signal,
1679 &audio_output.crtc_info,
1680 &audio_output.pll_info);
1681 break;
1682 }
1683 }
1684 }
1685
4562236b
HW		 1686 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
1687 struct pipe_ctx *pipe_ctx_old =
1688 &dc->current_context->res_ctx.pipe_ctx[i];
1689 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1690
1691 if (pipe_ctx->stream == NULL)
1692 continue;
1693
1694 if (pipe_ctx->stream == pipe_ctx_old->stream)
1695 continue;
1696
1697 if (pipe_ctx->top_pipe)
1698 continue;
1699
1700 if (context->res_ctx.pipe_ctx[i].audio != NULL) {
ab8812a3 1701
4562236b 1702 struct audio_output audio_output;
4562236b
HW		 1703
1704 build_audio_output(pipe_ctx, &audio_output);
1705
1706 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1707 pipe_ctx->stream_enc->funcs->dp_audio_setup(
1708 pipe_ctx->stream_enc,
1709 pipe_ctx->audio->inst,
1710 &pipe_ctx->stream->public.audio_info);
1711 else
1712 pipe_ctx->stream_enc->funcs->hdmi_audio_setup(
1713 pipe_ctx->stream_enc,
1714 pipe_ctx->audio->inst,
1715 &pipe_ctx->stream->public.audio_info,
1716 &audio_output.crtc_info);
1717
1718 pipe_ctx->audio->funcs->az_configure(
1719 pipe_ctx->audio,
1720 pipe_ctx->stream->signal,
1721 &audio_output.crtc_info,
1722 &pipe_ctx->stream->public.audio_info);
4562236b
HW		 1723 }
1724
1725 status = apply_single_controller_ctx_to_hw(
1726 pipe_ctx,
1727 context,
1728 dc);
1729
1730 if (DC_OK != status)
1731 return status;
1732 }
1733
cf437593 1734 dc->hwss.set_bandwidth(dc, context, true);
4562236b
HW		 1735
1736 /* to save power */
1737 apply_min_clocks(dc, context, &clocks_state, false);
1738
1739 dcb->funcs->set_scratch_critical_state(dcb, false);
1740
1741 switch_dp_clock_sources(dc, &context->res_ctx);
1742
cf437593 1743
4562236b
HW		 1744 return DC_OK;
1745}
1746
1747/*******************************************************************************
1748 * Front End programming
1749 ******************************************************************************/
1750static void set_default_colors(struct pipe_ctx *pipe_ctx)
1751{
1752 struct default_adjustment default_adjust = { 0 };
1753
1754 default_adjust.force_hw_default = false;
1755 if (pipe_ctx->surface == NULL)
1756 default_adjust.in_color_space = COLOR_SPACE_SRGB;
1757 else
1758 default_adjust.in_color_space =
1759 pipe_ctx->surface->public.color_space;
1760 if (pipe_ctx->stream == NULL)
1761 default_adjust.out_color_space = COLOR_SPACE_SRGB;
1762 else
1763 default_adjust.out_color_space =
1764 pipe_ctx->stream->public.output_color_space;
1765 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
1766 default_adjust.surface_pixel_format = pipe_ctx->scl_data.format;
1767
1768 /* display color depth */
1769 default_adjust.color_depth =
1770 pipe_ctx->stream->public.timing.display_color_depth;
1771
1772 /* Lb color depth */
1773 default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth;
1774
1775 pipe_ctx->opp->funcs->opp_set_csc_default(
1776 pipe_ctx->opp, &default_adjust);
1777}
1778
b06b7680
LE		 1779
1780/*******************************************************************************
1781 * In order to turn on/off specific surface we will program
1782 * Blender + CRTC
1783 *
1784 * In case that we have two surfaces and they have a different visibility
1785 * we can't turn off the CRTC since it will turn off the entire display
1786 *
1787 * |----------------------------------------------- |
1788 * |bottom pipe|curr pipe | | |
1789 * |Surface |Surface | Blender | CRCT |
1790 * |visibility |visibility | Configuration| |
1791 * |------------------------------------------------|
1792 * | off | off | CURRENT_PIPE | blank |
1793 * | off | on | CURRENT_PIPE | unblank |
1794 * | on | off | OTHER_PIPE | unblank |
1795 * | on | on | BLENDING | unblank |
1796 * -------------------------------------------------|
1797 *
1798 ******************************************************************************/
1799static void program_surface_visibility(const struct core_dc *dc,
4562236b
HW		 1800 struct pipe_ctx *pipe_ctx)
1801{
1802 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
b06b7680 1803 bool blank_target = false;
4562236b
HW		 1804
1805 if (pipe_ctx->bottom_pipe) {
b06b7680
LE		 1806
1807 /* For now we are supporting only two pipes */
1808 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
1809
4562236b
HW		 1810 if (pipe_ctx->bottom_pipe->surface->public.visible) {
1811 if (pipe_ctx->surface->public.visible)
1812 blender_mode = BLND_MODE_BLENDING;
1813 else
1814 blender_mode = BLND_MODE_OTHER_PIPE;
b06b7680
LE		 1815
1816 } else if (!pipe_ctx->surface->public.visible)
1817 blank_target = true;
1818
1819 } else if (!pipe_ctx->surface->public.visible)
1820 blank_target = true;
1821
4562236b 1822 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
b06b7680
LE		 1823 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target);
1824
4562236b
HW		 1825}
1826
1827/**
1828 * TODO REMOVE, USE UPDATE INSTEAD
1829 */
1830static void set_plane_config(
1831 const struct core_dc *dc,
1832 struct pipe_ctx *pipe_ctx,
1833 struct resource_context *res_ctx)
1834{
1835 struct mem_input *mi = pipe_ctx->mi;
1836 struct core_surface *surface = pipe_ctx->surface;
1837 struct xfm_grph_csc_adjustment adjust;
1838 struct out_csc_color_matrix tbl_entry;
1839 unsigned int i;
1840
1841 memset(&adjust, 0, sizeof(adjust));
1842 memset(&tbl_entry, 0, sizeof(tbl_entry));
1843 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1844
1845 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
1846
1847 set_default_colors(pipe_ctx);
1848 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
1849 == true) {
1850 tbl_entry.color_space =
1851 pipe_ctx->stream->public.output_color_space;
1852
1853 for (i = 0; i < 12; i++)
1854 tbl_entry.regval[i] =
1855 pipe_ctx->stream->public.csc_color_matrix.matrix[i];
1856
1857 pipe_ctx->opp->funcs->opp_set_csc_adjustment
1858 (pipe_ctx->opp, &tbl_entry);
1859 }
1860
1861 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
1862 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1863 adjust.temperature_matrix[0] =
1864 pipe_ctx->stream->
1865 public.gamut_remap_matrix.matrix[0];
1866 adjust.temperature_matrix[1] =
1867 pipe_ctx->stream->
1868 public.gamut_remap_matrix.matrix[1];
1869 adjust.temperature_matrix[2] =
1870 pipe_ctx->stream->
1871 public.gamut_remap_matrix.matrix[2];
1872 adjust.temperature_matrix[3] =
1873 pipe_ctx->stream->
1874 public.gamut_remap_matrix.matrix[4];
1875 adjust.temperature_matrix[4] =
1876 pipe_ctx->stream->
1877 public.gamut_remap_matrix.matrix[5];
1878 adjust.temperature_matrix[5] =
1879 pipe_ctx->stream->
1880 public.gamut_remap_matrix.matrix[6];
1881 adjust.temperature_matrix[6] =
1882 pipe_ctx->stream->
1883 public.gamut_remap_matrix.matrix[8];
1884 adjust.temperature_matrix[7] =
1885 pipe_ctx->stream->
1886 public.gamut_remap_matrix.matrix[9];
1887 adjust.temperature_matrix[8] =
1888 pipe_ctx->stream->
1889 public.gamut_remap_matrix.matrix[10];
1890 }
1891
1892 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
1893
1894 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1895 program_scaler(dc, pipe_ctx);
1896
b06b7680 1897 program_surface_visibility(dc, pipe_ctx);
4562236b
HW		 1898
1899 mi->funcs->mem_input_program_surface_config(
1900 mi,
1901 surface->public.format,
1902 &surface->public.tiling_info,
1903 &surface->public.plane_size,
1904 surface->public.rotation,
1905 NULL,
624d7c47
YS		 1906 false,
1907 pipe_ctx->surface->public.visible);
4562236b
HW		 1908
1909 if (dc->public.config.gpu_vm_support)
1910 mi->funcs->mem_input_program_pte_vm(
1911 pipe_ctx->mi,
1912 surface->public.format,
1913 &surface->public.tiling_info,
1914 surface->public.rotation);
1915}
1916
1917static void update_plane_addr(const struct core_dc *dc,
1918 struct pipe_ctx *pipe_ctx)
1919{
1920 struct core_surface *surface = pipe_ctx->surface;
1921
1922 if (surface == NULL)
1923 return;
1924
1925 pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
1926 pipe_ctx->mi,
1927 &surface->public.address,
1928 surface->public.flip_immediate);
1929
1930 surface->status.requested_address = surface->public.address;
4562236b
HW		 1931}
1932
1933void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
1934{
1935 struct core_surface *surface = pipe_ctx->surface;
1936
1937 if (surface == NULL)
1938 return;
1939
1940 surface->status.is_flip_pending =
1941 pipe_ctx->mi->funcs->mem_input_is_flip_pending(
1942 pipe_ctx->mi);
1943
1944 if (surface->status.is_flip_pending && !surface->public.visible)
1945 pipe_ctx->mi->current_address = pipe_ctx->mi->request_address;
1946
1947 surface->status.current_address = pipe_ctx->mi->current_address;
1948}
1949
1950void dce110_power_down(struct core_dc *dc)
1951{
1952 power_down_all_hw_blocks(dc);
1953 disable_vga_and_power_gate_all_controllers(dc);
1954}
1955
1956static bool wait_for_reset_trigger_to_occur(
1957 struct dc_context *dc_ctx,
1958 struct timing_generator *tg)
1959{
1960 bool rc = false;
1961
1962 /* To avoid endless loop we wait at most
1963 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1964 const uint32_t frames_to_wait_on_triggered_reset = 10;
1965 uint32_t i;
1966
1967 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1968
1969 if (!tg->funcs->is_counter_moving(tg)) {
1970 DC_ERROR("TG counter is not moving!\n");
1971 break;
1972 }
1973
1974 if (tg->funcs->did_triggered_reset_occur(tg)) {
1975 rc = true;
1976 /* usually occurs at i=1 */
1977 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1978 i);
1979 break;
1980 }
1981
1982 /* Wait for one frame. */
1983 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1984 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1985 }
1986
1987 if (false == rc)
1988 DC_ERROR("GSL: Timeout on reset trigger!\n");
1989
1990 return rc;
1991}
1992
1993/* Enable timing synchronization for a group of Timing Generators. */
1994static void dce110_enable_timing_synchronization(
1995 struct core_dc *dc,
1996 int group_index,
1997 int group_size,
1998 struct pipe_ctx *grouped_pipes[])
1999{
2000 struct dc_context *dc_ctx = dc->ctx;
2001 struct dcp_gsl_params gsl_params = { 0 };
2002 int i;
2003
2004 DC_SYNC_INFO("GSL: Setting-up...\n");
2005
2006 /* Designate a single TG in the group as a master.
2007 * Since HW doesn't care which one, we always assign
2008 * the 1st one in the group. */
2009 gsl_params.gsl_group = 0;
2010 gsl_params.gsl_master = grouped_pipes[0]->tg->inst;
2011
2012 for (i = 0; i < group_size; i++)
2013 grouped_pipes[i]->tg->funcs->setup_global_swap_lock(
2014 grouped_pipes[i]->tg, &gsl_params);
2015
2016 /* Reset slave controllers on master VSync */
2017 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2018
2019 for (i = 1 /* skip the master */; i < group_size; i++)
2020 grouped_pipes[i]->tg->funcs->enable_reset_trigger(
2021 grouped_pipes[i]->tg, gsl_params.gsl_group);
2022
2023
2024
2025 for (i = 1 /* skip the master */; i < group_size; i++) {
2026 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2027 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg);
2028 /* Regardless of success of the wait above, remove the reset or
2029 * the driver will start timing out on Display requests. */
2030 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2031 grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg);
2032 }
2033
2034
2035 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2036 * is that the sync'ed displays will not drift out of sync over time*/
2037 DC_SYNC_INFO("GSL: Restoring register states.\n");
2038 for (i = 0; i < group_size; i++)
2039 grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg);
2040
2041 DC_SYNC_INFO("GSL: Set-up complete.\n");
2042}
2043
2044static void init_hw(struct core_dc *dc)
2045{
2046 int i;
2047 struct dc_bios *bp;
2048 struct transform *xfm;
5e7773a2 2049 struct abm *abm;
4562236b
HW		 2050
2051 bp = dc->ctx->dc_bios;
2052 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2053 xfm = dc->res_pool->transforms[i];
2054 xfm->funcs->transform_reset(xfm);
2055
2056 dc->hwss.enable_display_power_gating(
2057 dc, i, bp,
2058 PIPE_GATING_CONTROL_INIT);
2059 dc->hwss.enable_display_power_gating(
2060 dc, i, bp,
2061 PIPE_GATING_CONTROL_DISABLE);
2062 dc->hwss.enable_display_pipe_clock_gating(
2063 dc->ctx,
2064 true);
2065 }
2066
e166ad43 2067 dce_clock_gating_power_up(dc->hwseq, false);
4562236b
HW		 2068 /***************************************/
2069
2070 for (i = 0; i < dc->link_count; i++) {
2071 /****************************************/
2072 /* Power up AND update implementation according to the
2073 * required signal (which may be different from the
2074 * default signal on connector). */
2075 struct core_link *link = dc->links[i];
2076 link->link_enc->funcs->hw_init(link->link_enc);
2077 }
2078
2079 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2080 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2081
2082 tg->funcs->disable_vga(tg);
2083
2084 /* Blank controller using driver code instead of
2085 * command table. */
2086 tg->funcs->set_blank(tg, true);
4b5e7d62 2087 hwss_wait_for_blank_complete(tg);
4562236b
HW		 2088 }
2089
2090 for (i = 0; i < dc->res_pool->audio_count; i++) {
2091 struct audio *audio = dc->res_pool->audios[i];
2092 audio->funcs->hw_init(audio);
2093 }
5e7773a2
AK		 2094
2095 abm = dc->res_pool->abm;
6728b30c
AK		 2096 if (abm != NULL) {
2097 abm->funcs->init_backlight(abm);
5e7773a2 2098 abm->funcs->abm_init(abm);
6728b30c 2099 }
4562236b
HW		 2100}
2101
4562236b
HW		 2102static void dce110_power_on_pipe_if_needed(
2103 struct core_dc *dc,
2104 struct pipe_ctx *pipe_ctx,
2105 struct validate_context *context)
2106{
2107 struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2108 struct dc_bios *dcb = dc->ctx->dc_bios;
2109 struct tg_color black_color = {0};
2110
2111 if (!old_pipe_ctx->stream && pipe_ctx->stream) {
2112 dc->hwss.enable_display_power_gating(
2113 dc,
2114 pipe_ctx->pipe_idx,
2115 dcb, PIPE_GATING_CONTROL_DISABLE);
2116
2117 /*
2118 * This is for powering on underlay, so crtc does not
2119 * need to be enabled
2120 */
2121
2122 pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg,
2123 &pipe_ctx->stream->public.timing,
2124 false);
2125
2126 pipe_ctx->tg->funcs->enable_advanced_request(
2127 pipe_ctx->tg,
2128 true,
2129 &pipe_ctx->stream->public.timing);
2130
2131 pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi,
2132 pipe_ctx->stream->public.timing.h_total,
2133 pipe_ctx->stream->public.timing.v_total,
2134 pipe_ctx->stream->public.timing.pix_clk_khz,
ab2541b6 2135 context->stream_count);
4562236b
HW		 2136
2137 /* TODO unhardcode*/
2138 color_space_to_black_color(dc,
2139 COLOR_SPACE_YCBCR601, &black_color);
2140 pipe_ctx->tg->funcs->set_blank_color(
2141 pipe_ctx->tg,
2142 &black_color);
2143 }
2144}
2145
cf437593
DL		 2146static void fill_display_configs(
2147 const struct validate_context *context,
2148 struct dm_pp_display_configuration *pp_display_cfg)
2149{
2150 int j;
2151 int num_cfgs = 0;
2152
2153 for (j = 0; j < context->stream_count; j++) {
2154 int k;
2155
2156 const struct core_stream *stream = context->streams[j];
2157 struct dm_pp_single_disp_config *cfg =
2158 &pp_display_cfg->disp_configs[num_cfgs];
2159 const struct pipe_ctx *pipe_ctx = NULL;
2160
2161 for (k = 0; k < MAX_PIPES; k++)
2162 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2163 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2164 break;
2165 }
2166
2167 ASSERT(pipe_ctx != NULL);
2168
2169 num_cfgs++;
2170 cfg->signal = pipe_ctx->stream->signal;
2171 cfg->pipe_idx = pipe_ctx->pipe_idx;
2172 cfg->src_height = stream->public.src.height;
2173 cfg->src_width = stream->public.src.width;
2174 cfg->ddi_channel_mapping =
2175 stream->sink->link->ddi_channel_mapping.raw;
2176 cfg->transmitter =
2177 stream->sink->link->link_enc->transmitter;
2178 cfg->link_settings.lane_count =
2179 stream->sink->link->public.cur_link_settings.lane_count;
2180 cfg->link_settings.link_rate =
2181 stream->sink->link->public.cur_link_settings.link_rate;
2182 cfg->link_settings.link_spread =
2183 stream->sink->link->public.cur_link_settings.link_spread;
2184 cfg->sym_clock = stream->phy_pix_clk;
2185 /* Round v_refresh*/
2186 cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
2187 cfg->v_refresh /= stream->public.timing.h_total;
2188 cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
2189 / stream->public.timing.v_total;
2190 }
2191
2192 pp_display_cfg->display_count = num_cfgs;
2193}
2194
2195static uint32_t get_min_vblank_time_us(const struct validate_context *context)
4562236b 2196{
cf437593
DL		 2197 uint8_t j;
2198 uint32_t min_vertical_blank_time = -1;
2199
2200 for (j = 0; j < context->stream_count; j++) {
2201 const struct dc_stream *stream = &context->streams[j]->public;
2202 uint32_t vertical_blank_in_pixels = 0;
2203 uint32_t vertical_blank_time = 0;
2204
2205 vertical_blank_in_pixels = stream->timing.h_total *
2206 (stream->timing.v_total
2207 - stream->timing.v_addressable);
2208
2209 vertical_blank_time = vertical_blank_in_pixels
2210 * 1000 / stream->timing.pix_clk_khz;
2211
2212 if (min_vertical_blank_time > vertical_blank_time)
2213 min_vertical_blank_time = vertical_blank_time;
2214 }
2215
2216 return min_vertical_blank_time;
4562236b
HW		 2217}
2218
cf437593
DL		 2219static int determine_sclk_from_bounding_box(
2220 const struct core_dc *dc,
2221 int required_sclk)
4562236b
HW		 2222{
2223 int i;
2224
cf437593
DL		 2225 /*
2226 * Some asics do not give us sclk levels, so we just report the actual
2227 * required sclk
2228 */
2229 if (dc->sclk_lvls.num_levels == 0)
2230 return required_sclk;
4562236b 2231
cf437593
DL		 2232 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2233 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2234 return dc->sclk_lvls.clocks_in_khz[i];
2235 }
2236 /*
2237 * even maximum level could not satisfy requirement, this
2238 * is unexpected at this stage, should have been caught at
2239 * validation time
2240 */
2241 ASSERT(0);
2242 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2243}
2244
2245static void pplib_apply_display_requirements(
2246 struct core_dc *dc,
2247 struct validate_context *context)
2248{
2249 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2250
2251 pp_display_cfg->all_displays_in_sync =
2252 context->bw_results.all_displays_in_sync;
2253 pp_display_cfg->nb_pstate_switch_disable =
2254 context->bw_results.nbp_state_change_enable == false;
2255 pp_display_cfg->cpu_cc6_disable =
2256 context->bw_results.cpuc_state_change_enable == false;
2257 pp_display_cfg->cpu_pstate_disable =
2258 context->bw_results.cpup_state_change_enable == false;
2259 pp_display_cfg->cpu_pstate_separation_time =
2260 context->bw_results.blackout_recovery_time_us;
2261
2262 pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
2263 / MEMORY_TYPE_MULTIPLIER;
2264
2265 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2266 dc,
2267 context->bw_results.required_sclk);
2268
2269 pp_display_cfg->min_engine_clock_deep_sleep_khz
2270 = context->bw_results.required_sclk_deep_sleep;
2271
2272 pp_display_cfg->avail_mclk_switch_time_us =
2273 get_min_vblank_time_us(context);
2274 /* TODO: dce11.2*/
2275 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
4562236b 2276
cf437593
DL		 2277 pp_display_cfg->disp_clk_khz = context->dispclk_khz;
2278
2279 fill_display_configs(context, pp_display_cfg);
2280
2281 /* TODO: is this still applicable?*/
2282 if (pp_display_cfg->display_count == 1) {
2283 const struct dc_crtc_timing *timing =
2284 &context->streams[0]->public.timing;
2285
2286 pp_display_cfg->crtc_index =
2287 pp_display_cfg->disp_configs[0].pipe_idx;
2288 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2289 / timing->pix_clk_khz;
2290 }
2291
2292 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2293 struct dm_pp_display_configuration)) != 0)
2294 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2295
2296 dc->prev_display_config = *pp_display_cfg;
2297}
2298
2299static void dce110_set_bandwidth(
2300 struct core_dc *dc,
2301 struct validate_context *context,
2302 bool decrease_allowed)
2303{
2304 dc->hwss.set_displaymarks(dc, context);
2305
2306 if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
2307 context->res_ctx.pool->display_clock->funcs->set_clock(
2308 context->res_ctx.pool->display_clock,
2309 context->dispclk_khz * 115 / 100);
2310 dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
2311 dc->current_context->dispclk_khz = context->dispclk_khz;
4562236b
HW		 2312 }
2313
cf437593 2314 pplib_apply_display_requirements(dc, context);
4562236b
HW		 2315}
2316
2317static void dce110_program_front_end_for_pipe(
2318 struct core_dc *dc, struct pipe_ctx *pipe_ctx)
2319{
2320 struct mem_input *mi = pipe_ctx->mi;
2321 struct pipe_ctx *old_pipe = NULL;
2322 struct core_surface *surface = pipe_ctx->surface;
2323 struct xfm_grph_csc_adjustment adjust;
2324 struct out_csc_color_matrix tbl_entry;
2325 unsigned int i;
2326
2327 memset(&tbl_entry, 0, sizeof(tbl_entry));
2328
2329 if (dc->current_context)
2330 old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2331
2332 memset(&adjust, 0, sizeof(adjust));
2333 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2334
2335 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2336
2337 set_default_colors(pipe_ctx);
2338 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
2339 == true) {
2340 tbl_entry.color_space =
2341 pipe_ctx->stream->public.output_color_space;
2342
2343 for (i = 0; i < 12; i++)
2344 tbl_entry.regval[i] =
2345 pipe_ctx->stream->public.csc_color_matrix.matrix[i];
2346
2347 pipe_ctx->opp->funcs->opp_set_csc_adjustment
2348 (pipe_ctx->opp, &tbl_entry);
2349 }
2350
2351 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
2352 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2353 adjust.temperature_matrix[0] =
2354 pipe_ctx->stream->
2355 public.gamut_remap_matrix.matrix[0];
2356 adjust.temperature_matrix[1] =
2357 pipe_ctx->stream->
2358 public.gamut_remap_matrix.matrix[1];
2359 adjust.temperature_matrix[2] =
2360 pipe_ctx->stream->
2361 public.gamut_remap_matrix.matrix[2];
2362 adjust.temperature_matrix[3] =
2363 pipe_ctx->stream->
2364 public.gamut_remap_matrix.matrix[4];
2365 adjust.temperature_matrix[4] =
2366 pipe_ctx->stream->
2367 public.gamut_remap_matrix.matrix[5];
2368 adjust.temperature_matrix[5] =
2369 pipe_ctx->stream->
2370 public.gamut_remap_matrix.matrix[6];
2371 adjust.temperature_matrix[6] =
2372 pipe_ctx->stream->
2373 public.gamut_remap_matrix.matrix[8];
2374 adjust.temperature_matrix[7] =
2375 pipe_ctx->stream->
2376 public.gamut_remap_matrix.matrix[9];
2377 adjust.temperature_matrix[8] =
2378 pipe_ctx->stream->
2379 public.gamut_remap_matrix.matrix[10];
2380 }
2381
2382 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
2383
2384 pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2385 if (old_pipe && memcmp(&old_pipe->scl_data,
2386 &pipe_ctx->scl_data,
2387 sizeof(struct scaler_data)) != 0)
2388 program_scaler(dc, pipe_ctx);
2389
2390 mi->funcs->mem_input_program_surface_config(
2391 mi,
2392 surface->public.format,
2393 &surface->public.tiling_info,
2394 &surface->public.plane_size,
2395 surface->public.rotation,
624d7c47 2396 NULL,
4562236b 2397 false,
624d7c47 2398 pipe_ctx->surface->public.visible);
4562236b
HW		 2399
2400 if (dc->public.config.gpu_vm_support)
2401 mi->funcs->mem_input_program_pte_vm(
2402 pipe_ctx->mi,
2403 surface->public.format,
2404 &surface->public.tiling_info,
2405 surface->public.rotation);
2406
2407 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2408 "Pipe:%d 0x%x: addr hi:0x%x, "
2409 "addr low:0x%x, "
2410 "src: %d, %d, %d,"
2411 " %d; dst: %d, %d, %d, %d;"
2412 "clip: %d, %d, %d, %d\n",
2413 pipe_ctx->pipe_idx,
2414 pipe_ctx->surface,
2415 pipe_ctx->surface->public.address.grph.addr.high_part,
2416 pipe_ctx->surface->public.address.grph.addr.low_part,
2417 pipe_ctx->surface->public.src_rect.x,
2418 pipe_ctx->surface->public.src_rect.y,
2419 pipe_ctx->surface->public.src_rect.width,
2420 pipe_ctx->surface->public.src_rect.height,
2421 pipe_ctx->surface->public.dst_rect.x,
2422 pipe_ctx->surface->public.dst_rect.y,
2423 pipe_ctx->surface->public.dst_rect.width,
2424 pipe_ctx->surface->public.dst_rect.height,
2425 pipe_ctx->surface->public.clip_rect.x,
2426 pipe_ctx->surface->public.clip_rect.y,
2427 pipe_ctx->surface->public.clip_rect.width,
2428 pipe_ctx->surface->public.clip_rect.height);
2429
2430 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2431 "Pipe %d: width, height, x, y\n"
2432 "viewport:%d, %d, %d, %d\n"
2433 "recout: %d, %d, %d, %d\n",
2434 pipe_ctx->pipe_idx,
2435 pipe_ctx->scl_data.viewport.width,
2436 pipe_ctx->scl_data.viewport.height,
2437 pipe_ctx->scl_data.viewport.x,
2438 pipe_ctx->scl_data.viewport.y,
2439 pipe_ctx->scl_data.recout.width,
2440 pipe_ctx->scl_data.recout.height,
2441 pipe_ctx->scl_data.recout.x,
2442 pipe_ctx->scl_data.recout.y);
2443}
2444
4562236b
HW		 2445static void dce110_apply_ctx_for_surface(
2446 struct core_dc *dc,
2447 struct core_surface *surface,
2448 struct validate_context *context)
2449{
2450 int i;
2451
2452 /* TODO remove when removing the surface reset workaroud*/
2453 if (!surface)
2454 return;
2455
2456 for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
2457 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2458
2459 if (pipe_ctx->surface != surface)
2460 continue;
2461
2462 dce110_program_front_end_for_pipe(dc, pipe_ctx);
b06b7680 2463 program_surface_visibility(dc, pipe_ctx);
4562236b
HW		 2464
2465 }
4562236b
HW		 2466}
2467
2468static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
2469{
2470 int i;
2471
2472 for (i = 0; i < dc->res_pool->pipe_count; i++)
2473 if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe)
2474 break;
2475
2476 if (i == dc->res_pool->pipe_count)
2477 return;
2478
2479 dc->hwss.enable_display_power_gating(
2480 dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2481 if (pipe->xfm)
2482 pipe->xfm->funcs->transform_reset(pipe->xfm);
2483 memset(&pipe->scl_data, 0, sizeof(struct scaler_data));
2484}
2485
2486static const struct hw_sequencer_funcs dce110_funcs = {
2487 .init_hw = init_hw,
2488 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
cf437593 2489 .prepare_pipe_for_context = dce110_power_on_pipe_if_needed,
4562236b
HW		 2490 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2491 .set_plane_config = set_plane_config,
2492 .update_plane_addr = update_plane_addr,
2493 .update_pending_status = dce110_update_pending_status,
d7194cf6 2494 .set_input_transfer_func = dce110_set_input_transfer_func,
90e508ba 2495 .set_output_transfer_func = dce110_set_output_transfer_func,
4562236b
HW		 2496 .power_down = dce110_power_down,
2497 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2498 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2499 .update_info_frame = dce110_update_info_frame,
2500 .enable_stream = dce110_enable_stream,
2501 .disable_stream = dce110_disable_stream,
2502 .unblank_stream = dce110_unblank_stream,
2503 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2504 .enable_display_power_gating = dce110_enable_display_power_gating,
2505 .power_down_front_end = dce110_power_down_fe,
2506 .pipe_control_lock = dce_pipe_control_lock,
4562236b 2507 .set_displaymarks = dce110_set_displaymarks,
4562236b
HW		 2508 .set_bandwidth = dce110_set_bandwidth,
2509 .set_drr = set_drr,
2510 .set_static_screen_control = set_static_screen_control,
2511 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
4b5e7d62 2512 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
4562236b
HW		 2513};
2514
2515bool dce110_hw_sequencer_construct(struct core_dc *dc)
2516{
2517 dc->hwss = dce110_funcs;
2518
2519 return true;
2520}
2521
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