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4562236b HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "dm_services.h" | |
27 | ||
28 | #include "link_encoder.h" | |
29 | #include "stream_encoder.h" | |
30 | ||
31 | #include "resource.h" | |
32 | #include "dce110/dce110_resource.h" | |
33 | ||
34 | #include "include/irq_service_interface.h" | |
35 | #include "dce/dce_audio.h" | |
36 | #include "dce110/dce110_timing_generator.h" | |
37 | #include "irq/dce110/irq_service_dce110.h" | |
38 | #include "dce110/dce110_timing_generator_v.h" | |
39 | #include "dce/dce_link_encoder.h" | |
40 | #include "dce/dce_stream_encoder.h" | |
c3489214 | 41 | #include "dce/dce_mem_input.h" |
4562236b | 42 | #include "dce110/dce110_mem_input_v.h" |
e6303950 | 43 | #include "dce/dce_ipp.h" |
4562236b HW |
44 | #include "dce/dce_transform.h" |
45 | #include "dce110/dce110_transform_v.h" | |
ab3ee7a5 | 46 | #include "dce/dce_opp.h" |
4562236b | 47 | #include "dce110/dce110_opp_v.h" |
9a70eba7 | 48 | #include "dce/dce_clocks.h" |
4562236b HW |
49 | #include "dce/dce_clock_source.h" |
50 | #include "dce/dce_hwseq.h" | |
51 | #include "dce110/dce110_hw_sequencer.h" | |
5e7773a2 AK |
52 | #include "dce/dce_abm.h" |
53 | #include "dce/dce_dmcu.h" | |
4562236b | 54 | |
1663ae1c BL |
55 | #ifdef ENABLE_FBC |
56 | #include "dce110/dce110_compressor.h" | |
57 | #endif | |
58 | ||
4562236b HW |
59 | #include "reg_helper.h" |
60 | ||
61 | #include "dce/dce_11_0_d.h" | |
62 | #include "dce/dce_11_0_sh_mask.h" | |
63 | ||
64 | #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT | |
65 | #include "gmc/gmc_8_2_d.h" | |
66 | #include "gmc/gmc_8_2_sh_mask.h" | |
67 | #endif | |
68 | ||
69 | #ifndef mmDP_DPHY_INTERNAL_CTRL | |
70 | #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 | |
71 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 | |
72 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 | |
73 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 | |
74 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 | |
75 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 | |
76 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 | |
77 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 | |
78 | #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 | |
79 | #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 | |
80 | #endif | |
81 | ||
82 | #ifndef mmBIOS_SCRATCH_2 | |
83 | #define mmBIOS_SCRATCH_2 0x05CB | |
84 | #define mmBIOS_SCRATCH_6 0x05CF | |
85 | #endif | |
86 | ||
87 | #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL | |
88 | #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC | |
89 | #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC | |
90 | #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC | |
91 | #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC | |
92 | #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC | |
93 | #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC | |
94 | #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC | |
95 | #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC | |
96 | #endif | |
97 | ||
98 | #ifndef mmDP_DPHY_FAST_TRAINING | |
99 | #define mmDP_DPHY_FAST_TRAINING 0x4ABC | |
100 | #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC | |
101 | #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC | |
102 | #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC | |
103 | #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC | |
104 | #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC | |
105 | #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC | |
106 | #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC | |
107 | #endif | |
108 | ||
109 | #ifndef DPHY_RX_FAST_TRAINING_CAPABLE | |
110 | #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 | |
111 | #endif | |
112 | ||
113 | static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { | |
114 | { | |
115 | .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), | |
116 | .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), | |
117 | }, | |
118 | { | |
119 | .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), | |
120 | .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), | |
121 | }, | |
122 | { | |
123 | .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), | |
124 | .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), | |
125 | }, | |
126 | { | |
127 | .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), | |
128 | .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), | |
129 | }, | |
130 | { | |
131 | .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), | |
132 | .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), | |
133 | }, | |
134 | { | |
135 | .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), | |
136 | .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), | |
137 | } | |
138 | }; | |
139 | ||
4562236b HW |
140 | /* set register offset */ |
141 | #define SR(reg_name)\ | |
142 | .reg_name = mm ## reg_name | |
143 | ||
144 | /* set register offset with instance */ | |
145 | #define SRI(reg_name, block, id)\ | |
146 | .reg_name = mm ## block ## id ## _ ## reg_name | |
147 | ||
9a70eba7 DL |
148 | static const struct dce_disp_clk_registers disp_clk_regs = { |
149 | CLK_COMMON_REG_LIST_DCE_BASE() | |
150 | }; | |
151 | ||
152 | static const struct dce_disp_clk_shift disp_clk_shift = { | |
153 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) | |
154 | }; | |
155 | ||
156 | static const struct dce_disp_clk_mask disp_clk_mask = { | |
157 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) | |
158 | }; | |
4562236b | 159 | |
5e7773a2 AK |
160 | static const struct dce_dmcu_registers dmcu_regs = { |
161 | DMCU_DCE110_COMMON_REG_LIST() | |
162 | }; | |
163 | ||
164 | static const struct dce_dmcu_shift dmcu_shift = { | |
165 | DMCU_MASK_SH_LIST_DCE110(__SHIFT) | |
166 | }; | |
167 | ||
168 | static const struct dce_dmcu_mask dmcu_mask = { | |
169 | DMCU_MASK_SH_LIST_DCE110(_MASK) | |
170 | }; | |
171 | ||
172 | static const struct dce_abm_registers abm_regs = { | |
173 | ABM_DCE110_COMMON_REG_LIST() | |
174 | }; | |
175 | ||
176 | static const struct dce_abm_shift abm_shift = { | |
177 | ABM_MASK_SH_LIST_DCE110(__SHIFT) | |
178 | }; | |
179 | ||
180 | static const struct dce_abm_mask abm_mask = { | |
181 | ABM_MASK_SH_LIST_DCE110(_MASK) | |
182 | }; | |
183 | ||
e6303950 DL |
184 | #define ipp_regs(id)\ |
185 | [id] = {\ | |
186 | IPP_DCE110_REG_LIST_DCE_BASE(id)\ | |
187 | } | |
188 | ||
189 | static const struct dce_ipp_registers ipp_regs[] = { | |
190 | ipp_regs(0), | |
191 | ipp_regs(1), | |
192 | ipp_regs(2) | |
193 | }; | |
194 | ||
195 | static const struct dce_ipp_shift ipp_shift = { | |
196 | IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) | |
197 | }; | |
198 | ||
199 | static const struct dce_ipp_mask ipp_mask = { | |
200 | IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) | |
201 | }; | |
202 | ||
4562236b HW |
203 | #define transform_regs(id)\ |
204 | [id] = {\ | |
205 | XFM_COMMON_REG_LIST_DCE110(id)\ | |
206 | } | |
207 | ||
208 | static const struct dce_transform_registers xfm_regs[] = { | |
209 | transform_regs(0), | |
210 | transform_regs(1), | |
211 | transform_regs(2) | |
212 | }; | |
213 | ||
214 | static const struct dce_transform_shift xfm_shift = { | |
215 | XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) | |
216 | }; | |
217 | ||
218 | static const struct dce_transform_mask xfm_mask = { | |
219 | XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) | |
220 | }; | |
221 | ||
222 | #define aux_regs(id)\ | |
223 | [id] = {\ | |
224 | AUX_REG_LIST(id)\ | |
225 | } | |
226 | ||
227 | static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { | |
228 | aux_regs(0), | |
229 | aux_regs(1), | |
230 | aux_regs(2), | |
231 | aux_regs(3), | |
232 | aux_regs(4), | |
233 | aux_regs(5) | |
234 | }; | |
235 | ||
236 | #define hpd_regs(id)\ | |
237 | [id] = {\ | |
238 | HPD_REG_LIST(id)\ | |
239 | } | |
240 | ||
241 | static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
242 | hpd_regs(0), | |
243 | hpd_regs(1), | |
244 | hpd_regs(2), | |
245 | hpd_regs(3), | |
246 | hpd_regs(4), | |
247 | hpd_regs(5) | |
248 | }; | |
249 | ||
250 | ||
251 | #define link_regs(id)\ | |
252 | [id] = {\ | |
253 | LE_DCE110_REG_LIST(id)\ | |
254 | } | |
255 | ||
256 | static const struct dce110_link_enc_registers link_enc_regs[] = { | |
257 | link_regs(0), | |
258 | link_regs(1), | |
259 | link_regs(2), | |
260 | link_regs(3), | |
261 | link_regs(4), | |
262 | link_regs(5), | |
263 | link_regs(6), | |
264 | }; | |
265 | ||
266 | #define stream_enc_regs(id)\ | |
267 | [id] = {\ | |
268 | SE_COMMON_REG_LIST(id),\ | |
269 | .TMDS_CNTL = 0,\ | |
270 | } | |
271 | ||
272 | static const struct dce110_stream_enc_registers stream_enc_regs[] = { | |
273 | stream_enc_regs(0), | |
274 | stream_enc_regs(1), | |
275 | stream_enc_regs(2) | |
276 | }; | |
277 | ||
278 | static const struct dce_stream_encoder_shift se_shift = { | |
279 | SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) | |
280 | }; | |
281 | ||
282 | static const struct dce_stream_encoder_mask se_mask = { | |
283 | SE_COMMON_MASK_SH_LIST_DCE110(_MASK) | |
284 | }; | |
285 | ||
ab3ee7a5 ZF |
286 | #define opp_regs(id)\ |
287 | [id] = {\ | |
288 | OPP_DCE_110_REG_LIST(id),\ | |
289 | } | |
290 | ||
291 | static const struct dce_opp_registers opp_regs[] = { | |
292 | opp_regs(0), | |
293 | opp_regs(1), | |
294 | opp_regs(2), | |
295 | opp_regs(3), | |
296 | opp_regs(4), | |
297 | opp_regs(5) | |
298 | }; | |
299 | ||
300 | static const struct dce_opp_shift opp_shift = { | |
301 | OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) | |
302 | }; | |
303 | ||
304 | static const struct dce_opp_mask opp_mask = { | |
305 | OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) | |
306 | }; | |
307 | ||
4562236b HW |
308 | #define audio_regs(id)\ |
309 | [id] = {\ | |
310 | AUD_COMMON_REG_LIST(id)\ | |
311 | } | |
312 | ||
313 | static const struct dce_audio_registers audio_regs[] = { | |
314 | audio_regs(0), | |
315 | audio_regs(1), | |
316 | audio_regs(2), | |
317 | audio_regs(3), | |
318 | audio_regs(4), | |
319 | audio_regs(5), | |
320 | audio_regs(6), | |
321 | }; | |
322 | ||
323 | static const struct dce_audio_shift audio_shift = { | |
324 | AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
325 | }; | |
326 | ||
327 | static const struct dce_aduio_mask audio_mask = { | |
328 | AUD_COMMON_MASK_SH_LIST(_MASK) | |
329 | }; | |
330 | ||
331 | /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ | |
ab3ee7a5 | 332 | |
4562236b HW |
333 | |
334 | #define clk_src_regs(id)\ | |
335 | [id] = {\ | |
336 | CS_COMMON_REG_LIST_DCE_100_110(id),\ | |
337 | } | |
338 | ||
339 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
340 | clk_src_regs(0), | |
341 | clk_src_regs(1), | |
342 | clk_src_regs(2) | |
343 | }; | |
344 | ||
345 | static const struct dce110_clk_src_shift cs_shift = { | |
346 | CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) | |
347 | }; | |
348 | ||
349 | static const struct dce110_clk_src_mask cs_mask = { | |
350 | CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) | |
351 | }; | |
352 | ||
353 | static const struct bios_registers bios_regs = { | |
354 | .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 | |
355 | }; | |
356 | ||
357 | static const struct resource_caps carrizo_resource_cap = { | |
358 | .num_timing_generator = 3, | |
359 | .num_video_plane = 1, | |
360 | .num_audio = 3, | |
361 | .num_stream_encoder = 3, | |
362 | .num_pll = 2, | |
363 | }; | |
364 | ||
365 | static const struct resource_caps stoney_resource_cap = { | |
366 | .num_timing_generator = 2, | |
367 | .num_video_plane = 1, | |
368 | .num_audio = 3, | |
369 | .num_stream_encoder = 3, | |
370 | .num_pll = 2, | |
371 | }; | |
372 | ||
373 | #define CTX ctx | |
374 | #define REG(reg) mm ## reg | |
375 | ||
376 | #ifndef mmCC_DC_HDMI_STRAPS | |
377 | #define mmCC_DC_HDMI_STRAPS 0x4819 | |
378 | #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 | |
379 | #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 | |
380 | #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 | |
381 | #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 | |
382 | #endif | |
383 | ||
384 | static void read_dce_straps( | |
385 | struct dc_context *ctx, | |
386 | struct resource_straps *straps) | |
387 | { | |
388 | REG_GET_2(CC_DC_HDMI_STRAPS, | |
389 | HDMI_DISABLE, &straps->hdmi_disable, | |
390 | AUDIO_STREAM_NUMBER, &straps->audio_stream_number); | |
391 | ||
392 | REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); | |
393 | } | |
394 | ||
395 | static struct audio *create_audio( | |
396 | struct dc_context *ctx, unsigned int inst) | |
397 | { | |
398 | return dce_audio_create(ctx, inst, | |
399 | &audio_regs[inst], &audio_shift, &audio_mask); | |
400 | } | |
401 | ||
402 | static struct timing_generator *dce110_timing_generator_create( | |
403 | struct dc_context *ctx, | |
404 | uint32_t instance, | |
405 | const struct dce110_timing_generator_offsets *offsets) | |
406 | { | |
407 | struct dce110_timing_generator *tg110 = | |
408 | dm_alloc(sizeof(struct dce110_timing_generator)); | |
409 | ||
410 | if (!tg110) | |
411 | return NULL; | |
412 | ||
413 | if (dce110_timing_generator_construct(tg110, ctx, instance, offsets)) | |
414 | return &tg110->base; | |
415 | ||
416 | BREAK_TO_DEBUGGER(); | |
417 | dm_free(tg110); | |
418 | return NULL; | |
419 | } | |
420 | ||
421 | static struct stream_encoder *dce110_stream_encoder_create( | |
422 | enum engine_id eng_id, | |
423 | struct dc_context *ctx) | |
424 | { | |
425 | struct dce110_stream_encoder *enc110 = | |
426 | dm_alloc(sizeof(struct dce110_stream_encoder)); | |
427 | ||
428 | if (!enc110) | |
429 | return NULL; | |
430 | ||
431 | if (dce110_stream_encoder_construct( | |
432 | enc110, ctx, ctx->dc_bios, eng_id, | |
433 | &stream_enc_regs[eng_id], &se_shift, &se_mask)) | |
434 | return &enc110->base; | |
435 | ||
436 | BREAK_TO_DEBUGGER(); | |
437 | dm_free(enc110); | |
438 | return NULL; | |
439 | } | |
440 | ||
441 | #define SRII(reg_name, block, id)\ | |
442 | .reg_name[id] = mm ## block ## id ## _ ## reg_name | |
443 | ||
444 | static const struct dce_hwseq_registers hwseq_stoney_reg = { | |
445 | HWSEQ_ST_REG_LIST() | |
446 | }; | |
447 | ||
448 | static const struct dce_hwseq_registers hwseq_cz_reg = { | |
449 | HWSEQ_CZ_REG_LIST() | |
450 | }; | |
451 | ||
452 | static const struct dce_hwseq_shift hwseq_shift = { | |
453 | HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), | |
454 | }; | |
455 | ||
456 | static const struct dce_hwseq_mask hwseq_mask = { | |
457 | HWSEQ_DCE11_MASK_SH_LIST(_MASK), | |
458 | }; | |
459 | ||
460 | static struct dce_hwseq *dce110_hwseq_create( | |
461 | struct dc_context *ctx) | |
462 | { | |
463 | struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); | |
464 | ||
465 | if (hws) { | |
466 | hws->ctx = ctx; | |
467 | hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? | |
468 | &hwseq_stoney_reg : &hwseq_cz_reg; | |
469 | hws->shifts = &hwseq_shift; | |
470 | hws->masks = &hwseq_mask; | |
471 | hws->wa.blnd_crtc_trigger = true; | |
472 | } | |
473 | return hws; | |
474 | } | |
475 | ||
476 | static const struct resource_create_funcs res_create_funcs = { | |
477 | .read_dce_straps = read_dce_straps, | |
478 | .create_audio = create_audio, | |
479 | .create_stream_encoder = dce110_stream_encoder_create, | |
480 | .create_hwseq = dce110_hwseq_create, | |
481 | }; | |
482 | ||
483 | #define mi_inst_regs(id) { \ | |
197062bf | 484 | MI_DCE11_REG_LIST(id), \ |
4562236b HW |
485 | .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ |
486 | } | |
487 | static const struct dce_mem_input_registers mi_regs[] = { | |
488 | mi_inst_regs(0), | |
489 | mi_inst_regs(1), | |
490 | mi_inst_regs(2), | |
491 | }; | |
492 | ||
493 | static const struct dce_mem_input_shift mi_shifts = { | |
197062bf | 494 | MI_DCE11_MASK_SH_LIST(__SHIFT), |
4562236b HW |
495 | .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT |
496 | }; | |
497 | ||
498 | static const struct dce_mem_input_mask mi_masks = { | |
197062bf | 499 | MI_DCE11_MASK_SH_LIST(_MASK), |
4562236b HW |
500 | .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK |
501 | }; | |
502 | ||
c3489214 | 503 | |
4562236b HW |
504 | static struct mem_input *dce110_mem_input_create( |
505 | struct dc_context *ctx, | |
c3489214 | 506 | uint32_t inst) |
4562236b | 507 | { |
c3489214 | 508 | struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); |
4562236b | 509 | |
c3489214 DL |
510 | if (!dce_mi) { |
511 | BREAK_TO_DEBUGGER(); | |
4562236b | 512 | return NULL; |
4562236b HW |
513 | } |
514 | ||
c3489214 DL |
515 | dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); |
516 | dce_mi->wa.single_head_rdreq_dmif_limit = 3; | |
517 | return &dce_mi->base; | |
4562236b HW |
518 | } |
519 | ||
520 | static void dce110_transform_destroy(struct transform **xfm) | |
521 | { | |
522 | dm_free(TO_DCE_TRANSFORM(*xfm)); | |
523 | *xfm = NULL; | |
524 | } | |
525 | ||
526 | static struct transform *dce110_transform_create( | |
527 | struct dc_context *ctx, | |
528 | uint32_t inst) | |
529 | { | |
530 | struct dce_transform *transform = | |
531 | dm_alloc(sizeof(struct dce_transform)); | |
532 | ||
533 | if (!transform) | |
534 | return NULL; | |
535 | ||
536 | if (dce_transform_construct(transform, ctx, inst, | |
537 | &xfm_regs[inst], &xfm_shift, &xfm_mask)) | |
538 | return &transform->base; | |
539 | ||
540 | BREAK_TO_DEBUGGER(); | |
541 | dm_free(transform); | |
542 | return NULL; | |
543 | } | |
544 | ||
545 | static struct input_pixel_processor *dce110_ipp_create( | |
e6303950 | 546 | struct dc_context *ctx, uint32_t inst) |
4562236b | 547 | { |
e6303950 | 548 | struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); |
4562236b | 549 | |
e6303950 DL |
550 | if (!ipp) { |
551 | BREAK_TO_DEBUGGER(); | |
4562236b | 552 | return NULL; |
e6303950 | 553 | } |
4562236b | 554 | |
e6303950 DL |
555 | dce_ipp_construct(ipp, ctx, inst, |
556 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
557 | return &ipp->base; | |
4562236b HW |
558 | } |
559 | ||
7fc698a0 TC |
560 | static const struct encoder_feature_support link_enc_feature = { |
561 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
562 | .max_hdmi_pixel_clock = 594000, | |
563 | .flags.bits.IS_HBR2_CAPABLE = true, | |
564 | .flags.bits.IS_TPS3_CAPABLE = true, | |
565 | .flags.bits.IS_YCBCR_CAPABLE = true | |
566 | }; | |
567 | ||
5394eb82 | 568 | static struct link_encoder *dce110_link_encoder_create( |
4562236b HW |
569 | const struct encoder_init_data *enc_init_data) |
570 | { | |
571 | struct dce110_link_encoder *enc110 = | |
572 | dm_alloc(sizeof(struct dce110_link_encoder)); | |
573 | ||
574 | if (!enc110) | |
575 | return NULL; | |
576 | ||
577 | if (dce110_link_encoder_construct( | |
578 | enc110, | |
579 | enc_init_data, | |
7fc698a0 | 580 | &link_enc_feature, |
4562236b HW |
581 | &link_enc_regs[enc_init_data->transmitter], |
582 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
583 | &link_enc_hpd_regs[enc_init_data->hpd_source])) { | |
584 | ||
4562236b HW |
585 | return &enc110->base; |
586 | } | |
587 | ||
588 | BREAK_TO_DEBUGGER(); | |
589 | dm_free(enc110); | |
590 | return NULL; | |
591 | } | |
592 | ||
593 | static struct output_pixel_processor *dce110_opp_create( | |
594 | struct dc_context *ctx, | |
ab3ee7a5 | 595 | uint32_t inst) |
4562236b HW |
596 | { |
597 | struct dce110_opp *opp = | |
598 | dm_alloc(sizeof(struct dce110_opp)); | |
599 | ||
600 | if (!opp) | |
601 | return NULL; | |
602 | ||
603 | if (dce110_opp_construct(opp, | |
ab3ee7a5 | 604 | ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) |
4562236b HW |
605 | return &opp->base; |
606 | ||
607 | BREAK_TO_DEBUGGER(); | |
608 | dm_free(opp); | |
609 | return NULL; | |
610 | } | |
611 | ||
612 | struct clock_source *dce110_clock_source_create( | |
613 | struct dc_context *ctx, | |
614 | struct dc_bios *bios, | |
615 | enum clock_source_id id, | |
616 | const struct dce110_clk_src_regs *regs, | |
617 | bool dp_clk_src) | |
618 | { | |
619 | struct dce110_clk_src *clk_src = | |
620 | dm_alloc(sizeof(struct dce110_clk_src)); | |
621 | ||
622 | if (!clk_src) | |
623 | return NULL; | |
624 | ||
625 | if (dce110_clk_src_construct(clk_src, ctx, bios, id, | |
626 | regs, &cs_shift, &cs_mask)) { | |
627 | clk_src->base.dp_clk_src = dp_clk_src; | |
628 | return &clk_src->base; | |
629 | } | |
630 | ||
631 | BREAK_TO_DEBUGGER(); | |
632 | return NULL; | |
633 | } | |
634 | ||
635 | void dce110_clock_source_destroy(struct clock_source **clk_src) | |
636 | { | |
637 | struct dce110_clk_src *dce110_clk_src; | |
638 | ||
639 | if (!clk_src) | |
640 | return; | |
641 | ||
642 | dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); | |
643 | ||
644 | if (dce110_clk_src->dp_ss_params) | |
645 | dm_free(dce110_clk_src->dp_ss_params); | |
646 | ||
647 | if (dce110_clk_src->hdmi_ss_params) | |
648 | dm_free(dce110_clk_src->hdmi_ss_params); | |
649 | ||
650 | if (dce110_clk_src->dvi_ss_params) | |
651 | dm_free(dce110_clk_src->dvi_ss_params); | |
652 | ||
653 | dm_free(dce110_clk_src); | |
654 | *clk_src = NULL; | |
655 | } | |
656 | ||
657 | static void destruct(struct dce110_resource_pool *pool) | |
658 | { | |
659 | unsigned int i; | |
660 | ||
661 | for (i = 0; i < pool->base.pipe_count; i++) { | |
662 | if (pool->base.opps[i] != NULL) | |
663 | dce110_opp_destroy(&pool->base.opps[i]); | |
664 | ||
665 | if (pool->base.transforms[i] != NULL) | |
666 | dce110_transform_destroy(&pool->base.transforms[i]); | |
667 | ||
668 | if (pool->base.ipps[i] != NULL) | |
e6303950 | 669 | dce_ipp_destroy(&pool->base.ipps[i]); |
4562236b HW |
670 | |
671 | if (pool->base.mis[i] != NULL) { | |
c3489214 | 672 | dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); |
4562236b HW |
673 | pool->base.mis[i] = NULL; |
674 | } | |
675 | ||
676 | if (pool->base.timing_generators[i] != NULL) { | |
677 | dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); | |
678 | pool->base.timing_generators[i] = NULL; | |
679 | } | |
680 | } | |
681 | ||
682 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
683 | if (pool->base.stream_enc[i] != NULL) | |
684 | dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); | |
685 | } | |
686 | ||
687 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
688 | if (pool->base.clock_sources[i] != NULL) { | |
689 | dce110_clock_source_destroy(&pool->base.clock_sources[i]); | |
690 | } | |
691 | } | |
692 | ||
693 | if (pool->base.dp_clock_source != NULL) | |
694 | dce110_clock_source_destroy(&pool->base.dp_clock_source); | |
695 | ||
696 | for (i = 0; i < pool->base.audio_count; i++) { | |
697 | if (pool->base.audios[i] != NULL) { | |
698 | dce_aud_destroy(&pool->base.audios[i]); | |
699 | } | |
700 | } | |
701 | ||
5e7773a2 AK |
702 | if (pool->base.abm != NULL) |
703 | dce_abm_destroy(&pool->base.abm); | |
704 | ||
705 | if (pool->base.dmcu != NULL) | |
706 | dce_dmcu_destroy(&pool->base.dmcu); | |
707 | ||
9a70eba7 DL |
708 | if (pool->base.display_clock != NULL) |
709 | dce_disp_clk_destroy(&pool->base.display_clock); | |
4562236b HW |
710 | |
711 | if (pool->base.irqs != NULL) { | |
712 | dal_irq_service_destroy(&pool->base.irqs); | |
713 | } | |
714 | } | |
715 | ||
716 | ||
717 | static void get_pixel_clock_parameters( | |
718 | const struct pipe_ctx *pipe_ctx, | |
719 | struct pixel_clk_params *pixel_clk_params) | |
720 | { | |
0971c40e | 721 | const struct dc_stream_state *stream = pipe_ctx->stream; |
4562236b HW |
722 | |
723 | /*TODO: is this halved for YCbCr 420? in that case we might want to move | |
724 | * the pixel clock normalization for hdmi up to here instead of doing it | |
725 | * in pll_adjust_pix_clk | |
726 | */ | |
4fa086b9 | 727 | pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; |
4562236b HW |
728 | pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; |
729 | pixel_clk_params->signal_type = pipe_ctx->stream->signal; | |
730 | pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; | |
731 | /* TODO: un-hardcode*/ | |
732 | pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * | |
733 | LINK_RATE_REF_FREQ_IN_KHZ; | |
734 | pixel_clk_params->flags.ENABLE_SS = 0; | |
735 | pixel_clk_params->color_depth = | |
4fa086b9 | 736 | stream->timing.display_color_depth; |
4562236b | 737 | pixel_clk_params->flags.DISPLAY_BLANKED = 1; |
4fa086b9 | 738 | pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == |
4562236b | 739 | PIXEL_ENCODING_YCBCR420); |
4fa086b9 LSL |
740 | pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; |
741 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { | |
181a888f CL |
742 | pixel_clk_params->color_depth = COLOR_DEPTH_888; |
743 | } | |
4fa086b9 | 744 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { |
d5b4f2bc CL |
745 | pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; |
746 | } | |
4562236b HW |
747 | } |
748 | ||
4562236b HW |
749 | enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) |
750 | { | |
10688217 | 751 | get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); |
4562236b HW |
752 | pipe_ctx->clock_source->funcs->get_pix_clk_dividers( |
753 | pipe_ctx->clock_source, | |
10688217 | 754 | &pipe_ctx->stream_res.pix_clk_params, |
4562236b | 755 | &pipe_ctx->pll_settings); |
529cad0f | 756 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, |
4562236b | 757 | &pipe_ctx->stream->bit_depth_params); |
4fa086b9 | 758 | pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; |
4562236b HW |
759 | |
760 | return DC_OK; | |
761 | } | |
762 | ||
763 | static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) | |
764 | { | |
765 | if (pipe_ctx->pipe_idx != underlay_idx) | |
766 | return true; | |
3be5262e | 767 | if (!pipe_ctx->plane_state) |
4562236b | 768 | return false; |
3be5262e | 769 | if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
4562236b HW |
770 | return false; |
771 | return true; | |
772 | } | |
773 | ||
9345d987 | 774 | static enum dc_status build_mapped_resource( |
fb3466a4 | 775 | const struct dc *dc, |
608ac7bb | 776 | struct dc_state *context, |
1dc90497 | 777 | struct dc_stream_state *stream) |
4562236b HW |
778 | { |
779 | enum dc_status status = DC_OK; | |
1dc90497 | 780 | struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); |
4562236b | 781 | |
1dc90497 AG |
782 | if (!pipe_ctx) |
783 | return DC_ERROR_UNEXPECTED; | |
4562236b | 784 | |
1dc90497 AG |
785 | if (!is_surface_pixel_format_supported(pipe_ctx, |
786 | dc->res_pool->underlay_pipe_index)) | |
787 | return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; | |
4562236b | 788 | |
1dc90497 | 789 | status = dce110_resource_build_pipe_hw_param(pipe_ctx); |
4562236b | 790 | |
1dc90497 AG |
791 | if (status != DC_OK) |
792 | return status; | |
4562236b | 793 | |
1dc90497 | 794 | /* TODO: validate audio ASIC caps, encoder */ |
4562236b | 795 | |
1dc90497 | 796 | resource_build_info_frame(pipe_ctx); |
4562236b HW |
797 | |
798 | return DC_OK; | |
799 | } | |
800 | ||
5394eb82 | 801 | static bool dce110_validate_bandwidth( |
fb3466a4 | 802 | struct dc *dc, |
608ac7bb | 803 | struct dc_state *context) |
4562236b | 804 | { |
45209ef7 | 805 | bool result = false; |
4562236b HW |
806 | |
807 | dm_logger_write( | |
808 | dc->ctx->logger, LOG_BANDWIDTH_CALCS, | |
809 | "%s: start", | |
810 | __func__); | |
811 | ||
45209ef7 | 812 | if (bw_calcs( |
4562236b | 813 | dc->ctx, |
77a4ea53 BL |
814 | dc->bw_dceip, |
815 | dc->bw_vbios, | |
4562236b | 816 | context->res_ctx.pipe_ctx, |
a2b8659d | 817 | dc->res_pool->pipe_count, |
9037d802 | 818 | &context->bw.dce)) |
45209ef7 | 819 | result = true; |
4562236b | 820 | |
45209ef7 | 821 | if (!result) |
4562236b HW |
822 | dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, |
823 | "%s: %dx%d@%d Bandwidth validation failed!\n", | |
824 | __func__, | |
4fa086b9 LSL |
825 | context->streams[0]->timing.h_addressable, |
826 | context->streams[0]->timing.v_addressable, | |
827 | context->streams[0]->timing.pix_clk_khz); | |
4562236b | 828 | |
608ac7bb | 829 | if (memcmp(&dc->current_state->bw.dce, |
9037d802 | 830 | &context->bw.dce, sizeof(context->bw.dce))) { |
4562236b HW |
831 | struct log_entry log_entry; |
832 | dm_logger_open( | |
833 | dc->ctx->logger, | |
834 | &log_entry, | |
835 | LOG_BANDWIDTH_CALCS); | |
836 | dm_logger_append(&log_entry, "%s: finish,\n" | |
837 | "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" | |
838 | "stutMark_b: %d stutMark_a: %d\n", | |
839 | __func__, | |
9037d802 DL |
840 | context->bw.dce.nbp_state_change_wm_ns[0].b_mark, |
841 | context->bw.dce.nbp_state_change_wm_ns[0].a_mark, | |
842 | context->bw.dce.urgent_wm_ns[0].b_mark, | |
843 | context->bw.dce.urgent_wm_ns[0].a_mark, | |
844 | context->bw.dce.stutter_exit_wm_ns[0].b_mark, | |
845 | context->bw.dce.stutter_exit_wm_ns[0].a_mark); | |
4562236b HW |
846 | dm_logger_append(&log_entry, |
847 | "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" | |
848 | "stutMark_b: %d stutMark_a: %d\n", | |
9037d802 DL |
849 | context->bw.dce.nbp_state_change_wm_ns[1].b_mark, |
850 | context->bw.dce.nbp_state_change_wm_ns[1].a_mark, | |
851 | context->bw.dce.urgent_wm_ns[1].b_mark, | |
852 | context->bw.dce.urgent_wm_ns[1].a_mark, | |
853 | context->bw.dce.stutter_exit_wm_ns[1].b_mark, | |
854 | context->bw.dce.stutter_exit_wm_ns[1].a_mark); | |
4562236b HW |
855 | dm_logger_append(&log_entry, |
856 | "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" | |
857 | "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", | |
9037d802 DL |
858 | context->bw.dce.nbp_state_change_wm_ns[2].b_mark, |
859 | context->bw.dce.nbp_state_change_wm_ns[2].a_mark, | |
860 | context->bw.dce.urgent_wm_ns[2].b_mark, | |
861 | context->bw.dce.urgent_wm_ns[2].a_mark, | |
862 | context->bw.dce.stutter_exit_wm_ns[2].b_mark, | |
863 | context->bw.dce.stutter_exit_wm_ns[2].a_mark, | |
864 | context->bw.dce.stutter_mode_enable); | |
4562236b HW |
865 | dm_logger_append(&log_entry, |
866 | "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" | |
867 | "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", | |
9037d802 DL |
868 | context->bw.dce.cpuc_state_change_enable, |
869 | context->bw.dce.cpup_state_change_enable, | |
870 | context->bw.dce.nbp_state_change_enable, | |
871 | context->bw.dce.all_displays_in_sync, | |
872 | context->bw.dce.dispclk_khz, | |
873 | context->bw.dce.sclk_khz, | |
874 | context->bw.dce.sclk_deep_sleep_khz, | |
875 | context->bw.dce.yclk_khz, | |
876 | context->bw.dce.blackout_recovery_time_us); | |
4562236b HW |
877 | dm_logger_close(&log_entry); |
878 | } | |
879 | return result; | |
880 | } | |
881 | ||
882 | static bool dce110_validate_surface_sets( | |
608ac7bb | 883 | struct dc_state *context) |
4562236b HW |
884 | { |
885 | int i; | |
886 | ||
19f89e23 AG |
887 | for (i = 0; i < context->stream_count; i++) { |
888 | if (context->stream_status[i].plane_count == 0) | |
4562236b HW |
889 | continue; |
890 | ||
19f89e23 | 891 | if (context->stream_status[i].plane_count > 2) |
4562236b HW |
892 | return false; |
893 | ||
19f89e23 | 894 | if (context->stream_status[i].plane_states[0]->format |
4562236b HW |
895 | >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
896 | return false; | |
897 | ||
19f89e23 AG |
898 | if (context->stream_status[i].plane_count == 2) { |
899 | if (context->stream_status[i].plane_states[1]->format | |
4562236b HW |
900 | < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
901 | return false; | |
19f89e23 AG |
902 | if (context->stream_status[i].plane_states[1]->src_rect.width > 1920 |
903 | || context->stream_status[i].plane_states[1]->src_rect.height > 1080) | |
4562236b HW |
904 | return false; |
905 | ||
19f89e23 | 906 | if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) |
4562236b HW |
907 | return false; |
908 | } | |
909 | } | |
910 | ||
911 | return true; | |
912 | } | |
913 | ||
1dc90497 | 914 | enum dc_status dce110_validate_global( |
fb3466a4 | 915 | struct dc *dc, |
608ac7bb | 916 | struct dc_state *context) |
4562236b | 917 | { |
19f89e23 | 918 | if (!dce110_validate_surface_sets(context)) |
4562236b HW |
919 | return DC_FAIL_SURFACE_VALIDATE; |
920 | ||
1dc90497 | 921 | return DC_OK; |
4562236b HW |
922 | } |
923 | ||
5394eb82 | 924 | static enum dc_status dce110_validate_guaranteed( |
fb3466a4 | 925 | struct dc *dc, |
0971c40e | 926 | struct dc_stream_state *dc_stream, |
608ac7bb | 927 | struct dc_state *context) |
4562236b HW |
928 | { |
929 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
930 | ||
4fa086b9 LSL |
931 | context->streams[0] = dc_stream; |
932 | dc_stream_retain(context->streams[0]); | |
ab2541b6 | 933 | context->stream_count++; |
4562236b | 934 | |
1dc90497 | 935 | result = resource_map_pool_resources(dc, context, dc_stream); |
4562236b HW |
936 | |
937 | if (result == DC_OK) | |
1dc90497 | 938 | result = resource_map_clock_resources(dc, context, dc_stream); |
4562236b HW |
939 | |
940 | if (result == DC_OK) | |
1dc90497 | 941 | result = build_mapped_resource(dc, context, dc_stream); |
4562236b HW |
942 | |
943 | if (result == DC_OK) { | |
ab2541b6 | 944 | validate_guaranteed_copy_streams( |
fb3466a4 | 945 | context, dc->caps.max_streams); |
4562236b HW |
946 | result = resource_build_scaling_params_for_context(dc, context); |
947 | } | |
948 | ||
949 | if (result == DC_OK) | |
45209ef7 DL |
950 | if (!dce110_validate_bandwidth(dc, context)) |
951 | result = DC_FAIL_BANDWIDTH_VALIDATE; | |
4562236b HW |
952 | |
953 | return result; | |
954 | } | |
955 | ||
745cc746 | 956 | static struct pipe_ctx *dce110_acquire_underlay( |
608ac7bb | 957 | struct dc_state *context, |
a2b8659d | 958 | const struct resource_pool *pool, |
0971c40e | 959 | struct dc_stream_state *stream) |
4562236b | 960 | { |
fb3466a4 | 961 | struct dc *dc = stream->ctx->dc; |
745cc746 | 962 | struct resource_context *res_ctx = &context->res_ctx; |
a2b8659d | 963 | unsigned int underlay_idx = pool->underlay_pipe_index; |
4562236b HW |
964 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; |
965 | ||
745cc746 | 966 | if (res_ctx->pipe_ctx[underlay_idx].stream) |
4562236b | 967 | return NULL; |
4562236b | 968 | |
6b670fa9 | 969 | pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; |
86a66c4e HW |
970 | pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; |
971 | /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ | |
972 | pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; | |
a6a6cb34 | 973 | pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; |
4562236b HW |
974 | pipe_ctx->pipe_idx = underlay_idx; |
975 | ||
976 | pipe_ctx->stream = stream; | |
977 | ||
608ac7bb | 978 | if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { |
745cc746 DL |
979 | struct tg_color black_color = {0}; |
980 | struct dc_bios *dcb = dc->ctx->dc_bios; | |
981 | ||
982 | dc->hwss.enable_display_power_gating( | |
983 | dc, | |
984 | pipe_ctx->pipe_idx, | |
985 | dcb, PIPE_GATING_CONTROL_DISABLE); | |
986 | ||
987 | /* | |
988 | * This is for powering on underlay, so crtc does not | |
989 | * need to be enabled | |
990 | */ | |
991 | ||
6b670fa9 | 992 | pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, |
4fa086b9 | 993 | &stream->timing, |
745cc746 DL |
994 | false); |
995 | ||
6b670fa9 HW |
996 | pipe_ctx->stream_res.tg->funcs->enable_advanced_request( |
997 | pipe_ctx->stream_res.tg, | |
745cc746 | 998 | true, |
4fa086b9 | 999 | &stream->timing); |
745cc746 | 1000 | |
86a66c4e | 1001 | pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, |
4fa086b9 LSL |
1002 | stream->timing.h_total, |
1003 | stream->timing.v_total, | |
1004 | stream->timing.pix_clk_khz, | |
745cc746 DL |
1005 | context->stream_count); |
1006 | ||
1007 | color_space_to_black_color(dc, | |
1008 | COLOR_SPACE_YCBCR601, &black_color); | |
6b670fa9 HW |
1009 | pipe_ctx->stream_res.tg->funcs->set_blank_color( |
1010 | pipe_ctx->stream_res.tg, | |
745cc746 DL |
1011 | &black_color); |
1012 | } | |
4562236b | 1013 | |
745cc746 | 1014 | return pipe_ctx; |
4562236b HW |
1015 | } |
1016 | ||
1017 | static void dce110_destroy_resource_pool(struct resource_pool **pool) | |
1018 | { | |
1019 | struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); | |
1020 | ||
1021 | destruct(dce110_pool); | |
1022 | dm_free(dce110_pool); | |
1023 | *pool = NULL; | |
1024 | } | |
1025 | ||
1026 | ||
1027 | static const struct resource_funcs dce110_res_pool_funcs = { | |
1028 | .destroy = dce110_destroy_resource_pool, | |
1029 | .link_enc_create = dce110_link_encoder_create, | |
4562236b HW |
1030 | .validate_guaranteed = dce110_validate_guaranteed, |
1031 | .validate_bandwidth = dce110_validate_bandwidth, | |
745cc746 | 1032 | .acquire_idle_pipe_for_layer = dce110_acquire_underlay, |
1dc90497 | 1033 | .validate_global = dce110_validate_global |
4562236b HW |
1034 | }; |
1035 | ||
cc0cb445 | 1036 | static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) |
4562236b HW |
1037 | { |
1038 | struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); | |
1039 | struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); | |
c3489214 | 1040 | struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); |
4562236b HW |
1041 | struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); |
1042 | ||
cc0cb445 LE |
1043 | if ((dce110_tgv == NULL) || |
1044 | (dce110_xfmv == NULL) || | |
1045 | (dce110_miv == NULL) || | |
1046 | (dce110_oppv == NULL)) | |
1047 | return false; | |
1048 | ||
1049 | if (!dce110_opp_v_construct(dce110_oppv, ctx)) | |
1050 | return false; | |
1051 | ||
4562236b HW |
1052 | dce110_timing_generator_v_construct(dce110_tgv, ctx); |
1053 | dce110_mem_input_v_construct(dce110_miv, ctx); | |
1054 | dce110_transform_v_construct(dce110_xfmv, ctx); | |
1055 | ||
1056 | pool->opps[pool->pipe_count] = &dce110_oppv->base; | |
1057 | pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; | |
1058 | pool->mis[pool->pipe_count] = &dce110_miv->base; | |
1059 | pool->transforms[pool->pipe_count] = &dce110_xfmv->base; | |
1060 | pool->pipe_count++; | |
1061 | ||
1062 | /* update the public caps to indicate an underlay is available */ | |
1063 | ctx->dc->caps.max_slave_planes = 1; | |
1064 | ctx->dc->caps.max_slave_planes = 1; | |
cc0cb445 LE |
1065 | |
1066 | return true; | |
4562236b HW |
1067 | } |
1068 | ||
fb3466a4 | 1069 | static void bw_calcs_data_update_from_pplib(struct dc *dc) |
4562236b HW |
1070 | { |
1071 | struct dm_pp_clock_levels clks = {0}; | |
1072 | ||
1073 | /*do system clock*/ | |
1074 | dm_pp_get_clock_levels_by_type( | |
1075 | dc->ctx, | |
1076 | DM_PP_CLOCK_TYPE_ENGINE_CLK, | |
1077 | &clks); | |
1078 | /* convert all the clock fro kHz to fix point mHz */ | |
77a4ea53 | 1079 | dc->bw_vbios->high_sclk = bw_frc_to_fixed( |
4562236b | 1080 | clks.clocks_in_khz[clks.num_levels-1], 1000); |
77a4ea53 | 1081 | dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( |
4562236b | 1082 | clks.clocks_in_khz[clks.num_levels/8], 1000); |
77a4ea53 | 1083 | dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( |
4562236b | 1084 | clks.clocks_in_khz[clks.num_levels*2/8], 1000); |
77a4ea53 | 1085 | dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( |
4562236b | 1086 | clks.clocks_in_khz[clks.num_levels*3/8], 1000); |
77a4ea53 | 1087 | dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( |
4562236b | 1088 | clks.clocks_in_khz[clks.num_levels*4/8], 1000); |
77a4ea53 | 1089 | dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( |
4562236b | 1090 | clks.clocks_in_khz[clks.num_levels*5/8], 1000); |
77a4ea53 | 1091 | dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( |
4562236b | 1092 | clks.clocks_in_khz[clks.num_levels*6/8], 1000); |
77a4ea53 | 1093 | dc->bw_vbios->low_sclk = bw_frc_to_fixed( |
4562236b HW |
1094 | clks.clocks_in_khz[0], 1000); |
1095 | dc->sclk_lvls = clks; | |
1096 | ||
1097 | /*do display clock*/ | |
1098 | dm_pp_get_clock_levels_by_type( | |
1099 | dc->ctx, | |
1100 | DM_PP_CLOCK_TYPE_DISPLAY_CLK, | |
1101 | &clks); | |
77a4ea53 | 1102 | dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( |
4562236b | 1103 | clks.clocks_in_khz[clks.num_levels-1], 1000); |
77a4ea53 | 1104 | dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( |
4562236b | 1105 | clks.clocks_in_khz[clks.num_levels>>1], 1000); |
77a4ea53 | 1106 | dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( |
4562236b HW |
1107 | clks.clocks_in_khz[0], 1000); |
1108 | ||
1109 | /*do memory clock*/ | |
1110 | dm_pp_get_clock_levels_by_type( | |
1111 | dc->ctx, | |
1112 | DM_PP_CLOCK_TYPE_MEMORY_CLK, | |
1113 | &clks); | |
1114 | ||
77a4ea53 | 1115 | dc->bw_vbios->low_yclk = bw_frc_to_fixed( |
4562236b | 1116 | clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); |
77a4ea53 | 1117 | dc->bw_vbios->mid_yclk = bw_frc_to_fixed( |
4562236b HW |
1118 | clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, |
1119 | 1000); | |
77a4ea53 | 1120 | dc->bw_vbios->high_yclk = bw_frc_to_fixed( |
4562236b HW |
1121 | clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, |
1122 | 1000); | |
1123 | } | |
1124 | ||
4562236b HW |
1125 | const struct resource_caps *dce110_resource_cap( |
1126 | struct hw_asic_id *asic_id) | |
1127 | { | |
1128 | if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) | |
1129 | return &stoney_resource_cap; | |
1130 | else | |
1131 | return &carrizo_resource_cap; | |
1132 | } | |
1133 | ||
1134 | static bool construct( | |
1135 | uint8_t num_virtual_links, | |
fb3466a4 | 1136 | struct dc *dc, |
4562236b HW |
1137 | struct dce110_resource_pool *pool, |
1138 | struct hw_asic_id asic_id) | |
1139 | { | |
1140 | unsigned int i; | |
1141 | struct dc_context *ctx = dc->ctx; | |
1515a47b | 1142 | struct dc_firmware_info info; |
4562236b HW |
1143 | struct dc_bios *bp; |
1144 | struct dm_pp_static_clock_info static_clk_info = {0}; | |
1145 | ||
1146 | ctx->dc_bios->regs = &bios_regs; | |
1147 | ||
1148 | pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); | |
1149 | pool->base.funcs = &dce110_res_pool_funcs; | |
1150 | ||
1151 | /************************************************* | |
1152 | * Resource + asic cap harcoding * | |
1153 | *************************************************/ | |
1154 | ||
1155 | pool->base.pipe_count = pool->base.res_cap->num_timing_generator; | |
1156 | pool->base.underlay_pipe_index = pool->base.pipe_count; | |
1157 | ||
fb3466a4 BL |
1158 | dc->caps.max_downscale_ratio = 150; |
1159 | dc->caps.i2c_speed_in_khz = 100; | |
1160 | dc->caps.max_cursor_size = 128; | |
4562236b HW |
1161 | |
1162 | /************************************************* | |
1163 | * Create resources * | |
1164 | *************************************************/ | |
1165 | ||
1166 | bp = ctx->dc_bios; | |
1167 | ||
1168 | if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && | |
1169 | info.external_clock_source_frequency_for_dp != 0) { | |
1170 | pool->base.dp_clock_source = | |
1171 | dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); | |
1172 | ||
1173 | pool->base.clock_sources[0] = | |
1174 | dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, | |
1175 | &clk_src_regs[0], false); | |
1176 | pool->base.clock_sources[1] = | |
1177 | dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, | |
1178 | &clk_src_regs[1], false); | |
1179 | ||
1180 | pool->base.clk_src_count = 2; | |
1181 | ||
1182 | /* TODO: find out if CZ support 3 PLLs */ | |
1183 | } | |
1184 | ||
1185 | if (pool->base.dp_clock_source == NULL) { | |
1186 | dm_error("DC: failed to create dp clock source!\n"); | |
1187 | BREAK_TO_DEBUGGER(); | |
1188 | goto res_create_fail; | |
1189 | } | |
1190 | ||
1191 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
1192 | if (pool->base.clock_sources[i] == NULL) { | |
1193 | dm_error("DC: failed to create clock sources!\n"); | |
1194 | BREAK_TO_DEBUGGER(); | |
1195 | goto res_create_fail; | |
1196 | } | |
1197 | } | |
1198 | ||
9a70eba7 DL |
1199 | pool->base.display_clock = dce110_disp_clk_create(ctx, |
1200 | &disp_clk_regs, | |
1201 | &disp_clk_shift, | |
1202 | &disp_clk_mask); | |
4562236b HW |
1203 | if (pool->base.display_clock == NULL) { |
1204 | dm_error("DC: failed to create display clock!\n"); | |
1205 | BREAK_TO_DEBUGGER(); | |
1206 | goto res_create_fail; | |
1207 | } | |
1208 | ||
5e7773a2 AK |
1209 | pool->base.dmcu = dce_dmcu_create(ctx, |
1210 | &dmcu_regs, | |
1211 | &dmcu_shift, | |
1212 | &dmcu_mask); | |
1213 | if (pool->base.dmcu == NULL) { | |
1214 | dm_error("DC: failed to create dmcu!\n"); | |
1215 | BREAK_TO_DEBUGGER(); | |
1216 | goto res_create_fail; | |
1217 | } | |
1218 | ||
1219 | pool->base.abm = dce_abm_create(ctx, | |
1220 | &abm_regs, | |
1221 | &abm_shift, | |
1222 | &abm_mask); | |
1223 | if (pool->base.abm == NULL) { | |
1224 | dm_error("DC: failed to create abm!\n"); | |
1225 | BREAK_TO_DEBUGGER(); | |
1226 | goto res_create_fail; | |
1227 | } | |
1228 | ||
4562236b HW |
1229 | /* get static clock information for PPLIB or firmware, save |
1230 | * max_clock_state | |
1231 | */ | |
3bad7c5c DL |
1232 | if (dm_pp_get_static_clocks(ctx, &static_clk_info)) |
1233 | pool->base.display_clock->max_clks_state = | |
e9c58bb4 | 1234 | static_clk_info.max_clocks_state; |
4562236b | 1235 | |
4562236b HW |
1236 | { |
1237 | struct irq_service_init_data init_data; | |
1238 | init_data.ctx = dc->ctx; | |
1239 | pool->base.irqs = dal_irq_service_dce110_create(&init_data); | |
1240 | if (!pool->base.irqs) | |
1241 | goto res_create_fail; | |
1242 | } | |
1243 | ||
1244 | for (i = 0; i < pool->base.pipe_count; i++) { | |
1245 | pool->base.timing_generators[i] = dce110_timing_generator_create( | |
1246 | ctx, i, &dce110_tg_offsets[i]); | |
1247 | if (pool->base.timing_generators[i] == NULL) { | |
1248 | BREAK_TO_DEBUGGER(); | |
1249 | dm_error("DC: failed to create tg!\n"); | |
1250 | goto res_create_fail; | |
1251 | } | |
1252 | ||
c3489214 | 1253 | pool->base.mis[i] = dce110_mem_input_create(ctx, i); |
4562236b HW |
1254 | if (pool->base.mis[i] == NULL) { |
1255 | BREAK_TO_DEBUGGER(); | |
1256 | dm_error( | |
1257 | "DC: failed to create memory input!\n"); | |
1258 | goto res_create_fail; | |
1259 | } | |
1260 | ||
e6303950 | 1261 | pool->base.ipps[i] = dce110_ipp_create(ctx, i); |
4562236b HW |
1262 | if (pool->base.ipps[i] == NULL) { |
1263 | BREAK_TO_DEBUGGER(); | |
1264 | dm_error( | |
1265 | "DC: failed to create input pixel processor!\n"); | |
1266 | goto res_create_fail; | |
1267 | } | |
1268 | ||
1269 | pool->base.transforms[i] = dce110_transform_create(ctx, i); | |
1270 | if (pool->base.transforms[i] == NULL) { | |
1271 | BREAK_TO_DEBUGGER(); | |
1272 | dm_error( | |
1273 | "DC: failed to create transform!\n"); | |
1274 | goto res_create_fail; | |
1275 | } | |
1276 | ||
ab3ee7a5 | 1277 | pool->base.opps[i] = dce110_opp_create(ctx, i); |
4562236b HW |
1278 | if (pool->base.opps[i] == NULL) { |
1279 | BREAK_TO_DEBUGGER(); | |
1280 | dm_error( | |
1281 | "DC: failed to create output pixel processor!\n"); | |
1282 | goto res_create_fail; | |
1283 | } | |
1284 | } | |
1285 | ||
1663ae1c BL |
1286 | #ifdef ENABLE_FBC |
1287 | dc->fbc_compressor = dce110_compressor_create(ctx); | |
1288 | ||
1289 | ||
1290 | ||
1291 | #endif | |
cc0cb445 LE |
1292 | if (!underlay_create(ctx, &pool->base)) |
1293 | goto res_create_fail; | |
4562236b HW |
1294 | |
1295 | if (!resource_construct(num_virtual_links, dc, &pool->base, | |
1296 | &res_create_funcs)) | |
1297 | goto res_create_fail; | |
1298 | ||
1299 | /* Create hardware sequencer */ | |
1300 | if (!dce110_hw_sequencer_construct(dc)) | |
1301 | goto res_create_fail; | |
1302 | ||
fb3466a4 | 1303 | dc->caps.max_planes = pool->base.pipe_count; |
d4e13b0d | 1304 | |
77a4ea53 | 1305 | bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); |
4562236b HW |
1306 | |
1307 | bw_calcs_data_update_from_pplib(dc); | |
1308 | ||
1309 | return true; | |
1310 | ||
1311 | res_create_fail: | |
1312 | destruct(pool); | |
1313 | return false; | |
1314 | } | |
1315 | ||
1316 | struct resource_pool *dce110_create_resource_pool( | |
1317 | uint8_t num_virtual_links, | |
fb3466a4 | 1318 | struct dc *dc, |
4562236b HW |
1319 | struct hw_asic_id asic_id) |
1320 | { | |
1321 | struct dce110_resource_pool *pool = | |
1322 | dm_alloc(sizeof(struct dce110_resource_pool)); | |
1323 | ||
1324 | if (!pool) | |
1325 | return NULL; | |
1326 | ||
1327 | if (construct(num_virtual_links, dc, pool, asic_id)) | |
1328 | return &pool->base; | |
1329 | ||
1330 | BREAK_TO_DEBUGGER(); | |
1331 | return NULL; | |
1332 | } |