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b8fdfcc6 HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc.cls | |
3 | * | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: AMD | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "dm_services.h" | |
28 | ||
29 | ||
30 | #include "stream_encoder.h" | |
31 | #include "resource.h" | |
32 | #include "include/irq_service_interface.h" | |
33 | #include "dce120_resource.h" | |
34 | #include "dce112/dce112_resource.h" | |
35 | ||
36 | #include "dce110/dce110_resource.h" | |
37 | #include "../virtual/virtual_stream_encoder.h" | |
38 | #include "dce120_timing_generator.h" | |
39 | #include "irq/dce120/irq_service_dce120.h" | |
40 | #include "dce/dce_opp.h" | |
41 | #include "dce/dce_clock_source.h" | |
42 | #include "dce/dce_clocks.h" | |
86b6a203 | 43 | #include "dce/dce_ipp.h" |
c3489214 | 44 | #include "dce/dce_mem_input.h" |
b8fdfcc6 HW |
45 | |
46 | #include "dce110/dce110_hw_sequencer.h" | |
47 | #include "dce120/dce120_hw_sequencer.h" | |
48 | #include "dce/dce_transform.h" | |
49 | ||
50 | #include "dce/dce_audio.h" | |
51 | #include "dce/dce_link_encoder.h" | |
52 | #include "dce/dce_stream_encoder.h" | |
53 | #include "dce/dce_hwseq.h" | |
54 | #include "dce/dce_abm.h" | |
55 | #include "dce/dce_dmcu.h" | |
56 | ||
57 | #include "vega10/DC/dce_12_0_offset.h" | |
58 | #include "vega10/DC/dce_12_0_sh_mask.h" | |
59 | #include "vega10/soc15ip.h" | |
60 | #include "vega10/NBIO/nbio_6_1_offset.h" | |
61 | #include "reg_helper.h" | |
62 | ||
63 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL | |
64 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f | |
65 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
66 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f | |
67 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
68 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f | |
69 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
70 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f | |
71 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
72 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f | |
73 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
74 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f | |
75 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
76 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f | |
77 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
78 | #endif | |
79 | ||
80 | enum dce120_clk_src_array_id { | |
81 | DCE120_CLK_SRC_PLL0, | |
82 | DCE120_CLK_SRC_PLL1, | |
83 | DCE120_CLK_SRC_PLL2, | |
84 | DCE120_CLK_SRC_PLL3, | |
85 | DCE120_CLK_SRC_PLL4, | |
86 | DCE120_CLK_SRC_PLL5, | |
87 | ||
88 | DCE120_CLK_SRC_TOTAL | |
89 | }; | |
90 | ||
91 | static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { | |
92 | { | |
93 | .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
94 | }, | |
95 | { | |
96 | .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
97 | }, | |
98 | { | |
99 | .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
100 | }, | |
101 | { | |
102 | .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
103 | }, | |
104 | { | |
105 | .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
106 | }, | |
107 | { | |
108 | .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
109 | } | |
110 | }; | |
111 | ||
112 | /* begin ********************* | |
113 | * macros to expend register list macro defined in HW object header file */ | |
114 | ||
115 | #define BASE_INNER(seg) \ | |
116 | DCE_BASE__INST0_SEG ## seg | |
117 | ||
118 | #define NBIO_BASE_INNER(seg) \ | |
119 | NBIF_BASE__INST0_SEG ## seg | |
120 | ||
121 | #define NBIO_BASE(seg) \ | |
122 | NBIO_BASE_INNER(seg) | |
123 | ||
124 | /* compile time expand base address. */ | |
125 | #define BASE(seg) \ | |
126 | BASE_INNER(seg) | |
127 | ||
128 | #define SR(reg_name)\ | |
129 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
130 | mm ## reg_name | |
131 | ||
132 | #define SRI(reg_name, block, id)\ | |
133 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
134 | mm ## block ## id ## _ ## reg_name | |
135 | ||
136 | /* macros to expend register list macro defined in HW object header file | |
137 | * end *********************/ | |
138 | ||
139 | ||
b8fdfcc6 HW |
140 | static const struct dce_dmcu_registers dmcu_regs = { |
141 | DMCU_DCE110_COMMON_REG_LIST() | |
142 | }; | |
143 | ||
144 | static const struct dce_dmcu_shift dmcu_shift = { | |
145 | DMCU_MASK_SH_LIST_DCE110(__SHIFT) | |
146 | }; | |
147 | ||
148 | static const struct dce_dmcu_mask dmcu_mask = { | |
149 | DMCU_MASK_SH_LIST_DCE110(_MASK) | |
150 | }; | |
151 | ||
152 | static const struct dce_abm_registers abm_regs = { | |
153 | ABM_DCE110_COMMON_REG_LIST() | |
154 | }; | |
155 | ||
156 | static const struct dce_abm_shift abm_shift = { | |
157 | ABM_MASK_SH_LIST_DCE110(__SHIFT) | |
158 | }; | |
159 | ||
160 | static const struct dce_abm_mask abm_mask = { | |
161 | ABM_MASK_SH_LIST_DCE110(_MASK) | |
162 | }; | |
163 | ||
86b6a203 DL |
164 | #define ipp_regs(id)\ |
165 | [id] = {\ | |
e6303950 | 166 | IPP_DCE110_REG_LIST_DCE_BASE(id)\ |
86b6a203 DL |
167 | } |
168 | ||
169 | static const struct dce_ipp_registers ipp_regs[] = { | |
170 | ipp_regs(0), | |
171 | ipp_regs(1), | |
172 | ipp_regs(2), | |
173 | ipp_regs(3), | |
174 | ipp_regs(4), | |
175 | ipp_regs(5) | |
176 | }; | |
177 | ||
178 | static const struct dce_ipp_shift ipp_shift = { | |
e6303950 | 179 | IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) |
86b6a203 DL |
180 | }; |
181 | ||
182 | static const struct dce_ipp_mask ipp_mask = { | |
e6303950 | 183 | IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) |
86b6a203 DL |
184 | }; |
185 | ||
b8fdfcc6 HW |
186 | #define transform_regs(id)\ |
187 | [id] = {\ | |
188 | XFM_COMMON_REG_LIST_DCE110(id)\ | |
189 | } | |
190 | ||
191 | static const struct dce_transform_registers xfm_regs[] = { | |
192 | transform_regs(0), | |
193 | transform_regs(1), | |
194 | transform_regs(2), | |
195 | transform_regs(3), | |
196 | transform_regs(4), | |
197 | transform_regs(5) | |
198 | }; | |
199 | ||
200 | static const struct dce_transform_shift xfm_shift = { | |
201 | XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) | |
202 | }; | |
203 | ||
204 | static const struct dce_transform_mask xfm_mask = { | |
205 | XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) | |
206 | }; | |
207 | ||
208 | #define aux_regs(id)\ | |
209 | [id] = {\ | |
210 | AUX_REG_LIST(id)\ | |
211 | } | |
212 | ||
213 | static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { | |
214 | aux_regs(0), | |
215 | aux_regs(1), | |
216 | aux_regs(2), | |
217 | aux_regs(3), | |
218 | aux_regs(4), | |
219 | aux_regs(5) | |
220 | }; | |
221 | ||
222 | #define hpd_regs(id)\ | |
223 | [id] = {\ | |
224 | HPD_REG_LIST(id)\ | |
225 | } | |
226 | ||
227 | static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
228 | hpd_regs(0), | |
229 | hpd_regs(1), | |
230 | hpd_regs(2), | |
231 | hpd_regs(3), | |
232 | hpd_regs(4), | |
233 | hpd_regs(5) | |
234 | }; | |
235 | ||
236 | #define link_regs(id)\ | |
237 | [id] = {\ | |
238 | LE_DCE120_REG_LIST(id), \ | |
239 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | |
240 | } | |
241 | ||
242 | static const struct dce110_link_enc_registers link_enc_regs[] = { | |
243 | link_regs(0), | |
244 | link_regs(1), | |
245 | link_regs(2), | |
246 | link_regs(3), | |
247 | link_regs(4), | |
248 | link_regs(5), | |
249 | link_regs(6), | |
250 | }; | |
251 | ||
252 | ||
253 | #define stream_enc_regs(id)\ | |
254 | [id] = {\ | |
255 | SE_COMMON_REG_LIST(id),\ | |
256 | .TMDS_CNTL = 0,\ | |
257 | } | |
258 | ||
259 | static const struct dce110_stream_enc_registers stream_enc_regs[] = { | |
260 | stream_enc_regs(0), | |
261 | stream_enc_regs(1), | |
262 | stream_enc_regs(2), | |
263 | stream_enc_regs(3), | |
264 | stream_enc_regs(4), | |
265 | stream_enc_regs(5) | |
266 | }; | |
267 | ||
268 | static const struct dce_stream_encoder_shift se_shift = { | |
269 | SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) | |
270 | }; | |
271 | ||
272 | static const struct dce_stream_encoder_mask se_mask = { | |
273 | SE_COMMON_MASK_SH_LIST_DCE120(_MASK) | |
274 | }; | |
275 | ||
276 | #define opp_regs(id)\ | |
277 | [id] = {\ | |
278 | OPP_DCE_120_REG_LIST(id),\ | |
279 | } | |
280 | ||
281 | static const struct dce_opp_registers opp_regs[] = { | |
282 | opp_regs(0), | |
283 | opp_regs(1), | |
284 | opp_regs(2), | |
285 | opp_regs(3), | |
286 | opp_regs(4), | |
287 | opp_regs(5) | |
288 | }; | |
289 | ||
290 | static const struct dce_opp_shift opp_shift = { | |
291 | OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) | |
292 | }; | |
293 | ||
294 | static const struct dce_opp_mask opp_mask = { | |
295 | OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) | |
296 | }; | |
297 | ||
298 | #define audio_regs(id)\ | |
299 | [id] = {\ | |
300 | AUD_COMMON_REG_LIST(id)\ | |
301 | } | |
302 | ||
303 | static struct dce_audio_registers audio_regs[] = { | |
304 | audio_regs(0), | |
305 | audio_regs(1), | |
306 | audio_regs(2), | |
307 | audio_regs(3), | |
308 | audio_regs(4), | |
309 | audio_regs(5) | |
310 | }; | |
311 | ||
312 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ | |
313 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ | |
314 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ | |
315 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) | |
316 | ||
317 | static const struct dce_audio_shift audio_shift = { | |
318 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
319 | }; | |
320 | ||
321 | static const struct dce_aduio_mask audio_mask = { | |
322 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) | |
323 | }; | |
324 | ||
325 | #define clk_src_regs(index, id)\ | |
326 | [index] = {\ | |
327 | CS_COMMON_REG_LIST_DCE_112(id),\ | |
328 | } | |
329 | ||
330 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
331 | clk_src_regs(0, A), | |
332 | clk_src_regs(1, B), | |
333 | clk_src_regs(2, C), | |
334 | clk_src_regs(3, D), | |
335 | clk_src_regs(4, E), | |
336 | clk_src_regs(5, F) | |
337 | }; | |
338 | ||
339 | static const struct dce110_clk_src_shift cs_shift = { | |
340 | CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) | |
341 | }; | |
342 | ||
343 | static const struct dce110_clk_src_mask cs_mask = { | |
344 | CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) | |
345 | }; | |
346 | ||
347 | struct output_pixel_processor *dce120_opp_create( | |
348 | struct dc_context *ctx, | |
349 | uint32_t inst) | |
350 | { | |
351 | struct dce110_opp *opp = | |
352 | dm_alloc(sizeof(struct dce110_opp)); | |
353 | ||
354 | if (!opp) | |
355 | return NULL; | |
356 | ||
357 | if (dce110_opp_construct(opp, | |
358 | ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) | |
359 | return &opp->base; | |
360 | ||
361 | BREAK_TO_DEBUGGER(); | |
362 | dm_free(opp); | |
363 | return NULL; | |
364 | } | |
365 | ||
b8fdfcc6 HW |
366 | static const struct bios_registers bios_regs = { |
367 | .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) | |
368 | }; | |
369 | ||
370 | static const struct resource_caps res_cap = { | |
6a4c32da | 371 | .num_timing_generator = 6, |
b8fdfcc6 HW |
372 | .num_audio = 7, |
373 | .num_stream_encoder = 6, | |
374 | .num_pll = 6, | |
375 | }; | |
376 | ||
377 | static const struct dc_debug debug_defaults = { | |
378 | .disable_clock_gate = true, | |
379 | }; | |
380 | ||
381 | struct clock_source *dce120_clock_source_create( | |
382 | struct dc_context *ctx, | |
383 | struct dc_bios *bios, | |
384 | enum clock_source_id id, | |
385 | const struct dce110_clk_src_regs *regs, | |
386 | bool dp_clk_src) | |
387 | { | |
388 | struct dce110_clk_src *clk_src = | |
76fd8eb8 | 389 | dm_alloc(sizeof(*clk_src)); |
b8fdfcc6 HW |
390 | |
391 | if (!clk_src) | |
392 | return NULL; | |
393 | ||
394 | if (dce110_clk_src_construct(clk_src, ctx, bios, id, | |
76fd8eb8 | 395 | regs, &cs_shift, &cs_mask)) { |
b8fdfcc6 HW |
396 | clk_src->base.dp_clk_src = dp_clk_src; |
397 | return &clk_src->base; | |
398 | } | |
399 | ||
400 | BREAK_TO_DEBUGGER(); | |
401 | return NULL; | |
402 | } | |
403 | ||
404 | void dce120_clock_source_destroy(struct clock_source **clk_src) | |
405 | { | |
406 | dm_free(TO_DCE110_CLK_SRC(*clk_src)); | |
407 | *clk_src = NULL; | |
408 | } | |
409 | ||
410 | ||
411 | bool dce120_hw_sequencer_create(struct core_dc *dc) | |
412 | { | |
413 | /* All registers used by dce11.2 match those in dce11 in offset and | |
414 | * structure | |
415 | */ | |
416 | dce120_hw_sequencer_construct(dc); | |
417 | ||
418 | /*TODO Move to separate file and Override what is needed */ | |
419 | ||
420 | return true; | |
421 | } | |
422 | ||
423 | static struct timing_generator *dce120_timing_generator_create( | |
424 | struct dc_context *ctx, | |
425 | uint32_t instance, | |
426 | const struct dce110_timing_generator_offsets *offsets) | |
427 | { | |
428 | struct dce110_timing_generator *tg110 = | |
429 | dm_alloc(sizeof(struct dce110_timing_generator)); | |
430 | ||
431 | if (!tg110) | |
432 | return NULL; | |
433 | ||
434 | if (dce120_timing_generator_construct(tg110, ctx, instance, offsets)) | |
435 | return &tg110->base; | |
436 | ||
437 | BREAK_TO_DEBUGGER(); | |
438 | dm_free(tg110); | |
439 | return NULL; | |
440 | } | |
441 | ||
b8fdfcc6 HW |
442 | static void dce120_transform_destroy(struct transform **xfm) |
443 | { | |
444 | dm_free(TO_DCE_TRANSFORM(*xfm)); | |
445 | *xfm = NULL; | |
446 | } | |
447 | ||
448 | static void destruct(struct dce110_resource_pool *pool) | |
449 | { | |
450 | unsigned int i; | |
451 | ||
452 | for (i = 0; i < pool->base.pipe_count; i++) { | |
453 | if (pool->base.opps[i] != NULL) | |
454 | dce110_opp_destroy(&pool->base.opps[i]); | |
455 | ||
456 | if (pool->base.transforms[i] != NULL) | |
457 | dce120_transform_destroy(&pool->base.transforms[i]); | |
458 | ||
459 | if (pool->base.ipps[i] != NULL) | |
e6303950 | 460 | dce_ipp_destroy(&pool->base.ipps[i]); |
b8fdfcc6 HW |
461 | |
462 | if (pool->base.mis[i] != NULL) { | |
c3489214 | 463 | dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); |
b8fdfcc6 HW |
464 | pool->base.mis[i] = NULL; |
465 | } | |
466 | ||
467 | if (pool->base.irqs != NULL) { | |
468 | dal_irq_service_destroy(&pool->base.irqs); | |
469 | } | |
470 | ||
471 | if (pool->base.timing_generators[i] != NULL) { | |
472 | dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); | |
473 | pool->base.timing_generators[i] = NULL; | |
474 | } | |
475 | } | |
476 | ||
477 | for (i = 0; i < pool->base.audio_count; i++) { | |
478 | if (pool->base.audios[i]) | |
479 | dce_aud_destroy(&pool->base.audios[i]); | |
480 | } | |
481 | ||
482 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
483 | if (pool->base.stream_enc[i] != NULL) | |
484 | dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); | |
485 | } | |
486 | ||
487 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
488 | if (pool->base.clock_sources[i] != NULL) | |
489 | dce120_clock_source_destroy( | |
490 | &pool->base.clock_sources[i]); | |
491 | } | |
492 | ||
493 | if (pool->base.dp_clock_source != NULL) | |
494 | dce120_clock_source_destroy(&pool->base.dp_clock_source); | |
495 | ||
496 | if (pool->base.abm != NULL) | |
497 | dce_abm_destroy(&pool->base.abm); | |
498 | ||
499 | if (pool->base.dmcu != NULL) | |
500 | dce_dmcu_destroy(&pool->base.dmcu); | |
501 | ||
502 | if (pool->base.display_clock != NULL) | |
503 | dce_disp_clk_destroy(&pool->base.display_clock); | |
504 | } | |
505 | ||
506 | static void read_dce_straps( | |
507 | struct dc_context *ctx, | |
508 | struct resource_straps *straps) | |
509 | { | |
510 | /* TODO: Registers are missing */ | |
511 | /*REG_GET_2(CC_DC_HDMI_STRAPS, | |
512 | HDMI_DISABLE, &straps->hdmi_disable, | |
513 | AUDIO_STREAM_NUMBER, &straps->audio_stream_number); | |
514 | ||
515 | REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/ | |
516 | } | |
517 | ||
518 | static struct audio *create_audio( | |
519 | struct dc_context *ctx, unsigned int inst) | |
520 | { | |
521 | return dce_audio_create(ctx, inst, | |
522 | &audio_regs[inst], &audio_shift, &audio_mask); | |
523 | } | |
524 | ||
525 | static const struct encoder_feature_support link_enc_feature = { | |
526 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
527 | .max_hdmi_pixel_clock = 600000, | |
528 | .ycbcr420_supported = true, | |
529 | .flags.bits.IS_HBR2_CAPABLE = true, | |
530 | .flags.bits.IS_HBR3_CAPABLE = true, | |
531 | .flags.bits.IS_TPS3_CAPABLE = true, | |
532 | .flags.bits.IS_TPS4_CAPABLE = true, | |
533 | .flags.bits.IS_YCBCR_CAPABLE = true | |
534 | }; | |
535 | ||
536 | struct link_encoder *dce120_link_encoder_create( | |
537 | const struct encoder_init_data *enc_init_data) | |
538 | { | |
539 | struct dce110_link_encoder *enc110 = | |
540 | dm_alloc(sizeof(struct dce110_link_encoder)); | |
541 | ||
542 | if (!enc110) | |
543 | return NULL; | |
544 | ||
545 | if (dce110_link_encoder_construct( | |
546 | enc110, | |
547 | enc_init_data, | |
548 | &link_enc_feature, | |
549 | &link_enc_regs[enc_init_data->transmitter], | |
550 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
551 | &link_enc_hpd_regs[enc_init_data->hpd_source])) { | |
552 | ||
553 | return &enc110->base; | |
554 | } | |
555 | ||
556 | BREAK_TO_DEBUGGER(); | |
557 | dm_free(enc110); | |
558 | return NULL; | |
559 | } | |
560 | ||
561 | static struct input_pixel_processor *dce120_ipp_create( | |
86b6a203 | 562 | struct dc_context *ctx, uint32_t inst) |
b8fdfcc6 | 563 | { |
86b6a203 | 564 | struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); |
b8fdfcc6 | 565 | |
86b6a203 DL |
566 | if (!ipp) { |
567 | BREAK_TO_DEBUGGER(); | |
b8fdfcc6 | 568 | return NULL; |
86b6a203 | 569 | } |
b8fdfcc6 | 570 | |
86b6a203 DL |
571 | dce_ipp_construct(ipp, ctx, inst, |
572 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
573 | return &ipp->base; | |
b8fdfcc6 HW |
574 | } |
575 | ||
576 | static struct stream_encoder *dce120_stream_encoder_create( | |
577 | enum engine_id eng_id, | |
578 | struct dc_context *ctx) | |
579 | { | |
580 | struct dce110_stream_encoder *enc110 = | |
581 | dm_alloc(sizeof(struct dce110_stream_encoder)); | |
582 | ||
583 | if (!enc110) | |
584 | return NULL; | |
585 | ||
586 | if (dce110_stream_encoder_construct( | |
587 | enc110, ctx, ctx->dc_bios, eng_id, | |
588 | &stream_enc_regs[eng_id], &se_shift, &se_mask)) | |
589 | return &enc110->base; | |
590 | ||
591 | BREAK_TO_DEBUGGER(); | |
592 | dm_free(enc110); | |
593 | return NULL; | |
594 | } | |
595 | ||
596 | #define SRII(reg_name, block, id)\ | |
597 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
598 | mm ## block ## id ## _ ## reg_name | |
599 | ||
600 | static const struct dce_hwseq_registers hwseq_reg = { | |
08b16886 | 601 | HWSEQ_DCE120_REG_LIST() |
b8fdfcc6 HW |
602 | }; |
603 | ||
604 | static const struct dce_hwseq_shift hwseq_shift = { | |
605 | HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) | |
606 | }; | |
607 | ||
608 | static const struct dce_hwseq_mask hwseq_mask = { | |
609 | HWSEQ_DCE12_MASK_SH_LIST(_MASK) | |
610 | }; | |
611 | ||
612 | static struct dce_hwseq *dce120_hwseq_create( | |
613 | struct dc_context *ctx) | |
614 | { | |
615 | struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); | |
616 | ||
617 | if (hws) { | |
618 | hws->ctx = ctx; | |
619 | hws->regs = &hwseq_reg; | |
620 | hws->shifts = &hwseq_shift; | |
621 | hws->masks = &hwseq_mask; | |
622 | } | |
623 | return hws; | |
624 | } | |
625 | ||
626 | static const struct resource_create_funcs res_create_funcs = { | |
627 | .read_dce_straps = read_dce_straps, | |
628 | .create_audio = create_audio, | |
629 | .create_stream_encoder = dce120_stream_encoder_create, | |
630 | .create_hwseq = dce120_hwseq_create, | |
631 | }; | |
632 | ||
633 | #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } | |
634 | static const struct dce_mem_input_registers mi_regs[] = { | |
635 | mi_inst_regs(0), | |
636 | mi_inst_regs(1), | |
637 | mi_inst_regs(2), | |
638 | mi_inst_regs(3), | |
639 | mi_inst_regs(4), | |
640 | mi_inst_regs(5), | |
641 | }; | |
642 | ||
643 | static const struct dce_mem_input_shift mi_shifts = { | |
644 | MI_DCE12_MASK_SH_LIST(__SHIFT) | |
645 | }; | |
646 | ||
647 | static const struct dce_mem_input_mask mi_masks = { | |
648 | MI_DCE12_MASK_SH_LIST(_MASK) | |
649 | }; | |
650 | ||
651 | static struct mem_input *dce120_mem_input_create( | |
652 | struct dc_context *ctx, | |
c3489214 | 653 | uint32_t inst) |
b8fdfcc6 | 654 | { |
c3489214 | 655 | struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); |
b8fdfcc6 | 656 | |
c3489214 DL |
657 | if (!dce_mi) { |
658 | BREAK_TO_DEBUGGER(); | |
b8fdfcc6 | 659 | return NULL; |
b8fdfcc6 HW |
660 | } |
661 | ||
c3489214 DL |
662 | dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); |
663 | return &dce_mi->base; | |
b8fdfcc6 HW |
664 | } |
665 | ||
666 | static struct transform *dce120_transform_create( | |
667 | struct dc_context *ctx, | |
668 | uint32_t inst) | |
669 | { | |
670 | struct dce_transform *transform = | |
671 | dm_alloc(sizeof(struct dce_transform)); | |
672 | ||
673 | if (!transform) | |
674 | return NULL; | |
675 | ||
676 | if (dce_transform_construct(transform, ctx, inst, | |
677 | &xfm_regs[inst], &xfm_shift, &xfm_mask)) { | |
678 | transform->lb_memory_size = 0x1404; /*5124*/ | |
679 | return &transform->base; | |
680 | } | |
681 | ||
682 | BREAK_TO_DEBUGGER(); | |
683 | dm_free(transform); | |
684 | return NULL; | |
685 | } | |
686 | ||
687 | static void dce120_destroy_resource_pool(struct resource_pool **pool) | |
688 | { | |
689 | struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); | |
690 | ||
691 | destruct(dce110_pool); | |
692 | dm_free(dce110_pool); | |
693 | *pool = NULL; | |
694 | } | |
695 | ||
696 | static const struct resource_funcs dce120_res_pool_funcs = { | |
697 | .destroy = dce120_destroy_resource_pool, | |
698 | .link_enc_create = dce120_link_encoder_create, | |
699 | .validate_with_context = dce112_validate_with_context, | |
700 | .validate_guaranteed = dce112_validate_guaranteed, | |
701 | .validate_bandwidth = dce112_validate_bandwidth | |
702 | }; | |
703 | ||
704 | static void bw_calcs_data_update_from_pplib(struct core_dc *dc) | |
705 | { | |
706 | struct dm_pp_clock_levels_with_latency eng_clks = {0}; | |
707 | struct dm_pp_clock_levels_with_latency mem_clks = {0}; | |
708 | struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; | |
709 | int i; | |
710 | unsigned int clk; | |
711 | unsigned int latency; | |
712 | ||
713 | /*do system clock*/ | |
714 | if (!dm_pp_get_clock_levels_by_type_with_latency( | |
715 | dc->ctx, | |
716 | DM_PP_CLOCK_TYPE_ENGINE_CLK, | |
717 | &eng_clks) || eng_clks.num_levels == 0) { | |
718 | ||
719 | eng_clks.num_levels = 8; | |
720 | clk = 300000; | |
721 | ||
722 | for (i = 0; i < eng_clks.num_levels; i++) { | |
723 | eng_clks.data[i].clocks_in_khz = clk; | |
724 | clk += 100000; | |
725 | } | |
726 | } | |
727 | ||
728 | /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ | |
729 | dc->bw_vbios.high_sclk = bw_frc_to_fixed( | |
730 | eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); | |
731 | dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( | |
732 | eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); | |
733 | dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( | |
734 | eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); | |
735 | dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( | |
736 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); | |
737 | dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( | |
738 | eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); | |
739 | dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( | |
740 | eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); | |
741 | dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( | |
742 | eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); | |
743 | dc->bw_vbios.low_sclk = bw_frc_to_fixed( | |
744 | eng_clks.data[0].clocks_in_khz, 1000); | |
745 | ||
746 | /*do memory clock*/ | |
747 | if (!dm_pp_get_clock_levels_by_type_with_latency( | |
748 | dc->ctx, | |
749 | DM_PP_CLOCK_TYPE_MEMORY_CLK, | |
750 | &mem_clks) || mem_clks.num_levels == 0) { | |
751 | ||
752 | mem_clks.num_levels = 3; | |
753 | clk = 250000; | |
754 | latency = 45; | |
755 | ||
756 | for (i = 0; i < eng_clks.num_levels; i++) { | |
757 | mem_clks.data[i].clocks_in_khz = clk; | |
758 | mem_clks.data[i].latency_in_us = latency; | |
759 | clk += 500000; | |
760 | latency -= 5; | |
761 | } | |
762 | ||
763 | } | |
764 | ||
765 | /* we don't need to call PPLIB for validation clock since they | |
766 | * also give us the highest sclk and highest mclk (UMA clock). | |
767 | * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): | |
768 | * YCLK = UMACLK*m_memoryTypeMultiplier | |
769 | */ | |
770 | dc->bw_vbios.low_yclk = bw_frc_to_fixed( | |
771 | mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); | |
772 | dc->bw_vbios.mid_yclk = bw_frc_to_fixed( | |
773 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, | |
774 | 1000); | |
775 | dc->bw_vbios.high_yclk = bw_frc_to_fixed( | |
776 | mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, | |
777 | 1000); | |
778 | ||
779 | /* Now notify PPLib/SMU about which Watermarks sets they should select | |
780 | * depending on DPM state they are in. And update BW MGR GFX Engine and | |
781 | * Memory clock member variables for Watermarks calculations for each | |
782 | * Watermark Set | |
783 | */ | |
784 | clk_ranges.num_wm_sets = 4; | |
785 | clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; | |
786 | clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = | |
787 | eng_clks.data[0].clocks_in_khz; | |
788 | clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = | |
789 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; | |
790 | clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = | |
791 | mem_clks.data[0].clocks_in_khz; | |
792 | clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = | |
793 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; | |
794 | ||
795 | clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; | |
796 | clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = | |
797 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; | |
798 | /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ | |
799 | clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; | |
800 | clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = | |
801 | mem_clks.data[0].clocks_in_khz; | |
802 | clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = | |
803 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; | |
804 | ||
805 | clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; | |
806 | clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = | |
807 | eng_clks.data[0].clocks_in_khz; | |
808 | clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = | |
809 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; | |
810 | clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = | |
811 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; | |
812 | /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ | |
813 | clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; | |
814 | ||
815 | clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; | |
816 | clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = | |
817 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; | |
818 | /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ | |
819 | clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; | |
820 | clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = | |
821 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; | |
822 | /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ | |
823 | clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; | |
824 | ||
825 | /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ | |
826 | dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); | |
827 | } | |
828 | ||
829 | static bool construct( | |
830 | uint8_t num_virtual_links, | |
831 | struct core_dc *dc, | |
832 | struct dce110_resource_pool *pool) | |
833 | { | |
834 | unsigned int i; | |
835 | struct dc_context *ctx = dc->ctx; | |
8fa9ca2e | 836 | struct irq_service_init_data irq_init_data; |
b8fdfcc6 HW |
837 | |
838 | ctx->dc_bios->regs = &bios_regs; | |
839 | ||
840 | pool->base.res_cap = &res_cap; | |
841 | pool->base.funcs = &dce120_res_pool_funcs; | |
842 | ||
843 | /* TODO: Fill more data from GreenlandAsicCapability.cpp */ | |
6a4c32da | 844 | pool->base.pipe_count = res_cap.num_timing_generator; |
b8fdfcc6 HW |
845 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
846 | ||
847 | dc->public.caps.max_downscale_ratio = 200; | |
848 | dc->public.caps.i2c_speed_in_khz = 100; | |
849 | dc->public.caps.max_cursor_size = 128; | |
850 | dc->public.debug = debug_defaults; | |
851 | ||
852 | /************************************************* | |
853 | * Create resources * | |
854 | *************************************************/ | |
855 | ||
856 | pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = | |
857 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
858 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |
859 | &clk_src_regs[0], false); | |
860 | pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = | |
861 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
862 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |
863 | &clk_src_regs[1], false); | |
864 | pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = | |
865 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
866 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |
867 | &clk_src_regs[2], false); | |
868 | pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = | |
869 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
870 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |
871 | &clk_src_regs[3], false); | |
872 | pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = | |
873 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
874 | CLOCK_SOURCE_COMBO_PHY_PLL4, | |
875 | &clk_src_regs[4], false); | |
876 | pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = | |
877 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
878 | CLOCK_SOURCE_COMBO_PHY_PLL5, | |
879 | &clk_src_regs[5], false); | |
880 | pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; | |
881 | ||
882 | pool->base.dp_clock_source = | |
883 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
884 | CLOCK_SOURCE_ID_DP_DTO, | |
885 | &clk_src_regs[0], true); | |
886 | ||
887 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
888 | if (pool->base.clock_sources[i] == NULL) { | |
889 | dm_error("DC: failed to create clock sources!\n"); | |
890 | BREAK_TO_DEBUGGER(); | |
891 | goto clk_src_create_fail; | |
892 | } | |
893 | } | |
894 | ||
b1a4eb99 | 895 | pool->base.display_clock = dce120_disp_clk_create(ctx); |
b8fdfcc6 HW |
896 | if (pool->base.display_clock == NULL) { |
897 | dm_error("DC: failed to create display clock!\n"); | |
898 | BREAK_TO_DEBUGGER(); | |
899 | goto disp_clk_create_fail; | |
900 | } | |
901 | ||
902 | pool->base.dmcu = dce_dmcu_create(ctx, | |
903 | &dmcu_regs, | |
904 | &dmcu_shift, | |
905 | &dmcu_mask); | |
906 | if (pool->base.dmcu == NULL) { | |
907 | dm_error("DC: failed to create dmcu!\n"); | |
908 | BREAK_TO_DEBUGGER(); | |
909 | goto res_create_fail; | |
910 | } | |
911 | ||
912 | pool->base.abm = dce_abm_create(ctx, | |
913 | &abm_regs, | |
914 | &abm_shift, | |
915 | &abm_mask); | |
916 | if (pool->base.abm == NULL) { | |
917 | dm_error("DC: failed to create abm!\n"); | |
918 | BREAK_TO_DEBUGGER(); | |
919 | goto res_create_fail; | |
920 | } | |
921 | ||
8fa9ca2e AD |
922 | irq_init_data.ctx = dc->ctx; |
923 | pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); | |
924 | if (!pool->base.irqs) | |
925 | goto irqs_create_fail; | |
b8fdfcc6 HW |
926 | |
927 | for (i = 0; i < pool->base.pipe_count; i++) { | |
928 | pool->base.timing_generators[i] = | |
929 | dce120_timing_generator_create( | |
930 | ctx, | |
931 | i, | |
932 | &dce120_tg_offsets[i]); | |
933 | if (pool->base.timing_generators[i] == NULL) { | |
934 | BREAK_TO_DEBUGGER(); | |
935 | dm_error("DC: failed to create tg!\n"); | |
936 | goto controller_create_fail; | |
937 | } | |
938 | ||
c3489214 | 939 | pool->base.mis[i] = dce120_mem_input_create(ctx, i); |
b8fdfcc6 HW |
940 | |
941 | if (pool->base.mis[i] == NULL) { | |
942 | BREAK_TO_DEBUGGER(); | |
943 | dm_error( | |
944 | "DC: failed to create memory input!\n"); | |
945 | goto controller_create_fail; | |
946 | } | |
947 | ||
86b6a203 | 948 | pool->base.ipps[i] = dce120_ipp_create(ctx, i); |
b8fdfcc6 HW |
949 | if (pool->base.ipps[i] == NULL) { |
950 | BREAK_TO_DEBUGGER(); | |
951 | dm_error( | |
952 | "DC: failed to create input pixel processor!\n"); | |
953 | goto controller_create_fail; | |
954 | } | |
955 | ||
956 | pool->base.transforms[i] = dce120_transform_create(ctx, i); | |
957 | if (pool->base.transforms[i] == NULL) { | |
958 | BREAK_TO_DEBUGGER(); | |
959 | dm_error( | |
960 | "DC: failed to create transform!\n"); | |
961 | goto res_create_fail; | |
962 | } | |
963 | ||
964 | pool->base.opps[i] = dce120_opp_create( | |
965 | ctx, | |
966 | i); | |
967 | if (pool->base.opps[i] == NULL) { | |
968 | BREAK_TO_DEBUGGER(); | |
969 | dm_error( | |
970 | "DC: failed to create output pixel processor!\n"); | |
971 | } | |
972 | } | |
973 | ||
974 | if (!resource_construct(num_virtual_links, dc, &pool->base, | |
975 | &res_create_funcs)) | |
976 | goto res_create_fail; | |
977 | ||
978 | /* Create hardware sequencer */ | |
979 | if (!dce120_hw_sequencer_create(dc)) | |
980 | goto controller_create_fail; | |
981 | ||
d4e13b0d AD |
982 | dc->public.caps.max_surfaces = pool->base.pipe_count; |
983 | ||
b8fdfcc6 HW |
984 | bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); |
985 | ||
986 | bw_calcs_data_update_from_pplib(dc); | |
987 | ||
988 | return true; | |
989 | ||
990 | irqs_create_fail: | |
991 | controller_create_fail: | |
992 | disp_clk_create_fail: | |
993 | clk_src_create_fail: | |
994 | res_create_fail: | |
995 | ||
996 | destruct(pool); | |
997 | ||
998 | return false; | |
999 | } | |
1000 | ||
1001 | struct resource_pool *dce120_create_resource_pool( | |
1002 | uint8_t num_virtual_links, | |
1003 | struct core_dc *dc) | |
1004 | { | |
1005 | struct dce110_resource_pool *pool = | |
1006 | dm_alloc(sizeof(struct dce110_resource_pool)); | |
1007 | ||
1008 | if (!pool) | |
1009 | return NULL; | |
1010 | ||
1011 | if (construct(num_virtual_links, dc, pool)) | |
1012 | return &pool->base; | |
1013 | ||
1014 | BREAK_TO_DEBUGGER(); | |
1015 | return NULL; | |
1016 | } |