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b8fdfcc6 HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc.cls | |
3 | * | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: AMD | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "dm_services.h" | |
28 | ||
29 | ||
30 | #include "stream_encoder.h" | |
31 | #include "resource.h" | |
32 | #include "include/irq_service_interface.h" | |
33 | #include "dce120_resource.h" | |
34 | #include "dce112/dce112_resource.h" | |
35 | ||
36 | #include "dce110/dce110_resource.h" | |
37 | #include "../virtual/virtual_stream_encoder.h" | |
38 | #include "dce120_timing_generator.h" | |
39 | #include "irq/dce120/irq_service_dce120.h" | |
40 | #include "dce/dce_opp.h" | |
41 | #include "dce/dce_clock_source.h" | |
42 | #include "dce/dce_clocks.h" | |
86b6a203 | 43 | #include "dce/dce_ipp.h" |
c3489214 | 44 | #include "dce/dce_mem_input.h" |
b8fdfcc6 HW |
45 | |
46 | #include "dce110/dce110_hw_sequencer.h" | |
47 | #include "dce120/dce120_hw_sequencer.h" | |
48 | #include "dce/dce_transform.h" | |
49 | ||
50 | #include "dce/dce_audio.h" | |
51 | #include "dce/dce_link_encoder.h" | |
52 | #include "dce/dce_stream_encoder.h" | |
53 | #include "dce/dce_hwseq.h" | |
54 | #include "dce/dce_abm.h" | |
55 | #include "dce/dce_dmcu.h" | |
56 | ||
57 | #include "vega10/DC/dce_12_0_offset.h" | |
58 | #include "vega10/DC/dce_12_0_sh_mask.h" | |
59 | #include "vega10/soc15ip.h" | |
60 | #include "vega10/NBIO/nbio_6_1_offset.h" | |
61 | #include "reg_helper.h" | |
62 | ||
792671d7 AG |
63 | #include "dce100/dce100_resource.h" |
64 | ||
b8fdfcc6 HW |
65 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL |
66 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f | |
67 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
68 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f | |
69 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
70 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f | |
71 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
72 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f | |
73 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
74 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f | |
75 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
76 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f | |
77 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
78 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f | |
79 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
80 | #endif | |
81 | ||
82 | enum dce120_clk_src_array_id { | |
83 | DCE120_CLK_SRC_PLL0, | |
84 | DCE120_CLK_SRC_PLL1, | |
85 | DCE120_CLK_SRC_PLL2, | |
86 | DCE120_CLK_SRC_PLL3, | |
87 | DCE120_CLK_SRC_PLL4, | |
88 | DCE120_CLK_SRC_PLL5, | |
89 | ||
90 | DCE120_CLK_SRC_TOTAL | |
91 | }; | |
92 | ||
93 | static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { | |
94 | { | |
95 | .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
96 | }, | |
97 | { | |
98 | .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
99 | }, | |
100 | { | |
101 | .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
102 | }, | |
103 | { | |
104 | .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
105 | }, | |
106 | { | |
107 | .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
108 | }, | |
109 | { | |
110 | .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), | |
111 | } | |
112 | }; | |
113 | ||
114 | /* begin ********************* | |
115 | * macros to expend register list macro defined in HW object header file */ | |
116 | ||
117 | #define BASE_INNER(seg) \ | |
118 | DCE_BASE__INST0_SEG ## seg | |
119 | ||
120 | #define NBIO_BASE_INNER(seg) \ | |
121 | NBIF_BASE__INST0_SEG ## seg | |
122 | ||
123 | #define NBIO_BASE(seg) \ | |
124 | NBIO_BASE_INNER(seg) | |
125 | ||
126 | /* compile time expand base address. */ | |
127 | #define BASE(seg) \ | |
128 | BASE_INNER(seg) | |
129 | ||
130 | #define SR(reg_name)\ | |
131 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
132 | mm ## reg_name | |
133 | ||
134 | #define SRI(reg_name, block, id)\ | |
135 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
136 | mm ## block ## id ## _ ## reg_name | |
137 | ||
138 | /* macros to expend register list macro defined in HW object header file | |
139 | * end *********************/ | |
140 | ||
141 | ||
b8fdfcc6 HW |
142 | static const struct dce_dmcu_registers dmcu_regs = { |
143 | DMCU_DCE110_COMMON_REG_LIST() | |
144 | }; | |
145 | ||
146 | static const struct dce_dmcu_shift dmcu_shift = { | |
147 | DMCU_MASK_SH_LIST_DCE110(__SHIFT) | |
148 | }; | |
149 | ||
150 | static const struct dce_dmcu_mask dmcu_mask = { | |
151 | DMCU_MASK_SH_LIST_DCE110(_MASK) | |
152 | }; | |
153 | ||
154 | static const struct dce_abm_registers abm_regs = { | |
155 | ABM_DCE110_COMMON_REG_LIST() | |
156 | }; | |
157 | ||
158 | static const struct dce_abm_shift abm_shift = { | |
159 | ABM_MASK_SH_LIST_DCE110(__SHIFT) | |
160 | }; | |
161 | ||
162 | static const struct dce_abm_mask abm_mask = { | |
163 | ABM_MASK_SH_LIST_DCE110(_MASK) | |
164 | }; | |
165 | ||
86b6a203 DL |
166 | #define ipp_regs(id)\ |
167 | [id] = {\ | |
e6303950 | 168 | IPP_DCE110_REG_LIST_DCE_BASE(id)\ |
86b6a203 DL |
169 | } |
170 | ||
171 | static const struct dce_ipp_registers ipp_regs[] = { | |
172 | ipp_regs(0), | |
173 | ipp_regs(1), | |
174 | ipp_regs(2), | |
175 | ipp_regs(3), | |
176 | ipp_regs(4), | |
177 | ipp_regs(5) | |
178 | }; | |
179 | ||
180 | static const struct dce_ipp_shift ipp_shift = { | |
e6303950 | 181 | IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) |
86b6a203 DL |
182 | }; |
183 | ||
184 | static const struct dce_ipp_mask ipp_mask = { | |
e6303950 | 185 | IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) |
86b6a203 DL |
186 | }; |
187 | ||
b8fdfcc6 HW |
188 | #define transform_regs(id)\ |
189 | [id] = {\ | |
190 | XFM_COMMON_REG_LIST_DCE110(id)\ | |
191 | } | |
192 | ||
193 | static const struct dce_transform_registers xfm_regs[] = { | |
194 | transform_regs(0), | |
195 | transform_regs(1), | |
196 | transform_regs(2), | |
197 | transform_regs(3), | |
198 | transform_regs(4), | |
199 | transform_regs(5) | |
200 | }; | |
201 | ||
202 | static const struct dce_transform_shift xfm_shift = { | |
203 | XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) | |
204 | }; | |
205 | ||
206 | static const struct dce_transform_mask xfm_mask = { | |
207 | XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) | |
208 | }; | |
209 | ||
210 | #define aux_regs(id)\ | |
211 | [id] = {\ | |
212 | AUX_REG_LIST(id)\ | |
213 | } | |
214 | ||
215 | static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { | |
216 | aux_regs(0), | |
217 | aux_regs(1), | |
218 | aux_regs(2), | |
219 | aux_regs(3), | |
220 | aux_regs(4), | |
221 | aux_regs(5) | |
222 | }; | |
223 | ||
224 | #define hpd_regs(id)\ | |
225 | [id] = {\ | |
226 | HPD_REG_LIST(id)\ | |
227 | } | |
228 | ||
229 | static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
230 | hpd_regs(0), | |
231 | hpd_regs(1), | |
232 | hpd_regs(2), | |
233 | hpd_regs(3), | |
234 | hpd_regs(4), | |
235 | hpd_regs(5) | |
236 | }; | |
237 | ||
238 | #define link_regs(id)\ | |
239 | [id] = {\ | |
240 | LE_DCE120_REG_LIST(id), \ | |
241 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | |
242 | } | |
243 | ||
244 | static const struct dce110_link_enc_registers link_enc_regs[] = { | |
245 | link_regs(0), | |
246 | link_regs(1), | |
247 | link_regs(2), | |
248 | link_regs(3), | |
249 | link_regs(4), | |
250 | link_regs(5), | |
251 | link_regs(6), | |
252 | }; | |
253 | ||
254 | ||
255 | #define stream_enc_regs(id)\ | |
256 | [id] = {\ | |
257 | SE_COMMON_REG_LIST(id),\ | |
258 | .TMDS_CNTL = 0,\ | |
259 | } | |
260 | ||
261 | static const struct dce110_stream_enc_registers stream_enc_regs[] = { | |
262 | stream_enc_regs(0), | |
263 | stream_enc_regs(1), | |
264 | stream_enc_regs(2), | |
265 | stream_enc_regs(3), | |
266 | stream_enc_regs(4), | |
267 | stream_enc_regs(5) | |
268 | }; | |
269 | ||
270 | static const struct dce_stream_encoder_shift se_shift = { | |
271 | SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) | |
272 | }; | |
273 | ||
274 | static const struct dce_stream_encoder_mask se_mask = { | |
275 | SE_COMMON_MASK_SH_LIST_DCE120(_MASK) | |
276 | }; | |
277 | ||
278 | #define opp_regs(id)\ | |
279 | [id] = {\ | |
280 | OPP_DCE_120_REG_LIST(id),\ | |
281 | } | |
282 | ||
283 | static const struct dce_opp_registers opp_regs[] = { | |
284 | opp_regs(0), | |
285 | opp_regs(1), | |
286 | opp_regs(2), | |
287 | opp_regs(3), | |
288 | opp_regs(4), | |
289 | opp_regs(5) | |
290 | }; | |
291 | ||
292 | static const struct dce_opp_shift opp_shift = { | |
293 | OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) | |
294 | }; | |
295 | ||
296 | static const struct dce_opp_mask opp_mask = { | |
297 | OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) | |
298 | }; | |
299 | ||
300 | #define audio_regs(id)\ | |
301 | [id] = {\ | |
302 | AUD_COMMON_REG_LIST(id)\ | |
303 | } | |
304 | ||
395f669e | 305 | static const struct dce_audio_registers audio_regs[] = { |
b8fdfcc6 HW |
306 | audio_regs(0), |
307 | audio_regs(1), | |
308 | audio_regs(2), | |
309 | audio_regs(3), | |
310 | audio_regs(4), | |
311 | audio_regs(5) | |
312 | }; | |
313 | ||
314 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ | |
315 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ | |
316 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ | |
317 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) | |
318 | ||
319 | static const struct dce_audio_shift audio_shift = { | |
320 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
321 | }; | |
322 | ||
323 | static const struct dce_aduio_mask audio_mask = { | |
324 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) | |
325 | }; | |
326 | ||
327 | #define clk_src_regs(index, id)\ | |
328 | [index] = {\ | |
329 | CS_COMMON_REG_LIST_DCE_112(id),\ | |
330 | } | |
331 | ||
332 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
333 | clk_src_regs(0, A), | |
334 | clk_src_regs(1, B), | |
335 | clk_src_regs(2, C), | |
336 | clk_src_regs(3, D), | |
337 | clk_src_regs(4, E), | |
338 | clk_src_regs(5, F) | |
339 | }; | |
340 | ||
341 | static const struct dce110_clk_src_shift cs_shift = { | |
342 | CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) | |
343 | }; | |
344 | ||
345 | static const struct dce110_clk_src_mask cs_mask = { | |
346 | CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) | |
347 | }; | |
348 | ||
349 | struct output_pixel_processor *dce120_opp_create( | |
350 | struct dc_context *ctx, | |
351 | uint32_t inst) | |
352 | { | |
353 | struct dce110_opp *opp = | |
2004f45e | 354 | kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); |
b8fdfcc6 HW |
355 | |
356 | if (!opp) | |
357 | return NULL; | |
358 | ||
9cf29399 DA |
359 | dce110_opp_construct(opp, |
360 | ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); | |
361 | return &opp->base; | |
b8fdfcc6 HW |
362 | } |
363 | ||
b8fdfcc6 HW |
364 | static const struct bios_registers bios_regs = { |
365 | .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) | |
366 | }; | |
367 | ||
368 | static const struct resource_caps res_cap = { | |
6a4c32da | 369 | .num_timing_generator = 6, |
b8fdfcc6 HW |
370 | .num_audio = 7, |
371 | .num_stream_encoder = 6, | |
372 | .num_pll = 6, | |
373 | }; | |
374 | ||
375 | static const struct dc_debug debug_defaults = { | |
376 | .disable_clock_gate = true, | |
377 | }; | |
378 | ||
379 | struct clock_source *dce120_clock_source_create( | |
380 | struct dc_context *ctx, | |
381 | struct dc_bios *bios, | |
382 | enum clock_source_id id, | |
383 | const struct dce110_clk_src_regs *regs, | |
384 | bool dp_clk_src) | |
385 | { | |
386 | struct dce110_clk_src *clk_src = | |
2004f45e | 387 | kzalloc(sizeof(*clk_src), GFP_KERNEL); |
b8fdfcc6 HW |
388 | |
389 | if (!clk_src) | |
390 | return NULL; | |
391 | ||
392 | if (dce110_clk_src_construct(clk_src, ctx, bios, id, | |
76fd8eb8 | 393 | regs, &cs_shift, &cs_mask)) { |
b8fdfcc6 HW |
394 | clk_src->base.dp_clk_src = dp_clk_src; |
395 | return &clk_src->base; | |
396 | } | |
397 | ||
398 | BREAK_TO_DEBUGGER(); | |
399 | return NULL; | |
400 | } | |
401 | ||
402 | void dce120_clock_source_destroy(struct clock_source **clk_src) | |
403 | { | |
2004f45e | 404 | kfree(TO_DCE110_CLK_SRC(*clk_src)); |
b8fdfcc6 HW |
405 | *clk_src = NULL; |
406 | } | |
407 | ||
408 | ||
fb3466a4 | 409 | bool dce120_hw_sequencer_create(struct dc *dc) |
b8fdfcc6 HW |
410 | { |
411 | /* All registers used by dce11.2 match those in dce11 in offset and | |
412 | * structure | |
413 | */ | |
414 | dce120_hw_sequencer_construct(dc); | |
415 | ||
416 | /*TODO Move to separate file and Override what is needed */ | |
417 | ||
418 | return true; | |
419 | } | |
420 | ||
421 | static struct timing_generator *dce120_timing_generator_create( | |
422 | struct dc_context *ctx, | |
423 | uint32_t instance, | |
424 | const struct dce110_timing_generator_offsets *offsets) | |
425 | { | |
426 | struct dce110_timing_generator *tg110 = | |
2004f45e | 427 | kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); |
b8fdfcc6 HW |
428 | |
429 | if (!tg110) | |
430 | return NULL; | |
431 | ||
432 | if (dce120_timing_generator_construct(tg110, ctx, instance, offsets)) | |
433 | return &tg110->base; | |
434 | ||
435 | BREAK_TO_DEBUGGER(); | |
2004f45e | 436 | kfree(tg110); |
b8fdfcc6 HW |
437 | return NULL; |
438 | } | |
439 | ||
b8fdfcc6 HW |
440 | static void dce120_transform_destroy(struct transform **xfm) |
441 | { | |
2004f45e | 442 | kfree(TO_DCE_TRANSFORM(*xfm)); |
b8fdfcc6 HW |
443 | *xfm = NULL; |
444 | } | |
445 | ||
446 | static void destruct(struct dce110_resource_pool *pool) | |
447 | { | |
448 | unsigned int i; | |
449 | ||
450 | for (i = 0; i < pool->base.pipe_count; i++) { | |
451 | if (pool->base.opps[i] != NULL) | |
452 | dce110_opp_destroy(&pool->base.opps[i]); | |
453 | ||
454 | if (pool->base.transforms[i] != NULL) | |
455 | dce120_transform_destroy(&pool->base.transforms[i]); | |
456 | ||
457 | if (pool->base.ipps[i] != NULL) | |
e6303950 | 458 | dce_ipp_destroy(&pool->base.ipps[i]); |
b8fdfcc6 HW |
459 | |
460 | if (pool->base.mis[i] != NULL) { | |
2004f45e | 461 | kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); |
b8fdfcc6 HW |
462 | pool->base.mis[i] = NULL; |
463 | } | |
464 | ||
465 | if (pool->base.irqs != NULL) { | |
466 | dal_irq_service_destroy(&pool->base.irqs); | |
467 | } | |
468 | ||
469 | if (pool->base.timing_generators[i] != NULL) { | |
2004f45e | 470 | kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); |
b8fdfcc6 HW |
471 | pool->base.timing_generators[i] = NULL; |
472 | } | |
473 | } | |
474 | ||
475 | for (i = 0; i < pool->base.audio_count; i++) { | |
476 | if (pool->base.audios[i]) | |
477 | dce_aud_destroy(&pool->base.audios[i]); | |
478 | } | |
479 | ||
480 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
481 | if (pool->base.stream_enc[i] != NULL) | |
2004f45e | 482 | kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); |
b8fdfcc6 HW |
483 | } |
484 | ||
485 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
486 | if (pool->base.clock_sources[i] != NULL) | |
487 | dce120_clock_source_destroy( | |
488 | &pool->base.clock_sources[i]); | |
489 | } | |
490 | ||
491 | if (pool->base.dp_clock_source != NULL) | |
492 | dce120_clock_source_destroy(&pool->base.dp_clock_source); | |
493 | ||
494 | if (pool->base.abm != NULL) | |
495 | dce_abm_destroy(&pool->base.abm); | |
496 | ||
497 | if (pool->base.dmcu != NULL) | |
498 | dce_dmcu_destroy(&pool->base.dmcu); | |
499 | ||
500 | if (pool->base.display_clock != NULL) | |
501 | dce_disp_clk_destroy(&pool->base.display_clock); | |
502 | } | |
503 | ||
504 | static void read_dce_straps( | |
505 | struct dc_context *ctx, | |
506 | struct resource_straps *straps) | |
507 | { | |
508 | /* TODO: Registers are missing */ | |
509 | /*REG_GET_2(CC_DC_HDMI_STRAPS, | |
510 | HDMI_DISABLE, &straps->hdmi_disable, | |
511 | AUDIO_STREAM_NUMBER, &straps->audio_stream_number); | |
512 | ||
513 | REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/ | |
514 | } | |
515 | ||
516 | static struct audio *create_audio( | |
517 | struct dc_context *ctx, unsigned int inst) | |
518 | { | |
519 | return dce_audio_create(ctx, inst, | |
520 | &audio_regs[inst], &audio_shift, &audio_mask); | |
521 | } | |
522 | ||
523 | static const struct encoder_feature_support link_enc_feature = { | |
524 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
525 | .max_hdmi_pixel_clock = 600000, | |
526 | .ycbcr420_supported = true, | |
527 | .flags.bits.IS_HBR2_CAPABLE = true, | |
528 | .flags.bits.IS_HBR3_CAPABLE = true, | |
529 | .flags.bits.IS_TPS3_CAPABLE = true, | |
530 | .flags.bits.IS_TPS4_CAPABLE = true, | |
531 | .flags.bits.IS_YCBCR_CAPABLE = true | |
532 | }; | |
533 | ||
2cf5a5e6 | 534 | static struct link_encoder *dce120_link_encoder_create( |
b8fdfcc6 HW |
535 | const struct encoder_init_data *enc_init_data) |
536 | { | |
537 | struct dce110_link_encoder *enc110 = | |
2004f45e | 538 | kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); |
b8fdfcc6 HW |
539 | |
540 | if (!enc110) | |
541 | return NULL; | |
542 | ||
c60ae112 DA |
543 | dce110_link_encoder_construct(enc110, |
544 | enc_init_data, | |
545 | &link_enc_feature, | |
546 | &link_enc_regs[enc_init_data->transmitter], | |
547 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
548 | &link_enc_hpd_regs[enc_init_data->hpd_source]); | |
b8fdfcc6 | 549 | |
c60ae112 | 550 | return &enc110->base; |
b8fdfcc6 HW |
551 | } |
552 | ||
553 | static struct input_pixel_processor *dce120_ipp_create( | |
86b6a203 | 554 | struct dc_context *ctx, uint32_t inst) |
b8fdfcc6 | 555 | { |
2004f45e | 556 | struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); |
b8fdfcc6 | 557 | |
86b6a203 DL |
558 | if (!ipp) { |
559 | BREAK_TO_DEBUGGER(); | |
b8fdfcc6 | 560 | return NULL; |
86b6a203 | 561 | } |
b8fdfcc6 | 562 | |
86b6a203 DL |
563 | dce_ipp_construct(ipp, ctx, inst, |
564 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
565 | return &ipp->base; | |
b8fdfcc6 HW |
566 | } |
567 | ||
568 | static struct stream_encoder *dce120_stream_encoder_create( | |
569 | enum engine_id eng_id, | |
570 | struct dc_context *ctx) | |
571 | { | |
572 | struct dce110_stream_encoder *enc110 = | |
2004f45e | 573 | kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); |
b8fdfcc6 HW |
574 | |
575 | if (!enc110) | |
576 | return NULL; | |
577 | ||
f29f918f DA |
578 | dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, |
579 | &stream_enc_regs[eng_id], | |
580 | &se_shift, &se_mask); | |
581 | return &enc110->base; | |
b8fdfcc6 HW |
582 | } |
583 | ||
584 | #define SRII(reg_name, block, id)\ | |
585 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
586 | mm ## block ## id ## _ ## reg_name | |
587 | ||
588 | static const struct dce_hwseq_registers hwseq_reg = { | |
08b16886 | 589 | HWSEQ_DCE120_REG_LIST() |
b8fdfcc6 HW |
590 | }; |
591 | ||
592 | static const struct dce_hwseq_shift hwseq_shift = { | |
593 | HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) | |
594 | }; | |
595 | ||
596 | static const struct dce_hwseq_mask hwseq_mask = { | |
597 | HWSEQ_DCE12_MASK_SH_LIST(_MASK) | |
598 | }; | |
599 | ||
600 | static struct dce_hwseq *dce120_hwseq_create( | |
601 | struct dc_context *ctx) | |
602 | { | |
2004f45e | 603 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); |
b8fdfcc6 HW |
604 | |
605 | if (hws) { | |
606 | hws->ctx = ctx; | |
607 | hws->regs = &hwseq_reg; | |
608 | hws->shifts = &hwseq_shift; | |
609 | hws->masks = &hwseq_mask; | |
610 | } | |
611 | return hws; | |
612 | } | |
613 | ||
614 | static const struct resource_create_funcs res_create_funcs = { | |
615 | .read_dce_straps = read_dce_straps, | |
616 | .create_audio = create_audio, | |
617 | .create_stream_encoder = dce120_stream_encoder_create, | |
618 | .create_hwseq = dce120_hwseq_create, | |
619 | }; | |
620 | ||
621 | #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } | |
622 | static const struct dce_mem_input_registers mi_regs[] = { | |
623 | mi_inst_regs(0), | |
624 | mi_inst_regs(1), | |
625 | mi_inst_regs(2), | |
626 | mi_inst_regs(3), | |
627 | mi_inst_regs(4), | |
628 | mi_inst_regs(5), | |
629 | }; | |
630 | ||
631 | static const struct dce_mem_input_shift mi_shifts = { | |
632 | MI_DCE12_MASK_SH_LIST(__SHIFT) | |
633 | }; | |
634 | ||
635 | static const struct dce_mem_input_mask mi_masks = { | |
636 | MI_DCE12_MASK_SH_LIST(_MASK) | |
637 | }; | |
638 | ||
639 | static struct mem_input *dce120_mem_input_create( | |
640 | struct dc_context *ctx, | |
c3489214 | 641 | uint32_t inst) |
b8fdfcc6 | 642 | { |
2004f45e HW |
643 | struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), |
644 | GFP_KERNEL); | |
b8fdfcc6 | 645 | |
c3489214 DL |
646 | if (!dce_mi) { |
647 | BREAK_TO_DEBUGGER(); | |
b8fdfcc6 | 648 | return NULL; |
b8fdfcc6 HW |
649 | } |
650 | ||
c3489214 DL |
651 | dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); |
652 | return &dce_mi->base; | |
b8fdfcc6 HW |
653 | } |
654 | ||
655 | static struct transform *dce120_transform_create( | |
656 | struct dc_context *ctx, | |
657 | uint32_t inst) | |
658 | { | |
659 | struct dce_transform *transform = | |
2004f45e | 660 | kzalloc(sizeof(struct dce_transform), GFP_KERNEL); |
b8fdfcc6 HW |
661 | |
662 | if (!transform) | |
663 | return NULL; | |
664 | ||
665 | if (dce_transform_construct(transform, ctx, inst, | |
666 | &xfm_regs[inst], &xfm_shift, &xfm_mask)) { | |
667 | transform->lb_memory_size = 0x1404; /*5124*/ | |
668 | return &transform->base; | |
669 | } | |
670 | ||
671 | BREAK_TO_DEBUGGER(); | |
2004f45e | 672 | kfree(transform); |
b8fdfcc6 HW |
673 | return NULL; |
674 | } | |
675 | ||
676 | static void dce120_destroy_resource_pool(struct resource_pool **pool) | |
677 | { | |
678 | struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); | |
679 | ||
680 | destruct(dce110_pool); | |
2004f45e | 681 | kfree(dce110_pool); |
b8fdfcc6 HW |
682 | *pool = NULL; |
683 | } | |
684 | ||
685 | static const struct resource_funcs dce120_res_pool_funcs = { | |
686 | .destroy = dce120_destroy_resource_pool, | |
687 | .link_enc_create = dce120_link_encoder_create, | |
b8fdfcc6 | 688 | .validate_guaranteed = dce112_validate_guaranteed, |
792671d7 | 689 | .validate_bandwidth = dce112_validate_bandwidth, |
1dc90497 AG |
690 | .validate_plane = dce100_validate_plane, |
691 | .add_stream_to_ctx = dce112_add_stream_to_ctx | |
b8fdfcc6 HW |
692 | }; |
693 | ||
fb3466a4 | 694 | static void bw_calcs_data_update_from_pplib(struct dc *dc) |
b8fdfcc6 HW |
695 | { |
696 | struct dm_pp_clock_levels_with_latency eng_clks = {0}; | |
697 | struct dm_pp_clock_levels_with_latency mem_clks = {0}; | |
698 | struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; | |
699 | int i; | |
700 | unsigned int clk; | |
701 | unsigned int latency; | |
702 | ||
703 | /*do system clock*/ | |
704 | if (!dm_pp_get_clock_levels_by_type_with_latency( | |
705 | dc->ctx, | |
706 | DM_PP_CLOCK_TYPE_ENGINE_CLK, | |
707 | &eng_clks) || eng_clks.num_levels == 0) { | |
708 | ||
709 | eng_clks.num_levels = 8; | |
710 | clk = 300000; | |
711 | ||
712 | for (i = 0; i < eng_clks.num_levels; i++) { | |
713 | eng_clks.data[i].clocks_in_khz = clk; | |
714 | clk += 100000; | |
715 | } | |
716 | } | |
717 | ||
718 | /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ | |
77a4ea53 | 719 | dc->bw_vbios->high_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 720 | eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); |
77a4ea53 | 721 | dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 722 | eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); |
77a4ea53 | 723 | dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 724 | eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); |
77a4ea53 | 725 | dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 726 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); |
77a4ea53 | 727 | dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 728 | eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); |
77a4ea53 | 729 | dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 730 | eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); |
77a4ea53 | 731 | dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( |
b8fdfcc6 | 732 | eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); |
77a4ea53 | 733 | dc->bw_vbios->low_sclk = bw_frc_to_fixed( |
b8fdfcc6 HW |
734 | eng_clks.data[0].clocks_in_khz, 1000); |
735 | ||
736 | /*do memory clock*/ | |
737 | if (!dm_pp_get_clock_levels_by_type_with_latency( | |
738 | dc->ctx, | |
739 | DM_PP_CLOCK_TYPE_MEMORY_CLK, | |
740 | &mem_clks) || mem_clks.num_levels == 0) { | |
741 | ||
742 | mem_clks.num_levels = 3; | |
743 | clk = 250000; | |
744 | latency = 45; | |
745 | ||
746 | for (i = 0; i < eng_clks.num_levels; i++) { | |
747 | mem_clks.data[i].clocks_in_khz = clk; | |
748 | mem_clks.data[i].latency_in_us = latency; | |
749 | clk += 500000; | |
750 | latency -= 5; | |
751 | } | |
752 | ||
753 | } | |
754 | ||
755 | /* we don't need to call PPLIB for validation clock since they | |
756 | * also give us the highest sclk and highest mclk (UMA clock). | |
757 | * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): | |
758 | * YCLK = UMACLK*m_memoryTypeMultiplier | |
759 | */ | |
77a4ea53 | 760 | dc->bw_vbios->low_yclk = bw_frc_to_fixed( |
b8fdfcc6 | 761 | mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); |
77a4ea53 | 762 | dc->bw_vbios->mid_yclk = bw_frc_to_fixed( |
b8fdfcc6 HW |
763 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, |
764 | 1000); | |
77a4ea53 | 765 | dc->bw_vbios->high_yclk = bw_frc_to_fixed( |
b8fdfcc6 HW |
766 | mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, |
767 | 1000); | |
768 | ||
769 | /* Now notify PPLib/SMU about which Watermarks sets they should select | |
770 | * depending on DPM state they are in. And update BW MGR GFX Engine and | |
771 | * Memory clock member variables for Watermarks calculations for each | |
772 | * Watermark Set | |
773 | */ | |
774 | clk_ranges.num_wm_sets = 4; | |
775 | clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; | |
776 | clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = | |
777 | eng_clks.data[0].clocks_in_khz; | |
778 | clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = | |
779 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; | |
780 | clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = | |
781 | mem_clks.data[0].clocks_in_khz; | |
782 | clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = | |
783 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; | |
784 | ||
785 | clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; | |
786 | clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = | |
787 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; | |
788 | /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ | |
789 | clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; | |
790 | clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = | |
791 | mem_clks.data[0].clocks_in_khz; | |
792 | clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = | |
793 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; | |
794 | ||
795 | clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; | |
796 | clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = | |
797 | eng_clks.data[0].clocks_in_khz; | |
798 | clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = | |
799 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; | |
800 | clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = | |
801 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; | |
802 | /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ | |
803 | clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; | |
804 | ||
805 | clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; | |
806 | clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = | |
807 | eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; | |
808 | /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ | |
809 | clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; | |
810 | clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = | |
811 | mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; | |
812 | /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ | |
813 | clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; | |
814 | ||
815 | /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ | |
816 | dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); | |
817 | } | |
818 | ||
819 | static bool construct( | |
820 | uint8_t num_virtual_links, | |
fb3466a4 | 821 | struct dc *dc, |
b8fdfcc6 HW |
822 | struct dce110_resource_pool *pool) |
823 | { | |
824 | unsigned int i; | |
825 | struct dc_context *ctx = dc->ctx; | |
8fa9ca2e | 826 | struct irq_service_init_data irq_init_data; |
b8fdfcc6 HW |
827 | |
828 | ctx->dc_bios->regs = &bios_regs; | |
829 | ||
830 | pool->base.res_cap = &res_cap; | |
831 | pool->base.funcs = &dce120_res_pool_funcs; | |
832 | ||
833 | /* TODO: Fill more data from GreenlandAsicCapability.cpp */ | |
6a4c32da | 834 | pool->base.pipe_count = res_cap.num_timing_generator; |
b8fdfcc6 HW |
835 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
836 | ||
fb3466a4 BL |
837 | dc->caps.max_downscale_ratio = 200; |
838 | dc->caps.i2c_speed_in_khz = 100; | |
839 | dc->caps.max_cursor_size = 128; | |
840 | dc->debug = debug_defaults; | |
b8fdfcc6 HW |
841 | |
842 | /************************************************* | |
843 | * Create resources * | |
844 | *************************************************/ | |
845 | ||
846 | pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = | |
847 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
848 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |
849 | &clk_src_regs[0], false); | |
850 | pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = | |
851 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
852 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |
853 | &clk_src_regs[1], false); | |
854 | pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = | |
855 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
856 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |
857 | &clk_src_regs[2], false); | |
858 | pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = | |
859 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
860 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |
861 | &clk_src_regs[3], false); | |
862 | pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = | |
863 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
864 | CLOCK_SOURCE_COMBO_PHY_PLL4, | |
865 | &clk_src_regs[4], false); | |
866 | pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = | |
867 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
868 | CLOCK_SOURCE_COMBO_PHY_PLL5, | |
869 | &clk_src_regs[5], false); | |
870 | pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; | |
871 | ||
872 | pool->base.dp_clock_source = | |
873 | dce120_clock_source_create(ctx, ctx->dc_bios, | |
874 | CLOCK_SOURCE_ID_DP_DTO, | |
875 | &clk_src_regs[0], true); | |
876 | ||
877 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
878 | if (pool->base.clock_sources[i] == NULL) { | |
879 | dm_error("DC: failed to create clock sources!\n"); | |
880 | BREAK_TO_DEBUGGER(); | |
881 | goto clk_src_create_fail; | |
882 | } | |
883 | } | |
884 | ||
b1a4eb99 | 885 | pool->base.display_clock = dce120_disp_clk_create(ctx); |
b8fdfcc6 HW |
886 | if (pool->base.display_clock == NULL) { |
887 | dm_error("DC: failed to create display clock!\n"); | |
888 | BREAK_TO_DEBUGGER(); | |
889 | goto disp_clk_create_fail; | |
890 | } | |
891 | ||
892 | pool->base.dmcu = dce_dmcu_create(ctx, | |
893 | &dmcu_regs, | |
894 | &dmcu_shift, | |
895 | &dmcu_mask); | |
896 | if (pool->base.dmcu == NULL) { | |
897 | dm_error("DC: failed to create dmcu!\n"); | |
898 | BREAK_TO_DEBUGGER(); | |
899 | goto res_create_fail; | |
900 | } | |
901 | ||
902 | pool->base.abm = dce_abm_create(ctx, | |
903 | &abm_regs, | |
904 | &abm_shift, | |
905 | &abm_mask); | |
906 | if (pool->base.abm == NULL) { | |
907 | dm_error("DC: failed to create abm!\n"); | |
908 | BREAK_TO_DEBUGGER(); | |
909 | goto res_create_fail; | |
910 | } | |
911 | ||
8fa9ca2e AD |
912 | irq_init_data.ctx = dc->ctx; |
913 | pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); | |
914 | if (!pool->base.irqs) | |
915 | goto irqs_create_fail; | |
b8fdfcc6 HW |
916 | |
917 | for (i = 0; i < pool->base.pipe_count; i++) { | |
918 | pool->base.timing_generators[i] = | |
919 | dce120_timing_generator_create( | |
920 | ctx, | |
921 | i, | |
922 | &dce120_tg_offsets[i]); | |
923 | if (pool->base.timing_generators[i] == NULL) { | |
924 | BREAK_TO_DEBUGGER(); | |
925 | dm_error("DC: failed to create tg!\n"); | |
926 | goto controller_create_fail; | |
927 | } | |
928 | ||
c3489214 | 929 | pool->base.mis[i] = dce120_mem_input_create(ctx, i); |
b8fdfcc6 HW |
930 | |
931 | if (pool->base.mis[i] == NULL) { | |
932 | BREAK_TO_DEBUGGER(); | |
933 | dm_error( | |
934 | "DC: failed to create memory input!\n"); | |
935 | goto controller_create_fail; | |
936 | } | |
937 | ||
86b6a203 | 938 | pool->base.ipps[i] = dce120_ipp_create(ctx, i); |
b8fdfcc6 HW |
939 | if (pool->base.ipps[i] == NULL) { |
940 | BREAK_TO_DEBUGGER(); | |
941 | dm_error( | |
942 | "DC: failed to create input pixel processor!\n"); | |
943 | goto controller_create_fail; | |
944 | } | |
945 | ||
946 | pool->base.transforms[i] = dce120_transform_create(ctx, i); | |
947 | if (pool->base.transforms[i] == NULL) { | |
948 | BREAK_TO_DEBUGGER(); | |
949 | dm_error( | |
950 | "DC: failed to create transform!\n"); | |
951 | goto res_create_fail; | |
952 | } | |
953 | ||
954 | pool->base.opps[i] = dce120_opp_create( | |
955 | ctx, | |
956 | i); | |
957 | if (pool->base.opps[i] == NULL) { | |
958 | BREAK_TO_DEBUGGER(); | |
959 | dm_error( | |
960 | "DC: failed to create output pixel processor!\n"); | |
961 | } | |
962 | } | |
963 | ||
964 | if (!resource_construct(num_virtual_links, dc, &pool->base, | |
965 | &res_create_funcs)) | |
966 | goto res_create_fail; | |
967 | ||
968 | /* Create hardware sequencer */ | |
969 | if (!dce120_hw_sequencer_create(dc)) | |
970 | goto controller_create_fail; | |
971 | ||
fb3466a4 | 972 | dc->caps.max_planes = pool->base.pipe_count; |
d4e13b0d | 973 | |
77a4ea53 | 974 | bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); |
b8fdfcc6 HW |
975 | |
976 | bw_calcs_data_update_from_pplib(dc); | |
977 | ||
978 | return true; | |
979 | ||
980 | irqs_create_fail: | |
981 | controller_create_fail: | |
982 | disp_clk_create_fail: | |
983 | clk_src_create_fail: | |
984 | res_create_fail: | |
985 | ||
986 | destruct(pool); | |
987 | ||
988 | return false; | |
989 | } | |
990 | ||
991 | struct resource_pool *dce120_create_resource_pool( | |
992 | uint8_t num_virtual_links, | |
fb3466a4 | 993 | struct dc *dc) |
b8fdfcc6 HW |
994 | { |
995 | struct dce110_resource_pool *pool = | |
2004f45e | 996 | kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); |
b8fdfcc6 HW |
997 | |
998 | if (!pool) | |
999 | return NULL; | |
1000 | ||
1001 | if (construct(num_virtual_links, dc, pool)) | |
1002 | return &pool->base; | |
1003 | ||
1004 | BREAK_TO_DEBUGGER(); | |
1005 | return NULL; | |
1006 | } |