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drm/amd/display: log HUBP using DTN logging
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hw_sequencer.c
CommitLineData
70ccab60
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
70ccab60 27#include "core_types.h"
70ccab60 28#include "resource.h"
b02c3b05 29#include "custom_float.h"
70ccab60
HW		 30#include "dcn10_hw_sequencer.h"
31#include "dce110/dce110_hw_sequencer.h"
5aff86c1 32#include "dce/dce_hwseq.h"
70ccab60 33#include "abm.h"
2248eb6b 34#include "dcn10/dcn10_mem_input.h"
587cdfe9
VP		 35#include "dcn10/dcn10_dpp.h"
36#include "dcn10/dcn10_mpc.h"
70ccab60
HW		 37#include "timing_generator.h"
38#include "opp.h"
39#include "ipp.h"
b02c3b05 40#include "mpc.h"
70ccab60
HW		 41#include "raven1/DCN/dcn_1_0_offset.h"
42#include "raven1/DCN/dcn_1_0_sh_mask.h"
43#include "vega10/soc15ip.h"
184debdb 44#include "reg_helper.h"
70ccab60 45
184debdb
DL		 46#define CTX \
47 hws->ctx
48#define REG(reg)\
49 hws->regs->reg
70ccab60 50
184debdb
DL		 51#undef FN
52#define FN(reg_name, field_name) \
53 hws->shifts->field_name, hws->masks->field_name
70ccab60 54
2b13d7d3
TC		 55
56static void verify_allow_pstate_change_high(
57 struct dce_hwseq *hws)
58{
59 /* pstate latency is ~20us so if we wait over 40us and pstate allow
60 * still not asserted, we are probably stuck and going to hang
61 */
62 static unsigned int pstate_wait_timeout_us = 40;
63 static unsigned int max_sampled_pstate_wait_us; /* data collection */
64 static bool forced_pstate_allow; /* help with revert wa */
65
66 unsigned int debug_index = 0x7;
67 unsigned int debug_data;
68 unsigned int force_allow_pstate = 0x30;
69 unsigned int i;
70
71 if (forced_pstate_allow) {
72 /* we hacked to force pstate allow to prevent hang last time
73 * we verify_allow_pstate_change_high. so disable force
74 * here so we can check status
75 */
76 REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, 0);
77 forced_pstate_allow = false;
78 }
79
80 /* description "3-0: Pipe0 cursor0 QOS
81 * 7-4: Pipe1 cursor0 QOS
82 * 11-8: Pipe2 cursor0 QOS
83 * 15-12: Pipe3 cursor0 QOS
84 * 16: Pipe0 Plane0 Allow Pstate Change
85 * 17: Pipe1 Plane0 Allow Pstate Change
86 * 18: Pipe2 Plane0 Allow Pstate Change
87 * 19: Pipe3 Plane0 Allow Pstate Change
88 * 20: Pipe0 Plane1 Allow Pstate Change
89 * 21: Pipe1 Plane1 Allow Pstate Change
90 * 22: Pipe2 Plane1 Allow Pstate Change
91 * 23: Pipe3 Plane1 Allow Pstate Change
92 * 24: Pipe0 cursor0 Allow Pstate Change
93 * 25: Pipe1 cursor0 Allow Pstate Change
94 * 26: Pipe2 cursor0 Allow Pstate Change
95 * 27: Pipe3 cursor0 Allow Pstate Change
96 * 28: WB0 Allow Pstate Change
97 * 29: WB1 Allow Pstate Change
98 * 30: Arbiter's allow_pstate_change
99 * 31: SOC pstate change request
100 */
101
102 REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
103
104 for (i = 0; i < pstate_wait_timeout_us; i++) {
105 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
106
107 if (debug_data & (1 << 30))
108 return;
109
110 if (max_sampled_pstate_wait_us < i)
111 max_sampled_pstate_wait_us = i;
112
113 udelay(1);
114 }
115
116 /* force pstate allow to prevent system hang
117 * and break to debugger to investigate
118 */
119 REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
120 forced_pstate_allow = true;
121 BREAK_TO_DEBUGGER();
122}
123
70ccab60 124static void enable_dppclk(
184debdb 125 struct dce_hwseq *hws,
70ccab60
HW		 126 uint8_t plane_id,
127 uint32_t requested_pix_clk,
128 bool dppclk_div)
129{
184debdb 130 dm_logger_write(hws->ctx->logger, LOG_SURFACE,
70ccab60
HW		 131 "dppclk_rate_control for pipe %d programed to %d\n",
132 plane_id,
133 dppclk_div);
134
4e5095ca 135 if (hws->shifts->DPPCLK_RATE_CONTROL)
184debdb 136 REG_UPDATE_2(DPP_CONTROL[plane_id],
4e5095ca 137 DPPCLK_RATE_CONTROL, dppclk_div,
70ccab60 138 DPP_CLOCK_ENABLE, 1);
4e5095ca
DL		 139 else
140 REG_UPDATE(DPP_CONTROL[plane_id],
70ccab60 141 DPP_CLOCK_ENABLE, 1);
70ccab60
HW		 142}
143
144static void enable_power_gating_plane(
184debdb 145 struct dce_hwseq *hws,
70ccab60
HW		 146 bool enable)
147{
70ccab60
HW		 148 bool force_on = 1; /* disable power gating */
149
150 if (enable)
151 force_on = 0;
152
153 /* DCHUBP0/1/2/3 */
184debdb
DL		 154 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
155 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
156 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
157 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
70ccab60
HW		 158
159 /* DPP0/1/2/3 */
184debdb
DL		 160 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
161 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
162 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
163 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
70ccab60
HW		 164}
165
0a87425a
TC		 166static void disable_vga(
167 struct dce_hwseq *hws)
168{
169 REG_WRITE(D1VGA_CONTROL, 0);
170 REG_WRITE(D2VGA_CONTROL, 0);
171 REG_WRITE(D3VGA_CONTROL, 0);
172 REG_WRITE(D4VGA_CONTROL, 0);
173}
174
70ccab60 175static void dpp_pg_control(
184debdb 176 struct dce_hwseq *hws,
70ccab60
HW		 177 unsigned int dpp_inst,
178 bool power_on)
179{
70ccab60
HW		 180 uint32_t power_gate = power_on ? 0 : 1;
181 uint32_t pwr_status = power_on ? 0 : 2;
182
184debdb 183 if (hws->ctx->dc->debug.disable_dpp_power_gate)
70ccab60
HW		 184 return;
185
186 switch (dpp_inst) {
187 case 0: /* DPP0 */
184debdb 188 REG_UPDATE(DOMAIN1_PG_CONFIG,
70ccab60
HW		 189 DOMAIN1_POWER_GATE, power_gate);
190
184debdb
DL		 191 REG_WAIT(DOMAIN1_PG_STATUS,
192 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 193 break;
194 case 1: /* DPP1 */
184debdb 195 REG_UPDATE(DOMAIN3_PG_CONFIG,
70ccab60
HW		 196 DOMAIN3_POWER_GATE, power_gate);
197
184debdb
DL		 198 REG_WAIT(DOMAIN3_PG_STATUS,
199 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 200 break;
201 case 2: /* DPP2 */
184debdb 202 REG_UPDATE(DOMAIN5_PG_CONFIG,
70ccab60
HW		 203 DOMAIN5_POWER_GATE, power_gate);
204
184debdb
DL		 205 REG_WAIT(DOMAIN5_PG_STATUS,
206 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 207 break;
208 case 3: /* DPP3 */
184debdb 209 REG_UPDATE(DOMAIN7_PG_CONFIG,
70ccab60
HW		 210 DOMAIN7_POWER_GATE, power_gate);
211
184debdb
DL		 212 REG_WAIT(DOMAIN7_PG_STATUS,
213 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 214 break;
215 default:
216 BREAK_TO_DEBUGGER();
217 break;
218 }
219}
220
08b16886
ZF		 221static uint32_t convert_and_clamp(
222 uint32_t wm_ns,
223 uint32_t refclk_mhz,
224 uint32_t clamp_value)
225{
226 uint32_t ret_val = 0;
227 ret_val = wm_ns * refclk_mhz;
228 ret_val /= 1000;
229
230 if (ret_val > clamp_value)
231 ret_val = clamp_value;
232
233 return ret_val;
234}
235
236static void program_watermarks(
237 struct dce_hwseq *hws,
238 struct dcn_watermark_set *watermarks,
239 unsigned int refclk_mhz)
240{
241 uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
242 /*
243 * Need to clamp to max of the register values (i.e. no wrap)
244 * for dcn1, all wm registers are 21-bit wide
245 */
246 uint32_t prog_wm_value;
247
248 /* Repeat for water mark set A, B, C and D. */
249 /* clock state A */
250 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
251 refclk_mhz, 0x1fffff);
252 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
253
254 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
255 "URGENCY_WATERMARK_A calculated =%d\n"
256 "HW register value = 0x%x\n",
257 watermarks->a.urgent_ns, prog_wm_value);
258
259 prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
260 refclk_mhz, 0x1fffff);
261 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
262 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
263 "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
264 "HW register value = 0x%x\n",
265 watermarks->a.pte_meta_urgent_ns, prog_wm_value);
266
267
268 prog_wm_value = convert_and_clamp(
269 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
270 refclk_mhz, 0x1fffff);
271
272 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
273 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
274 "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
275 "HW register value = 0x%x\n",
276 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
277
278
279 prog_wm_value = convert_and_clamp(
280 watermarks->a.cstate_pstate.cstate_exit_ns,
281 refclk_mhz, 0x1fffff);
282 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
283 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
284 "SR_EXIT_WATERMARK_A calculated =%d\n"
285 "HW register value = 0x%x\n",
286 watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
287
288
289 prog_wm_value = convert_and_clamp(
290 watermarks->a.cstate_pstate.pstate_change_ns,
291 refclk_mhz, 0x1fffff);
292 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
293 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
294 "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
295 "HW register value = 0x%x\n\n",
296 watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
297
298
299 /* clock state B */
300 prog_wm_value = convert_and_clamp(
301 watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
302 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
303 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
304 "URGENCY_WATERMARK_B calculated =%d\n"
305 "HW register value = 0x%x\n",
306 watermarks->b.urgent_ns, prog_wm_value);
307
308
309 prog_wm_value = convert_and_clamp(
310 watermarks->b.pte_meta_urgent_ns,
311 refclk_mhz, 0x1fffff);
312 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
313 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
314 "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
315 "HW register value = 0x%x\n",
316 watermarks->b.pte_meta_urgent_ns, prog_wm_value);
317
318
319 prog_wm_value = convert_and_clamp(
320 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
321 refclk_mhz, 0x1fffff);
322 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
323 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
324 "SR_ENTER_WATERMARK_B calculated =%d\n"
325 "HW register value = 0x%x\n",
326 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
327
328
329 prog_wm_value = convert_and_clamp(
330 watermarks->b.cstate_pstate.cstate_exit_ns,
331 refclk_mhz, 0x1fffff);
332 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
333 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
334 "SR_EXIT_WATERMARK_B calculated =%d\n"
335 "HW register value = 0x%x\n",
336 watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
337
338 prog_wm_value = convert_and_clamp(
339 watermarks->b.cstate_pstate.pstate_change_ns,
340 refclk_mhz, 0x1fffff);
341 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
342 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
343 "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
344 "HW register value = 0x%x\n",
345 watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
346
347 /* clock state C */
348 prog_wm_value = convert_and_clamp(
349 watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
350 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
351 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
352 "URGENCY_WATERMARK_C calculated =%d\n"
353 "HW register value = 0x%x\n",
354 watermarks->c.urgent_ns, prog_wm_value);
355
356
357 prog_wm_value = convert_and_clamp(
358 watermarks->c.pte_meta_urgent_ns,
359 refclk_mhz, 0x1fffff);
360 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
361 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
362 "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
363 "HW register value = 0x%x\n",
364 watermarks->c.pte_meta_urgent_ns, prog_wm_value);
365
366
367 prog_wm_value = convert_and_clamp(
368 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
369 refclk_mhz, 0x1fffff);
370 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
371 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
372 "SR_ENTER_WATERMARK_C calculated =%d\n"
373 "HW register value = 0x%x\n",
374 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
375
376
377 prog_wm_value = convert_and_clamp(
378 watermarks->c.cstate_pstate.cstate_exit_ns,
379 refclk_mhz, 0x1fffff);
380 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
381 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
382 "SR_EXIT_WATERMARK_C calculated =%d\n"
383 "HW register value = 0x%x\n",
384 watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
385
386
387 prog_wm_value = convert_and_clamp(
388 watermarks->c.cstate_pstate.pstate_change_ns,
389 refclk_mhz, 0x1fffff);
390 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
391 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
392 "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
393 "HW register value = 0x%x\n",
394 watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
395
396 /* clock state D */
397 prog_wm_value = convert_and_clamp(
398 watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
399 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
400 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
401 "URGENCY_WATERMARK_D calculated =%d\n"
402 "HW register value = 0x%x\n",
403 watermarks->d.urgent_ns, prog_wm_value);
404
405 prog_wm_value = convert_and_clamp(
406 watermarks->d.pte_meta_urgent_ns,
407 refclk_mhz, 0x1fffff);
408 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
409 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
410 "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
411 "HW register value = 0x%x\n",
412 watermarks->d.pte_meta_urgent_ns, prog_wm_value);
413
414
415 prog_wm_value = convert_and_clamp(
416 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
417 refclk_mhz, 0x1fffff);
418 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
419 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
420 "SR_ENTER_WATERMARK_D calculated =%d\n"
421 "HW register value = 0x%x\n",
422 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
423
424
425 prog_wm_value = convert_and_clamp(
426 watermarks->d.cstate_pstate.cstate_exit_ns,
427 refclk_mhz, 0x1fffff);
428 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
429 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
430 "SR_EXIT_WATERMARK_D calculated =%d\n"
431 "HW register value = 0x%x\n",
432 watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
433
434
435 prog_wm_value = convert_and_clamp(
436 watermarks->d.cstate_pstate.pstate_change_ns,
437 refclk_mhz, 0x1fffff);
438 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
439 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
440 "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
441 "HW register value = 0x%x\n\n",
442 watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
443
444 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
445 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
446 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
447 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
448 REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
449 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
450 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
451 DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
452
453 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
454 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
455 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
456
457#if 0
458 REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
459 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
460 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
461#endif
462}
463
464
465static void dcn10_update_dchub(
466 struct dce_hwseq *hws,
467 struct dchub_init_data *dh_data)
468{
469 /* TODO: port code from dal2 */
470 switch (dh_data->fb_mode) {
471 case FRAME_BUFFER_MODE_ZFB_ONLY:
472 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
473 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
474 SDPIF_FB_TOP, 0);
475
476 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
477 SDPIF_FB_BASE, 0x0FFFF);
478
479 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
480 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
481
482 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
483 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
484
485 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
486 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
487 dh_data->zfb_size_in_byte - 1) >> 22);
488 break;
489 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
490 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
491
492 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
493 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
494
495 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
496 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
497
498 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
499 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
500 dh_data->zfb_size_in_byte - 1) >> 22);
501 break;
502 case FRAME_BUFFER_MODE_LOCAL_ONLY:
503 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
504 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
505 SDPIF_AGP_BASE, 0);
506
507 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
508 SDPIF_AGP_BOT, 0X03FFFF);
509
510 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
511 SDPIF_AGP_TOP, 0);
512 break;
513 default:
514 break;
515 }
516
517 dh_data->dchub_initialzied = true;
518 dh_data->dchub_info_valid = false;
519}
520
70ccab60 521static void hubp_pg_control(
184debdb 522 struct dce_hwseq *hws,
70ccab60
HW		 523 unsigned int hubp_inst,
524 bool power_on)
525{
70ccab60
HW		 526 uint32_t power_gate = power_on ? 0 : 1;
527 uint32_t pwr_status = power_on ? 0 : 2;
528
184debdb 529 if (hws->ctx->dc->debug.disable_hubp_power_gate)
70ccab60
HW		 530 return;
531
532 switch (hubp_inst) {
533 case 0: /* DCHUBP0 */
184debdb 534 REG_UPDATE(DOMAIN0_PG_CONFIG,
70ccab60
HW		 535 DOMAIN0_POWER_GATE, power_gate);
536
184debdb
DL		 537 REG_WAIT(DOMAIN0_PG_STATUS,
538 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 539 break;
540 case 1: /* DCHUBP1 */
184debdb 541 REG_UPDATE(DOMAIN2_PG_CONFIG,
70ccab60
HW		 542 DOMAIN2_POWER_GATE, power_gate);
543
184debdb
DL		 544 REG_WAIT(DOMAIN2_PG_STATUS,
545 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 546 break;
547 case 2: /* DCHUBP2 */
184debdb 548 REG_UPDATE(DOMAIN4_PG_CONFIG,
70ccab60
HW		 549 DOMAIN4_POWER_GATE, power_gate);
550
184debdb
DL		 551 REG_WAIT(DOMAIN4_PG_STATUS,
552 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 553 break;
554 case 3: /* DCHUBP3 */
184debdb 555 REG_UPDATE(DOMAIN6_PG_CONFIG,
70ccab60
HW		 556 DOMAIN6_POWER_GATE, power_gate);
557
184debdb
DL		 558 REG_WAIT(DOMAIN6_PG_STATUS,
559 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
70ccab60
HW		 560 break;
561 default:
562 BREAK_TO_DEBUGGER();
563 break;
564 }
565}
566
567static void power_on_plane(
184debdb 568 struct dce_hwseq *hws,
cfe4645e 569 int plane_id)
70ccab60 570{
184debdb 571 REG_SET(DC_IP_REQUEST_CNTL, 0,
70ccab60 572 IP_REQUEST_EN, 1);
184debdb
DL		 573 dpp_pg_control(hws, plane_id, true);
574 hubp_pg_control(hws, plane_id, true);
575 REG_SET(DC_IP_REQUEST_CNTL, 0,
70ccab60 576 IP_REQUEST_EN, 0);
184debdb 577 dm_logger_write(hws->ctx->logger, LOG_DC,
cfe4645e 578 "Un-gated front end for pipe %d\n", plane_id);
70ccab60
HW		 579}
580
70ccab60
HW		 581static void bios_golden_init(struct core_dc *dc)
582{
583 struct dc_bios *bp = dc->ctx->dc_bios;
584 int i;
585
586 /* initialize dcn global */
587 bp->funcs->enable_disp_power_gating(bp,
588 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
589
590 for (i = 0; i < dc->res_pool->pipe_count; i++) {
591 /* initialize dcn per pipe */
592 bp->funcs->enable_disp_power_gating(bp,
593 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
594 }
595}
596
b02c3b05 597static void dcn10_init_hw(struct core_dc *dc)
70ccab60
HW		 598{
599 int i;
b02c3b05 600 struct abm *abm = dc->res_pool->abm;
184debdb 601 struct dce_hwseq *hws = dc->hwseq;
70ccab60 602
70ccab60 603 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
b02c3b05
DL		 604 REG_WRITE(REFCLK_CNTL, 0);
605 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
184debdb
DL		 606 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
607
608 if (!dc->public.debug.disable_clock_gate) {
609 /* enable all DCN clock gating */
610 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
611
612 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
70ccab60 613
184debdb
DL		 614 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
615 }
616
617 enable_power_gating_plane(dc->hwseq, true);
70ccab60
HW		 618 return;
619 }
620 /* end of FPGA. Below if real ASIC */
621
622 bios_golden_init(dc);
623
0a87425a
TC		 624 disable_vga(dc->hwseq);
625
70ccab60
HW		 626 for (i = 0; i < dc->link_count; i++) {
627 /* Power up AND update implementation according to the
628 * required signal (which may be different from the
629 * default signal on connector).
630 */
d0778ebf 631 struct dc_link *link = dc->links[i];
70ccab60
HW		 632
633 link->link_enc->funcs->hw_init(link->link_enc);
634 }
635
636 for (i = 0; i < dc->res_pool->pipe_count; i++) {
b02c3b05
DL		 637 struct transform *xfm = dc->res_pool->transforms[i];
638 struct timing_generator *tg = dc->res_pool->timing_generators[i];
639 struct mpcc *mpcc = dc->res_pool->mpcc[i];
f0558542
DL		 640 struct mpcc_cfg mpcc_cfg;
641
b02c3b05 642 xfm->funcs->transform_reset(xfm);
f0558542
DL		 643 mpcc_cfg.opp_id = 0xf;
644 mpcc_cfg.top_dpp_id = 0xf;
645 mpcc_cfg.bot_mpcc_id = 0xf;
646 mpcc_cfg.top_of_tree = true;
647 mpcc->funcs->set(mpcc, &mpcc_cfg);
70ccab60 648
70ccab60
HW		 649 /* Blank controller using driver code instead of
650 * command table.
651 */
652 tg->funcs->set_blank(tg, true);
653 hwss_wait_for_blank_complete(tg);
654 }
655
656 for (i = 0; i < dc->res_pool->audio_count; i++) {
657 struct audio *audio = dc->res_pool->audios[i];
658
659 audio->funcs->hw_init(audio);
660 }
661
70ccab60
HW		 662 if (abm != NULL) {
663 abm->funcs->init_backlight(abm);
664 abm->funcs->abm_init(abm);
665 }
666
667 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
184debdb 668 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
70ccab60 669
5970f2ae
HW		 670 if (!dc->public.debug.disable_clock_gate) {
671 /* enable all DCN clock gating */
184debdb 672 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
5970f2ae 673
184debdb 674 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
5970f2ae 675
184debdb
DL		 676 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
677 }
5970f2ae 678
184debdb 679 enable_power_gating_plane(dc->hwseq, true);
70ccab60
HW		 680}
681
682static enum dc_status dcn10_prog_pixclk_crtc_otg(
683 struct pipe_ctx *pipe_ctx,
684 struct validate_context *context,
685 struct core_dc *dc)
686{
687 struct core_stream *stream = pipe_ctx->stream;
688 enum dc_color_space color_space;
689 struct tg_color black_color = {0};
690 bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
691 false:true;
692 bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
693
694
695 /* by upper caller loop, pipe0 is parent pipe and be called first.
696 * back end is set up by for pipe0. Other children pipe share back end
697 * with pipe 0. No program is needed.
698 */
699 if (pipe_ctx->top_pipe != NULL)
700 return DC_OK;
701
702 /* TODO check if timing_changed, disable stream if timing changed */
703
704 /* HW program guide assume display already disable
705 * by unplug sequence. OTG assume stop.
706 */
707 pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, true);
708
709 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
710 pipe_ctx->clock_source,
711 &pipe_ctx->pix_clk_params,
712 &pipe_ctx->pll_settings)) {
713 BREAK_TO_DEBUGGER();
714 return DC_ERROR_UNEXPECTED;
715 }
716 pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
717 pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
718 pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
719 pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
720
721 pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
722
723 pipe_ctx->tg->funcs->program_timing(
724 pipe_ctx->tg,
725 &stream->public.timing,
726 true);
727
728 pipe_ctx->opp->funcs->opp_set_stereo_polarity(
729 pipe_ctx->opp,
730 enableStereo,
731 rightEyePolarity);
732
733#if 0 /* move to after enable_crtc */
734 /* TODO: OPP FMT, ABM. etc. should be done here. */
735 /* or FPGA now. instance 0 only. TODO: move to opp.c */
736
737 inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt;
738
739 pipe_ctx->opp->funcs->opp_program_fmt(
740 pipe_ctx->opp,
741 &stream->bit_depth_params,
742 &stream->clamping);
743#endif
744 /* program otg blank color */
745 color_space = stream->public.output_color_space;
746 color_space_to_black_color(dc, color_space, &black_color);
747 pipe_ctx->tg->funcs->set_blank_color(
748 pipe_ctx->tg,
749 &black_color);
750
751 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
752 hwss_wait_for_blank_complete(pipe_ctx->tg);
753
754 /* VTG is within DCHUB command block. DCFCLK is always on */
755 if (false == pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
756 BREAK_TO_DEBUGGER();
757 return DC_ERROR_UNEXPECTED;
758 }
759
760 /* TODO program crtc source select for non-virtual signal*/
761 /* TODO program FMT */
762 /* TODO setup link_enc */
763 /* TODO set stream attributes */
764 /* TODO program audio */
765 /* TODO enable stream if timing changed */
766 /* TODO unblank stream if DP */
767
768 return DC_OK;
769}
770
771static void reset_back_end_for_pipe(
772 struct core_dc *dc,
773 struct pipe_ctx *pipe_ctx,
774 struct validate_context *context)
775{
776 int i;
70ccab60
HW		 777
778 if (pipe_ctx->stream_enc == NULL) {
779 pipe_ctx->stream = NULL;
780 return;
781 }
782
783 /* TODOFPGA break core_link_disable_stream into 2 functions:
784 * disable_stream and disable_link. disable_link will disable PHYPLL
785 * which is used by otg. Move disable_link after disable_crtc
786 */
787 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
788 core_link_disable_stream(pipe_ctx);
789
790 /* by upper caller loop, parent pipe: pipe0, will be reset last.
791 * back end share by all pipes and will be disable only when disable
792 * parent pipe.
793 */
794 if (pipe_ctx->top_pipe == NULL) {
795 pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
796
797 pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, false);
798 }
799
800 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
801 resource_unreference_clock_source(
802 &context->res_ctx, dc->res_pool,
803 &pipe_ctx->clock_source);
804
805 for (i = 0; i < dc->res_pool->pipe_count; i++)
806 if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx)
807 break;
808
809 if (i == dc->res_pool->pipe_count)
810 return;
811
812 pipe_ctx->stream = NULL;
cfe4645e
DL		 813 dm_logger_write(dc->ctx->logger, LOG_DC,
814 "Reset back end for pipe %d, tg:%d\n",
815 pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
70ccab60
HW		 816}
817
a74b2734
TC		 818/* trigger HW to start disconnect plane from stream on the next vsync */
819static void plane_atomic_disconnect(struct core_dc *dc,
cfe4645e 820 int fe_idx)
70ccab60 821{
f0558542 822 struct mpcc_cfg mpcc_cfg;
cfe4645e
DL		 823 struct mem_input *mi = dc->res_pool->mis[fe_idx];
824 struct transform *xfm = dc->res_pool->transforms[fe_idx];
825 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
826 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
a74b2734
TC		 827 unsigned int opp_id = mpcc->opp_id;
828 int opp_id_cached = mpcc->opp_id;
829
830 /*Already reset*/
831 if (opp_id == 0xf)
832 return;
70ccab60 833
6be425f3
EY		 834 if (dc->public.debug.sanity_checks)
835 verify_allow_pstate_change_high(dc->hwseq);
836
189f73e3 837 mi->funcs->dcc_control(mi, false, false);
189f73e3 838
6be425f3
EY		 839 if (dc->public.debug.sanity_checks)
840 verify_allow_pstate_change_high(dc->hwseq);
841
f0558542
DL		 842 mpcc_cfg.opp_id = 0xf;
843 mpcc_cfg.top_dpp_id = 0xf;
844 mpcc_cfg.bot_mpcc_id = 0xf;
cfe4645e
DL		 845 mpcc_cfg.top_of_tree = tg->inst == mpcc->inst;
846 mpcc->funcs->set(mpcc, &mpcc_cfg);
70ccab60 847
6be425f3
EY		 848 /*
849 * Hack to preserve old opp_id for plane_atomic_disable
850 * to find the correct otg
851 */
a74b2734
TC		 852 mpcc->opp_id = opp_id_cached;
853
854 /* todo:call remove pipe from tree */
855 /* flag mpcc idle pending */
856
6be425f3
EY		 857 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
858 "[debug_mpo: plane_atomic_disconnect pending on mpcc %d]\n",
859 fe_idx);*/
d65359d5
TC		 860 xfm->funcs->transform_reset(xfm);
861}
862
a74b2734
TC		 863/* disable HW used by plane.
864 * note: cannot disable until disconnect is complete */
865static void plane_atomic_disable(struct core_dc *dc,
d65359d5
TC		 866 int fe_idx)
867{
868 struct dce_hwseq *hws = dc->hwseq;
869 struct mem_input *mi = dc->res_pool->mis[fe_idx];
870 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
871 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
872 unsigned int opp_id = mpcc->opp_id;
873
d65359d5
TC		 874 if (opp_id == 0xf)
875 return;
876
cfe4645e 877 mpcc->funcs->wait_for_idle(mpcc);
6be425f3
EY		 878 dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[mpcc->inst] = false;
879 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
880 "[debug_mpo: atomic disable finished on mpcc %d]\n",
881 fe_idx);*/
189f73e3 882
d65359d5
TC		 883 mi->funcs->set_blank(mi, true);
884
2b13d7d3
TC		 885 if (dc->public.debug.sanity_checks)
886 verify_allow_pstate_change_high(dc->hwseq);
887
d21becbe
TC		 888 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
889 HUBP_CLOCK_ENABLE, 0);
890 REG_UPDATE(DPP_CONTROL[fe_idx],
891 DPP_CLOCK_ENABLE, 0);
71a2f23e 892
d65359d5 893 if (tg->inst == mpcc->inst)
71a2f23e
EY		 894 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
895 OPP_PIPE_CLOCK_EN, 0);
70ccab60 896
a74b2734 897 mpcc->opp_id = 0xf;
2b13d7d3
TC		 898
899 if (dc->public.debug.sanity_checks)
900 verify_allow_pstate_change_high(dc->hwseq);
cfe4645e 901}
70ccab60 902
6be425f3
EY		 903/*
904 * kill power to plane hw
a74b2734 905 * note: cannot power down until plane is disable
6be425f3
EY		 906 */
907static void plane_atomic_power_down(struct core_dc *dc, int fe_idx)
a74b2734 908{
6be425f3
EY		 909 struct dce_hwseq *hws = dc->hwseq;
910
911 REG_SET(DC_IP_REQUEST_CNTL, 0,
912 IP_REQUEST_EN, 1);
913 dpp_pg_control(hws, fe_idx, false);
914 hubp_pg_control(hws, fe_idx, false);
915 REG_SET(DC_IP_REQUEST_CNTL, 0,
916 IP_REQUEST_EN, 0);
917 dm_logger_write(dc->ctx->logger, LOG_DC,
918 "Power gated front end %d\n", fe_idx);
a74b2734 919
6be425f3
EY		 920 if (dc->public.debug.sanity_checks)
921 verify_allow_pstate_change_high(dc->hwseq);
a74b2734 922}
6be425f3 923
a74b2734
TC		 924
925static void reset_front_end(
926 struct core_dc *dc,
927 int fe_idx)
928{
929 struct dce_hwseq *hws = dc->hwseq;
930 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
931 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
932 unsigned int opp_id = mpcc->opp_id;
933
934 /*Already reset*/
935 if (opp_id == 0xf)
936 return;
937
938 tg->funcs->lock(tg);
939
940 plane_atomic_disconnect(dc, fe_idx);
941
942 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
943 tg->funcs->unlock(tg);
944
945 if (dc->public.debug.sanity_checks)
946 verify_allow_pstate_change_high(dc->hwseq);
947
948 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
949 REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
950 VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);
951
952 plane_atomic_disable(dc, fe_idx);
953
954 dm_logger_write(dc->ctx->logger, LOG_DC,
955 "Reset front end %d\n",
956 fe_idx);
957}
958
cfe4645e
DL		 959static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx)
960{
184debdb 961 struct dce_hwseq *hws = dc->hwseq;
70ccab60 962
cfe4645e 963 reset_front_end(dc, fe_idx);
70ccab60 964
184debdb 965 REG_SET(DC_IP_REQUEST_CNTL, 0,
cfe4645e 966 IP_REQUEST_EN, 1);
184debdb
DL		 967 dpp_pg_control(hws, fe_idx, false);
968 hubp_pg_control(hws, fe_idx, false);
969 REG_SET(DC_IP_REQUEST_CNTL, 0,
cfe4645e 970 IP_REQUEST_EN, 0);
70ccab60 971 dm_logger_write(dc->ctx->logger, LOG_DC,
cfe4645e 972 "Power gated front end %d\n", fe_idx);
2b13d7d3
TC		 973
974 if (dc->public.debug.sanity_checks)
975 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 976}
977
cfe4645e
DL		 978static void reset_hw_ctx_wrap(
979 struct core_dc *dc,
980 struct validate_context *context)
70ccab60
HW		 981{
982 int i;
983
cfe4645e 984 /* Reset Front End*/
6be425f3
EY		 985 /* Lock*/
986 for (i = 0; i < dc->res_pool->pipe_count; i++) {
987 struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
988 struct timing_generator *tg = cur_pipe_ctx->tg;
989
990 if (cur_pipe_ctx->stream)
991 tg->funcs->lock(tg);
992 }
993 /* Disconnect*/
994 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
995 struct pipe_ctx *pipe_ctx_old =
996 &dc->current_context->res_ctx.pipe_ctx[i];
997 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
998
999 if (!pipe_ctx->stream ||
1000 !pipe_ctx->surface ||
1001 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1002
1003 plane_atomic_disconnect(dc, i);
1004 }
1005 }
1006 /* Unlock*/
1007 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1008 struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
1009 struct timing_generator *tg = cur_pipe_ctx->tg;
1010
1011 if (cur_pipe_ctx->stream)
1012 tg->funcs->unlock(tg);
1013 }
1014
1015 /* Disable and Powerdown*/
cfe4645e
DL		 1016 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1017 struct pipe_ctx *pipe_ctx_old =
1018 &dc->current_context->res_ctx.pipe_ctx[i];
1019 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1020
1021 /*if (!pipe_ctx_old->stream)
1022 continue;*/
1023
6be425f3
EY		 1024 if (pipe_ctx->stream && pipe_ctx->surface
1025 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1026 continue;
1027
1028 plane_atomic_disable(dc, i);
1029
cfe4645e 1030 if (!pipe_ctx->stream || !pipe_ctx->surface)
6be425f3 1031 plane_atomic_power_down(dc, i);
cfe4645e 1032 }
6be425f3 1033
cfe4645e 1034 /* Reset Back End*/
70ccab60
HW		 1035 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1036 struct pipe_ctx *pipe_ctx_old =
1037 &dc->current_context->res_ctx.pipe_ctx[i];
1038 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1039
1040 if (!pipe_ctx_old->stream)
1041 continue;
1042
1043 if (!pipe_ctx->stream ||
1044 pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
cfe4645e 1045 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context);
70ccab60
HW		 1046 }
1047}
1048
cfe4645e
DL		 1049static bool patch_address_for_sbs_tb_stereo(
1050 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
70ccab60 1051{
e12cfcb1 1052 struct dc_surface *surface = pipe_ctx->surface;
70ccab60
HW		 1053 bool sec_split = pipe_ctx->top_pipe &&
1054 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
e12cfcb1 1055 if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
70ccab60
HW		 1056 (pipe_ctx->stream->public.timing.timing_3d_format ==
1057 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1058 pipe_ctx->stream->public.timing.timing_3d_format ==
1059 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
e12cfcb1
HW		 1060 *addr = surface->address.grph_stereo.left_addr;
1061 surface->address.grph_stereo.left_addr =
1062 surface->address.grph_stereo.right_addr;
70ccab60 1063 return true;
cdc5e048
VP		 1064 } else {
1065 if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE &&
e12cfcb1
HW		 1066 surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1067 surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1068 surface->address.grph_stereo.right_addr =
1069 surface->address.grph_stereo.left_addr;
cdc5e048 1070 }
70ccab60
HW		 1071 }
1072 return false;
1073}
1074
1075static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx)
1076{
1077 bool addr_patched = false;
1078 PHYSICAL_ADDRESS_LOC addr;
e12cfcb1 1079 struct dc_surface *surface = pipe_ctx->surface;
70ccab60
HW		 1080
1081 if (surface == NULL)
1082 return;
1083 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1084 pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
1085 pipe_ctx->mi,
e12cfcb1
HW		 1086 &surface->address,
1087 surface->flip_immediate);
1088 surface->status.requested_address = surface->address;
70ccab60 1089 if (addr_patched)
e12cfcb1 1090 pipe_ctx->surface->address.grph_stereo.left_addr = addr;
70ccab60
HW		 1091}
1092
1093static bool dcn10_set_input_transfer_func(
e12cfcb1 1094 struct pipe_ctx *pipe_ctx, const struct dc_surface *surface)
70ccab60
HW		 1095{
1096 struct input_pixel_processor *ipp = pipe_ctx->ipp;
7b0c470f 1097 const struct dc_transfer_func *tf = NULL;
70ccab60
HW		 1098 bool result = true;
1099
1100 if (ipp == NULL)
1101 return false;
1102
e12cfcb1
HW		 1103 if (surface->in_transfer_func)
1104 tf = surface->in_transfer_func;
70ccab60 1105
e12cfcb1 1106 if (surface->gamma_correction && dce_use_lut(surface))
cfe4645e 1107 ipp->funcs->ipp_program_input_lut(ipp,
e12cfcb1 1108 surface->gamma_correction);
5aff86c1 1109
70ccab60
HW		 1110 if (tf == NULL)
1111 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
7b0c470f
LSL		 1112 else if (tf->type == TF_TYPE_PREDEFINED) {
1113 switch (tf->tf) {
70ccab60
HW		 1114 case TRANSFER_FUNCTION_SRGB:
1115 ipp->funcs->ipp_set_degamma(ipp,
1116 IPP_DEGAMMA_MODE_HW_sRGB);
1117 break;
1118 case TRANSFER_FUNCTION_BT709:
1119 ipp->funcs->ipp_set_degamma(ipp,
1120 IPP_DEGAMMA_MODE_HW_xvYCC);
1121 break;
1122 case TRANSFER_FUNCTION_LINEAR:
1123 ipp->funcs->ipp_set_degamma(ipp,
1124 IPP_DEGAMMA_MODE_BYPASS);
1125 break;
1126 case TRANSFER_FUNCTION_PQ:
1127 result = false;
1128 break;
1129 default:
1130 result = false;
1131 break;
1132 }
7b0c470f 1133 } else if (tf->type == TF_TYPE_BYPASS) {
70ccab60
HW		 1134 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
1135 } else {
1136 /*TF_TYPE_DISTRIBUTED_POINTS*/
1137 result = false;
1138 }
1139
1140 return result;
1141}
1142/*modify the method to handle rgb for arr_points*/
1143static bool convert_to_custom_float(
1144 struct pwl_result_data *rgb_resulted,
1145 struct curve_points *arr_points,
1146 uint32_t hw_points_num)
1147{
1148 struct custom_float_format fmt;
1149
1150 struct pwl_result_data *rgb = rgb_resulted;
1151
1152 uint32_t i = 0;
1153
1154 fmt.exponenta_bits = 6;
1155 fmt.mantissa_bits = 12;
1156 fmt.sign = false;
1157
1158 if (!convert_to_custom_float_format(
1159 arr_points[0].x,
1160 &fmt,
1161 &arr_points[0].custom_float_x)) {
1162 BREAK_TO_DEBUGGER();
1163 return false;
1164 }
1165
1166 if (!convert_to_custom_float_format(
1167 arr_points[0].offset,
1168 &fmt,
1169 &arr_points[0].custom_float_offset)) {
1170 BREAK_TO_DEBUGGER();
1171 return false;
1172 }
1173
1174 if (!convert_to_custom_float_format(
1175 arr_points[0].slope,
1176 &fmt,
1177 &arr_points[0].custom_float_slope)) {
1178 BREAK_TO_DEBUGGER();
1179 return false;
1180 }
1181
1182 fmt.mantissa_bits = 10;
1183 fmt.sign = false;
1184
1185 if (!convert_to_custom_float_format(
1186 arr_points[1].x,
1187 &fmt,
1188 &arr_points[1].custom_float_x)) {
1189 BREAK_TO_DEBUGGER();
1190 return false;
1191 }
1192
1193 if (!convert_to_custom_float_format(
1194 arr_points[1].y,
1195 &fmt,
1196 &arr_points[1].custom_float_y)) {
1197 BREAK_TO_DEBUGGER();
1198 return false;
1199 }
1200
1201 if (!convert_to_custom_float_format(
1202 arr_points[1].slope,
1203 &fmt,
1204 &arr_points[1].custom_float_slope)) {
1205 BREAK_TO_DEBUGGER();
1206 return false;
1207 }
1208
1209 fmt.mantissa_bits = 12;
1210 fmt.sign = true;
1211
1212 while (i != hw_points_num) {
1213 if (!convert_to_custom_float_format(
1214 rgb->red,
1215 &fmt,
1216 &rgb->red_reg)) {
1217 BREAK_TO_DEBUGGER();
1218 return false;
1219 }
1220
1221 if (!convert_to_custom_float_format(
1222 rgb->green,
1223 &fmt,
1224 &rgb->green_reg)) {
1225 BREAK_TO_DEBUGGER();
1226 return false;
1227 }
1228
1229 if (!convert_to_custom_float_format(
1230 rgb->blue,
1231 &fmt,
1232 &rgb->blue_reg)) {
1233 BREAK_TO_DEBUGGER();
1234 return false;
1235 }
1236
1237 if (!convert_to_custom_float_format(
1238 rgb->delta_red,
1239 &fmt,
1240 &rgb->delta_red_reg)) {
1241 BREAK_TO_DEBUGGER();
1242 return false;
1243 }
1244
1245 if (!convert_to_custom_float_format(
1246 rgb->delta_green,
1247 &fmt,
1248 &rgb->delta_green_reg)) {
1249 BREAK_TO_DEBUGGER();
1250 return false;
1251 }
1252
1253 if (!convert_to_custom_float_format(
1254 rgb->delta_blue,
1255 &fmt,
1256 &rgb->delta_blue_reg)) {
1257 BREAK_TO_DEBUGGER();
1258 return false;
1259 }
1260
1261 ++rgb;
1262 ++i;
1263 }
1264
1265 return true;
1266}
1267#define MAX_REGIONS_NUMBER 34
1268#define MAX_LOW_POINT 25
1269#define NUMBER_SEGMENTS 32
1270
1271static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
1272 *output_tf, struct pwl_params *regamma_params)
1273{
1274 struct curve_points *arr_points;
1275 struct pwl_result_data *rgb_resulted;
1276 struct pwl_result_data *rgb;
1277 struct pwl_result_data *rgb_plus_1;
1278 struct fixed31_32 y_r;
1279 struct fixed31_32 y_g;
1280 struct fixed31_32 y_b;
1281 struct fixed31_32 y1_min;
1282 struct fixed31_32 y3_max;
1283
1284 int32_t segment_start, segment_end;
1285 int32_t i;
1286 uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
1287
1288 if (output_tf == NULL || regamma_params == NULL ||
1289 output_tf->type == TF_TYPE_BYPASS)
1290 return false;
1291
1292 arr_points = regamma_params->arr_points;
1293 rgb_resulted = regamma_params->rgb_resulted;
1294 hw_points = 0;
1295
1296 memset(regamma_params, 0, sizeof(struct pwl_params));
1297 memset(seg_distr, 0, sizeof(seg_distr));
1298
1299 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1300 /* 32 segments
1301 * segments are from 2^-25 to 2^7
1302 */
1303 for (i = 0; i < 32 ; i++)
1304 seg_distr[i] = 3;
1305
1306 segment_start = -25;
1307 segment_end = 7;
1308 } else {
1309 /* 10 segments
1310 * segment is from 2^-10 to 2^0
1311 * There are less than 256 points, for optimization
1312 */
1313 seg_distr[0] = 3;
1314 seg_distr[1] = 4;
1315 seg_distr[2] = 4;
1316 seg_distr[3] = 4;
1317 seg_distr[4] = 4;
1318 seg_distr[5] = 4;
1319 seg_distr[6] = 4;
1320 seg_distr[7] = 4;
1321 seg_distr[8] = 5;
1322 seg_distr[9] = 5;
1323
1324 segment_start = -10;
1325 segment_end = 0;
1326 }
1327
1328 for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
1329 seg_distr[i] = -1;
1330
1331 for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
1332 if (seg_distr[k] != -1)
1333 hw_points += (1 << seg_distr[k]);
1334 }
1335
1336 j = 0;
1337 for (k = 0; k < (segment_end - segment_start); k++) {
1338 increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
1339 start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1340 for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
1341 if (j == hw_points - 1)
1342 break;
1343 rgb_resulted[j].red = output_tf->tf_pts.red[i];
1344 rgb_resulted[j].green = output_tf->tf_pts.green[i];
1345 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
1346 j++;
1347 }
1348 }
1349
1350 /* last point */
1351 start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1352 rgb_resulted[hw_points - 1].red =
1353 output_tf->tf_pts.red[start_index];
1354 rgb_resulted[hw_points - 1].green =
1355 output_tf->tf_pts.green[start_index];
1356 rgb_resulted[hw_points - 1].blue =
1357 output_tf->tf_pts.blue[start_index];
1358
1359 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1360 dal_fixed31_32_from_int(segment_start));
1361 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1362 dal_fixed31_32_from_int(segment_end));
1363 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1364 dal_fixed31_32_from_int(segment_end));
1365
1366 y_r = rgb_resulted[0].red;
1367 y_g = rgb_resulted[0].green;
1368 y_b = rgb_resulted[0].blue;
1369
1370 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
1371
1372 arr_points[0].y = y1_min;
1373 arr_points[0].slope = dal_fixed31_32_div(
1374 arr_points[0].y,
1375 arr_points[0].x);
1376 y_r = rgb_resulted[hw_points - 1].red;
1377 y_g = rgb_resulted[hw_points - 1].green;
1378 y_b = rgb_resulted[hw_points - 1].blue;
1379
1380 /* see comment above, m_arrPoints[1].y should be the Y value for the
1381 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
1382 */
1383 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
1384
1385 arr_points[1].y = y3_max;
1386 arr_points[2].y = y3_max;
1387
1388 arr_points[1].slope = dal_fixed31_32_zero;
1389 arr_points[2].slope = dal_fixed31_32_zero;
1390
1391 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1392 /* for PQ, we want to have a straight line from last HW X point,
1393 * and the slope to be such that we hit 1.0 at 10000 nits.
1394 */
1395 const struct fixed31_32 end_value =
1396 dal_fixed31_32_from_int(125);
1397
1398 arr_points[1].slope = dal_fixed31_32_div(
1399 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1400 dal_fixed31_32_sub(end_value, arr_points[1].x));
1401 arr_points[2].slope = dal_fixed31_32_div(
1402 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1403 dal_fixed31_32_sub(end_value, arr_points[1].x));
1404 }
1405
1406 regamma_params->hw_points_num = hw_points;
1407
1408 i = 1;
1409 for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
1410 if (seg_distr[k] != -1) {
1411 regamma_params->arr_curve_points[k].segments_num =
1412 seg_distr[k];
1413 regamma_params->arr_curve_points[i].offset =
1414 regamma_params->arr_curve_points[k].
1415 offset + (1 << seg_distr[k]);
1416 }
1417 i++;
1418 }
1419
1420 if (seg_distr[k] != -1)
1421 regamma_params->arr_curve_points[k].segments_num =
1422 seg_distr[k];
1423
1424 rgb = rgb_resulted;
1425 rgb_plus_1 = rgb_resulted + 1;
1426
1427 i = 1;
1428
1429 while (i != hw_points + 1) {
1430 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
1431 rgb_plus_1->red = rgb->red;
1432 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
1433 rgb_plus_1->green = rgb->green;
1434 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
1435 rgb_plus_1->blue = rgb->blue;
1436
1437 rgb->delta_red = dal_fixed31_32_sub(
1438 rgb_plus_1->red,
1439 rgb->red);
1440 rgb->delta_green = dal_fixed31_32_sub(
1441 rgb_plus_1->green,
1442 rgb->green);
1443 rgb->delta_blue = dal_fixed31_32_sub(
1444 rgb_plus_1->blue,
1445 rgb->blue);
1446
1447 ++rgb_plus_1;
1448 ++rgb;
1449 ++i;
1450 }
1451
1452 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
1453
1454 return true;
1455}
1456
1457static bool dcn10_set_output_transfer_func(
1458 struct pipe_ctx *pipe_ctx,
70ccab60
HW		 1459 const struct core_stream *stream)
1460{
c8d7bd8b 1461 struct transform *xfm = pipe_ctx->xfm;
70ccab60 1462
c8d7bd8b 1463 if (xfm == NULL)
f46661dd
AZ		 1464 return false;
1465
c8d7bd8b 1466 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
70ccab60
HW		 1467
1468 if (stream->public.out_transfer_func &&
1469 stream->public.out_transfer_func->type ==
1470 TF_TYPE_PREDEFINED &&
1471 stream->public.out_transfer_func->tf ==
1472 TRANSFER_FUNCTION_SRGB) {
c8d7bd8b 1473 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
70ccab60 1474 } else if (dcn10_translate_regamma_to_hw_format(
c8d7bd8b
YHL		 1475 stream->public.out_transfer_func, &xfm->regamma_params)) {
1476 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
1477 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
70ccab60 1478 } else {
c8d7bd8b 1479 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
70ccab60
HW		 1480 }
1481
1482 return true;
1483}
1484
1485static void dcn10_pipe_control_lock(
1486 struct core_dc *dc,
1487 struct pipe_ctx *pipe,
1488 bool lock)
1489{
70ccab60
HW		 1490 /* use TG master update lock to lock everything on the TG
1491 * therefore only top pipe need to lock
1492 */
1493 if (pipe->top_pipe)
1494 return;
1495
2b13d7d3
TC		 1496 if (dc->public.debug.sanity_checks)
1497 verify_allow_pstate_change_high(dc->hwseq);
1498
70ccab60 1499 if (lock)
cfe4645e 1500 pipe->tg->funcs->lock(pipe->tg);
70ccab60 1501 else
cfe4645e 1502 pipe->tg->funcs->unlock(pipe->tg);
2b13d7d3
TC		 1503
1504 if (dc->public.debug.sanity_checks)
1505 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 1506}
1507
1508static bool wait_for_reset_trigger_to_occur(
1509 struct dc_context *dc_ctx,
1510 struct timing_generator *tg)
1511{
1512 bool rc = false;
1513
1514 /* To avoid endless loop we wait at most
1515 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1516 const uint32_t frames_to_wait_on_triggered_reset = 10;
1517 int i;
1518
1519 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1520
1521 if (!tg->funcs->is_counter_moving(tg)) {
1522 DC_ERROR("TG counter is not moving!\n");
1523 break;
1524 }
1525
1526 if (tg->funcs->did_triggered_reset_occur(tg)) {
1527 rc = true;
1528 /* usually occurs at i=1 */
1529 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1530 i);
1531 break;
1532 }
1533
1534 /* Wait for one frame. */
1535 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1536 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1537 }
1538
1539 if (false == rc)
1540 DC_ERROR("GSL: Timeout on reset trigger!\n");
1541
1542 return rc;
1543}
1544
1545static void dcn10_enable_timing_synchronization(
1546 struct core_dc *dc,
1547 int group_index,
1548 int group_size,
1549 struct pipe_ctx *grouped_pipes[])
1550{
1551 struct dc_context *dc_ctx = dc->ctx;
1552 int i;
1553
1554 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1555
1556 for (i = 1; i < group_size; i++)
1557 grouped_pipes[i]->tg->funcs->enable_reset_trigger(
1558 grouped_pipes[i]->tg, grouped_pipes[0]->tg->inst);
1559
1560
1561 DC_SYNC_INFO("Waiting for trigger\n");
1562
1563 /* Need to get only check 1 pipe for having reset as all the others are
1564 * synchronized. Look at last pipe programmed to reset.
1565 */
1566 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->tg);
1567 for (i = 1; i < group_size; i++)
1568 grouped_pipes[i]->tg->funcs->disable_reset_trigger(
1569 grouped_pipes[i]->tg);
1570
1571 DC_SYNC_INFO("Sync complete\n");
1572}
1573
c9742685
DL		 1574static void print_rq_dlg_ttu(
1575 struct core_dc *core_dc,
1576 struct pipe_ctx *pipe_ctx)
1577{
1578 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1579 "\n============== DML TTU Output parameters [%d] ==============\n"
1580 "qos_level_low_wm: %d, \n"
1581 "qos_level_high_wm: %d, \n"
1582 "min_ttu_vblank: %d, \n"
1583 "qos_level_flip: %d, \n"
1584 "refcyc_per_req_delivery_l: %d, \n"
1585 "qos_level_fixed_l: %d, \n"
1586 "qos_ramp_disable_l: %d, \n"
1587 "refcyc_per_req_delivery_pre_l: %d, \n"
1588 "refcyc_per_req_delivery_c: %d, \n"
1589 "qos_level_fixed_c: %d, \n"
1590 "qos_ramp_disable_c: %d, \n"
1591 "refcyc_per_req_delivery_pre_c: %d\n"
1592 "=============================================================\n",
1593 pipe_ctx->pipe_idx,
1594 pipe_ctx->ttu_regs.qos_level_low_wm,
1595 pipe_ctx->ttu_regs.qos_level_high_wm,
1596 pipe_ctx->ttu_regs.min_ttu_vblank,
1597 pipe_ctx->ttu_regs.qos_level_flip,
1598 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1599 pipe_ctx->ttu_regs.qos_level_fixed_l,
1600 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1601 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1602 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1603 pipe_ctx->ttu_regs.qos_level_fixed_c,
1604 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1605 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1606 );
1607
1608 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1609 "\n============== DML DLG Output parameters [%d] ==============\n"
1610 "refcyc_h_blank_end: %d, \n"
1611 "dlg_vblank_end: %d, \n"
1612 "min_dst_y_next_start: %d, \n"
1613 "refcyc_per_htotal: %d, \n"
1614 "refcyc_x_after_scaler: %d, \n"
1615 "dst_y_after_scaler: %d, \n"
1616 "dst_y_prefetch: %d, \n"
1617 "dst_y_per_vm_vblank: %d, \n"
1618 "dst_y_per_row_vblank: %d, \n"
1619 "ref_freq_to_pix_freq: %d, \n"
1620 "vratio_prefetch: %d, \n"
1621 "refcyc_per_pte_group_vblank_l: %d, \n"
1622 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1623 "dst_y_per_pte_row_nom_l: %d, \n"
1624 "refcyc_per_pte_group_nom_l: %d, \n",
1625 pipe_ctx->pipe_idx,
1626 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1627 pipe_ctx->dlg_regs.dlg_vblank_end,
1628 pipe_ctx->dlg_regs.min_dst_y_next_start,
1629 pipe_ctx->dlg_regs.refcyc_per_htotal,
1630 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1631 pipe_ctx->dlg_regs.dst_y_after_scaler,
1632 pipe_ctx->dlg_regs.dst_y_prefetch,
1633 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1634 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1635 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1636 pipe_ctx->dlg_regs.vratio_prefetch,
1637 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1638 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1639 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1640 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1641 );
1642
1643 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1644 "\ndst_y_per_meta_row_nom_l: %d, \n"
1645 "refcyc_per_meta_chunk_nom_l: %d, \n"
1646 "refcyc_per_line_delivery_pre_l: %d, \n"
1647 "refcyc_per_line_delivery_l: %d, \n"
1648 "vratio_prefetch_c: %d, \n"
1649 "refcyc_per_pte_group_vblank_c: %d, \n"
1650 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1651 "dst_y_per_pte_row_nom_c: %d, \n"
1652 "refcyc_per_pte_group_nom_c: %d, \n"
1653 "dst_y_per_meta_row_nom_c: %d, \n"
1654 "refcyc_per_meta_chunk_nom_c: %d, \n"
1655 "refcyc_per_line_delivery_pre_c: %d, \n"
1656 "refcyc_per_line_delivery_c: %d \n"
1657 "========================================================\n",
1658 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1659 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1660 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1661 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1662 pipe_ctx->dlg_regs.vratio_prefetch_c,
1663 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1664 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1665 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1666 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1667 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1668 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1669 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1670 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1671 );
1672
1673 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1674 "\n============== DML RQ Output parameters [%d] ==============\n"
1675 "chunk_size: %d \n"
1676 "min_chunk_size: %d \n"
1677 "meta_chunk_size: %d \n"
1678 "min_meta_chunk_size: %d \n"
1679 "dpte_group_size: %d \n"
1680 "mpte_group_size: %d \n"
1681 "swath_height: %d \n"
1682 "pte_row_height_linear: %d \n"
1683 "========================================================\n",
1684 pipe_ctx->pipe_idx,
1685 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1686 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1687 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1688 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1689 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1690 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1691 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1692 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1693 );
1694}
1695
70ccab60
HW		 1696static void dcn10_power_on_fe(
1697 struct core_dc *dc,
1698 struct pipe_ctx *pipe_ctx,
1699 struct validate_context *context)
1700{
e12cfcb1 1701 struct dc_surface *dc_surface = pipe_ctx->surface;
184debdb 1702 struct dce_hwseq *hws = dc->hwseq;
70ccab60 1703
184debdb 1704 power_on_plane(dc->hwseq,
cfe4645e 1705 pipe_ctx->pipe_idx);
70ccab60 1706
c9742685 1707 /* enable DCFCLK current DCHUB */
d21becbe
TC		 1708 REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1709 HUBP_CLOCK_ENABLE, 1);
1710
1711 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1712 REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst],
1713 OPP_PIPE_CLOCK_EN, 1);
51666631 1714 /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
c9742685
DL		 1715
1716 if (dc_surface) {
1717 dm_logger_write(dc->ctx->logger, LOG_DC,
1718 "Pipe:%d 0x%x: addr hi:0x%x, "
1719 "addr low:0x%x, "
1720 "src: %d, %d, %d,"
1721 " %d; dst: %d, %d, %d, %d;\n",
70ccab60 1722 pipe_ctx->pipe_idx,
c9742685
DL		 1723 dc_surface,
1724 dc_surface->address.grph.addr.high_part,
1725 dc_surface->address.grph.addr.low_part,
1726 dc_surface->src_rect.x,
1727 dc_surface->src_rect.y,
1728 dc_surface->src_rect.width,
1729 dc_surface->src_rect.height,
1730 dc_surface->dst_rect.x,
1731 dc_surface->dst_rect.y,
1732 dc_surface->dst_rect.width,
1733 dc_surface->dst_rect.height);
1734
1735 dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
1736 "Pipe %d: width, height, x, y\n"
1737 "viewport:%d, %d, %d, %d\n"
1738 "recout: %d, %d, %d, %d\n",
1739 pipe_ctx->pipe_idx,
1740 pipe_ctx->scl_data.viewport.width,
1741 pipe_ctx->scl_data.viewport.height,
1742 pipe_ctx->scl_data.viewport.x,
1743 pipe_ctx->scl_data.viewport.y,
1744 pipe_ctx->scl_data.recout.width,
1745 pipe_ctx->scl_data.recout.height,
1746 pipe_ctx->scl_data.recout.x,
1747 pipe_ctx->scl_data.recout.y);
1748 print_rq_dlg_ttu(dc, pipe_ctx);
70ccab60 1749 }
70ccab60
HW		 1750}
1751
1752static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1753{
1754 struct xfm_grph_csc_adjustment adjust;
1755 memset(&adjust, 0, sizeof(adjust));
1756 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1757
1758
1759 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
1760 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1761 adjust.temperature_matrix[0] =
1762 pipe_ctx->stream->
1763 public.gamut_remap_matrix.matrix[0];
1764 adjust.temperature_matrix[1] =
1765 pipe_ctx->stream->
1766 public.gamut_remap_matrix.matrix[1];
1767 adjust.temperature_matrix[2] =
1768 pipe_ctx->stream->
1769 public.gamut_remap_matrix.matrix[2];
1770 adjust.temperature_matrix[3] =
1771 pipe_ctx->stream->
1772 public.gamut_remap_matrix.matrix[4];
1773 adjust.temperature_matrix[4] =
1774 pipe_ctx->stream->
1775 public.gamut_remap_matrix.matrix[5];
1776 adjust.temperature_matrix[5] =
1777 pipe_ctx->stream->
1778 public.gamut_remap_matrix.matrix[6];
1779 adjust.temperature_matrix[6] =
1780 pipe_ctx->stream->
1781 public.gamut_remap_matrix.matrix[8];
1782 adjust.temperature_matrix[7] =
1783 pipe_ctx->stream->
1784 public.gamut_remap_matrix.matrix[9];
1785 adjust.temperature_matrix[8] =
1786 pipe_ctx->stream->
1787 public.gamut_remap_matrix.matrix[10];
1788 }
1789
1790 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
1791}
1792
abe07e80
YHL		 1793
1794static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1795 enum dc_color_space colorspace,
1796 uint16_t *matrix)
1797{
1798 int i;
1799 struct out_csc_color_matrix tbl_entry;
1800
1801 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
1802 == true) {
1803 enum dc_color_space color_space =
1804 pipe_ctx->stream->public.output_color_space;
1805
1806 //uint16_t matrix[12];
1807 for (i = 0; i < 12; i++)
1808 tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i];
1809
1810 tbl_entry.color_space = color_space;
1811 //tbl_entry.regval = matrix;
f4d5abf5 1812 pipe_ctx->xfm->funcs->opp_set_csc_adjustment(pipe_ctx->xfm, &tbl_entry);
abe07e80
YHL		 1813 }
1814}
4b28b76b
DL		 1815static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1816{
e12cfcb1 1817 if (pipe_ctx->surface->visible)
4b28b76b
DL		 1818 return true;
1819 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1820 return true;
1821 return false;
1822}
1823
1824static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1825{
e12cfcb1 1826 if (pipe_ctx->surface->visible)
4b28b76b
DL		 1827 return true;
1828 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1829 return true;
1830 return false;
1831}
1832
1833static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1834{
e12cfcb1 1835 if (pipe_ctx->surface->visible)
4b28b76b
DL		 1836 return true;
1837 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1838 return true;
1839 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1840 return true;
1841 return false;
1842}
1843
ad327346
DL		 1844static bool is_rgb_cspace(enum dc_color_space output_color_space)
1845{
1846 switch (output_color_space) {
1847 case COLOR_SPACE_SRGB:
1848 case COLOR_SPACE_SRGB_LIMITED:
1849 case COLOR_SPACE_2020_RGB_FULLRANGE:
1850 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1851 case COLOR_SPACE_ADOBERGB:
1852 return true;
1853 case COLOR_SPACE_YCBCR601:
1854 case COLOR_SPACE_YCBCR709:
1855 case COLOR_SPACE_YCBCR601_LIMITED:
1856 case COLOR_SPACE_YCBCR709_LIMITED:
1857 case COLOR_SPACE_2020_YCBCR:
1858 return false;
1859 default:
1860 /* Add a case to switch */
1861 BREAK_TO_DEBUGGER();
1862 return false;
1863 }
1864}
1865
87449a90
AK		 1866static void dcn10_get_surface_visual_confirm_color(
1867 const struct pipe_ctx *pipe_ctx,
1868 struct tg_color *color)
1869{
1870 uint32_t color_value = MAX_TG_COLOR_VALUE;
1871
1872 switch (pipe_ctx->scl_data.format) {
1873 case PIXEL_FORMAT_ARGB8888:
1874 /* set boarder color to red */
1875 color->color_r_cr = color_value;
1876 break;
1877
1878 case PIXEL_FORMAT_ARGB2101010:
1879 /* set boarder color to blue */
1880 color->color_b_cb = color_value;
1881 break;
1882 case PIXEL_FORMAT_420BPP8:
1883 /* set boarder color to green */
1884 color->color_g_y = color_value;
1885 break;
1886 case PIXEL_FORMAT_420BPP10:
1887 /* set boarder color to yellow */
1888 color->color_g_y = color_value;
1889 color->color_r_cr = color_value;
1890 break;
1891 case PIXEL_FORMAT_FP16:
1892 /* set boarder color to white */
1893 color->color_r_cr = color_value;
1894 color->color_b_cb = color_value;
1895 color->color_g_y = color_value;
1896 break;
1897 default:
1898 break;
1899 }
1900}
1901
70ccab60
HW		 1902static void update_dchubp_dpp(
1903 struct core_dc *dc,
1904 struct pipe_ctx *pipe_ctx,
1905 struct validate_context *context)
1906{
184debdb 1907 struct dce_hwseq *hws = dc->hwseq;
70ccab60
HW		 1908 struct mem_input *mi = pipe_ctx->mi;
1909 struct input_pixel_processor *ipp = pipe_ctx->ipp;
e12cfcb1
HW		 1910 struct dc_surface *surface = pipe_ctx->surface;
1911 union plane_size size = surface->plane_size;
70ccab60 1912 struct default_adjustment ocsc = {0};
70ccab60 1913 struct tg_color black_color = {0};
f0558542 1914 struct mpcc_cfg mpcc_cfg;
e12cfcb1 1915 bool per_pixel_alpha = surface->per_pixel_alpha && pipe_ctx->bottom_pipe;
cbfd33fd 1916
ba326a91 1917 /* TODO: proper fix once fpga works */
70ccab60
HW		 1918 /* depends on DML calculation, DPP clock value may change dynamically */
1919 enable_dppclk(
184debdb 1920 dc->hwseq,
70ccab60
HW		 1921 pipe_ctx->pipe_idx,
1922 pipe_ctx->pix_clk_params.requested_pix_clk,
9037d802 1923 context->bw.dcn.calc_clk.dppclk_div);
c66a54dc
DL		 1924 dc->current_context->bw.dcn.cur_clk.dppclk_div =
1925 context->bw.dcn.calc_clk.dppclk_div;
1926 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
70ccab60 1927
184debdb
DL		 1928 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1929 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1930 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1931 */
1932 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->tg->inst);
70ccab60
HW		 1933
1934 update_plane_addr(dc, pipe_ctx);
1935
1936 mi->funcs->mem_input_setup(
1937 mi,
1938 &pipe_ctx->dlg_regs,
1939 &pipe_ctx->ttu_regs,
1940 &pipe_ctx->rq_regs,
1941 &pipe_ctx->pipe_dlg_param);
1942
1943 size.grph.surface_size = pipe_ctx->scl_data.viewport;
1944
1945 if (dc->public.config.gpu_vm_support)
1946 mi->funcs->mem_input_program_pte_vm(
1947 pipe_ctx->mi,
e12cfcb1
HW		 1948 surface->format,
1949 &surface->tiling_info,
1950 surface->rotation);
70ccab60
HW		 1951
1952 ipp->funcs->ipp_setup(ipp,
e12cfcb1 1953 surface->format,
70ccab60
HW		 1954 1,
1955 IPP_OUTPUT_FORMAT_12_BIT_FIX);
1956
ba326a91 1957 pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha;
f0558542
DL		 1958 mpcc_cfg.top_dpp_id = pipe_ctx->pipe_idx;
1959 if (pipe_ctx->bottom_pipe)
1960 mpcc_cfg.bot_mpcc_id = pipe_ctx->bottom_pipe->mpcc->inst;
1961 else
1962 mpcc_cfg.bot_mpcc_id = 0xf;
cfe4645e
DL		 1963 mpcc_cfg.opp_id = pipe_ctx->tg->inst;
1964 mpcc_cfg.top_of_tree = pipe_ctx->pipe_idx == pipe_ctx->tg->inst;
f0558542 1965 mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
ad327346
DL		 1966 /* DCN1.0 has output CM before MPC which seems to screw with
1967 * pre-multiplied alpha.
1968 */
1969 mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
1970 pipe_ctx->stream->public.output_color_space)
1971 && per_pixel_alpha;
f0558542 1972 pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg);
cbfd33fd 1973
87449a90
AK		 1974 if (dc->public.debug.surface_visual_confirm) {
1975 dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color);
1976 } else {
1977 color_space_to_black_color(
1978 dc, pipe_ctx->stream->public.output_color_space,
1979 &black_color);
1980 }
f0558542 1981 pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color);
70ccab60
HW		 1982
1983 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1984 /* scaler configuration */
1985 pipe_ctx->xfm->funcs->transform_set_scaler(
1986 pipe_ctx->xfm, &pipe_ctx->scl_data);
4bd3ae5f
VP		 1987 mi->funcs->mem_program_viewport(mi,
1988 &pipe_ctx->scl_data.viewport, &pipe_ctx->scl_data.viewport_c);
70ccab60
HW		 1989
1990 /*gamut remap*/
1991 program_gamut_remap(pipe_ctx);
1992
1993 /*TODO add adjustments parameters*/
1994 ocsc.out_color_space = pipe_ctx->stream->public.output_color_space;
7db90a6b 1995 pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc);
70ccab60
HW		 1996
1997 mi->funcs->mem_input_program_surface_config(
1998 mi,
e12cfcb1
HW		 1999 surface->format,
2000 &surface->tiling_info,
70ccab60 2001 &size,
e12cfcb1
HW		 2002 surface->rotation,
2003 &surface->dcc,
2004 surface->horizontal_mirror);
70ccab60 2005
4b28b76b 2006 mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
70ccab60
HW		 2007}
2008
2009static void program_all_pipe_in_tree(
2010 struct core_dc *dc,
2011 struct pipe_ctx *pipe_ctx,
2012 struct validate_context *context)
2013{
2014 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
2015
1a2c82a2 2016 if (pipe_ctx->top_pipe == NULL) {
70ccab60
HW		 2017
2018 /* lock otg_master_update to process all pipes associated with
2019 * this OTG. this is done only one time.
2020 */
1a2c82a2 2021 /* watermark is for all pipes */
08b16886 2022 program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
2b13d7d3
TC		 2023
2024 if (dc->public.debug.sanity_checks) {
2025 /* pstate stuck check after watermark update */
2026 verify_allow_pstate_change_high(dc->hwseq);
2027 }
2028
cfe4645e 2029 pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
cbfd33fd 2030
70ccab60
HW		 2031 pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2032 pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2033 pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2034 pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2035 pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
cbfd33fd 2036
70ccab60
HW		 2037 pipe_ctx->tg->funcs->program_global_sync(
2038 pipe_ctx->tg);
4b28b76b 2039 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
1a2c82a2 2040 }
cbfd33fd 2041
46239f73 2042 if (pipe_ctx->surface != NULL) {
1a2c82a2 2043 dcn10_power_on_fe(dc, pipe_ctx, context);
70ccab60
HW		 2044 update_dchubp_dpp(dc, pipe_ctx, context);
2045 }
2046
2b13d7d3
TC		 2047 if (dc->public.debug.sanity_checks) {
2048 /* pstate stuck check after each pipe is programmed */
2049 verify_allow_pstate_change_high(dc->hwseq);
2050 }
2051
70ccab60
HW		 2052 if (pipe_ctx->bottom_pipe != NULL)
2053 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2054}
2055
2056static void dcn10_pplib_apply_display_requirements(
2057 struct core_dc *dc,
2058 struct validate_context *context)
2059{
2060 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2061
2062 pp_display_cfg->all_displays_in_sync = false;/*todo*/
2063 pp_display_cfg->nb_pstate_switch_disable = false;
c66a54dc
DL		 2064 pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2065 pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
2066 pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2067 pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
70ccab60 2068 pp_display_cfg->avail_mclk_switch_time_us =
c66a54dc 2069 context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
70ccab60 2070 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
c66a54dc
DL		 2071 context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
2072 pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2073 pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
70ccab60
HW		 2074 dce110_fill_display_configs(context, pp_display_cfg);
2075
2076 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2077 struct dm_pp_display_configuration)) != 0)
2078 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2079
2080 dc->prev_display_config = *pp_display_cfg;
2081}
2082
2083static void dcn10_apply_ctx_for_surface(
2084 struct core_dc *dc,
e12cfcb1 2085 const struct dc_surface *surface,
70ccab60
HW		 2086 struct validate_context *context)
2087{
7f10f3c2 2088 int i, be_idx;
70ccab60 2089
2b13d7d3
TC		 2090 if (dc->public.debug.sanity_checks)
2091 verify_allow_pstate_change_high(dc->hwseq);
2092
7f10f3c2
TC		 2093 if (!surface)
2094 return;
2095
2096 for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++)
2097 if (surface == context->res_ctx.pipe_ctx[be_idx].surface)
2098 break;
2099
cfe4645e 2100 /* reset unused mpcc */
71a2f23e 2101 for (i = 0; i < dc->res_pool->pipe_count; i++) {
cfe4645e
DL		 2102 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2103 struct pipe_ctx *old_pipe_ctx =
2104 &dc->current_context->res_ctx.pipe_ctx[i];
7f10f3c2
TC		 2105
2106 if (!pipe_ctx->surface && !old_pipe_ctx->surface)
2107 continue;
2108
4bdbab3e
EY		 2109 /*
2110 * Powergate reused pipes that are not powergated
2111 * fairly hacky right now, using opp_id as indicator
2112 */
7f10f3c2 2113
4bdbab3e 2114 if (pipe_ctx->surface && !old_pipe_ctx->surface) {
aa985070 2115 if (pipe_ctx->mpcc->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) {
4bdbab3e 2116 dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
aa985070
EY		 2117 /*
2118 * power down fe will unlock when calling reset, need
2119 * to lock it back here. Messy, need rework.
2120 */
2121 pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
2122 }
4bdbab3e 2123 }
cfe4645e 2124
7f10f3c2 2125
cfe4645e
DL		 2126 if ((!pipe_ctx->surface && old_pipe_ctx->surface)
2127 || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
2128 struct mpcc_cfg mpcc_cfg;
1674d35b 2129 int opp_id_cached = old_pipe_ctx->mpcc->opp_id;
cfe4645e 2130
7f10f3c2
TC		 2131 if (old_pipe_ctx->tg->inst != be_idx)
2132 continue;
2133
71a2f23e
EY		 2134 if (!old_pipe_ctx->top_pipe) {
2135 ASSERT(0);
2136 continue;
2137 }
2138
4bdbab3e 2139 /* reset mpc */
1674d35b 2140 mpcc_cfg.opp_id = 0xf;
cfe4645e
DL		 2141 mpcc_cfg.top_dpp_id = 0xf;
2142 mpcc_cfg.bot_mpcc_id = 0xf;
2143 mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
2144 old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg);
87480687 2145 old_pipe_ctx->top_pipe->opp->mpcc_disconnect_pending[old_pipe_ctx->mpcc->inst] = true;
2b13d7d3 2146
6be425f3
EY		 2147 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2148 "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
2149 old_pipe_ctx->mpcc->inst);*/
2150
2b13d7d3
TC		 2151 if (dc->public.debug.sanity_checks)
2152 verify_allow_pstate_change_high(dc->hwseq);
2153
1674d35b
EY		 2154 /*
2155 * the mpcc is the only thing that keeps track of the mpcc
2156 * mapping for reset front end right now. Might need some
2157 * rework.
2158 */
2159 old_pipe_ctx->mpcc->opp_id = opp_id_cached;
cfe4645e
DL		 2160
2161 old_pipe_ctx->top_pipe = NULL;
2162 old_pipe_ctx->bottom_pipe = NULL;
2163 old_pipe_ctx->surface = NULL;
2164
2165 dm_logger_write(dc->ctx->logger, LOG_DC,
2166 "Reset mpcc for pipe %d\n",
2167 old_pipe_ctx->pipe_idx);
2168 }
71a2f23e 2169 }
cfe4645e 2170
70ccab60
HW		 2171 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2172 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2173
cfe4645e 2174 if (pipe_ctx->surface != surface)
70ccab60
HW		 2175 continue;
2176
2177 /* looking for top pipe to program */
f0558542 2178 if (!pipe_ctx->top_pipe)
70ccab60
HW		 2179 program_all_pipe_in_tree(dc, pipe_ctx, context);
2180 }
2181
c9742685
DL		 2182 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2183 "\n============== Watermark parameters ==============\n"
2184 "a.urgent_ns: %d \n"
2185 "a.cstate_enter_plus_exit: %d \n"
2186 "a.cstate_exit: %d \n"
2187 "a.pstate_change: %d \n"
2188 "a.pte_meta_urgent: %d \n"
2189 "b.urgent_ns: %d \n"
2190 "b.cstate_enter_plus_exit: %d \n"
2191 "b.cstate_exit: %d \n"
2192 "b.pstate_change: %d \n"
2193 "b.pte_meta_urgent: %d \n",
2194 context->bw.dcn.watermarks.a.urgent_ns,
2195 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2196 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2197 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2198 context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2199 context->bw.dcn.watermarks.b.urgent_ns,
2200 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2201 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2202 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2203 context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2204 );
2205 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2206 "\nc.urgent_ns: %d \n"
2207 "c.cstate_enter_plus_exit: %d \n"
2208 "c.cstate_exit: %d \n"
2209 "c.pstate_change: %d \n"
2210 "c.pte_meta_urgent: %d \n"
2211 "d.urgent_ns: %d \n"
2212 "d.cstate_enter_plus_exit: %d \n"
2213 "d.cstate_exit: %d \n"
2214 "d.pstate_change: %d \n"
2215 "d.pte_meta_urgent: %d \n"
2216 "========================================================\n",
2217 context->bw.dcn.watermarks.c.urgent_ns,
2218 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2219 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2220 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2221 context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2222 context->bw.dcn.watermarks.d.urgent_ns,
2223 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2224 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2225 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2226 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2227 );
2b13d7d3
TC		 2228
2229 if (dc->public.debug.sanity_checks)
2230 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 2231}
2232
2233static void dcn10_set_bandwidth(
2234 struct core_dc *dc,
2235 struct validate_context *context,
2236 bool decrease_allowed)
2237{
2238 struct dm_pp_clock_for_voltage_req clock;
2239
2240 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2241 return;
2242
c66a54dc
DL		 2243 if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2244 > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
70ccab60
HW		 2245 dc->res_pool->display_clock->funcs->set_clock(
2246 dc->res_pool->display_clock,
9037d802 2247 context->bw.dcn.calc_clk.dispclk_khz);
c66a54dc
DL		 2248 dc->current_context->bw.dcn.cur_clk.dispclk_khz =
2249 context->bw.dcn.calc_clk.dispclk_khz;
70ccab60 2250 }
c66a54dc
DL		 2251 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2252 > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
70ccab60 2253 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
9037d802 2254 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
70ccab60 2255 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
c66a54dc
DL		 2256 dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
2257 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
70ccab60 2258 }
c66a54dc
DL		 2259 if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2260 > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
70ccab60 2261 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
9037d802 2262 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
70ccab60 2263 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
9037d802 2264 dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
c66a54dc
DL		 2265 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
2266 }
2267 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2268 > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2269 dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2270 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2271 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2272 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2273 }
2274 /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2275 if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2276 < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) {
2277 dc->current_context->bw.dcn.calc_clk.dram_ccm_us =
2278 context->bw.dcn.calc_clk.dram_ccm_us;
2279 context->bw.dcn.cur_clk.dram_ccm_us =
2280 context->bw.dcn.calc_clk.dram_ccm_us;
2281 }
2282 if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2283 < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2284 dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us =
2285 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2286 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2287 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
70ccab60
HW		 2288 }
2289 dcn10_pplib_apply_display_requirements(dc, context);
2b13d7d3
TC		 2290
2291 /* need to fix this function. not doing the right thing here */
70ccab60
HW		 2292}
2293
70ccab60
HW		 2294static void set_drr(struct pipe_ctx **pipe_ctx,
2295 int num_pipes, int vmin, int vmax)
2296{
2297 int i = 0;
2298 struct drr_params params = {0};
2299
2300 params.vertical_total_max = vmax;
2301 params.vertical_total_min = vmin;
2302
2303 /* TODO: If multiple pipes are to be supported, you need
2304 * some GSL stuff
2305 */
2306 for (i = 0; i < num_pipes; i++) {
2307 pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
2308 }
2309}
2310
2311static void get_position(struct pipe_ctx **pipe_ctx,
2312 int num_pipes,
2313 struct crtc_position *position)
2314{
2315 int i = 0;
2316
2317 /* TODO: handle pipes > 1
2318 */
2319 for (i = 0; i < num_pipes; i++)
2320 pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
2321}
2322
2323static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2324 int num_pipes, const struct dc_static_screen_events *events)
2325{
2326 unsigned int i;
2327 unsigned int value = 0;
2328
2329 if (events->surface_update)
2330 value |= 0x80;
2331 if (events->cursor_update)
2332 value |= 0x2;
2333
2334 for (i = 0; i < num_pipes; i++)
2335 pipe_ctx[i]->tg->funcs->
2336 set_static_screen_control(pipe_ctx[i]->tg, value);
2337}
2338
2339static void set_plane_config(
2340 const struct core_dc *dc,
2341 struct pipe_ctx *pipe_ctx,
2342 struct resource_context *res_ctx)
2343{
2344 /* TODO */
2345 program_gamut_remap(pipe_ctx);
2346}
2347
4fac6da2
DL		 2348static void dcn10_config_stereo_parameters(
2349 struct core_stream *stream, struct crtc_stereo_flags *flags)
7f5c22d1
VP		 2350{
2351 enum view_3d_format view_format = stream->public.view_format;
2352 enum dc_timing_3d_format timing_3d_format =\
2353 stream->public.timing.timing_3d_format;
2354 bool non_stereo_timing = false;
2355
2356 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2357 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2358 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2359 non_stereo_timing = true;
2360
2361 if (non_stereo_timing == false &&
2362 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2363
2364 flags->PROGRAM_STEREO = 1;
2365 flags->PROGRAM_POLARITY = 1;
2366 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2367 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2368 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2369 enum display_dongle_type dongle = \
d0778ebf 2370 stream->sink->link->ddc->dongle_type;
7f5c22d1
VP		 2371 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2372 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2373 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2374 flags->DISABLE_STEREO_DP_SYNC = 1;
2375 }
2376 flags->RIGHT_EYE_POLARITY =\
2377 stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
2378 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2379 flags->FRAME_PACKED = 1;
2380 }
2381
2382 return;
2383}
2384
4fac6da2 2385static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
7f5c22d1
VP		 2386{
2387 struct crtc_stereo_flags flags = { 0 };
2388 struct core_stream *stream = pipe_ctx->stream;
2389
2390 dcn10_config_stereo_parameters(stream, &flags);
2391
2392 pipe_ctx->opp->funcs->opp_set_stereo_polarity(
2393 pipe_ctx->opp,
2394 flags.PROGRAM_STEREO == 1 ? true:false,
2395 stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
2396
2397 pipe_ctx->tg->funcs->program_stereo(
2398 pipe_ctx->tg,
2399 &stream->public.timing,
2400 &flags);
2401
7f5c22d1
VP		 2402 return;
2403}
2404
2248eb6b
TC		 2405
2406static void log_mpc_crc(struct core_dc *dc)
6d244be8
TC		 2407{
2408 struct dc_context *dc_ctx = dc->ctx;
51666631 2409 struct dce_hwseq *hws = dc->hwseq;
6d244be8 2410
51666631
DL		 2411 if (REG(MPC_CRC_RESULT_GB))
2412 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
2413 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
2414 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
2415 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
2416 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
2248eb6b
TC		 2417}
2418
2419static void dcn10_log_hw_state(struct core_dc *dc)
2420{
2421 struct dc_context *dc_ctx = dc->ctx;
2422 struct resource_pool *pool = dc->res_pool;
2423 int i;
2424
2425 DTN_INFO_BEGIN();
2426
2427 DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t"
2428 "mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t"
2429 "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
2430
2431 for (i = 0; i < pool->pipe_count; i++) {
2432 struct mem_input *mi = pool->mis[i];
2433 struct dcn_hubp_state s;
2434
2435 dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);
2436
2437 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t "
2438 "%d \t %d \t %d \t %d \t"
2439 "%d \t %d \t %d \n",
2440 i,
2441 s.pixel_format,
2442 s.inuse_addr_hi,
2443 s.viewport_width,
2444 s.viewport_height,
2445 s.rotation_angle,
2446 s.h_mirror_en,
2447 s.sw_mode,
2448 s.dcc_en,
2449 s.blank_en,
2450 s.ttu_disable,
2451 s.min_ttu_vblank,
2452 s.qos_level_low_wm,
2453 s.qos_level_high_wm);
2454 }
2455 DTN_INFO("\n");
2456
2457 log_mpc_crc(dc);
2458
2459 DTN_INFO_END();
6d244be8
TC		 2460}
2461
6be425f3
EY		 2462static void dcn10_wait_for_mpcc_disconnect(
2463 struct core_dc *dc,
2464 struct resource_pool *res_pool,
2465 struct pipe_ctx *pipe_ctx)
87480687
EY		 2466{
2467 int i;
87480687 2468
6be425f3
EY		 2469 if (!pipe_ctx->opp || !pipe_ctx->mpcc)
2470 return;
2471
2472 for (i = 0; i < MAX_PIPES; i++) {
87480687
EY		 2473 if (pipe_ctx->opp->mpcc_disconnect_pending[i]) {
2474 pipe_ctx->mpcc->funcs->wait_for_idle(res_pool->mpcc[i]);
2475 pipe_ctx->opp->mpcc_disconnect_pending[i] = false;
6be425f3
EY		 2476 res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true);
2477 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2478 "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2479 i);*/
87480687
EY		 2480 }
2481 }
6be425f3 2482
87480687
EY		 2483}
2484
4fac6da2
DL		 2485static bool dcn10_dummy_display_power_gating(
2486 struct core_dc *dc,
2487 uint8_t controller_id,
2488 struct dc_bios *dcb,
2b13d7d3
TC		 2489 enum pipe_gating_control power_gating)
2490{
2491 return true;
2492}
2493
2494void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2495{
e12cfcb1 2496 struct dc_surface *surface = pipe_ctx->surface;
2b13d7d3
TC		 2497 struct timing_generator *tg = pipe_ctx->tg;
2498
2499 if (surface->ctx->dc->debug.sanity_checks) {
2500 struct core_dc *dc = DC_TO_CORE(surface->ctx->dc);
2501
2502 verify_allow_pstate_change_high(dc->hwseq);
2503 }
2504
2505 if (surface == NULL)
2506 return;
2507
2508 surface->status.is_flip_pending =
2509 pipe_ctx->mi->funcs->mem_input_is_flip_pending(
2510 pipe_ctx->mi);
2511
2512 /* DCN we read INUSE address in MI, do we still need this wa? */
2513 if (surface->status.is_flip_pending &&
e12cfcb1 2514 !surface->visible) {
2b13d7d3
TC		 2515 pipe_ctx->mi->current_address =
2516 pipe_ctx->mi->request_address;
2517 BREAK_TO_DEBUGGER();
2518 }
2519
2520 surface->status.current_address = pipe_ctx->mi->current_address;
2521 if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2522 tg->funcs->is_stereo_left_eye) {
2523 surface->status.is_right_eye =
2524 !tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
2525 }
2526}
4fac6da2 2527
70ccab60 2528static const struct hw_sequencer_funcs dcn10_funcs = {
1bf56e62 2529 .program_gamut_remap = program_gamut_remap,
abe07e80 2530 .program_csc_matrix = program_csc_matrix,
b02c3b05 2531 .init_hw = dcn10_init_hw,
70ccab60
HW		 2532 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2533 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2534 .set_plane_config = set_plane_config,
2535 .update_plane_addr = update_plane_addr,
08b16886 2536 .update_dchub = dcn10_update_dchub,
2b13d7d3 2537 .update_pending_status = dcn10_update_pending_status,
70ccab60
HW		 2538 .set_input_transfer_func = dcn10_set_input_transfer_func,
2539 .set_output_transfer_func = dcn10_set_output_transfer_func,
2540 .power_down = dce110_power_down,
2541 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2542 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2543 .update_info_frame = dce110_update_info_frame,
2544 .enable_stream = dce110_enable_stream,
2545 .disable_stream = dce110_disable_stream,
2546 .unblank_stream = dce110_unblank_stream,
4fac6da2 2547 .enable_display_power_gating = dcn10_dummy_display_power_gating,
70ccab60
HW		 2548 .power_down_front_end = dcn10_power_down_fe,
2549 .power_on_front_end = dcn10_power_on_fe,
2550 .pipe_control_lock = dcn10_pipe_control_lock,
2551 .set_bandwidth = dcn10_set_bandwidth,
2552 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2553 .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2554 .set_drr = set_drr,
2555 .get_position = get_position,
7f5c22d1 2556 .set_static_screen_control = set_static_screen_control,
15e17335
CL		 2557 .setup_stereo = dcn10_setup_stereo,
2558 .set_avmute = dce110_set_avmute,
87480687
EY		 2559 .log_hw_state = dcn10_log_hw_state,
2560 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect
70ccab60
HW		 2561};
2562
2563
b02c3b05 2564void dcn10_hw_sequencer_construct(struct core_dc *dc)
70ccab60
HW		 2565{
2566 dc->hwss = dcn10_funcs;
70ccab60
HW		 2567}
2568
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