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drm/amd/display: Minor update to DML
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hw_sequencer.c
CommitLineData
70ccab60
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
70ccab60 27#include "core_types.h"
70ccab60 28#include "resource.h"
b02c3b05 29#include "custom_float.h"
70ccab60
HW		 30#include "dcn10_hw_sequencer.h"
31#include "dce110/dce110_hw_sequencer.h"
5aff86c1 32#include "dce/dce_hwseq.h"
70ccab60 33#include "abm.h"
214435ff 34#include "dcn10/dcn10_timing_generator.h"
587cdfe9
VP		 35#include "dcn10/dcn10_dpp.h"
36#include "dcn10/dcn10_mpc.h"
70ccab60
HW		 37#include "timing_generator.h"
38#include "opp.h"
39#include "ipp.h"
b02c3b05 40#include "mpc.h"
184debdb 41#include "reg_helper.h"
a6def445 42#include "custom_float.h"
86be9a04 43#include "dcn10_hubp.h"
70ccab60 44
184debdb
DL		 45#define CTX \
46 hws->ctx
47#define REG(reg)\
48 hws->regs->reg
70ccab60 49
184debdb
DL		 50#undef FN
51#define FN(reg_name, field_name) \
52 hws->shifts->field_name, hws->masks->field_name
70ccab60 53
fb3466a4 54static void log_mpc_crc(struct dc *dc)
71395011
TC		 55{
56 struct dc_context *dc_ctx = dc->ctx;
57 struct dce_hwseq *hws = dc->hwseq;
58
59 if (REG(MPC_CRC_RESULT_GB))
60 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
61 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
62 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
63 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
64 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
65}
66
eb4e33b7
TC		 67void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
68{
69 static const uint32_t ref_clk_mhz = 48;
70 static const unsigned int frac = 10;
71 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
72
73 DTN_INFO("%d.%d \t ",
74 us_x10 / frac,
75 us_x10 % frac);
76}
77
78#define DTN_INFO_MICRO_SEC(ref_cycle) \
79 print_microsec(dc_ctx, ref_cycle)
80
233dcd20
TC		 81struct dcn_hubbub_wm_set {
82 uint32_t wm_set;
83 uint32_t data_urgent;
84 uint32_t pte_meta_urgent;
85 uint32_t sr_enter;
86 uint32_t sr_exit;
87 uint32_t dram_clk_chanage;
88};
89
90struct dcn_hubbub_wm {
91 struct dcn_hubbub_wm_set sets[4];
92};
93
94static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,
95 struct dcn_hubbub_wm *wm)
96{
97 struct dcn_hubbub_wm_set *s;
98
99 s = &wm->sets[0];
100 s->wm_set = 0;
101 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
102 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
103 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
104 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
105 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
106
107 s = &wm->sets[1];
108 s->wm_set = 1;
109 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
110 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
111 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
112 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
113 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
114
115 s = &wm->sets[2];
116 s->wm_set = 2;
117 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
118 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
119 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
120 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
121 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
122
123 s = &wm->sets[3];
124 s->wm_set = 3;
125 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
126 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
127 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
128 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
129 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
130}
131
fb3466a4 132static void dcn10_log_hubbub_state(struct dc *dc)
233dcd20
TC		 133{
134 struct dc_context *dc_ctx = dc->ctx;
135 struct dcn_hubbub_wm wm;
136 int i;
137
138 dcn10_hubbub_wm_read_state(dc->hwseq, &wm);
139
140 DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
141 "sr_enter \t sr_exit \t dram_clk_change \n");
142
143 for (i = 0; i < 4; i++) {
144 struct dcn_hubbub_wm_set *s;
145
146 s = &wm.sets[i];
147 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
148 DTN_INFO_MICRO_SEC(s->data_urgent);
149 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
150 DTN_INFO_MICRO_SEC(s->sr_enter);
151 DTN_INFO_MICRO_SEC(s->sr_exit);
152 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
153 DTN_INFO("\n");
154 }
155
156 DTN_INFO("\n");
157}
158
fb3466a4 159static void dcn10_log_hw_state(struct dc *dc)
71395011
TC		 160{
161 struct dc_context *dc_ctx = dc->ctx;
162 struct resource_pool *pool = dc->res_pool;
163 int i;
164
165 DTN_INFO_BEGIN();
166
233dcd20
TC		 167 dcn10_log_hubbub_state(dc);
168
eb4e33b7
TC		 169 DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
170 "rotation \t mirror \t sw_mode \t "
171 "dcc_en \t blank_en \t ttu_dis \t underflow \t "
71395011
TC		 172 "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
173
174 for (i = 0; i < pool->pipe_count; i++) {
8feabd03 175 struct hubp *hubp = pool->hubps[i];
71395011
TC		 176 struct dcn_hubp_state s;
177
8feabd03 178 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
71395011 179
eb4e33b7
TC		 180 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
181 "%xh \t %xh \t %xh \t "
182 "%d \t %d \t %d \t %xh \t",
71395011
TC		 183 i,
184 s.pixel_format,
185 s.inuse_addr_hi,
186 s.viewport_width,
187 s.viewport_height,
188 s.rotation_angle,
189 s.h_mirror_en,
190 s.sw_mode,
191 s.dcc_en,
192 s.blank_en,
193 s.ttu_disable,
eb4e33b7
TC		 194 s.underflow_status);
195 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
196 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
197 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
198 DTN_INFO("\n");
71395011
TC		 199 }
200 DTN_INFO("\n");
201
214435ff
CM		 202 DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
203 "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
204
205 for (i = 0; i < pool->pipe_count; i++) {
206 struct timing_generator *tg = pool->timing_generators[i];
6f54d0b1 207 struct dcn_otg_state s = {0};
214435ff
CM		 208
209 tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
210
6f54d0b1
LT		 211 //only print if OTG master is enabled
212 if ((s.otg_enabled & 1) == 0)
213 continue;
214
214435ff
CM		 215 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
216 "%d \t %d \t %d \t %d \t %d \t %d \t "
217 "%d \t %d \t %d \t %d \t %d \t ",
218 i,
219 s.v_blank_start,
220 s.v_blank_end,
221 s.v_sync_a_start,
222 s.v_sync_a_end,
223 s.v_sync_a_pol,
224 s.v_total_max,
225 s.v_total_min,
226 s.h_blank_start,
227 s.h_blank_end,
228 s.h_sync_a_start,
229 s.h_sync_a_end,
230 s.h_sync_a_pol,
231 s.h_total,
232 s.v_total,
233 s.underflow_occurred_status);
234 DTN_INFO("\n");
235 }
236 DTN_INFO("\n");
237
71395011
TC		 238 log_mpc_crc(dc);
239
240 DTN_INFO_END();
241}
2b13d7d3
TC		 242
243static void verify_allow_pstate_change_high(
244 struct dce_hwseq *hws)
245{
246 /* pstate latency is ~20us so if we wait over 40us and pstate allow
247 * still not asserted, we are probably stuck and going to hang
ff79cbdc
BL		 248 *
249 * TODO: Figure out why it takes ~100us on linux
250 * pstate takes around ~100us on linux. Unknown currently as to
251 * why it takes that long on linux
2b13d7d3 252 */
ff79cbdc
BL		 253 static unsigned int pstate_wait_timeout_us = 200;
254 static unsigned int pstate_wait_expected_timeout_us = 40;
2b13d7d3
TC		 255 static unsigned int max_sampled_pstate_wait_us; /* data collection */
256 static bool forced_pstate_allow; /* help with revert wa */
08b8ccfb 257 static bool should_log_hw_state; /* prevent hw state log by default */
2b13d7d3
TC		 258
259 unsigned int debug_index = 0x7;
260 unsigned int debug_data;
2b13d7d3
TC		 261 unsigned int i;
262
263 if (forced_pstate_allow) {
264 /* we hacked to force pstate allow to prevent hang last time
265 * we verify_allow_pstate_change_high. so disable force
266 * here so we can check status
267 */
458e9d03
BL		 268 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
269 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
270 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
2b13d7d3
TC		 271 forced_pstate_allow = false;
272 }
273
274 /* description "3-0: Pipe0 cursor0 QOS
275 * 7-4: Pipe1 cursor0 QOS
276 * 11-8: Pipe2 cursor0 QOS
277 * 15-12: Pipe3 cursor0 QOS
278 * 16: Pipe0 Plane0 Allow Pstate Change
279 * 17: Pipe1 Plane0 Allow Pstate Change
280 * 18: Pipe2 Plane0 Allow Pstate Change
281 * 19: Pipe3 Plane0 Allow Pstate Change
282 * 20: Pipe0 Plane1 Allow Pstate Change
283 * 21: Pipe1 Plane1 Allow Pstate Change
284 * 22: Pipe2 Plane1 Allow Pstate Change
285 * 23: Pipe3 Plane1 Allow Pstate Change
286 * 24: Pipe0 cursor0 Allow Pstate Change
287 * 25: Pipe1 cursor0 Allow Pstate Change
288 * 26: Pipe2 cursor0 Allow Pstate Change
289 * 27: Pipe3 cursor0 Allow Pstate Change
290 * 28: WB0 Allow Pstate Change
291 * 29: WB1 Allow Pstate Change
292 * 30: Arbiter's allow_pstate_change
293 * 31: SOC pstate change request
294 */
295
296 REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
297
298 for (i = 0; i < pstate_wait_timeout_us; i++) {
299 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
300
ff79cbdc
BL		 301 if (debug_data & (1 << 30)) {
302
303 if (i > pstate_wait_expected_timeout_us)
304 dm_logger_write(hws->ctx->logger, LOG_WARNING,
e66a5755 305 "pstate took longer than expected ~%dus\n",
ff79cbdc 306 i);
2b13d7d3 307
ff79cbdc
BL		 308 return;
309 }
2b13d7d3
TC		 310 if (max_sampled_pstate_wait_us < i)
311 max_sampled_pstate_wait_us = i;
312
313 udelay(1);
314 }
315
316 /* force pstate allow to prevent system hang
317 * and break to debugger to investigate
318 */
458e9d03
BL		 319 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
320 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
321 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
2b13d7d3 322 forced_pstate_allow = true;
71395011 323
08b8ccfb 324 if (should_log_hw_state) {
fb3466a4 325 dcn10_log_hw_state(hws->ctx->dc);
08b8ccfb 326 }
71395011 327
ff79cbdc 328 dm_logger_write(hws->ctx->logger, LOG_WARNING,
e66a5755 329 "pstate TEST_DEBUG_DATA: 0x%X\n",
ff79cbdc 330 debug_data);
2b13d7d3
TC		 331 BREAK_TO_DEBUGGER();
332}
333
70ccab60 334static void enable_dppclk(
184debdb 335 struct dce_hwseq *hws,
70ccab60
HW		 336 uint8_t plane_id,
337 uint32_t requested_pix_clk,
338 bool dppclk_div)
339{
184debdb 340 dm_logger_write(hws->ctx->logger, LOG_SURFACE,
70ccab60
HW		 341 "dppclk_rate_control for pipe %d programed to %d\n",
342 plane_id,
343 dppclk_div);
344
4e5095ca 345 if (hws->shifts->DPPCLK_RATE_CONTROL)
184debdb 346 REG_UPDATE_2(DPP_CONTROL[plane_id],
4e5095ca 347 DPPCLK_RATE_CONTROL, dppclk_div,
70ccab60 348 DPP_CLOCK_ENABLE, 1);
4e5095ca
DL		 349 else
350 REG_UPDATE(DPP_CONTROL[plane_id],
70ccab60 351 DPP_CLOCK_ENABLE, 1);
70ccab60
HW		 352}
353
354static void enable_power_gating_plane(
184debdb 355 struct dce_hwseq *hws,
70ccab60
HW		 356 bool enable)
357{
70ccab60
HW		 358 bool force_on = 1; /* disable power gating */
359
360 if (enable)
361 force_on = 0;
362
363 /* DCHUBP0/1/2/3 */
184debdb
DL		 364 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
365 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
366 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
367 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
70ccab60
HW		 368
369 /* DPP0/1/2/3 */
184debdb
DL		 370 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
371 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
372 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
373 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
70ccab60
HW		 374}
375
0a87425a
TC		 376static void disable_vga(
377 struct dce_hwseq *hws)
378{
379 REG_WRITE(D1VGA_CONTROL, 0);
380 REG_WRITE(D2VGA_CONTROL, 0);
381 REG_WRITE(D3VGA_CONTROL, 0);
382 REG_WRITE(D4VGA_CONTROL, 0);
383}
384
70ccab60 385static void dpp_pg_control(
184debdb 386 struct dce_hwseq *hws,
70ccab60
HW		 387 unsigned int dpp_inst,
388 bool power_on)
389{
70ccab60
HW		 390 uint32_t power_gate = power_on ? 0 : 1;
391 uint32_t pwr_status = power_on ? 0 : 2;
392
184debdb 393 if (hws->ctx->dc->debug.disable_dpp_power_gate)
70ccab60
HW		 394 return;
395
396 switch (dpp_inst) {
397 case 0: /* DPP0 */
184debdb 398 REG_UPDATE(DOMAIN1_PG_CONFIG,
70ccab60
HW		 399 DOMAIN1_POWER_GATE, power_gate);
400
184debdb 401 REG_WAIT(DOMAIN1_PG_STATUS,
8a5d8245
TC		 402 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
403 1, 1000);
70ccab60
HW		 404 break;
405 case 1: /* DPP1 */
184debdb 406 REG_UPDATE(DOMAIN3_PG_CONFIG,
70ccab60
HW		 407 DOMAIN3_POWER_GATE, power_gate);
408
184debdb 409 REG_WAIT(DOMAIN3_PG_STATUS,
8a5d8245
TC		 410 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
411 1, 1000);
70ccab60
HW		 412 break;
413 case 2: /* DPP2 */
184debdb 414 REG_UPDATE(DOMAIN5_PG_CONFIG,
70ccab60
HW		 415 DOMAIN5_POWER_GATE, power_gate);
416
184debdb 417 REG_WAIT(DOMAIN5_PG_STATUS,
8a5d8245
TC		 418 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
419 1, 1000);
70ccab60
HW		 420 break;
421 case 3: /* DPP3 */
184debdb 422 REG_UPDATE(DOMAIN7_PG_CONFIG,
70ccab60
HW		 423 DOMAIN7_POWER_GATE, power_gate);
424
184debdb 425 REG_WAIT(DOMAIN7_PG_STATUS,
8a5d8245
TC		 426 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
427 1, 1000);
70ccab60
HW		 428 break;
429 default:
430 BREAK_TO_DEBUGGER();
431 break;
432 }
433}
434
08b16886
ZF		 435static uint32_t convert_and_clamp(
436 uint32_t wm_ns,
437 uint32_t refclk_mhz,
438 uint32_t clamp_value)
439{
440 uint32_t ret_val = 0;
441 ret_val = wm_ns * refclk_mhz;
442 ret_val /= 1000;
443
444 if (ret_val > clamp_value)
445 ret_val = clamp_value;
446
447 return ret_val;
448}
449
450static void program_watermarks(
451 struct dce_hwseq *hws,
452 struct dcn_watermark_set *watermarks,
453 unsigned int refclk_mhz)
454{
455 uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
456 /*
457 * Need to clamp to max of the register values (i.e. no wrap)
458 * for dcn1, all wm registers are 21-bit wide
459 */
460 uint32_t prog_wm_value;
461
cbb4d72e
YS		 462 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
463 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
464
08b16886
ZF		 465 /* Repeat for water mark set A, B, C and D. */
466 /* clock state A */
467 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
468 refclk_mhz, 0x1fffff);
469 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
470
215a6f05 471 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 472 "URGENCY_WATERMARK_A calculated =%d\n"
473 "HW register value = 0x%x\n",
474 watermarks->a.urgent_ns, prog_wm_value);
475
476 prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
477 refclk_mhz, 0x1fffff);
478 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
215a6f05 479 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 480 "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
481 "HW register value = 0x%x\n",
482 watermarks->a.pte_meta_urgent_ns, prog_wm_value);
483
9a5bcd47
EB		 484 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
485 prog_wm_value = convert_and_clamp(
486 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
487 refclk_mhz, 0x1fffff);
488 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
489 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
490 "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
491 "HW register value = 0x%x\n",
492 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
493
494
495 prog_wm_value = convert_and_clamp(
496 watermarks->a.cstate_pstate.cstate_exit_ns,
497 refclk_mhz, 0x1fffff);
498 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
499 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
500 "SR_EXIT_WATERMARK_A calculated =%d\n"
501 "HW register value = 0x%x\n",
502 watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
503 }
08b16886
ZF		 504
505 prog_wm_value = convert_and_clamp(
506 watermarks->a.cstate_pstate.pstate_change_ns,
507 refclk_mhz, 0x1fffff);
508 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
215a6f05 509 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 510 "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
511 "HW register value = 0x%x\n\n",
512 watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
513
514
515 /* clock state B */
516 prog_wm_value = convert_and_clamp(
517 watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
518 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
215a6f05 519 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 520 "URGENCY_WATERMARK_B calculated =%d\n"
521 "HW register value = 0x%x\n",
522 watermarks->b.urgent_ns, prog_wm_value);
523
524
525 prog_wm_value = convert_and_clamp(
526 watermarks->b.pte_meta_urgent_ns,
527 refclk_mhz, 0x1fffff);
528 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
215a6f05 529 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 530 "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
531 "HW register value = 0x%x\n",
532 watermarks->b.pte_meta_urgent_ns, prog_wm_value);
533
534
9a5bcd47
EB		 535 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
536 prog_wm_value = convert_and_clamp(
537 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
538 refclk_mhz, 0x1fffff);
539 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
540 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
541 "SR_ENTER_WATERMARK_B calculated =%d\n"
542 "HW register value = 0x%x\n",
543 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
544
545
546 prog_wm_value = convert_and_clamp(
547 watermarks->b.cstate_pstate.cstate_exit_ns,
548 refclk_mhz, 0x1fffff);
549 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
550 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
551 "SR_EXIT_WATERMARK_B calculated =%d\n"
552 "HW register value = 0x%x\n",
553 watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
554 }
08b16886
ZF		 555
556 prog_wm_value = convert_and_clamp(
557 watermarks->b.cstate_pstate.pstate_change_ns,
558 refclk_mhz, 0x1fffff);
559 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
215a6f05 560 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 561 "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
562 "HW register value = 0x%x\n",
563 watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
564
565 /* clock state C */
566 prog_wm_value = convert_and_clamp(
567 watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
568 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
215a6f05 569 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 570 "URGENCY_WATERMARK_C calculated =%d\n"
571 "HW register value = 0x%x\n",
572 watermarks->c.urgent_ns, prog_wm_value);
573
574
575 prog_wm_value = convert_and_clamp(
576 watermarks->c.pte_meta_urgent_ns,
577 refclk_mhz, 0x1fffff);
578 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
215a6f05 579 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 580 "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
581 "HW register value = 0x%x\n",
582 watermarks->c.pte_meta_urgent_ns, prog_wm_value);
583
584
9a5bcd47
EB		 585 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
586 prog_wm_value = convert_and_clamp(
587 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
588 refclk_mhz, 0x1fffff);
589 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
590 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
591 "SR_ENTER_WATERMARK_C calculated =%d\n"
592 "HW register value = 0x%x\n",
593 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
594
595
596 prog_wm_value = convert_and_clamp(
597 watermarks->c.cstate_pstate.cstate_exit_ns,
598 refclk_mhz, 0x1fffff);
599 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
600 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
601 "SR_EXIT_WATERMARK_C calculated =%d\n"
602 "HW register value = 0x%x\n",
603 watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
604 }
08b16886
ZF		 605
606 prog_wm_value = convert_and_clamp(
607 watermarks->c.cstate_pstate.pstate_change_ns,
608 refclk_mhz, 0x1fffff);
609 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
215a6f05 610 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 611 "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
612 "HW register value = 0x%x\n",
613 watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
614
615 /* clock state D */
616 prog_wm_value = convert_and_clamp(
617 watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
618 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
215a6f05 619 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 620 "URGENCY_WATERMARK_D calculated =%d\n"
621 "HW register value = 0x%x\n",
622 watermarks->d.urgent_ns, prog_wm_value);
623
624 prog_wm_value = convert_and_clamp(
625 watermarks->d.pte_meta_urgent_ns,
626 refclk_mhz, 0x1fffff);
627 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
215a6f05 628 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 629 "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
630 "HW register value = 0x%x\n",
631 watermarks->d.pte_meta_urgent_ns, prog_wm_value);
632
633
9a5bcd47
EB		 634 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
635 prog_wm_value = convert_and_clamp(
636 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
637 refclk_mhz, 0x1fffff);
638 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
639 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
640 "SR_ENTER_WATERMARK_D calculated =%d\n"
641 "HW register value = 0x%x\n",
642 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
643
644
645 prog_wm_value = convert_and_clamp(
646 watermarks->d.cstate_pstate.cstate_exit_ns,
647 refclk_mhz, 0x1fffff);
648 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
649 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
650 "SR_EXIT_WATERMARK_D calculated =%d\n"
651 "HW register value = 0x%x\n",
652 watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
653 }
08b16886
ZF		 654
655
656 prog_wm_value = convert_and_clamp(
657 watermarks->d.cstate_pstate.pstate_change_ns,
658 refclk_mhz, 0x1fffff);
659 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
215a6f05 660 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 661 "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
662 "HW register value = 0x%x\n\n",
663 watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
664
665 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
666 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
cbb4d72e 667
08b16886
ZF		 668 REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
669 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
670 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
671 DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
672
673 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
674 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
675 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
676
677#if 0
678 REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
679 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
680 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
681#endif
682}
683
684
685static void dcn10_update_dchub(
686 struct dce_hwseq *hws,
687 struct dchub_init_data *dh_data)
688{
689 /* TODO: port code from dal2 */
690 switch (dh_data->fb_mode) {
691 case FRAME_BUFFER_MODE_ZFB_ONLY:
692 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
693 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
694 SDPIF_FB_TOP, 0);
695
696 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
697 SDPIF_FB_BASE, 0x0FFFF);
698
699 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
700 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
701
702 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
703 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
704
705 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
706 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
707 dh_data->zfb_size_in_byte - 1) >> 22);
708 break;
709 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
710 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
711
712 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
713 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
714
715 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
716 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
717
718 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
719 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
720 dh_data->zfb_size_in_byte - 1) >> 22);
721 break;
722 case FRAME_BUFFER_MODE_LOCAL_ONLY:
723 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
724 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
725 SDPIF_AGP_BASE, 0);
726
727 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
728 SDPIF_AGP_BOT, 0X03FFFF);
729
730 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
731 SDPIF_AGP_TOP, 0);
732 break;
733 default:
734 break;
735 }
736
737 dh_data->dchub_initialzied = true;
738 dh_data->dchub_info_valid = false;
739}
740
70ccab60 741static void hubp_pg_control(
184debdb 742 struct dce_hwseq *hws,
70ccab60
HW		 743 unsigned int hubp_inst,
744 bool power_on)
745{
70ccab60
HW		 746 uint32_t power_gate = power_on ? 0 : 1;
747 uint32_t pwr_status = power_on ? 0 : 2;
748
184debdb 749 if (hws->ctx->dc->debug.disable_hubp_power_gate)
70ccab60
HW		 750 return;
751
752 switch (hubp_inst) {
753 case 0: /* DCHUBP0 */
184debdb 754 REG_UPDATE(DOMAIN0_PG_CONFIG,
70ccab60
HW		 755 DOMAIN0_POWER_GATE, power_gate);
756
184debdb 757 REG_WAIT(DOMAIN0_PG_STATUS,
8a5d8245
TC		 758 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
759 1, 1000);
70ccab60
HW		 760 break;
761 case 1: /* DCHUBP1 */
184debdb 762 REG_UPDATE(DOMAIN2_PG_CONFIG,
70ccab60
HW		 763 DOMAIN2_POWER_GATE, power_gate);
764
184debdb 765 REG_WAIT(DOMAIN2_PG_STATUS,
8a5d8245
TC		 766 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
767 1, 1000);
70ccab60
HW		 768 break;
769 case 2: /* DCHUBP2 */
184debdb 770 REG_UPDATE(DOMAIN4_PG_CONFIG,
70ccab60
HW		 771 DOMAIN4_POWER_GATE, power_gate);
772
184debdb 773 REG_WAIT(DOMAIN4_PG_STATUS,
8a5d8245
TC		 774 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
775 1, 1000);
70ccab60
HW		 776 break;
777 case 3: /* DCHUBP3 */
184debdb 778 REG_UPDATE(DOMAIN6_PG_CONFIG,
70ccab60
HW		 779 DOMAIN6_POWER_GATE, power_gate);
780
184debdb 781 REG_WAIT(DOMAIN6_PG_STATUS,
8a5d8245
TC		 782 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
783 1, 1000);
70ccab60
HW		 784 break;
785 default:
786 BREAK_TO_DEBUGGER();
787 break;
788 }
789}
790
791static void power_on_plane(
184debdb 792 struct dce_hwseq *hws,
cfe4645e 793 int plane_id)
70ccab60 794{
5df921d4
KC		 795 if (REG(DC_IP_REQUEST_CNTL)) {
796 REG_SET(DC_IP_REQUEST_CNTL, 0,
797 IP_REQUEST_EN, 1);
798 dpp_pg_control(hws, plane_id, true);
799 hubp_pg_control(hws, plane_id, true);
800 REG_SET(DC_IP_REQUEST_CNTL, 0,
801 IP_REQUEST_EN, 0);
802 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
803 "Un-gated front end for pipe %d\n", plane_id);
804 }
70ccab60
HW		 805}
806
41f97c07
HW		 807static void undo_DEGVIDCN10_253_wa(struct dc *dc)
808{
809 struct dce_hwseq *hws = dc->hwseq;
8feabd03 810 struct hubp *hubp = dc->res_pool->hubps[0];
c9bb686b
EY		 811 int pwr_status = 0;
812
813 REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status);
814 /* Don't need to blank if hubp is power gated*/
815 if (pwr_status == 2)
816 return;
41f97c07 817
8feabd03 818 hubp->funcs->set_blank(hubp, true);
41f97c07
HW		 819
820 REG_SET(DC_IP_REQUEST_CNTL, 0,
821 IP_REQUEST_EN, 1);
822
823 hubp_pg_control(hws, 0, false);
824 REG_SET(DC_IP_REQUEST_CNTL, 0,
825 IP_REQUEST_EN, 0);
826}
827
41f97c07
HW		 828static void apply_DEGVIDCN10_253_wa(struct dc *dc)
829{
830 struct dce_hwseq *hws = dc->hwseq;
8feabd03 831 struct hubp *hubp = dc->res_pool->hubps[0];
41f97c07 832
6bf52028
HW		 833 if (dc->debug.disable_stutter)
834 return;
835
41f97c07
HW		 836 REG_SET(DC_IP_REQUEST_CNTL, 0,
837 IP_REQUEST_EN, 1);
838
839 hubp_pg_control(hws, 0, true);
840 REG_SET(DC_IP_REQUEST_CNTL, 0,
841 IP_REQUEST_EN, 0);
842
8feabd03 843 hubp->funcs->set_hubp_blank_en(hubp, false);
41f97c07
HW		 844}
845
fb3466a4 846static void bios_golden_init(struct dc *dc)
70ccab60
HW		 847{
848 struct dc_bios *bp = dc->ctx->dc_bios;
849 int i;
850
851 /* initialize dcn global */
852 bp->funcs->enable_disp_power_gating(bp,
853 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
854
855 for (i = 0; i < dc->res_pool->pipe_count; i++) {
856 /* initialize dcn per pipe */
857 bp->funcs->enable_disp_power_gating(bp,
858 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
859 }
860}
861
fb3466a4 862static void dcn10_init_hw(struct dc *dc)
70ccab60
HW		 863{
864 int i;
b02c3b05 865 struct abm *abm = dc->res_pool->abm;
184debdb 866 struct dce_hwseq *hws = dc->hwseq;
70ccab60 867
70ccab60 868 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
b02c3b05
DL		 869 REG_WRITE(REFCLK_CNTL, 0);
870 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
184debdb
DL		 871 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
872
fb3466a4 873 if (!dc->debug.disable_clock_gate) {
184debdb
DL		 874 /* enable all DCN clock gating */
875 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
876
877 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
70ccab60 878
184debdb
DL		 879 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
880 }
881
882 enable_power_gating_plane(dc->hwseq, true);
70ccab60
HW		 883 return;
884 }
885 /* end of FPGA. Below if real ASIC */
886
887 bios_golden_init(dc);
888
0a87425a
TC		 889 disable_vga(dc->hwseq);
890
70ccab60
HW		 891 for (i = 0; i < dc->link_count; i++) {
892 /* Power up AND update implementation according to the
893 * required signal (which may be different from the
894 * default signal on connector).
895 */
d0778ebf 896 struct dc_link *link = dc->links[i];
70ccab60
HW		 897
898 link->link_enc->funcs->hw_init(link->link_enc);
899 }
900
901 for (i = 0; i < dc->res_pool->pipe_count; i++) {
d94585a0 902 struct dpp *dpp = dc->res_pool->dpps[i];
b02c3b05 903 struct timing_generator *tg = dc->res_pool->timing_generators[i];
f0558542 904
d94585a0 905 dpp->funcs->dpp_reset(dpp);
cc408d72 906 dc->res_pool->mpc->funcs->remove(
7f4a7253
EB		 907 dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree),
908 dc->res_pool->opps[i]->inst, i);
70ccab60 909
70ccab60
HW		 910 /* Blank controller using driver code instead of
911 * command table.
912 */
913 tg->funcs->set_blank(tg, true);
914 hwss_wait_for_blank_complete(tg);
915 }
916
917 for (i = 0; i < dc->res_pool->audio_count; i++) {
918 struct audio *audio = dc->res_pool->audios[i];
919
920 audio->funcs->hw_init(audio);
921 }
922
70ccab60
HW		 923 if (abm != NULL) {
924 abm->funcs->init_backlight(abm);
925 abm->funcs->abm_init(abm);
926 }
927
928 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
184debdb 929 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
70ccab60 930
fb3466a4 931 if (!dc->debug.disable_clock_gate) {
5970f2ae 932 /* enable all DCN clock gating */
184debdb 933 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
5970f2ae 934
184debdb 935 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
5970f2ae 936
184debdb
DL		 937 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
938 }
5970f2ae 939
184debdb 940 enable_power_gating_plane(dc->hwseq, true);
70ccab60
HW		 941}
942
943static enum dc_status dcn10_prog_pixclk_crtc_otg(
944 struct pipe_ctx *pipe_ctx,
608ac7bb 945 struct dc_state *context,
fb3466a4 946 struct dc *dc)
70ccab60 947{
0971c40e 948 struct dc_stream_state *stream = pipe_ctx->stream;
70ccab60
HW		 949 enum dc_color_space color_space;
950 struct tg_color black_color = {0};
4fa086b9 951 bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
70ccab60 952 false:true;
4fa086b9 953 bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
70ccab60
HW		 954
955
956 /* by upper caller loop, pipe0 is parent pipe and be called first.
957 * back end is set up by for pipe0. Other children pipe share back end
958 * with pipe 0. No program is needed.
959 */
960 if (pipe_ctx->top_pipe != NULL)
961 return DC_OK;
962
963 /* TODO check if timing_changed, disable stream if timing changed */
964
965 /* HW program guide assume display already disable
966 * by unplug sequence. OTG assume stop.
967 */
6b670fa9 968 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
70ccab60
HW		 969
970 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
971 pipe_ctx->clock_source,
10688217 972 &pipe_ctx->stream_res.pix_clk_params,
70ccab60
HW		 973 &pipe_ctx->pll_settings)) {
974 BREAK_TO_DEBUGGER();
975 return DC_ERROR_UNEXPECTED;
976 }
6b670fa9
HW		 977 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
978 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
979 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
980 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
70ccab60 981
6b670fa9 982 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
70ccab60 983
6b670fa9
HW		 984 pipe_ctx->stream_res.tg->funcs->program_timing(
985 pipe_ctx->stream_res.tg,
4fa086b9 986 &stream->timing,
70ccab60
HW		 987 true);
988
a6a6cb34
HW		 989 pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
990 pipe_ctx->stream_res.opp,
70ccab60
HW		 991 enableStereo,
992 rightEyePolarity);
993
994#if 0 /* move to after enable_crtc */
995 /* TODO: OPP FMT, ABM. etc. should be done here. */
996 /* or FPGA now. instance 0 only. TODO: move to opp.c */
997
6b670fa9 998 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
70ccab60 999
a6a6cb34
HW		 1000 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1001 pipe_ctx->stream_res.opp,
70ccab60
HW		 1002 &stream->bit_depth_params,
1003 &stream->clamping);
1004#endif
1005 /* program otg blank color */
4fa086b9 1006 color_space = stream->output_color_space;
70ccab60 1007 color_space_to_black_color(dc, color_space, &black_color);
6b670fa9
HW		 1008 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1009 pipe_ctx->stream_res.tg,
70ccab60
HW		 1010 &black_color);
1011
6b670fa9
HW		 1012 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1013 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
70ccab60
HW		 1014
1015 /* VTG is within DCHUB command block. DCFCLK is always on */
6b670fa9 1016 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
70ccab60
HW		 1017 BREAK_TO_DEBUGGER();
1018 return DC_ERROR_UNEXPECTED;
1019 }
1020
1021 /* TODO program crtc source select for non-virtual signal*/
1022 /* TODO program FMT */
1023 /* TODO setup link_enc */
1024 /* TODO set stream attributes */
1025 /* TODO program audio */
1026 /* TODO enable stream if timing changed */
1027 /* TODO unblank stream if DP */
1028
1029 return DC_OK;
1030}
1031
1032static void reset_back_end_for_pipe(
fb3466a4 1033 struct dc *dc,
70ccab60 1034 struct pipe_ctx *pipe_ctx,
608ac7bb 1035 struct dc_state *context)
70ccab60
HW		 1036{
1037 int i;
70ccab60 1038
8e9c4c8c 1039 if (pipe_ctx->stream_res.stream_enc == NULL) {
70ccab60
HW		 1040 pipe_ctx->stream = NULL;
1041 return;
1042 }
1043
d050f8ed
HW		 1044 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1045 /* DPMS may already disable */
1046 if (!pipe_ctx->stream->dpms_off)
1047 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
1048 }
70ccab60
HW		 1049
1050 /* by upper caller loop, parent pipe: pipe0, will be reset last.
1051 * back end share by all pipes and will be disable only when disable
1052 * parent pipe.
1053 */
1054 if (pipe_ctx->top_pipe == NULL) {
6b670fa9 1055 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
70ccab60 1056
6b670fa9 1057 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
70ccab60
HW		 1058 }
1059
70ccab60 1060 for (i = 0; i < dc->res_pool->pipe_count; i++)
608ac7bb 1061 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
70ccab60
HW		 1062 break;
1063
1064 if (i == dc->res_pool->pipe_count)
1065 return;
1066
1067 pipe_ctx->stream = NULL;
39902db0 1068 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
cfe4645e 1069 "Reset back end for pipe %d, tg:%d\n",
6b670fa9 1070 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
70ccab60
HW		 1071}
1072
a74b2734 1073/* trigger HW to start disconnect plane from stream on the next vsync */
fb3466a4 1074static void plane_atomic_disconnect(struct dc *dc,
cfe4645e 1075 int fe_idx)
70ccab60 1076{
8feabd03 1077 struct hubp *hubp = dc->res_pool->hubps[fe_idx];
cc408d72
DL		 1078 struct mpc *mpc = dc->res_pool->mpc;
1079 int opp_id, z_idx;
1080 int mpcc_id = -1;
1081
1082 /* look at tree rather than mi here to know if we already reset */
1083 for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
1084 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
a74b2734 1085
cc408d72
DL		 1086 for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) {
1087 if (opp->mpc_tree.dpp[z_idx] == fe_idx) {
1088 mpcc_id = opp->mpc_tree.mpcc[z_idx];
1089 break;
1090 }
1091 }
1092 if (mpcc_id != -1)
1093 break;
1094 }
a74b2734 1095 /*Already reset*/
cc408d72 1096 if (opp_id == dc->res_pool->pipe_count)
a74b2734 1097 return;
70ccab60 1098
fb3466a4 1099 if (dc->debug.sanity_checks)
6be425f3 1100 verify_allow_pstate_change_high(dc->hwseq);
8feabd03 1101 hubp->funcs->dcc_control(hubp, false, false);
fb3466a4 1102 if (dc->debug.sanity_checks)
6be425f3
EY		 1103 verify_allow_pstate_change_high(dc->hwseq);
1104
7f4a7253
EB		 1105 mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
1106 dc->res_pool->opps[opp_id]->inst, fe_idx);
d65359d5
TC		 1107}
1108
a74b2734
TC		 1109/* disable HW used by plane.
1110 * note: cannot disable until disconnect is complete */
fb3466a4 1111static void plane_atomic_disable(struct dc *dc,
d65359d5
TC		 1112 int fe_idx)
1113{
1114 struct dce_hwseq *hws = dc->hwseq;
8feabd03 1115 struct hubp *hubp = dc->res_pool->hubps[fe_idx];
cc408d72 1116 struct mpc *mpc = dc->res_pool->mpc;
8feabd03 1117 int opp_id = hubp->opp_id;
d65359d5 1118
e75504b1 1119 if (opp_id == 0xf)
d65359d5
TC		 1120 return;
1121
8feabd03
YHL		 1122 mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
1123 dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
6be425f3
EY		 1124 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
1125 "[debug_mpo: atomic disable finished on mpcc %d]\n",
1126 fe_idx);*/
189f73e3 1127
8feabd03 1128 hubp->funcs->set_blank(hubp, true);
d65359d5 1129
fb3466a4 1130 if (dc->debug.sanity_checks)
2b13d7d3
TC		 1131 verify_allow_pstate_change_high(dc->hwseq);
1132
d21becbe
TC		 1133 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
1134 HUBP_CLOCK_ENABLE, 0);
1135 REG_UPDATE(DPP_CONTROL[fe_idx],
1136 DPP_CLOCK_ENABLE, 0);
71a2f23e 1137
e75504b1
DL		 1138 if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
1139 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
71a2f23e 1140 OPP_PIPE_CLOCK_EN, 0);
70ccab60 1141
fb3466a4 1142 if (dc->debug.sanity_checks)
2b13d7d3 1143 verify_allow_pstate_change_high(dc->hwseq);
cfe4645e 1144}
70ccab60 1145
6be425f3
EY		 1146/*
1147 * kill power to plane hw
a74b2734 1148 * note: cannot power down until plane is disable
6be425f3 1149 */
fb3466a4 1150static void plane_atomic_power_down(struct dc *dc, int fe_idx)
a74b2734 1151{
6be425f3 1152 struct dce_hwseq *hws = dc->hwseq;
d94585a0 1153 struct dpp *dpp = dc->res_pool->dpps[fe_idx];
6be425f3 1154
5df921d4
KC		 1155 if (REG(DC_IP_REQUEST_CNTL)) {
1156 REG_SET(DC_IP_REQUEST_CNTL, 0,
1157 IP_REQUEST_EN, 1);
1158 dpp_pg_control(hws, fe_idx, false);
1159 hubp_pg_control(hws, fe_idx, false);
d94585a0 1160 dpp->funcs->dpp_reset(dpp);
5df921d4
KC		 1161 REG_SET(DC_IP_REQUEST_CNTL, 0,
1162 IP_REQUEST_EN, 0);
1163 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
1164 "Power gated front end %d\n", fe_idx);
a74b2734 1165
5df921d4
KC		 1166 if (dc->debug.sanity_checks)
1167 verify_allow_pstate_change_high(dc->hwseq);
1168 }
a74b2734 1169}
6be425f3 1170
a74b2734
TC		 1171
1172static void reset_front_end(
fb3466a4 1173 struct dc *dc,
a74b2734
TC		 1174 int fe_idx)
1175{
1176 struct dce_hwseq *hws = dc->hwseq;
cc408d72 1177 struct timing_generator *tg;
8feabd03 1178 int opp_id = dc->res_pool->hubps[fe_idx]->opp_id;
a74b2734
TC		 1179
1180 /*Already reset*/
1181 if (opp_id == 0xf)
1182 return;
1183
cc408d72 1184 tg = dc->res_pool->timing_generators[opp_id];
a74b2734
TC		 1185 tg->funcs->lock(tg);
1186
1187 plane_atomic_disconnect(dc, fe_idx);
1188
1189 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
1190 tg->funcs->unlock(tg);
1191
fb3466a4 1192 if (dc->debug.sanity_checks)
cc408d72 1193 verify_allow_pstate_change_high(hws);
a74b2734
TC		 1194
1195 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
1196 REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
8a5d8245
TC		 1197 VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
1198 1, 100000);
a74b2734
TC		 1199
1200 plane_atomic_disable(dc, fe_idx);
1201
1202 dm_logger_write(dc->ctx->logger, LOG_DC,
1203 "Reset front end %d\n",
1204 fe_idx);
1205}
1206
fb3466a4 1207static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
cfe4645e 1208{
184debdb 1209 struct dce_hwseq *hws = dc->hwseq;
d94585a0 1210 struct dpp *dpp = dc->res_pool->dpps[fe_idx];
70ccab60 1211
cfe4645e 1212 reset_front_end(dc, fe_idx);
70ccab60 1213
184debdb 1214 REG_SET(DC_IP_REQUEST_CNTL, 0,
cfe4645e 1215 IP_REQUEST_EN, 1);
184debdb
DL		 1216 dpp_pg_control(hws, fe_idx, false);
1217 hubp_pg_control(hws, fe_idx, false);
d94585a0 1218 dpp->funcs->dpp_reset(dpp);
184debdb 1219 REG_SET(DC_IP_REQUEST_CNTL, 0,
cfe4645e 1220 IP_REQUEST_EN, 0);
39902db0 1221 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
cfe4645e 1222 "Power gated front end %d\n", fe_idx);
2b13d7d3 1223
fb3466a4 1224 if (dc->debug.sanity_checks)
2b13d7d3 1225 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 1226}
1227
cfe4645e 1228static void reset_hw_ctx_wrap(
fb3466a4 1229 struct dc *dc,
608ac7bb 1230 struct dc_state *context)
70ccab60
HW		 1231{
1232 int i;
1233
cfe4645e 1234 /* Reset Front End*/
6be425f3
EY		 1235 /* Lock*/
1236 for (i = 0; i < dc->res_pool->pipe_count; i++) {
608ac7bb 1237 struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
6b670fa9 1238 struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
6be425f3
EY		 1239
1240 if (cur_pipe_ctx->stream)
1241 tg->funcs->lock(tg);
1242 }
1243 /* Disconnect*/
1244 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1245 struct pipe_ctx *pipe_ctx_old =
608ac7bb 1246 &dc->current_state->res_ctx.pipe_ctx[i];
6be425f3
EY		 1247 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1248
1249 if (!pipe_ctx->stream ||
3be5262e 1250 !pipe_ctx->plane_state ||
6be425f3
EY		 1251 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1252
1253 plane_atomic_disconnect(dc, i);
1254 }
1255 }
1256 /* Unlock*/
1257 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
608ac7bb 1258 struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
6b670fa9 1259 struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
6be425f3
EY		 1260
1261 if (cur_pipe_ctx->stream)
1262 tg->funcs->unlock(tg);
1263 }
1264
1265 /* Disable and Powerdown*/
cfe4645e
DL		 1266 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1267 struct pipe_ctx *pipe_ctx_old =
608ac7bb 1268 &dc->current_state->res_ctx.pipe_ctx[i];
cfe4645e
DL		 1269 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1270
1271 /*if (!pipe_ctx_old->stream)
1272 continue;*/
1273
3be5262e 1274 if (pipe_ctx->stream && pipe_ctx->plane_state
6be425f3
EY		 1275 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1276 continue;
1277
1278 plane_atomic_disable(dc, i);
1279
3be5262e 1280 if (!pipe_ctx->stream || !pipe_ctx->plane_state)
6be425f3 1281 plane_atomic_power_down(dc, i);
cfe4645e 1282 }
6be425f3 1283
cfe4645e 1284 /* Reset Back End*/
70ccab60
HW		 1285 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1286 struct pipe_ctx *pipe_ctx_old =
608ac7bb 1287 &dc->current_state->res_ctx.pipe_ctx[i];
70ccab60
HW		 1288 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1289
1290 if (!pipe_ctx_old->stream)
1291 continue;
1292
56e6ed45
YS		 1293 if (pipe_ctx_old->top_pipe)
1294 continue;
1295
70ccab60 1296 if (!pipe_ctx->stream ||
21e67d4d
HW		 1297 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1298 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1299
608ac7bb 1300 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
21e67d4d
HW		 1301
1302 if (old_clk)
1303 old_clk->funcs->cs_power_down(old_clk);
1304 }
70ccab60 1305 }
21e67d4d 1306
70ccab60
HW		 1307}
1308
cfe4645e
DL		 1309static bool patch_address_for_sbs_tb_stereo(
1310 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
70ccab60 1311{
3be5262e 1312 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
70ccab60 1313 bool sec_split = pipe_ctx->top_pipe &&
3be5262e
HW		 1314 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1315 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
4fa086b9 1316 (pipe_ctx->stream->timing.timing_3d_format ==
70ccab60 1317 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
4fa086b9 1318 pipe_ctx->stream->timing.timing_3d_format ==
70ccab60 1319 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
3be5262e
HW		 1320 *addr = plane_state->address.grph_stereo.left_addr;
1321 plane_state->address.grph_stereo.left_addr =
1322 plane_state->address.grph_stereo.right_addr;
70ccab60 1323 return true;
cdc5e048 1324 } else {
4fa086b9 1325 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
3be5262e
HW		 1326 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1327 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1328 plane_state->address.grph_stereo.right_addr =
1329 plane_state->address.grph_stereo.left_addr;
cdc5e048 1330 }
70ccab60
HW		 1331 }
1332 return false;
1333}
1334
9d6f264b
YS		 1335static void toggle_watermark_change_req(struct dce_hwseq *hws)
1336{
1337 uint32_t watermark_change_req;
1338
1339 REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
1340 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
1341
1342 if (watermark_change_req)
1343 watermark_change_req = 0;
1344 else
1345 watermark_change_req = 1;
1346
1347 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
1348 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
1349}
1350
fb3466a4 1351static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
70ccab60
HW		 1352{
1353 bool addr_patched = false;
1354 PHYSICAL_ADDRESS_LOC addr;
3be5262e 1355 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
70ccab60 1356
3be5262e 1357 if (plane_state == NULL)
70ccab60
HW		 1358 return;
1359 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
8feabd03
YHL		 1360 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1361 pipe_ctx->plane_res.hubp,
3be5262e
HW		 1362 &plane_state->address,
1363 plane_state->flip_immediate);
1364 plane_state->status.requested_address = plane_state->address;
70ccab60 1365 if (addr_patched)
3be5262e 1366 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
70ccab60
HW		 1367}
1368
1369static bool dcn10_set_input_transfer_func(
3be5262e 1370 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
70ccab60 1371{
d94585a0 1372 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
7b0c470f 1373 const struct dc_transfer_func *tf = NULL;
70ccab60
HW		 1374 bool result = true;
1375
d94585a0 1376 if (dpp_base == NULL)
70ccab60
HW		 1377 return false;
1378
3be5262e
HW		 1379 if (plane_state->in_transfer_func)
1380 tf = plane_state->in_transfer_func;
70ccab60 1381
3be5262e 1382 if (plane_state->gamma_correction && dce_use_lut(plane_state))
d94585a0 1383 dpp_base->funcs->ipp_program_input_lut(dpp_base,
3be5262e 1384 plane_state->gamma_correction);
5aff86c1 1385
70ccab60 1386 if (tf == NULL)
d94585a0 1387 dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
7b0c470f
LSL		 1388 else if (tf->type == TF_TYPE_PREDEFINED) {
1389 switch (tf->tf) {
70ccab60 1390 case TRANSFER_FUNCTION_SRGB:
d94585a0 1391 dpp_base->funcs->ipp_set_degamma(dpp_base,
70ccab60
HW		 1392 IPP_DEGAMMA_MODE_HW_sRGB);
1393 break;
1394 case TRANSFER_FUNCTION_BT709:
d94585a0 1395 dpp_base->funcs->ipp_set_degamma(dpp_base,
70ccab60
HW		 1396 IPP_DEGAMMA_MODE_HW_xvYCC);
1397 break;
1398 case TRANSFER_FUNCTION_LINEAR:
d94585a0 1399 dpp_base->funcs->ipp_set_degamma(dpp_base,
70ccab60
HW		 1400 IPP_DEGAMMA_MODE_BYPASS);
1401 break;
1402 case TRANSFER_FUNCTION_PQ:
1403 result = false;
1404 break;
1405 default:
1406 result = false;
1407 break;
1408 }
7b0c470f 1409 } else if (tf->type == TF_TYPE_BYPASS) {
d94585a0 1410 dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
70ccab60
HW		 1411 } else {
1412 /*TF_TYPE_DISTRIBUTED_POINTS*/
1413 result = false;
1414 }
1415
1416 return result;
1417}
1418/*modify the method to handle rgb for arr_points*/
1419static bool convert_to_custom_float(
1420 struct pwl_result_data *rgb_resulted,
1421 struct curve_points *arr_points,
1422 uint32_t hw_points_num)
1423{
1424 struct custom_float_format fmt;
1425
1426 struct pwl_result_data *rgb = rgb_resulted;
1427
1428 uint32_t i = 0;
1429
1430 fmt.exponenta_bits = 6;
1431 fmt.mantissa_bits = 12;
1432 fmt.sign = false;
1433
1434 if (!convert_to_custom_float_format(
1435 arr_points[0].x,
1436 &fmt,
1437 &arr_points[0].custom_float_x)) {
1438 BREAK_TO_DEBUGGER();
1439 return false;
1440 }
1441
1442 if (!convert_to_custom_float_format(
1443 arr_points[0].offset,
1444 &fmt,
1445 &arr_points[0].custom_float_offset)) {
1446 BREAK_TO_DEBUGGER();
1447 return false;
1448 }
1449
1450 if (!convert_to_custom_float_format(
1451 arr_points[0].slope,
1452 &fmt,
1453 &arr_points[0].custom_float_slope)) {
1454 BREAK_TO_DEBUGGER();
1455 return false;
1456 }
1457
1458 fmt.mantissa_bits = 10;
1459 fmt.sign = false;
1460
1461 if (!convert_to_custom_float_format(
1462 arr_points[1].x,
1463 &fmt,
1464 &arr_points[1].custom_float_x)) {
1465 BREAK_TO_DEBUGGER();
1466 return false;
1467 }
1468
1469 if (!convert_to_custom_float_format(
1470 arr_points[1].y,
1471 &fmt,
1472 &arr_points[1].custom_float_y)) {
1473 BREAK_TO_DEBUGGER();
1474 return false;
1475 }
1476
1477 if (!convert_to_custom_float_format(
1478 arr_points[1].slope,
1479 &fmt,
1480 &arr_points[1].custom_float_slope)) {
1481 BREAK_TO_DEBUGGER();
1482 return false;
1483 }
1484
1485 fmt.mantissa_bits = 12;
1486 fmt.sign = true;
1487
1488 while (i != hw_points_num) {
1489 if (!convert_to_custom_float_format(
1490 rgb->red,
1491 &fmt,
1492 &rgb->red_reg)) {
1493 BREAK_TO_DEBUGGER();
1494 return false;
1495 }
1496
1497 if (!convert_to_custom_float_format(
1498 rgb->green,
1499 &fmt,
1500 &rgb->green_reg)) {
1501 BREAK_TO_DEBUGGER();
1502 return false;
1503 }
1504
1505 if (!convert_to_custom_float_format(
1506 rgb->blue,
1507 &fmt,
1508 &rgb->blue_reg)) {
1509 BREAK_TO_DEBUGGER();
1510 return false;
1511 }
1512
1513 if (!convert_to_custom_float_format(
1514 rgb->delta_red,
1515 &fmt,
1516 &rgb->delta_red_reg)) {
1517 BREAK_TO_DEBUGGER();
1518 return false;
1519 }
1520
1521 if (!convert_to_custom_float_format(
1522 rgb->delta_green,
1523 &fmt,
1524 &rgb->delta_green_reg)) {
1525 BREAK_TO_DEBUGGER();
1526 return false;
1527 }
1528
1529 if (!convert_to_custom_float_format(
1530 rgb->delta_blue,
1531 &fmt,
1532 &rgb->delta_blue_reg)) {
1533 BREAK_TO_DEBUGGER();
1534 return false;
1535 }
1536
1537 ++rgb;
1538 ++i;
1539 }
1540
1541 return true;
1542}
1543#define MAX_REGIONS_NUMBER 34
1544#define MAX_LOW_POINT 25
1545#define NUMBER_SEGMENTS 32
1546
1547static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
1548 *output_tf, struct pwl_params *regamma_params)
1549{
1550 struct curve_points *arr_points;
1551 struct pwl_result_data *rgb_resulted;
1552 struct pwl_result_data *rgb;
1553 struct pwl_result_data *rgb_plus_1;
1554 struct fixed31_32 y_r;
1555 struct fixed31_32 y_g;
1556 struct fixed31_32 y_b;
1557 struct fixed31_32 y1_min;
1558 struct fixed31_32 y3_max;
1559
1560 int32_t segment_start, segment_end;
1561 int32_t i;
1562 uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
1563
1564 if (output_tf == NULL || regamma_params == NULL ||
1565 output_tf->type == TF_TYPE_BYPASS)
1566 return false;
1567
1568 arr_points = regamma_params->arr_points;
1569 rgb_resulted = regamma_params->rgb_resulted;
1570 hw_points = 0;
1571
1572 memset(regamma_params, 0, sizeof(struct pwl_params));
1573 memset(seg_distr, 0, sizeof(seg_distr));
1574
1575 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1576 /* 32 segments
1577 * segments are from 2^-25 to 2^7
1578 */
1579 for (i = 0; i < 32 ; i++)
1580 seg_distr[i] = 3;
1581
1582 segment_start = -25;
1583 segment_end = 7;
1584 } else {
1585 /* 10 segments
1586 * segment is from 2^-10 to 2^0
1587 * There are less than 256 points, for optimization
1588 */
1589 seg_distr[0] = 3;
1590 seg_distr[1] = 4;
1591 seg_distr[2] = 4;
1592 seg_distr[3] = 4;
1593 seg_distr[4] = 4;
1594 seg_distr[5] = 4;
1595 seg_distr[6] = 4;
1596 seg_distr[7] = 4;
1597 seg_distr[8] = 5;
1598 seg_distr[9] = 5;
1599
1600 segment_start = -10;
1601 segment_end = 0;
1602 }
1603
1604 for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
1605 seg_distr[i] = -1;
1606
1607 for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
1608 if (seg_distr[k] != -1)
1609 hw_points += (1 << seg_distr[k]);
1610 }
1611
1612 j = 0;
1613 for (k = 0; k < (segment_end - segment_start); k++) {
1614 increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
1615 start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1616 for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
1617 if (j == hw_points - 1)
1618 break;
1619 rgb_resulted[j].red = output_tf->tf_pts.red[i];
1620 rgb_resulted[j].green = output_tf->tf_pts.green[i];
1621 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
1622 j++;
1623 }
1624 }
1625
1626 /* last point */
1627 start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1628 rgb_resulted[hw_points - 1].red =
1629 output_tf->tf_pts.red[start_index];
1630 rgb_resulted[hw_points - 1].green =
1631 output_tf->tf_pts.green[start_index];
1632 rgb_resulted[hw_points - 1].blue =
1633 output_tf->tf_pts.blue[start_index];
1634
1635 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1636 dal_fixed31_32_from_int(segment_start));
1637 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1638 dal_fixed31_32_from_int(segment_end));
1639 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1640 dal_fixed31_32_from_int(segment_end));
1641
1642 y_r = rgb_resulted[0].red;
1643 y_g = rgb_resulted[0].green;
1644 y_b = rgb_resulted[0].blue;
1645
1646 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
1647
1648 arr_points[0].y = y1_min;
1649 arr_points[0].slope = dal_fixed31_32_div(
1650 arr_points[0].y,
1651 arr_points[0].x);
1652 y_r = rgb_resulted[hw_points - 1].red;
1653 y_g = rgb_resulted[hw_points - 1].green;
1654 y_b = rgb_resulted[hw_points - 1].blue;
1655
1656 /* see comment above, m_arrPoints[1].y should be the Y value for the
1657 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
1658 */
1659 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
1660
1661 arr_points[1].y = y3_max;
1662 arr_points[2].y = y3_max;
1663
1664 arr_points[1].slope = dal_fixed31_32_zero;
1665 arr_points[2].slope = dal_fixed31_32_zero;
1666
1667 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1668 /* for PQ, we want to have a straight line from last HW X point,
1669 * and the slope to be such that we hit 1.0 at 10000 nits.
1670 */
1671 const struct fixed31_32 end_value =
1672 dal_fixed31_32_from_int(125);
1673
1674 arr_points[1].slope = dal_fixed31_32_div(
1675 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1676 dal_fixed31_32_sub(end_value, arr_points[1].x));
1677 arr_points[2].slope = dal_fixed31_32_div(
1678 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1679 dal_fixed31_32_sub(end_value, arr_points[1].x));
1680 }
1681
1682 regamma_params->hw_points_num = hw_points;
1683
1684 i = 1;
1685 for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
1686 if (seg_distr[k] != -1) {
1687 regamma_params->arr_curve_points[k].segments_num =
1688 seg_distr[k];
1689 regamma_params->arr_curve_points[i].offset =
1690 regamma_params->arr_curve_points[k].
1691 offset + (1 << seg_distr[k]);
1692 }
1693 i++;
1694 }
1695
1696 if (seg_distr[k] != -1)
1697 regamma_params->arr_curve_points[k].segments_num =
1698 seg_distr[k];
1699
1700 rgb = rgb_resulted;
1701 rgb_plus_1 = rgb_resulted + 1;
1702
1703 i = 1;
1704
1705 while (i != hw_points + 1) {
1706 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
1707 rgb_plus_1->red = rgb->red;
1708 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
1709 rgb_plus_1->green = rgb->green;
1710 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
1711 rgb_plus_1->blue = rgb->blue;
1712
1713 rgb->delta_red = dal_fixed31_32_sub(
1714 rgb_plus_1->red,
1715 rgb->red);
1716 rgb->delta_green = dal_fixed31_32_sub(
1717 rgb_plus_1->green,
1718 rgb->green);
1719 rgb->delta_blue = dal_fixed31_32_sub(
1720 rgb_plus_1->blue,
1721 rgb->blue);
1722
1723 ++rgb_plus_1;
1724 ++rgb;
1725 ++i;
1726 }
1727
1728 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
1729
1730 return true;
1731}
1732
1733static bool dcn10_set_output_transfer_func(
1734 struct pipe_ctx *pipe_ctx,
0971c40e 1735 const struct dc_stream_state *stream)
70ccab60 1736{
d94585a0 1737 struct dpp *dpp = pipe_ctx->plane_res.dpp;
70ccab60 1738
d94585a0 1739 if (dpp == NULL)
f46661dd
AZ		 1740 return false;
1741
d94585a0 1742 dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
70ccab60 1743
4fa086b9
LSL		 1744 if (stream->out_transfer_func &&
1745 stream->out_transfer_func->type ==
70ccab60 1746 TF_TYPE_PREDEFINED &&
4fa086b9 1747 stream->out_transfer_func->tf ==
70ccab60 1748 TRANSFER_FUNCTION_SRGB) {
d94585a0 1749 dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_SRGB);
70ccab60 1750 } else if (dcn10_translate_regamma_to_hw_format(
d94585a0
YHL		 1751 stream->out_transfer_func, &dpp->regamma_params)) {
1752 dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params);
1753 dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_USER);
70ccab60 1754 } else {
d94585a0 1755 dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_BYPASS);
70ccab60
HW		 1756 }
1757
1758 return true;
1759}
1760
1761static void dcn10_pipe_control_lock(
fb3466a4 1762 struct dc *dc,
70ccab60
HW		 1763 struct pipe_ctx *pipe,
1764 bool lock)
1765{
8feabd03
YHL		 1766 struct hubp *hubp = NULL;
1767 hubp = dc->res_pool->hubps[pipe->pipe_idx];
70ccab60
HW		 1768 /* use TG master update lock to lock everything on the TG
1769 * therefore only top pipe need to lock
1770 */
1771 if (pipe->top_pipe)
1772 return;
1773
fb3466a4 1774 if (dc->debug.sanity_checks)
2b13d7d3
TC		 1775 verify_allow_pstate_change_high(dc->hwseq);
1776
70ccab60 1777 if (lock)
6b670fa9 1778 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
70ccab60 1779 else
6b670fa9 1780 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
2b13d7d3 1781
fb3466a4 1782 if (dc->debug.sanity_checks)
2b13d7d3 1783 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 1784}
1785
1786static bool wait_for_reset_trigger_to_occur(
1787 struct dc_context *dc_ctx,
1788 struct timing_generator *tg)
1789{
1790 bool rc = false;
1791
1792 /* To avoid endless loop we wait at most
1793 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1794 const uint32_t frames_to_wait_on_triggered_reset = 10;
1795 int i;
1796
1797 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1798
1799 if (!tg->funcs->is_counter_moving(tg)) {
1800 DC_ERROR("TG counter is not moving!\n");
1801 break;
1802 }
1803
1804 if (tg->funcs->did_triggered_reset_occur(tg)) {
1805 rc = true;
1806 /* usually occurs at i=1 */
1807 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1808 i);
1809 break;
1810 }
1811
1812 /* Wait for one frame. */
1813 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1814 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1815 }
1816
1817 if (false == rc)
1818 DC_ERROR("GSL: Timeout on reset trigger!\n");
1819
1820 return rc;
1821}
1822
1823static void dcn10_enable_timing_synchronization(
fb3466a4 1824 struct dc *dc,
70ccab60
HW		 1825 int group_index,
1826 int group_size,
1827 struct pipe_ctx *grouped_pipes[])
1828{
1829 struct dc_context *dc_ctx = dc->ctx;
1830 int i;
1831
1832 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1833
1834 for (i = 1; i < group_size; i++)
6b670fa9
HW		 1835 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1836 grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst);
70ccab60
HW		 1837
1838
1839 DC_SYNC_INFO("Waiting for trigger\n");
1840
1841 /* Need to get only check 1 pipe for having reset as all the others are
1842 * synchronized. Look at last pipe programmed to reset.
1843 */
6b670fa9 1844 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
70ccab60 1845 for (i = 1; i < group_size; i++)
6b670fa9
HW		 1846 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1847 grouped_pipes[i]->stream_res.tg);
70ccab60
HW		 1848
1849 DC_SYNC_INFO("Sync complete\n");
1850}
1851
c9742685 1852static void print_rq_dlg_ttu(
fb3466a4 1853 struct dc *core_dc,
c9742685
DL		 1854 struct pipe_ctx *pipe_ctx)
1855{
1856 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1857 "\n============== DML TTU Output parameters [%d] ==============\n"
1858 "qos_level_low_wm: %d, \n"
1859 "qos_level_high_wm: %d, \n"
1860 "min_ttu_vblank: %d, \n"
1861 "qos_level_flip: %d, \n"
1862 "refcyc_per_req_delivery_l: %d, \n"
1863 "qos_level_fixed_l: %d, \n"
1864 "qos_ramp_disable_l: %d, \n"
1865 "refcyc_per_req_delivery_pre_l: %d, \n"
1866 "refcyc_per_req_delivery_c: %d, \n"
1867 "qos_level_fixed_c: %d, \n"
1868 "qos_ramp_disable_c: %d, \n"
1869 "refcyc_per_req_delivery_pre_c: %d\n"
1870 "=============================================================\n",
1871 pipe_ctx->pipe_idx,
1872 pipe_ctx->ttu_regs.qos_level_low_wm,
1873 pipe_ctx->ttu_regs.qos_level_high_wm,
1874 pipe_ctx->ttu_regs.min_ttu_vblank,
1875 pipe_ctx->ttu_regs.qos_level_flip,
1876 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1877 pipe_ctx->ttu_regs.qos_level_fixed_l,
1878 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1879 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1880 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1881 pipe_ctx->ttu_regs.qos_level_fixed_c,
1882 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1883 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1884 );
1885
1886 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1887 "\n============== DML DLG Output parameters [%d] ==============\n"
1888 "refcyc_h_blank_end: %d, \n"
1889 "dlg_vblank_end: %d, \n"
1890 "min_dst_y_next_start: %d, \n"
1891 "refcyc_per_htotal: %d, \n"
1892 "refcyc_x_after_scaler: %d, \n"
1893 "dst_y_after_scaler: %d, \n"
1894 "dst_y_prefetch: %d, \n"
1895 "dst_y_per_vm_vblank: %d, \n"
1896 "dst_y_per_row_vblank: %d, \n"
1897 "ref_freq_to_pix_freq: %d, \n"
1898 "vratio_prefetch: %d, \n"
1899 "refcyc_per_pte_group_vblank_l: %d, \n"
1900 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1901 "dst_y_per_pte_row_nom_l: %d, \n"
1902 "refcyc_per_pte_group_nom_l: %d, \n",
1903 pipe_ctx->pipe_idx,
1904 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1905 pipe_ctx->dlg_regs.dlg_vblank_end,
1906 pipe_ctx->dlg_regs.min_dst_y_next_start,
1907 pipe_ctx->dlg_regs.refcyc_per_htotal,
1908 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1909 pipe_ctx->dlg_regs.dst_y_after_scaler,
1910 pipe_ctx->dlg_regs.dst_y_prefetch,
1911 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1912 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1913 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1914 pipe_ctx->dlg_regs.vratio_prefetch,
1915 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1916 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1917 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1918 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1919 );
1920
1921 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1922 "\ndst_y_per_meta_row_nom_l: %d, \n"
1923 "refcyc_per_meta_chunk_nom_l: %d, \n"
1924 "refcyc_per_line_delivery_pre_l: %d, \n"
1925 "refcyc_per_line_delivery_l: %d, \n"
1926 "vratio_prefetch_c: %d, \n"
1927 "refcyc_per_pte_group_vblank_c: %d, \n"
1928 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1929 "dst_y_per_pte_row_nom_c: %d, \n"
1930 "refcyc_per_pte_group_nom_c: %d, \n"
1931 "dst_y_per_meta_row_nom_c: %d, \n"
1932 "refcyc_per_meta_chunk_nom_c: %d, \n"
1933 "refcyc_per_line_delivery_pre_c: %d, \n"
1934 "refcyc_per_line_delivery_c: %d \n"
1935 "========================================================\n",
1936 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1937 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1938 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1939 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1940 pipe_ctx->dlg_regs.vratio_prefetch_c,
1941 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1942 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1943 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1944 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1945 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1946 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1947 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1948 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1949 );
1950
1951 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1952 "\n============== DML RQ Output parameters [%d] ==============\n"
1953 "chunk_size: %d \n"
1954 "min_chunk_size: %d \n"
1955 "meta_chunk_size: %d \n"
1956 "min_meta_chunk_size: %d \n"
1957 "dpte_group_size: %d \n"
1958 "mpte_group_size: %d \n"
1959 "swath_height: %d \n"
1960 "pte_row_height_linear: %d \n"
1961 "========================================================\n",
1962 pipe_ctx->pipe_idx,
1963 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1964 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1965 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1966 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1967 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1968 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1969 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1970 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1971 );
1972}
1973
70ccab60 1974static void dcn10_power_on_fe(
fb3466a4 1975 struct dc *dc,
70ccab60 1976 struct pipe_ctx *pipe_ctx,
608ac7bb 1977 struct dc_state *context)
70ccab60 1978{
3be5262e 1979 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
184debdb 1980 struct dce_hwseq *hws = dc->hwseq;
70ccab60 1981
fb3466a4 1982 if (dc->debug.sanity_checks) {
665da60f
CM		 1983 verify_allow_pstate_change_high(dc->hwseq);
1984 }
1985
184debdb 1986 power_on_plane(dc->hwseq,
cfe4645e 1987 pipe_ctx->pipe_idx);
70ccab60 1988
c9742685 1989 /* enable DCFCLK current DCHUB */
d21becbe
TC		 1990 REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1991 HUBP_CLOCK_ENABLE, 1);
1992
1993 /* make sure OPP_PIPE_CLOCK_EN = 1 */
6b670fa9 1994 REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
d21becbe 1995 OPP_PIPE_CLOCK_EN, 1);
51666631 1996 /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
c9742685 1997
3be5262e 1998 if (plane_state) {
61a44fc6 1999 dm_logger_write(dc->ctx->logger, LOG_DC,
c9742685
DL		 2000 "Pipe:%d 0x%x: addr hi:0x%x, "
2001 "addr low:0x%x, "
2002 "src: %d, %d, %d,"
2003 " %d; dst: %d, %d, %d, %d;\n",
70ccab60 2004 pipe_ctx->pipe_idx,
3be5262e
HW		 2005 plane_state,
2006 plane_state->address.grph.addr.high_part,
2007 plane_state->address.grph.addr.low_part,
2008 plane_state->src_rect.x,
2009 plane_state->src_rect.y,
2010 plane_state->src_rect.width,
2011 plane_state->src_rect.height,
2012 plane_state->dst_rect.x,
2013 plane_state->dst_rect.y,
2014 plane_state->dst_rect.width,
2015 plane_state->dst_rect.height);
c9742685 2016
61a44fc6 2017 dm_logger_write(dc->ctx->logger, LOG_DC,
3eea71e3 2018 "Pipe %d: width, height, x, y format:%d\n"
c9742685
DL		 2019 "viewport:%d, %d, %d, %d\n"
2020 "recout: %d, %d, %d, %d\n",
2021 pipe_ctx->pipe_idx,
3eea71e3 2022 plane_state->format,
6702a9ac
HW		 2023 pipe_ctx->plane_res.scl_data.viewport.width,
2024 pipe_ctx->plane_res.scl_data.viewport.height,
2025 pipe_ctx->plane_res.scl_data.viewport.x,
2026 pipe_ctx->plane_res.scl_data.viewport.y,
2027 pipe_ctx->plane_res.scl_data.recout.width,
2028 pipe_ctx->plane_res.scl_data.recout.height,
2029 pipe_ctx->plane_res.scl_data.recout.x,
2030 pipe_ctx->plane_res.scl_data.recout.y);
c9742685 2031 print_rq_dlg_ttu(dc, pipe_ctx);
70ccab60 2032 }
665da60f 2033
fb3466a4 2034 if (dc->debug.sanity_checks) {
665da60f
CM		 2035 verify_allow_pstate_change_high(dc->hwseq);
2036 }
70ccab60
HW		 2037}
2038
2039static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2040{
d94585a0 2041 struct dpp_grph_csc_adjustment adjust;
70ccab60
HW		 2042 memset(&adjust, 0, sizeof(adjust));
2043 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2044
2045
4fa086b9 2046 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
70ccab60
HW		 2047 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2048 adjust.temperature_matrix[0] =
2049 pipe_ctx->stream->
4fa086b9 2050 gamut_remap_matrix.matrix[0];
70ccab60
HW		 2051 adjust.temperature_matrix[1] =
2052 pipe_ctx->stream->
4fa086b9 2053 gamut_remap_matrix.matrix[1];
70ccab60
HW		 2054 adjust.temperature_matrix[2] =
2055 pipe_ctx->stream->
4fa086b9 2056 gamut_remap_matrix.matrix[2];
70ccab60
HW		 2057 adjust.temperature_matrix[3] =
2058 pipe_ctx->stream->
4fa086b9 2059 gamut_remap_matrix.matrix[4];
70ccab60
HW		 2060 adjust.temperature_matrix[4] =
2061 pipe_ctx->stream->
4fa086b9 2062 gamut_remap_matrix.matrix[5];
70ccab60
HW		 2063 adjust.temperature_matrix[5] =
2064 pipe_ctx->stream->
4fa086b9 2065 gamut_remap_matrix.matrix[6];
70ccab60
HW		 2066 adjust.temperature_matrix[6] =
2067 pipe_ctx->stream->
4fa086b9 2068 gamut_remap_matrix.matrix[8];
70ccab60
HW		 2069 adjust.temperature_matrix[7] =
2070 pipe_ctx->stream->
4fa086b9 2071 gamut_remap_matrix.matrix[9];
70ccab60
HW		 2072 adjust.temperature_matrix[8] =
2073 pipe_ctx->stream->
4fa086b9 2074 gamut_remap_matrix.matrix[10];
70ccab60
HW		 2075 }
2076
d94585a0 2077 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
70ccab60
HW		 2078}
2079
abe07e80
YHL		 2080
2081static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2082 enum dc_color_space colorspace,
2083 uint16_t *matrix)
2084{
2085 int i;
2086 struct out_csc_color_matrix tbl_entry;
2087
4fa086b9 2088 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
abe07e80
YHL		 2089 == true) {
2090 enum dc_color_space color_space =
4fa086b9 2091 pipe_ctx->stream->output_color_space;
abe07e80
YHL		 2092
2093 //uint16_t matrix[12];
2094 for (i = 0; i < 12; i++)
4fa086b9 2095 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
abe07e80
YHL		 2096
2097 tbl_entry.color_space = color_space;
2098 //tbl_entry.regval = matrix;
d94585a0 2099 pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
abe07e80
YHL		 2100 }
2101}
4b28b76b
DL		 2102static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2103{
3be5262e 2104 if (pipe_ctx->plane_state->visible)
4b28b76b
DL		 2105 return true;
2106 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
2107 return true;
2108 return false;
2109}
2110
2111static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2112{
3be5262e 2113 if (pipe_ctx->plane_state->visible)
4b28b76b
DL		 2114 return true;
2115 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
2116 return true;
2117 return false;
2118}
2119
2120static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2121{
3be5262e 2122 if (pipe_ctx->plane_state->visible)
4b28b76b
DL		 2123 return true;
2124 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
2125 return true;
2126 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
2127 return true;
2128 return false;
2129}
2130
ad327346
DL		 2131static bool is_rgb_cspace(enum dc_color_space output_color_space)
2132{
2133 switch (output_color_space) {
2134 case COLOR_SPACE_SRGB:
2135 case COLOR_SPACE_SRGB_LIMITED:
2136 case COLOR_SPACE_2020_RGB_FULLRANGE:
2137 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
2138 case COLOR_SPACE_ADOBERGB:
2139 return true;
2140 case COLOR_SPACE_YCBCR601:
2141 case COLOR_SPACE_YCBCR709:
2142 case COLOR_SPACE_YCBCR601_LIMITED:
2143 case COLOR_SPACE_YCBCR709_LIMITED:
2144 case COLOR_SPACE_2020_YCBCR:
2145 return false;
2146 default:
2147 /* Add a case to switch */
2148 BREAK_TO_DEBUGGER();
2149 return false;
2150 }
2151}
2152
87449a90
AK		 2153static void dcn10_get_surface_visual_confirm_color(
2154 const struct pipe_ctx *pipe_ctx,
2155 struct tg_color *color)
2156{
2157 uint32_t color_value = MAX_TG_COLOR_VALUE;
2158
6702a9ac 2159 switch (pipe_ctx->plane_res.scl_data.format) {
87449a90
AK		 2160 case PIXEL_FORMAT_ARGB8888:
2161 /* set boarder color to red */
2162 color->color_r_cr = color_value;
2163 break;
2164
2165 case PIXEL_FORMAT_ARGB2101010:
2166 /* set boarder color to blue */
2167 color->color_b_cb = color_value;
2168 break;
2169 case PIXEL_FORMAT_420BPP8:
2170 /* set boarder color to green */
2171 color->color_g_y = color_value;
2172 break;
2173 case PIXEL_FORMAT_420BPP10:
2174 /* set boarder color to yellow */
2175 color->color_g_y = color_value;
2176 color->color_r_cr = color_value;
2177 break;
2178 case PIXEL_FORMAT_FP16:
2179 /* set boarder color to white */
2180 color->color_r_cr = color_value;
2181 color->color_b_cb = color_value;
2182 color->color_g_y = color_value;
2183 break;
2184 default:
2185 break;
2186 }
2187}
2188
8feabd03 2189static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
0cb8a881
YHL		 2190 struct vm_system_aperture_param *apt,
2191 struct dce_hwseq *hws)
2192{
2193 PHYSICAL_ADDRESS_LOC physical_page_number;
2194 uint32_t logical_addr_low;
2195 uint32_t logical_addr_high;
2196
2197 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
2198 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
2199 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
2200 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
2201
2202 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2203 LOGICAL_ADDR, &logical_addr_low);
2204
2205 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2206 LOGICAL_ADDR, &logical_addr_high);
2207
2208 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
2209 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
2210 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
2211}
2212
2213/* Temporary read settings, future will get values from kmd directly */
8feabd03 2214static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
0cb8a881
YHL		 2215 struct vm_context0_param *vm0,
2216 struct dce_hwseq *hws)
2217{
2218 PHYSICAL_ADDRESS_LOC fb_base;
2219 PHYSICAL_ADDRESS_LOC fb_offset;
2220 uint32_t fb_base_value;
2221 uint32_t fb_offset_value;
2222
2223 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
2224 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
2225
2226 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
2227 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
2228 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
2229 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
2230
2231 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
2232 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
2233 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
2234 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
2235
2236 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
2237 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
2238 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
2239 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
2240
2241 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
2242 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
2243 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
2244 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
2245
2246 /*
2247 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
2248 * Therefore we need to do
2249 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
2250 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
2251 */
2252 fb_base.quad_part = (uint64_t)fb_base_value << 24;
2253 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
2254 vm0->pte_base.quad_part += fb_base.quad_part;
2255 vm0->pte_base.quad_part -= fb_offset.quad_part;
2256}
2257
8feabd03 2258static void dcn10_program_pte_vm(struct hubp *hubp,
0cb8a881
YHL		 2259 enum surface_pixel_format format,
2260 union dc_tiling_info *tiling_info,
2261 enum dc_rotation_angle rotation,
2262 struct dce_hwseq *hws)
2263{
8feabd03 2264 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
0cb8a881
YHL		 2265 struct vm_system_aperture_param apt = { {{ 0 } } };
2266 struct vm_context0_param vm0 = { { { 0 } } };
2267
2268
8feabd03
YHL		 2269 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
2270 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
0cb8a881 2271
8feabd03
YHL		 2272 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
2273 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
0cb8a881
YHL		 2274}
2275
70ccab60 2276static void update_dchubp_dpp(
fb3466a4 2277 struct dc *dc,
70ccab60 2278 struct pipe_ctx *pipe_ctx,
608ac7bb 2279 struct dc_state *context)
70ccab60 2280{
184debdb 2281 struct dce_hwseq *hws = dc->hwseq;
8feabd03 2282 struct hubp *hubp = pipe_ctx->plane_res.hubp;
d94585a0 2283 struct dpp *dpp = pipe_ctx->plane_res.dpp;
3be5262e
HW		 2284 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2285 union plane_size size = plane_state->plane_size;
cc408d72
DL		 2286 struct mpcc_cfg mpcc_cfg = {0};
2287 struct pipe_ctx *top_pipe;
3be5262e 2288 bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
cbfd33fd 2289
ba326a91 2290 /* TODO: proper fix once fpga works */
70ccab60
HW		 2291 /* depends on DML calculation, DPP clock value may change dynamically */
2292 enable_dppclk(
184debdb 2293 dc->hwseq,
70ccab60 2294 pipe_ctx->pipe_idx,
10688217 2295 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
9037d802 2296 context->bw.dcn.calc_clk.dppclk_div);
608ac7bb 2297 dc->current_state->bw.dcn.cur_clk.dppclk_div =
c66a54dc
DL		 2298 context->bw.dcn.calc_clk.dppclk_div;
2299 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
70ccab60 2300
184debdb
DL		 2301 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2302 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2303 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2304 */
6b670fa9 2305 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
70ccab60 2306
8feabd03
YHL		 2307 hubp->funcs->hubp_setup(
2308 hubp,
70ccab60
HW		 2309 &pipe_ctx->dlg_regs,
2310 &pipe_ctx->ttu_regs,
2311 &pipe_ctx->rq_regs,
2312 &pipe_ctx->pipe_dlg_param);
2313
6702a9ac 2314 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
70ccab60 2315
fb3466a4 2316 if (dc->config.gpu_vm_support)
0cb8a881 2317 dcn10_program_pte_vm(
8feabd03 2318 pipe_ctx->plane_res.hubp,
3be5262e
HW		 2319 plane_state->format,
2320 &plane_state->tiling_info,
0cb8a881
YHL		 2321 plane_state->rotation,
2322 hws
2323 );
70ccab60 2324
d94585a0 2325 dpp->funcs->ipp_setup(dpp,
3be5262e 2326 plane_state->format,
264efa31 2327 EXPANSION_MODE_ZERO);
70ccab60 2328
8feabd03 2329 mpcc_cfg.dpp_id = hubp->inst;
7f4a7253
EB		 2330 mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
2331 mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree);
cc408d72
DL		 2332 for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
2333 mpcc_cfg.z_index++;
fb3466a4 2334 if (dc->debug.surface_visual_confirm)
cc408d72
DL		 2335 dcn10_get_surface_visual_confirm_color(
2336 pipe_ctx, &mpcc_cfg.black_color);
f0558542 2337 else
cc408d72
DL		 2338 color_space_to_black_color(
2339 dc, pipe_ctx->stream->output_color_space,
2340 &mpcc_cfg.black_color);
f0558542 2341 mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
ad327346
DL		 2342 /* DCN1.0 has output CM before MPC which seems to screw with
2343 * pre-multiplied alpha.
2344 */
2345 mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
4fa086b9 2346 pipe_ctx->stream->output_color_space)
ad327346 2347 && per_pixel_alpha;
8feabd03
YHL		 2348 hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
2349 hubp->opp_id = mpcc_cfg.opp_id;
70ccab60 2350
6702a9ac
HW		 2351 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2352 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
70ccab60 2353 /* scaler configuration */
d94585a0
YHL		 2354 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2355 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2356
8feabd03 2357 hubp->funcs->mem_program_viewport(hubp,
6702a9ac 2358 &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);
70ccab60
HW		 2359
2360 /*gamut remap*/
2361 program_gamut_remap(pipe_ctx);
2362
69b516c9
S		 2363 program_csc_matrix(pipe_ctx,
2364 pipe_ctx->stream->output_color_space,
2365 pipe_ctx->stream->csc_color_matrix.matrix);
70ccab60 2366
8feabd03
YHL		 2367 hubp->funcs->hubp_program_surface_config(
2368 hubp,
3be5262e
HW		 2369 plane_state->format,
2370 &plane_state->tiling_info,
70ccab60 2371 &size,
3be5262e
HW		 2372 plane_state->rotation,
2373 &plane_state->dcc,
2374 plane_state->horizontal_mirror);
70ccab60 2375
50d4cfdc
YS		 2376 dc->hwss.update_plane_addr(dc, pipe_ctx);
2377
8eb5def9 2378 if (is_pipe_tree_visible(pipe_ctx))
8feabd03 2379 hubp->funcs->set_blank(hubp, false);
70ccab60
HW		 2380}
2381
9d6f264b 2382
70ccab60 2383static void program_all_pipe_in_tree(
fb3466a4 2384 struct dc *dc,
70ccab60 2385 struct pipe_ctx *pipe_ctx,
608ac7bb 2386 struct dc_state *context)
70ccab60
HW		 2387{
2388 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
2389
1a2c82a2 2390 if (pipe_ctx->top_pipe == NULL) {
70ccab60
HW		 2391
2392 /* lock otg_master_update to process all pipes associated with
2393 * this OTG. this is done only one time.
2394 */
1a2c82a2 2395 /* watermark is for all pipes */
08b16886 2396 program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
2b13d7d3 2397
fb3466a4 2398 if (dc->debug.sanity_checks) {
2b13d7d3
TC		 2399 /* pstate stuck check after watermark update */
2400 verify_allow_pstate_change_high(dc->hwseq);
2401 }
2402
6b670fa9 2403 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
cbfd33fd 2404
6b670fa9
HW		 2405 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2406 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2407 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2408 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2409 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
cbfd33fd 2410
6b670fa9
HW		 2411 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2412 pipe_ctx->stream_res.tg);
2413 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
1a2c82a2 2414 }
cbfd33fd 2415
3be5262e 2416 if (pipe_ctx->plane_state != NULL) {
067c878a
YS		 2417 struct dc_cursor_position position = { 0 };
2418 struct pipe_ctx *cur_pipe_ctx =
2419 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2420
1a2c82a2 2421 dcn10_power_on_fe(dc, pipe_ctx, context);
9d6f264b
YS		 2422
2423 /* temporary dcn1 wa:
5667ff5c
DA		 2424 * watermark update requires toggle after a/b/c/d sets are programmed
2425 * if hubp is pg then wm value doesn't get properaged to hubp
2426 * need to toggle after ungate to ensure wm gets to hubp.
2427 *
2428 * final solution: we need to get SMU to do the toggle as
2429 * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
2430 * both driver and fw accessing same register
2431 */
9d6f264b
YS		 2432 toggle_watermark_change_req(dc->hwseq);
2433
70ccab60 2434 update_dchubp_dpp(dc, pipe_ctx, context);
067c878a
YS		 2435
2436 /* TODO: this is a hack w/a for switching from mpo to pipe split */
2437 dc_stream_set_cursor_position(pipe_ctx->stream, &position);
2438
2439 dc_stream_set_cursor_attributes(pipe_ctx->stream,
2440 &pipe_ctx->stream->cursor_attributes);
2441
2442 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
2443 dc->hwss.set_input_transfer_func(
2444 pipe_ctx, pipe_ctx->plane_state);
2445 dc->hwss.set_output_transfer_func(
2446 pipe_ctx, pipe_ctx->stream);
2447 }
70ccab60
HW		 2448 }
2449
fb3466a4 2450 if (dc->debug.sanity_checks) {
2b13d7d3
TC		 2451 /* pstate stuck check after each pipe is programmed */
2452 verify_allow_pstate_change_high(dc->hwseq);
2453 }
2454
e1b522bf 2455 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
70ccab60
HW		 2456 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2457}
2458
2459static void dcn10_pplib_apply_display_requirements(
fb3466a4 2460 struct dc *dc,
608ac7bb 2461 struct dc_state *context)
70ccab60
HW		 2462{
2463 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2464
2465 pp_display_cfg->all_displays_in_sync = false;/*todo*/
2466 pp_display_cfg->nb_pstate_switch_disable = false;
c66a54dc
DL		 2467 pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2468 pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
2469 pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2470 pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
70ccab60 2471 pp_display_cfg->avail_mclk_switch_time_us =
c66a54dc 2472 context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
70ccab60 2473 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
c66a54dc
DL		 2474 context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
2475 pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2476 pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
70ccab60
HW		 2477 dce110_fill_display_configs(context, pp_display_cfg);
2478
2479 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2480 struct dm_pp_display_configuration)) != 0)
2481 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2482
2483 dc->prev_display_config = *pp_display_cfg;
2484}
2485
6bf52028
HW		 2486static void optimize_shared_resources(struct dc *dc)
2487{
2488 if (dc->current_state->stream_count == 0) {
2489 apply_DEGVIDCN10_253_wa(dc);
2490 /* S0i2 message */
2491 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
2492 }
441ad741
EY		 2493
2494 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2495 dcn_bw_notify_pplib_of_wm_ranges(dc);
6bf52028
HW		 2496}
2497
2498static void ready_shared_resources(struct dc *dc, struct dc_state *context)
2499{
2500 if (dc->current_state->stream_count == 0 &&
2501 !dc->debug.disable_stutter)
2502 undo_DEGVIDCN10_253_wa(dc);
2503
2504 /* S0i2 message */
2505 if (dc->current_state->stream_count == 0 &&
2506 context->stream_count != 0)
2507 dcn10_pplib_apply_display_requirements(dc, context);
2508}
2509
70ccab60 2510static void dcn10_apply_ctx_for_surface(
fb3466a4 2511 struct dc *dc,
3e9ad616
EY		 2512 const struct dc_stream_state *stream,
2513 int num_planes,
608ac7bb 2514 struct dc_state *context)
70ccab60 2515{
7f10f3c2 2516 int i, be_idx;
70ccab60 2517
fb3466a4 2518 if (dc->debug.sanity_checks)
2b13d7d3
TC		 2519 verify_allow_pstate_change_high(dc->hwseq);
2520
3e9ad616
EY		 2521 be_idx = -1;
2522 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2523 if (stream == context->res_ctx.pipe_ctx[i].stream) {
2524 be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
7f10f3c2 2525 break;
3e9ad616
EY		 2526 }
2527 }
2528
2529 ASSERT(be_idx != -1);
2530
2531 if (num_planes == 0) {
2532 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2533 struct pipe_ctx *old_pipe_ctx =
608ac7bb 2534 &dc->current_state->res_ctx.pipe_ctx[i];
3e9ad616 2535
4e772ae5
YS		 2536 if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) {
2537 old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true);
3e9ad616 2538 dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx);
4e772ae5 2539 }
3e9ad616
EY		 2540 }
2541 return;
2542 }
7f10f3c2 2543
cfe4645e 2544 /* reset unused mpcc */
71a2f23e 2545 for (i = 0; i < dc->res_pool->pipe_count; i++) {
cfe4645e
DL		 2546 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2547 struct pipe_ctx *old_pipe_ctx =
608ac7bb 2548 &dc->current_state->res_ctx.pipe_ctx[i];
7f10f3c2 2549
3be5262e 2550 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
7f10f3c2
TC		 2551 continue;
2552
4bdbab3e
EY		 2553 /*
2554 * Powergate reused pipes that are not powergated
2555 * fairly hacky right now, using opp_id as indicator
2556 */
7f10f3c2 2557
3be5262e 2558 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
8feabd03 2559 if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
4bdbab3e 2560 dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
aa985070
EY		 2561 /*
2562 * power down fe will unlock when calling reset, need
2563 * to lock it back here. Messy, need rework.
2564 */
6b670fa9 2565 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
aa985070 2566 }
4bdbab3e 2567 }
cfe4645e 2568
7f10f3c2 2569
3be5262e 2570 if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state)
cfe4645e 2571 || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
6b670fa9 2572 if (old_pipe_ctx->stream_res.tg->inst != be_idx)
7f10f3c2
TC		 2573 continue;
2574
71a2f23e
EY		 2575 if (!old_pipe_ctx->top_pipe) {
2576 ASSERT(0);
2577 continue;
2578 }
2579
4bdbab3e 2580 /* reset mpc */
cc408d72
DL		 2581 dc->res_pool->mpc->funcs->remove(
2582 dc->res_pool->mpc,
7f4a7253
EB		 2583 &(old_pipe_ctx->stream_res.opp->mpc_tree),
2584 old_pipe_ctx->stream_res.opp->inst,
cc408d72 2585 old_pipe_ctx->pipe_idx);
8feabd03 2586 old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true;
2b13d7d3 2587
6be425f3
EY		 2588 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2589 "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
2590 old_pipe_ctx->mpcc->inst);*/
2591
fb3466a4 2592 if (dc->debug.sanity_checks)
2b13d7d3
TC		 2593 verify_allow_pstate_change_high(dc->hwseq);
2594
cfe4645e
DL		 2595 old_pipe_ctx->top_pipe = NULL;
2596 old_pipe_ctx->bottom_pipe = NULL;
3be5262e 2597 old_pipe_ctx->plane_state = NULL;
50d4cfdc 2598 old_pipe_ctx->stream = NULL;
cfe4645e
DL		 2599
2600 dm_logger_write(dc->ctx->logger, LOG_DC,
2601 "Reset mpcc for pipe %d\n",
2602 old_pipe_ctx->pipe_idx);
2603 }
71a2f23e 2604 }
cfe4645e 2605
70ccab60
HW		 2606 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2607 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2608
3e9ad616 2609 if (pipe_ctx->stream != stream)
70ccab60
HW		 2610 continue;
2611
2612 /* looking for top pipe to program */
f0558542 2613 if (!pipe_ctx->top_pipe)
70ccab60
HW		 2614 program_all_pipe_in_tree(dc, pipe_ctx, context);
2615 }
2616
c9742685
DL		 2617 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2618 "\n============== Watermark parameters ==============\n"
2619 "a.urgent_ns: %d \n"
2620 "a.cstate_enter_plus_exit: %d \n"
2621 "a.cstate_exit: %d \n"
2622 "a.pstate_change: %d \n"
2623 "a.pte_meta_urgent: %d \n"
2624 "b.urgent_ns: %d \n"
2625 "b.cstate_enter_plus_exit: %d \n"
2626 "b.cstate_exit: %d \n"
2627 "b.pstate_change: %d \n"
2628 "b.pte_meta_urgent: %d \n",
2629 context->bw.dcn.watermarks.a.urgent_ns,
2630 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2631 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2632 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2633 context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2634 context->bw.dcn.watermarks.b.urgent_ns,
2635 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2636 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2637 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2638 context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2639 );
2640 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2641 "\nc.urgent_ns: %d \n"
2642 "c.cstate_enter_plus_exit: %d \n"
2643 "c.cstate_exit: %d \n"
2644 "c.pstate_change: %d \n"
2645 "c.pte_meta_urgent: %d \n"
2646 "d.urgent_ns: %d \n"
2647 "d.cstate_enter_plus_exit: %d \n"
2648 "d.cstate_exit: %d \n"
2649 "d.pstate_change: %d \n"
2650 "d.pte_meta_urgent: %d \n"
2651 "========================================================\n",
2652 context->bw.dcn.watermarks.c.urgent_ns,
2653 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2654 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2655 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2656 context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2657 context->bw.dcn.watermarks.d.urgent_ns,
2658 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2659 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2660 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2661 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2662 );
2b13d7d3 2663
fb3466a4 2664 if (dc->debug.sanity_checks)
2b13d7d3 2665 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 2666}
2667
2668static void dcn10_set_bandwidth(
fb3466a4 2669 struct dc *dc,
608ac7bb 2670 struct dc_state *context,
70ccab60
HW		 2671 bool decrease_allowed)
2672{
5f06b3cf
TC		 2673 struct pp_smu_display_requirement_rv *smu_req_cur =
2674 &dc->res_pool->pp_smu_req;
2675 struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2676 struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
70ccab60 2677
fb3466a4 2678 if (dc->debug.sanity_checks) {
665da60f
CM		 2679 verify_allow_pstate_change_high(dc->hwseq);
2680 }
2681
70ccab60
HW		 2682 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2683 return;
2684
c66a54dc 2685 if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
608ac7bb 2686 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
70ccab60
HW		 2687 dc->res_pool->display_clock->funcs->set_clock(
2688 dc->res_pool->display_clock,
9037d802 2689 context->bw.dcn.calc_clk.dispclk_khz);
608ac7bb 2690 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
c66a54dc 2691 context->bw.dcn.calc_clk.dispclk_khz;
70ccab60 2692 }
c66a54dc 2693 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
608ac7bb 2694 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
5f06b3cf
TC		 2695 smu_req.hard_min_dcefclk_khz =
2696 context->bw.dcn.calc_clk.dcfclk_khz;
70ccab60 2697 }
c66a54dc 2698 if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
608ac7bb 2699 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
5f06b3cf 2700 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
c66a54dc
DL		 2701 }
2702 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
608ac7bb
JZ		 2703 > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2704 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
c66a54dc
DL		 2705 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2706 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2707 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2708 }
5f06b3cf
TC		 2709
2710 smu_req.display_count = context->stream_count;
2711
2712 if (pp_smu->set_display_requirement)
2713 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2714
2715 *smu_req_cur = smu_req;
2716
c66a54dc
DL		 2717 /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2718 if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
608ac7bb
JZ		 2719 < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2720 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
c66a54dc
DL		 2721 context->bw.dcn.calc_clk.dram_ccm_us;
2722 context->bw.dcn.cur_clk.dram_ccm_us =
2723 context->bw.dcn.calc_clk.dram_ccm_us;
2724 }
2725 if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
608ac7bb
JZ		 2726 < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2727 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
c66a54dc
DL		 2728 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2729 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2730 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
70ccab60
HW		 2731 }
2732 dcn10_pplib_apply_display_requirements(dc, context);
2b13d7d3 2733
fb3466a4 2734 if (dc->debug.sanity_checks) {
665da60f
CM		 2735 verify_allow_pstate_change_high(dc->hwseq);
2736 }
2737
2b13d7d3 2738 /* need to fix this function. not doing the right thing here */
70ccab60
HW		 2739}
2740
70ccab60
HW		 2741static void set_drr(struct pipe_ctx **pipe_ctx,
2742 int num_pipes, int vmin, int vmax)
2743{
2744 int i = 0;
2745 struct drr_params params = {0};
2746
2747 params.vertical_total_max = vmax;
2748 params.vertical_total_min = vmin;
2749
2750 /* TODO: If multiple pipes are to be supported, you need
2751 * some GSL stuff
2752 */
2753 for (i = 0; i < num_pipes; i++) {
6b670fa9 2754 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
70ccab60
HW		 2755 }
2756}
2757
2758static void get_position(struct pipe_ctx **pipe_ctx,
2759 int num_pipes,
2760 struct crtc_position *position)
2761{
2762 int i = 0;
2763
2764 /* TODO: handle pipes > 1
2765 */
2766 for (i = 0; i < num_pipes; i++)
6b670fa9 2767 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
70ccab60
HW		 2768}
2769
2770static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2771 int num_pipes, const struct dc_static_screen_events *events)
2772{
2773 unsigned int i;
2774 unsigned int value = 0;
2775
2776 if (events->surface_update)
2777 value |= 0x80;
2778 if (events->cursor_update)
2779 value |= 0x2;
2780
2781 for (i = 0; i < num_pipes; i++)
6b670fa9
HW		 2782 pipe_ctx[i]->stream_res.tg->funcs->
2783 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
70ccab60
HW		 2784}
2785
2786static void set_plane_config(
fb3466a4 2787 const struct dc *dc,
70ccab60
HW		 2788 struct pipe_ctx *pipe_ctx,
2789 struct resource_context *res_ctx)
2790{
2791 /* TODO */
2792 program_gamut_remap(pipe_ctx);
2793}
2794
4fac6da2 2795static void dcn10_config_stereo_parameters(
0971c40e 2796 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
7f5c22d1 2797{
4fa086b9 2798 enum view_3d_format view_format = stream->view_format;
7f5c22d1 2799 enum dc_timing_3d_format timing_3d_format =\
4fa086b9 2800 stream->timing.timing_3d_format;
7f5c22d1
VP		 2801 bool non_stereo_timing = false;
2802
2803 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2804 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2805 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2806 non_stereo_timing = true;
2807
2808 if (non_stereo_timing == false &&
2809 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2810
2811 flags->PROGRAM_STEREO = 1;
2812 flags->PROGRAM_POLARITY = 1;
2813 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2814 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2815 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2816 enum display_dongle_type dongle = \
d0778ebf 2817 stream->sink->link->ddc->dongle_type;
7f5c22d1
VP		 2818 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2819 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2820 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2821 flags->DISABLE_STEREO_DP_SYNC = 1;
2822 }
2823 flags->RIGHT_EYE_POLARITY =\
4fa086b9 2824 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
7f5c22d1
VP		 2825 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2826 flags->FRAME_PACKED = 1;
2827 }
2828
2829 return;
2830}
2831
fb3466a4 2832static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
7f5c22d1
VP		 2833{
2834 struct crtc_stereo_flags flags = { 0 };
0971c40e 2835 struct dc_stream_state *stream = pipe_ctx->stream;
7f5c22d1
VP		 2836
2837 dcn10_config_stereo_parameters(stream, &flags);
2838
a6a6cb34
HW		 2839 pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
2840 pipe_ctx->stream_res.opp,
7f5c22d1 2841 flags.PROGRAM_STEREO == 1 ? true:false,
4fa086b9 2842 stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
7f5c22d1 2843
6b670fa9
HW		 2844 pipe_ctx->stream_res.tg->funcs->program_stereo(
2845 pipe_ctx->stream_res.tg,
4fa086b9 2846 &stream->timing,
7f5c22d1
VP		 2847 &flags);
2848
7f5c22d1
VP		 2849 return;
2850}
2851
6be425f3 2852static void dcn10_wait_for_mpcc_disconnect(
fb3466a4 2853 struct dc *dc,
6be425f3
EY		 2854 struct resource_pool *res_pool,
2855 struct pipe_ctx *pipe_ctx)
87480687
EY		 2856{
2857 int i;
87480687 2858
fb3466a4 2859 if (dc->debug.sanity_checks) {
665da60f
CM		 2860 verify_allow_pstate_change_high(dc->hwseq);
2861 }
2862
a6a6cb34 2863 if (!pipe_ctx->stream_res.opp)
6be425f3
EY		 2864 return;
2865
2866 for (i = 0; i < MAX_PIPES; i++) {
a6a6cb34 2867 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
cc408d72 2868 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
a6a6cb34 2869 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
8feabd03 2870 res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
6be425f3
EY		 2871 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2872 "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2873 i);*/
87480687
EY		 2874 }
2875 }
6be425f3 2876
fb3466a4 2877 if (dc->debug.sanity_checks) {
665da60f
CM		 2878 verify_allow_pstate_change_high(dc->hwseq);
2879 }
2880
87480687
EY		 2881}
2882
4fac6da2 2883static bool dcn10_dummy_display_power_gating(
fb3466a4 2884 struct dc *dc,
4fac6da2
DL		 2885 uint8_t controller_id,
2886 struct dc_bios *dcb,
2b13d7d3
TC		 2887 enum pipe_gating_control power_gating)
2888{
2889 return true;
2890}
2891
2892void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2893{
3be5262e 2894 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
6b670fa9 2895 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2b13d7d3 2896
3be5262e 2897 if (plane_state == NULL)
2b13d7d3
TC		 2898 return;
2899
3be5262e 2900 plane_state->status.is_flip_pending =
8feabd03
YHL		 2901 pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2902 pipe_ctx->plane_res.hubp);
2b13d7d3 2903
8feabd03
YHL		 2904 plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2905 if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2b13d7d3 2906 tg->funcs->is_stereo_left_eye) {
3be5262e 2907 plane_state->status.is_right_eye =
6b670fa9 2908 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2b13d7d3
TC		 2909 }
2910}
4fac6da2 2911
0cb8a881
YHL		 2912
2913
70ccab60 2914static const struct hw_sequencer_funcs dcn10_funcs = {
1bf56e62 2915 .program_gamut_remap = program_gamut_remap,
abe07e80 2916 .program_csc_matrix = program_csc_matrix,
b02c3b05 2917 .init_hw = dcn10_init_hw,
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HW		 2918 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2919 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2920 .set_plane_config = set_plane_config,
503a7c6f 2921 .update_plane_addr = dcn10_update_plane_addr,
08b16886 2922 .update_dchub = dcn10_update_dchub,
2b13d7d3 2923 .update_pending_status = dcn10_update_pending_status,
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HW		 2924 .set_input_transfer_func = dcn10_set_input_transfer_func,
2925 .set_output_transfer_func = dcn10_set_output_transfer_func,
2926 .power_down = dce110_power_down,
2927 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2928 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2929 .update_info_frame = dce110_update_info_frame,
2930 .enable_stream = dce110_enable_stream,
2931 .disable_stream = dce110_disable_stream,
2932 .unblank_stream = dce110_unblank_stream,
4fac6da2 2933 .enable_display_power_gating = dcn10_dummy_display_power_gating,
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HW		 2934 .power_down_front_end = dcn10_power_down_fe,
2935 .power_on_front_end = dcn10_power_on_fe,
2936 .pipe_control_lock = dcn10_pipe_control_lock,
2937 .set_bandwidth = dcn10_set_bandwidth,
2938 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2939 .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2940 .set_drr = set_drr,
2941 .get_position = get_position,
7f5c22d1 2942 .set_static_screen_control = set_static_screen_control,
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CL		 2943 .setup_stereo = dcn10_setup_stereo,
2944 .set_avmute = dce110_set_avmute,
87480687 2945 .log_hw_state = dcn10_log_hw_state,
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HW		 2946 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2947 .ready_shared_resources = ready_shared_resources,
2948 .optimize_shared_resources = optimize_shared_resources,
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AJ		 2949 .edp_backlight_control = hwss_edp_backlight_control,
2950 .edp_power_control = hwss_edp_power_control
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HW		 2951};
2952
2953
fb3466a4 2954void dcn10_hw_sequencer_construct(struct dc *dc)
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HW		 2955{
2956 dc->hwss = dcn10_funcs;
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HW		 2957}
2958
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