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drm/amd/display: Refine disable VGA
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hw_sequencer.c
CommitLineData
70ccab60
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
70ccab60 27#include "core_types.h"
70ccab60 28#include "resource.h"
b02c3b05 29#include "custom_float.h"
70ccab60
HW		 30#include "dcn10_hw_sequencer.h"
31#include "dce110/dce110_hw_sequencer.h"
5aff86c1 32#include "dce/dce_hwseq.h"
70ccab60 33#include "abm.h"
214435ff 34#include "dcn10/dcn10_timing_generator.h"
587cdfe9
VP		 35#include "dcn10/dcn10_dpp.h"
36#include "dcn10/dcn10_mpc.h"
70ccab60
HW		 37#include "timing_generator.h"
38#include "opp.h"
39#include "ipp.h"
b02c3b05 40#include "mpc.h"
184debdb 41#include "reg_helper.h"
a6def445 42#include "custom_float.h"
86be9a04 43#include "dcn10_hubp.h"
70ccab60 44
184debdb
DL		 45#define CTX \
46 hws->ctx
47#define REG(reg)\
48 hws->regs->reg
70ccab60 49
184debdb
DL		 50#undef FN
51#define FN(reg_name, field_name) \
52 hws->shifts->field_name, hws->masks->field_name
70ccab60 53
fb3466a4 54static void log_mpc_crc(struct dc *dc)
71395011
TC		 55{
56 struct dc_context *dc_ctx = dc->ctx;
57 struct dce_hwseq *hws = dc->hwseq;
58
59 if (REG(MPC_CRC_RESULT_GB))
60 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
61 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
62 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
63 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
64 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
65}
66
eb4e33b7
TC		 67void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
68{
69 static const uint32_t ref_clk_mhz = 48;
70 static const unsigned int frac = 10;
71 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
72
73 DTN_INFO("%d.%d \t ",
74 us_x10 / frac,
75 us_x10 % frac);
76}
77
78#define DTN_INFO_MICRO_SEC(ref_cycle) \
79 print_microsec(dc_ctx, ref_cycle)
80
233dcd20
TC		 81struct dcn_hubbub_wm_set {
82 uint32_t wm_set;
83 uint32_t data_urgent;
84 uint32_t pte_meta_urgent;
85 uint32_t sr_enter;
86 uint32_t sr_exit;
87 uint32_t dram_clk_chanage;
88};
89
90struct dcn_hubbub_wm {
91 struct dcn_hubbub_wm_set sets[4];
92};
93
94static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,
95 struct dcn_hubbub_wm *wm)
96{
97 struct dcn_hubbub_wm_set *s;
98
99 s = &wm->sets[0];
100 s->wm_set = 0;
101 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
102 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
103 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
104 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
105 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
106
107 s = &wm->sets[1];
108 s->wm_set = 1;
109 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
110 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
111 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
112 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
113 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
114
115 s = &wm->sets[2];
116 s->wm_set = 2;
117 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
118 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
119 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
120 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
121 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
122
123 s = &wm->sets[3];
124 s->wm_set = 3;
125 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
126 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
127 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
128 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
129 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
130}
131
fb3466a4 132static void dcn10_log_hubbub_state(struct dc *dc)
233dcd20
TC		 133{
134 struct dc_context *dc_ctx = dc->ctx;
135 struct dcn_hubbub_wm wm;
136 int i;
137
138 dcn10_hubbub_wm_read_state(dc->hwseq, &wm);
139
140 DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
141 "sr_enter \t sr_exit \t dram_clk_change \n");
142
143 for (i = 0; i < 4; i++) {
144 struct dcn_hubbub_wm_set *s;
145
146 s = &wm.sets[i];
147 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
148 DTN_INFO_MICRO_SEC(s->data_urgent);
149 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
150 DTN_INFO_MICRO_SEC(s->sr_enter);
151 DTN_INFO_MICRO_SEC(s->sr_exit);
152 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
153 DTN_INFO("\n");
154 }
155
156 DTN_INFO("\n");
157}
158
fb3466a4 159static void dcn10_log_hw_state(struct dc *dc)
71395011
TC		 160{
161 struct dc_context *dc_ctx = dc->ctx;
162 struct resource_pool *pool = dc->res_pool;
163 int i;
164
165 DTN_INFO_BEGIN();
166
233dcd20
TC		 167 dcn10_log_hubbub_state(dc);
168
eb4e33b7
TC		 169 DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
170 "rotation \t mirror \t sw_mode \t "
171 "dcc_en \t blank_en \t ttu_dis \t underflow \t "
71395011
TC		 172 "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
173
174 for (i = 0; i < pool->pipe_count; i++) {
8feabd03 175 struct hubp *hubp = pool->hubps[i];
71395011
TC		 176 struct dcn_hubp_state s;
177
8feabd03 178 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
71395011 179
eb4e33b7
TC		 180 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
181 "%xh \t %xh \t %xh \t "
182 "%d \t %d \t %d \t %xh \t",
71395011
TC		 183 i,
184 s.pixel_format,
185 s.inuse_addr_hi,
186 s.viewport_width,
187 s.viewport_height,
188 s.rotation_angle,
189 s.h_mirror_en,
190 s.sw_mode,
191 s.dcc_en,
192 s.blank_en,
193 s.ttu_disable,
eb4e33b7
TC		 194 s.underflow_status);
195 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
196 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
197 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
198 DTN_INFO("\n");
71395011
TC		 199 }
200 DTN_INFO("\n");
201
214435ff
CM		 202 DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
203 "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
204
e99a30de 205 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
214435ff 206 struct timing_generator *tg = pool->timing_generators[i];
6f54d0b1 207 struct dcn_otg_state s = {0};
214435ff
CM		 208
209 tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
210
6f54d0b1
LT		 211 //only print if OTG master is enabled
212 if ((s.otg_enabled & 1) == 0)
213 continue;
214
214435ff
CM		 215 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
216 "%d \t %d \t %d \t %d \t %d \t %d \t "
217 "%d \t %d \t %d \t %d \t %d \t ",
218 i,
219 s.v_blank_start,
220 s.v_blank_end,
221 s.v_sync_a_start,
222 s.v_sync_a_end,
223 s.v_sync_a_pol,
224 s.v_total_max,
225 s.v_total_min,
226 s.h_blank_start,
227 s.h_blank_end,
228 s.h_sync_a_start,
229 s.h_sync_a_end,
230 s.h_sync_a_pol,
231 s.h_total,
232 s.v_total,
233 s.underflow_occurred_status);
234 DTN_INFO("\n");
235 }
236 DTN_INFO("\n");
237
71395011
TC		 238 log_mpc_crc(dc);
239
240 DTN_INFO_END();
241}
2b13d7d3
TC		 242
243static void verify_allow_pstate_change_high(
244 struct dce_hwseq *hws)
245{
246 /* pstate latency is ~20us so if we wait over 40us and pstate allow
247 * still not asserted, we are probably stuck and going to hang
ff79cbdc
BL		 248 *
249 * TODO: Figure out why it takes ~100us on linux
250 * pstate takes around ~100us on linux. Unknown currently as to
251 * why it takes that long on linux
2b13d7d3 252 */
ff79cbdc
BL		 253 static unsigned int pstate_wait_timeout_us = 200;
254 static unsigned int pstate_wait_expected_timeout_us = 40;
2b13d7d3
TC		 255 static unsigned int max_sampled_pstate_wait_us; /* data collection */
256 static bool forced_pstate_allow; /* help with revert wa */
08b8ccfb 257 static bool should_log_hw_state; /* prevent hw state log by default */
2b13d7d3
TC		 258
259 unsigned int debug_index = 0x7;
260 unsigned int debug_data;
2b13d7d3
TC		 261 unsigned int i;
262
263 if (forced_pstate_allow) {
264 /* we hacked to force pstate allow to prevent hang last time
265 * we verify_allow_pstate_change_high. so disable force
266 * here so we can check status
267 */
458e9d03
BL		 268 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
269 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
270 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
2b13d7d3
TC		 271 forced_pstate_allow = false;
272 }
273
274 /* description "3-0: Pipe0 cursor0 QOS
275 * 7-4: Pipe1 cursor0 QOS
276 * 11-8: Pipe2 cursor0 QOS
277 * 15-12: Pipe3 cursor0 QOS
278 * 16: Pipe0 Plane0 Allow Pstate Change
279 * 17: Pipe1 Plane0 Allow Pstate Change
280 * 18: Pipe2 Plane0 Allow Pstate Change
281 * 19: Pipe3 Plane0 Allow Pstate Change
282 * 20: Pipe0 Plane1 Allow Pstate Change
283 * 21: Pipe1 Plane1 Allow Pstate Change
284 * 22: Pipe2 Plane1 Allow Pstate Change
285 * 23: Pipe3 Plane1 Allow Pstate Change
286 * 24: Pipe0 cursor0 Allow Pstate Change
287 * 25: Pipe1 cursor0 Allow Pstate Change
288 * 26: Pipe2 cursor0 Allow Pstate Change
289 * 27: Pipe3 cursor0 Allow Pstate Change
290 * 28: WB0 Allow Pstate Change
291 * 29: WB1 Allow Pstate Change
292 * 30: Arbiter's allow_pstate_change
293 * 31: SOC pstate change request
294 */
295
296 REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
297
298 for (i = 0; i < pstate_wait_timeout_us; i++) {
299 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
300
ff79cbdc
BL		 301 if (debug_data & (1 << 30)) {
302
303 if (i > pstate_wait_expected_timeout_us)
304 dm_logger_write(hws->ctx->logger, LOG_WARNING,
e66a5755 305 "pstate took longer than expected ~%dus\n",
ff79cbdc 306 i);
2b13d7d3 307
ff79cbdc
BL		 308 return;
309 }
2b13d7d3
TC		 310 if (max_sampled_pstate_wait_us < i)
311 max_sampled_pstate_wait_us = i;
312
313 udelay(1);
314 }
315
316 /* force pstate allow to prevent system hang
317 * and break to debugger to investigate
318 */
458e9d03
BL		 319 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
320 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
321 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
2b13d7d3 322 forced_pstate_allow = true;
71395011 323
08b8ccfb 324 if (should_log_hw_state) {
fb3466a4 325 dcn10_log_hw_state(hws->ctx->dc);
08b8ccfb 326 }
71395011 327
ff79cbdc 328 dm_logger_write(hws->ctx->logger, LOG_WARNING,
e66a5755 329 "pstate TEST_DEBUG_DATA: 0x%X\n",
ff79cbdc 330 debug_data);
2b13d7d3
TC		 331 BREAK_TO_DEBUGGER();
332}
333
70ccab60 334static void enable_dppclk(
184debdb 335 struct dce_hwseq *hws,
70ccab60
HW		 336 uint8_t plane_id,
337 uint32_t requested_pix_clk,
338 bool dppclk_div)
339{
184debdb 340 dm_logger_write(hws->ctx->logger, LOG_SURFACE,
70ccab60
HW		 341 "dppclk_rate_control for pipe %d programed to %d\n",
342 plane_id,
343 dppclk_div);
344
4e5095ca 345 if (hws->shifts->DPPCLK_RATE_CONTROL)
184debdb 346 REG_UPDATE_2(DPP_CONTROL[plane_id],
4e5095ca 347 DPPCLK_RATE_CONTROL, dppclk_div,
70ccab60 348 DPP_CLOCK_ENABLE, 1);
4e5095ca
DL		 349 else
350 REG_UPDATE(DPP_CONTROL[plane_id],
70ccab60 351 DPP_CLOCK_ENABLE, 1);
70ccab60
HW		 352}
353
354static void enable_power_gating_plane(
184debdb 355 struct dce_hwseq *hws,
70ccab60
HW		 356 bool enable)
357{
70ccab60
HW		 358 bool force_on = 1; /* disable power gating */
359
360 if (enable)
361 force_on = 0;
362
363 /* DCHUBP0/1/2/3 */
184debdb
DL		 364 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
365 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
366 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
367 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
70ccab60
HW		 368
369 /* DPP0/1/2/3 */
184debdb
DL		 370 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
371 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
372 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
373 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
70ccab60
HW		 374}
375
0a87425a
TC		 376static void disable_vga(
377 struct dce_hwseq *hws)
378{
d28f2463
CZ		 379 unsigned int in_vga1_mode = 0;
380 unsigned int in_vga2_mode = 0;
381 unsigned int in_vga3_mode = 0;
382 unsigned int in_vga4_mode = 0;
383
384 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
385 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
386 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
387 REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
388
389 if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
390 in_vga3_mode == 0 && in_vga4_mode == 0)
d49c4a5c
EY		 391 return;
392
0a87425a 393 REG_WRITE(D1VGA_CONTROL, 0);
d28f2463
CZ		 394 REG_WRITE(D2VGA_CONTROL, 0);
395 REG_WRITE(D3VGA_CONTROL, 0);
396 REG_WRITE(D4VGA_CONTROL, 0);
29d79459
BL		 397
398 /* HW Engineer's Notes:
399 * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
400 * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
401 *
402 * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
403 * VGA_TEST_ENABLE, to leave it in the same state as before.
404 */
405 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
406 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
0a87425a
TC		 407}
408
70ccab60 409static void dpp_pg_control(
184debdb 410 struct dce_hwseq *hws,
70ccab60
HW		 411 unsigned int dpp_inst,
412 bool power_on)
413{
70ccab60
HW		 414 uint32_t power_gate = power_on ? 0 : 1;
415 uint32_t pwr_status = power_on ? 0 : 2;
416
184debdb 417 if (hws->ctx->dc->debug.disable_dpp_power_gate)
70ccab60
HW		 418 return;
419
420 switch (dpp_inst) {
421 case 0: /* DPP0 */
184debdb 422 REG_UPDATE(DOMAIN1_PG_CONFIG,
70ccab60
HW		 423 DOMAIN1_POWER_GATE, power_gate);
424
184debdb 425 REG_WAIT(DOMAIN1_PG_STATUS,
8a5d8245
TC		 426 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
427 1, 1000);
70ccab60
HW		 428 break;
429 case 1: /* DPP1 */
184debdb 430 REG_UPDATE(DOMAIN3_PG_CONFIG,
70ccab60
HW		 431 DOMAIN3_POWER_GATE, power_gate);
432
184debdb 433 REG_WAIT(DOMAIN3_PG_STATUS,
8a5d8245
TC		 434 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
435 1, 1000);
70ccab60
HW		 436 break;
437 case 2: /* DPP2 */
184debdb 438 REG_UPDATE(DOMAIN5_PG_CONFIG,
70ccab60
HW		 439 DOMAIN5_POWER_GATE, power_gate);
440
184debdb 441 REG_WAIT(DOMAIN5_PG_STATUS,
8a5d8245
TC		 442 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
443 1, 1000);
70ccab60
HW		 444 break;
445 case 3: /* DPP3 */
184debdb 446 REG_UPDATE(DOMAIN7_PG_CONFIG,
70ccab60
HW		 447 DOMAIN7_POWER_GATE, power_gate);
448
184debdb 449 REG_WAIT(DOMAIN7_PG_STATUS,
8a5d8245
TC		 450 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
451 1, 1000);
70ccab60
HW		 452 break;
453 default:
454 BREAK_TO_DEBUGGER();
455 break;
456 }
457}
458
08b16886
ZF		 459static uint32_t convert_and_clamp(
460 uint32_t wm_ns,
461 uint32_t refclk_mhz,
462 uint32_t clamp_value)
463{
464 uint32_t ret_val = 0;
465 ret_val = wm_ns * refclk_mhz;
466 ret_val /= 1000;
467
468 if (ret_val > clamp_value)
469 ret_val = clamp_value;
470
471 return ret_val;
472}
473
474static void program_watermarks(
475 struct dce_hwseq *hws,
476 struct dcn_watermark_set *watermarks,
477 unsigned int refclk_mhz)
478{
479 uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
480 /*
481 * Need to clamp to max of the register values (i.e. no wrap)
482 * for dcn1, all wm registers are 21-bit wide
483 */
484 uint32_t prog_wm_value;
485
cbb4d72e
YS		 486 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
487 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
488
08b16886
ZF		 489 /* Repeat for water mark set A, B, C and D. */
490 /* clock state A */
491 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
492 refclk_mhz, 0x1fffff);
493 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
494
215a6f05 495 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 496 "URGENCY_WATERMARK_A calculated =%d\n"
497 "HW register value = 0x%x\n",
498 watermarks->a.urgent_ns, prog_wm_value);
499
500 prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
501 refclk_mhz, 0x1fffff);
502 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
215a6f05 503 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 504 "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
505 "HW register value = 0x%x\n",
506 watermarks->a.pte_meta_urgent_ns, prog_wm_value);
507
9a5bcd47
EB		 508 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
509 prog_wm_value = convert_and_clamp(
510 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
511 refclk_mhz, 0x1fffff);
512 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
513 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
514 "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
515 "HW register value = 0x%x\n",
516 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
517
518
519 prog_wm_value = convert_and_clamp(
520 watermarks->a.cstate_pstate.cstate_exit_ns,
521 refclk_mhz, 0x1fffff);
522 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
523 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
524 "SR_EXIT_WATERMARK_A calculated =%d\n"
525 "HW register value = 0x%x\n",
526 watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
527 }
08b16886
ZF		 528
529 prog_wm_value = convert_and_clamp(
530 watermarks->a.cstate_pstate.pstate_change_ns,
531 refclk_mhz, 0x1fffff);
532 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
215a6f05 533 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 534 "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
535 "HW register value = 0x%x\n\n",
536 watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
537
538
539 /* clock state B */
540 prog_wm_value = convert_and_clamp(
541 watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
542 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
215a6f05 543 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 544 "URGENCY_WATERMARK_B calculated =%d\n"
545 "HW register value = 0x%x\n",
546 watermarks->b.urgent_ns, prog_wm_value);
547
548
549 prog_wm_value = convert_and_clamp(
550 watermarks->b.pte_meta_urgent_ns,
551 refclk_mhz, 0x1fffff);
552 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
215a6f05 553 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 554 "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
555 "HW register value = 0x%x\n",
556 watermarks->b.pte_meta_urgent_ns, prog_wm_value);
557
558
9a5bcd47
EB		 559 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
560 prog_wm_value = convert_and_clamp(
561 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
562 refclk_mhz, 0x1fffff);
563 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
564 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
565 "SR_ENTER_WATERMARK_B calculated =%d\n"
566 "HW register value = 0x%x\n",
567 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
568
569
570 prog_wm_value = convert_and_clamp(
571 watermarks->b.cstate_pstate.cstate_exit_ns,
572 refclk_mhz, 0x1fffff);
573 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
574 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
575 "SR_EXIT_WATERMARK_B calculated =%d\n"
576 "HW register value = 0x%x\n",
577 watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
578 }
08b16886
ZF		 579
580 prog_wm_value = convert_and_clamp(
581 watermarks->b.cstate_pstate.pstate_change_ns,
582 refclk_mhz, 0x1fffff);
583 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
215a6f05 584 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 585 "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
586 "HW register value = 0x%x\n",
587 watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
588
589 /* clock state C */
590 prog_wm_value = convert_and_clamp(
591 watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
592 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
215a6f05 593 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 594 "URGENCY_WATERMARK_C calculated =%d\n"
595 "HW register value = 0x%x\n",
596 watermarks->c.urgent_ns, prog_wm_value);
597
598
599 prog_wm_value = convert_and_clamp(
600 watermarks->c.pte_meta_urgent_ns,
601 refclk_mhz, 0x1fffff);
602 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
215a6f05 603 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 604 "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
605 "HW register value = 0x%x\n",
606 watermarks->c.pte_meta_urgent_ns, prog_wm_value);
607
608
9a5bcd47
EB		 609 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
610 prog_wm_value = convert_and_clamp(
611 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
612 refclk_mhz, 0x1fffff);
613 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
614 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
615 "SR_ENTER_WATERMARK_C calculated =%d\n"
616 "HW register value = 0x%x\n",
617 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
618
619
620 prog_wm_value = convert_and_clamp(
621 watermarks->c.cstate_pstate.cstate_exit_ns,
622 refclk_mhz, 0x1fffff);
623 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
624 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
625 "SR_EXIT_WATERMARK_C calculated =%d\n"
626 "HW register value = 0x%x\n",
627 watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
628 }
08b16886
ZF		 629
630 prog_wm_value = convert_and_clamp(
631 watermarks->c.cstate_pstate.pstate_change_ns,
632 refclk_mhz, 0x1fffff);
633 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
215a6f05 634 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 635 "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
636 "HW register value = 0x%x\n",
637 watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
638
639 /* clock state D */
640 prog_wm_value = convert_and_clamp(
641 watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
642 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
215a6f05 643 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 644 "URGENCY_WATERMARK_D calculated =%d\n"
645 "HW register value = 0x%x\n",
646 watermarks->d.urgent_ns, prog_wm_value);
647
648 prog_wm_value = convert_and_clamp(
649 watermarks->d.pte_meta_urgent_ns,
650 refclk_mhz, 0x1fffff);
651 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
215a6f05 652 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 653 "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
654 "HW register value = 0x%x\n",
655 watermarks->d.pte_meta_urgent_ns, prog_wm_value);
656
657
9a5bcd47
EB		 658 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
659 prog_wm_value = convert_and_clamp(
660 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
661 refclk_mhz, 0x1fffff);
662 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
663 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
664 "SR_ENTER_WATERMARK_D calculated =%d\n"
665 "HW register value = 0x%x\n",
666 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
667
668
669 prog_wm_value = convert_and_clamp(
670 watermarks->d.cstate_pstate.cstate_exit_ns,
671 refclk_mhz, 0x1fffff);
672 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
673 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
674 "SR_EXIT_WATERMARK_D calculated =%d\n"
675 "HW register value = 0x%x\n",
676 watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
677 }
08b16886
ZF		 678
679
680 prog_wm_value = convert_and_clamp(
681 watermarks->d.cstate_pstate.pstate_change_ns,
682 refclk_mhz, 0x1fffff);
683 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
215a6f05 684 dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,
08b16886
ZF		 685 "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
686 "HW register value = 0x%x\n\n",
687 watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
688
689 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
690 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
cbb4d72e 691
08b16886
ZF		 692 REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
693 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
694 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
695 DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
696
697 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
698 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
699 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
700
701#if 0
702 REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
703 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
704 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
705#endif
706}
707
708
709static void dcn10_update_dchub(
710 struct dce_hwseq *hws,
711 struct dchub_init_data *dh_data)
712{
713 /* TODO: port code from dal2 */
714 switch (dh_data->fb_mode) {
715 case FRAME_BUFFER_MODE_ZFB_ONLY:
716 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
717 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
718 SDPIF_FB_TOP, 0);
719
720 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
721 SDPIF_FB_BASE, 0x0FFFF);
722
723 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
724 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
725
726 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
727 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
728
729 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
730 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
731 dh_data->zfb_size_in_byte - 1) >> 22);
732 break;
733 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
734 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
735
736 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
737 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
738
739 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
740 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
741
742 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
743 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
744 dh_data->zfb_size_in_byte - 1) >> 22);
745 break;
746 case FRAME_BUFFER_MODE_LOCAL_ONLY:
747 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
748 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
749 SDPIF_AGP_BASE, 0);
750
751 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
752 SDPIF_AGP_BOT, 0X03FFFF);
753
754 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
755 SDPIF_AGP_TOP, 0);
756 break;
757 default:
758 break;
759 }
760
761 dh_data->dchub_initialzied = true;
762 dh_data->dchub_info_valid = false;
763}
764
70ccab60 765static void hubp_pg_control(
184debdb 766 struct dce_hwseq *hws,
70ccab60
HW		 767 unsigned int hubp_inst,
768 bool power_on)
769{
70ccab60
HW		 770 uint32_t power_gate = power_on ? 0 : 1;
771 uint32_t pwr_status = power_on ? 0 : 2;
772
184debdb 773 if (hws->ctx->dc->debug.disable_hubp_power_gate)
70ccab60
HW		 774 return;
775
776 switch (hubp_inst) {
777 case 0: /* DCHUBP0 */
184debdb 778 REG_UPDATE(DOMAIN0_PG_CONFIG,
70ccab60
HW		 779 DOMAIN0_POWER_GATE, power_gate);
780
184debdb 781 REG_WAIT(DOMAIN0_PG_STATUS,
8a5d8245
TC		 782 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
783 1, 1000);
70ccab60
HW		 784 break;
785 case 1: /* DCHUBP1 */
184debdb 786 REG_UPDATE(DOMAIN2_PG_CONFIG,
70ccab60
HW		 787 DOMAIN2_POWER_GATE, power_gate);
788
184debdb 789 REG_WAIT(DOMAIN2_PG_STATUS,
8a5d8245
TC		 790 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
791 1, 1000);
70ccab60
HW		 792 break;
793 case 2: /* DCHUBP2 */
184debdb 794 REG_UPDATE(DOMAIN4_PG_CONFIG,
70ccab60
HW		 795 DOMAIN4_POWER_GATE, power_gate);
796
184debdb 797 REG_WAIT(DOMAIN4_PG_STATUS,
8a5d8245
TC		 798 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
799 1, 1000);
70ccab60
HW		 800 break;
801 case 3: /* DCHUBP3 */
184debdb 802 REG_UPDATE(DOMAIN6_PG_CONFIG,
70ccab60
HW		 803 DOMAIN6_POWER_GATE, power_gate);
804
184debdb 805 REG_WAIT(DOMAIN6_PG_STATUS,
8a5d8245
TC		 806 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
807 1, 1000);
70ccab60
HW		 808 break;
809 default:
810 BREAK_TO_DEBUGGER();
811 break;
812 }
813}
814
815static void power_on_plane(
184debdb 816 struct dce_hwseq *hws,
cfe4645e 817 int plane_id)
70ccab60 818{
5df921d4
KC		 819 if (REG(DC_IP_REQUEST_CNTL)) {
820 REG_SET(DC_IP_REQUEST_CNTL, 0,
821 IP_REQUEST_EN, 1);
822 dpp_pg_control(hws, plane_id, true);
823 hubp_pg_control(hws, plane_id, true);
824 REG_SET(DC_IP_REQUEST_CNTL, 0,
825 IP_REQUEST_EN, 0);
826 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
827 "Un-gated front end for pipe %d\n", plane_id);
828 }
70ccab60
HW		 829}
830
41f97c07
HW		 831static void undo_DEGVIDCN10_253_wa(struct dc *dc)
832{
833 struct dce_hwseq *hws = dc->hwseq;
8feabd03 834 struct hubp *hubp = dc->res_pool->hubps[0];
c9bb686b
EY		 835 int pwr_status = 0;
836
837 REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status);
838 /* Don't need to blank if hubp is power gated*/
839 if (pwr_status == 2)
840 return;
41f97c07 841
8feabd03 842 hubp->funcs->set_blank(hubp, true);
41f97c07
HW		 843
844 REG_SET(DC_IP_REQUEST_CNTL, 0,
845 IP_REQUEST_EN, 1);
846
847 hubp_pg_control(hws, 0, false);
848 REG_SET(DC_IP_REQUEST_CNTL, 0,
849 IP_REQUEST_EN, 0);
850}
851
41f97c07
HW		 852static void apply_DEGVIDCN10_253_wa(struct dc *dc)
853{
854 struct dce_hwseq *hws = dc->hwseq;
8feabd03 855 struct hubp *hubp = dc->res_pool->hubps[0];
41f97c07 856
6bf52028
HW		 857 if (dc->debug.disable_stutter)
858 return;
859
41f97c07
HW		 860 REG_SET(DC_IP_REQUEST_CNTL, 0,
861 IP_REQUEST_EN, 1);
862
863 hubp_pg_control(hws, 0, true);
864 REG_SET(DC_IP_REQUEST_CNTL, 0,
865 IP_REQUEST_EN, 0);
866
8feabd03 867 hubp->funcs->set_hubp_blank_en(hubp, false);
41f97c07
HW		 868}
869
fb3466a4 870static void bios_golden_init(struct dc *dc)
70ccab60
HW		 871{
872 struct dc_bios *bp = dc->ctx->dc_bios;
873 int i;
874
875 /* initialize dcn global */
876 bp->funcs->enable_disp_power_gating(bp,
877 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
878
879 for (i = 0; i < dc->res_pool->pipe_count; i++) {
880 /* initialize dcn per pipe */
881 bp->funcs->enable_disp_power_gating(bp,
882 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
883 }
884}
885
fb3466a4 886static void dcn10_init_hw(struct dc *dc)
70ccab60
HW		 887{
888 int i;
b02c3b05 889 struct abm *abm = dc->res_pool->abm;
184debdb 890 struct dce_hwseq *hws = dc->hwseq;
70ccab60 891
70ccab60 892 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
b02c3b05
DL		 893 REG_WRITE(REFCLK_CNTL, 0);
894 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
184debdb
DL		 895 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
896
fb3466a4 897 if (!dc->debug.disable_clock_gate) {
184debdb
DL		 898 /* enable all DCN clock gating */
899 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
900
901 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
70ccab60 902
184debdb
DL		 903 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
904 }
905
906 enable_power_gating_plane(dc->hwseq, true);
70ccab60
HW		 907 return;
908 }
909 /* end of FPGA. Below if real ASIC */
910
911 bios_golden_init(dc);
912
0a87425a
TC		 913 disable_vga(dc->hwseq);
914
70ccab60
HW		 915 for (i = 0; i < dc->link_count; i++) {
916 /* Power up AND update implementation according to the
917 * required signal (which may be different from the
918 * default signal on connector).
919 */
d0778ebf 920 struct dc_link *link = dc->links[i];
70ccab60
HW		 921
922 link->link_enc->funcs->hw_init(link->link_enc);
923 }
924
925 for (i = 0; i < dc->res_pool->pipe_count; i++) {
d94585a0 926 struct dpp *dpp = dc->res_pool->dpps[i];
b02c3b05 927 struct timing_generator *tg = dc->res_pool->timing_generators[i];
f0558542 928
d94585a0 929 dpp->funcs->dpp_reset(dpp);
cc408d72 930 dc->res_pool->mpc->funcs->remove(
7f4a7253
EB		 931 dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree),
932 dc->res_pool->opps[i]->inst, i);
70ccab60 933
70ccab60
HW		 934 /* Blank controller using driver code instead of
935 * command table.
936 */
937 tg->funcs->set_blank(tg, true);
938 hwss_wait_for_blank_complete(tg);
939 }
940
941 for (i = 0; i < dc->res_pool->audio_count; i++) {
942 struct audio *audio = dc->res_pool->audios[i];
943
944 audio->funcs->hw_init(audio);
945 }
946
70ccab60
HW		 947 if (abm != NULL) {
948 abm->funcs->init_backlight(abm);
949 abm->funcs->abm_init(abm);
950 }
951
952 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
184debdb 953 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
70ccab60 954
fb3466a4 955 if (!dc->debug.disable_clock_gate) {
5970f2ae 956 /* enable all DCN clock gating */
184debdb 957 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
5970f2ae 958
184debdb 959 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
5970f2ae 960
184debdb
DL		 961 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
962 }
5970f2ae 963
184debdb 964 enable_power_gating_plane(dc->hwseq, true);
70ccab60
HW		 965}
966
967static enum dc_status dcn10_prog_pixclk_crtc_otg(
968 struct pipe_ctx *pipe_ctx,
608ac7bb 969 struct dc_state *context,
fb3466a4 970 struct dc *dc)
70ccab60 971{
0971c40e 972 struct dc_stream_state *stream = pipe_ctx->stream;
70ccab60
HW		 973 enum dc_color_space color_space;
974 struct tg_color black_color = {0};
4fa086b9 975 bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
70ccab60 976 false:true;
4fa086b9 977 bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
70ccab60
HW		 978
979
980 /* by upper caller loop, pipe0 is parent pipe and be called first.
981 * back end is set up by for pipe0. Other children pipe share back end
982 * with pipe 0. No program is needed.
983 */
984 if (pipe_ctx->top_pipe != NULL)
985 return DC_OK;
986
987 /* TODO check if timing_changed, disable stream if timing changed */
988
989 /* HW program guide assume display already disable
990 * by unplug sequence. OTG assume stop.
991 */
6b670fa9 992 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
70ccab60
HW		 993
994 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
995 pipe_ctx->clock_source,
10688217 996 &pipe_ctx->stream_res.pix_clk_params,
70ccab60
HW		 997 &pipe_ctx->pll_settings)) {
998 BREAK_TO_DEBUGGER();
999 return DC_ERROR_UNEXPECTED;
1000 }
6b670fa9
HW		 1001 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1002 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1003 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1004 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
70ccab60 1005
6b670fa9 1006 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
70ccab60 1007
6b670fa9
HW		 1008 pipe_ctx->stream_res.tg->funcs->program_timing(
1009 pipe_ctx->stream_res.tg,
4fa086b9 1010 &stream->timing,
70ccab60
HW		 1011 true);
1012
a6a6cb34
HW		 1013 pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
1014 pipe_ctx->stream_res.opp,
70ccab60
HW		 1015 enableStereo,
1016 rightEyePolarity);
1017
1018#if 0 /* move to after enable_crtc */
1019 /* TODO: OPP FMT, ABM. etc. should be done here. */
1020 /* or FPGA now. instance 0 only. TODO: move to opp.c */
1021
6b670fa9 1022 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
70ccab60 1023
a6a6cb34
HW		 1024 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1025 pipe_ctx->stream_res.opp,
70ccab60
HW		 1026 &stream->bit_depth_params,
1027 &stream->clamping);
1028#endif
1029 /* program otg blank color */
4fa086b9 1030 color_space = stream->output_color_space;
70ccab60 1031 color_space_to_black_color(dc, color_space, &black_color);
6b670fa9
HW		 1032 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1033 pipe_ctx->stream_res.tg,
70ccab60
HW		 1034 &black_color);
1035
6b670fa9
HW		 1036 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1037 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
70ccab60
HW		 1038
1039 /* VTG is within DCHUB command block. DCFCLK is always on */
6b670fa9 1040 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
70ccab60
HW		 1041 BREAK_TO_DEBUGGER();
1042 return DC_ERROR_UNEXPECTED;
1043 }
1044
1045 /* TODO program crtc source select for non-virtual signal*/
1046 /* TODO program FMT */
1047 /* TODO setup link_enc */
1048 /* TODO set stream attributes */
1049 /* TODO program audio */
1050 /* TODO enable stream if timing changed */
1051 /* TODO unblank stream if DP */
1052
1053 return DC_OK;
1054}
1055
1056static void reset_back_end_for_pipe(
fb3466a4 1057 struct dc *dc,
70ccab60 1058 struct pipe_ctx *pipe_ctx,
608ac7bb 1059 struct dc_state *context)
70ccab60
HW		 1060{
1061 int i;
70ccab60 1062
8e9c4c8c 1063 if (pipe_ctx->stream_res.stream_enc == NULL) {
70ccab60
HW		 1064 pipe_ctx->stream = NULL;
1065 return;
1066 }
1067
d050f8ed
HW		 1068 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1069 /* DPMS may already disable */
1070 if (!pipe_ctx->stream->dpms_off)
1071 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
1072 }
70ccab60
HW		 1073
1074 /* by upper caller loop, parent pipe: pipe0, will be reset last.
1075 * back end share by all pipes and will be disable only when disable
1076 * parent pipe.
1077 */
1078 if (pipe_ctx->top_pipe == NULL) {
6b670fa9 1079 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
70ccab60 1080
6b670fa9 1081 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
70ccab60
HW		 1082 }
1083
70ccab60 1084 for (i = 0; i < dc->res_pool->pipe_count; i++)
608ac7bb 1085 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
70ccab60
HW		 1086 break;
1087
1088 if (i == dc->res_pool->pipe_count)
1089 return;
1090
1091 pipe_ctx->stream = NULL;
39902db0 1092 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
cfe4645e 1093 "Reset back end for pipe %d, tg:%d\n",
6b670fa9 1094 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
70ccab60
HW		 1095}
1096
a74b2734 1097/* trigger HW to start disconnect plane from stream on the next vsync */
fb3466a4 1098static void plane_atomic_disconnect(struct dc *dc,
cfe4645e 1099 int fe_idx)
70ccab60 1100{
8feabd03 1101 struct hubp *hubp = dc->res_pool->hubps[fe_idx];
cc408d72
DL		 1102 struct mpc *mpc = dc->res_pool->mpc;
1103 int opp_id, z_idx;
1104 int mpcc_id = -1;
1105
1106 /* look at tree rather than mi here to know if we already reset */
1107 for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
1108 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
a74b2734 1109
cc408d72
DL		 1110 for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) {
1111 if (opp->mpc_tree.dpp[z_idx] == fe_idx) {
1112 mpcc_id = opp->mpc_tree.mpcc[z_idx];
1113 break;
1114 }
1115 }
1116 if (mpcc_id != -1)
1117 break;
1118 }
a74b2734 1119 /*Already reset*/
cc408d72 1120 if (opp_id == dc->res_pool->pipe_count)
a74b2734 1121 return;
70ccab60 1122
fb3466a4 1123 if (dc->debug.sanity_checks)
6be425f3 1124 verify_allow_pstate_change_high(dc->hwseq);
8feabd03 1125 hubp->funcs->dcc_control(hubp, false, false);
fb3466a4 1126 if (dc->debug.sanity_checks)
6be425f3
EY		 1127 verify_allow_pstate_change_high(dc->hwseq);
1128
7f4a7253
EB		 1129 mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
1130 dc->res_pool->opps[opp_id]->inst, fe_idx);
d65359d5
TC		 1131}
1132
a74b2734
TC		 1133/* disable HW used by plane.
1134 * note: cannot disable until disconnect is complete */
fb3466a4 1135static void plane_atomic_disable(struct dc *dc,
d65359d5
TC		 1136 int fe_idx)
1137{
1138 struct dce_hwseq *hws = dc->hwseq;
8feabd03 1139 struct hubp *hubp = dc->res_pool->hubps[fe_idx];
cc408d72 1140 struct mpc *mpc = dc->res_pool->mpc;
8feabd03 1141 int opp_id = hubp->opp_id;
d65359d5 1142
e75504b1 1143 if (opp_id == 0xf)
d65359d5
TC		 1144 return;
1145
8feabd03
YHL		 1146 mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
1147 dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
6be425f3
EY		 1148 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
1149 "[debug_mpo: atomic disable finished on mpcc %d]\n",
1150 fe_idx);*/
189f73e3 1151
8feabd03 1152 hubp->funcs->set_blank(hubp, true);
d65359d5 1153
fb3466a4 1154 if (dc->debug.sanity_checks)
2b13d7d3
TC		 1155 verify_allow_pstate_change_high(dc->hwseq);
1156
d21becbe
TC		 1157 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
1158 HUBP_CLOCK_ENABLE, 0);
1159 REG_UPDATE(DPP_CONTROL[fe_idx],
1160 DPP_CLOCK_ENABLE, 0);
71a2f23e 1161
e75504b1
DL		 1162 if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
1163 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
71a2f23e 1164 OPP_PIPE_CLOCK_EN, 0);
70ccab60 1165
fb3466a4 1166 if (dc->debug.sanity_checks)
2b13d7d3 1167 verify_allow_pstate_change_high(dc->hwseq);
cfe4645e 1168}
70ccab60 1169
6be425f3
EY		 1170/*
1171 * kill power to plane hw
a74b2734 1172 * note: cannot power down until plane is disable
6be425f3 1173 */
fb3466a4 1174static void plane_atomic_power_down(struct dc *dc, int fe_idx)
a74b2734 1175{
6be425f3 1176 struct dce_hwseq *hws = dc->hwseq;
d94585a0 1177 struct dpp *dpp = dc->res_pool->dpps[fe_idx];
6be425f3 1178
5df921d4
KC		 1179 if (REG(DC_IP_REQUEST_CNTL)) {
1180 REG_SET(DC_IP_REQUEST_CNTL, 0,
1181 IP_REQUEST_EN, 1);
1182 dpp_pg_control(hws, fe_idx, false);
1183 hubp_pg_control(hws, fe_idx, false);
d94585a0 1184 dpp->funcs->dpp_reset(dpp);
5df921d4
KC		 1185 REG_SET(DC_IP_REQUEST_CNTL, 0,
1186 IP_REQUEST_EN, 0);
1187 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
1188 "Power gated front end %d\n", fe_idx);
a74b2734 1189
5df921d4
KC		 1190 if (dc->debug.sanity_checks)
1191 verify_allow_pstate_change_high(dc->hwseq);
1192 }
a74b2734 1193}
6be425f3 1194
a74b2734
TC		 1195
1196static void reset_front_end(
fb3466a4 1197 struct dc *dc,
a74b2734
TC		 1198 int fe_idx)
1199{
1200 struct dce_hwseq *hws = dc->hwseq;
cc408d72 1201 struct timing_generator *tg;
8feabd03 1202 int opp_id = dc->res_pool->hubps[fe_idx]->opp_id;
a74b2734
TC		 1203
1204 /*Already reset*/
1205 if (opp_id == 0xf)
1206 return;
1207
cc408d72 1208 tg = dc->res_pool->timing_generators[opp_id];
a74b2734
TC		 1209 tg->funcs->lock(tg);
1210
1211 plane_atomic_disconnect(dc, fe_idx);
1212
1213 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
1214 tg->funcs->unlock(tg);
1215
fb3466a4 1216 if (dc->debug.sanity_checks)
cc408d72 1217 verify_allow_pstate_change_high(hws);
a74b2734
TC		 1218
1219 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
1220 REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
8a5d8245
TC		 1221 VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
1222 1, 100000);
a74b2734
TC		 1223
1224 plane_atomic_disable(dc, fe_idx);
1225
1226 dm_logger_write(dc->ctx->logger, LOG_DC,
1227 "Reset front end %d\n",
1228 fe_idx);
1229}
1230
fb3466a4 1231static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
cfe4645e 1232{
184debdb 1233 struct dce_hwseq *hws = dc->hwseq;
d94585a0 1234 struct dpp *dpp = dc->res_pool->dpps[fe_idx];
70ccab60 1235
cfe4645e 1236 reset_front_end(dc, fe_idx);
70ccab60 1237
184debdb 1238 REG_SET(DC_IP_REQUEST_CNTL, 0,
cfe4645e 1239 IP_REQUEST_EN, 1);
184debdb
DL		 1240 dpp_pg_control(hws, fe_idx, false);
1241 hubp_pg_control(hws, fe_idx, false);
d94585a0 1242 dpp->funcs->dpp_reset(dpp);
184debdb 1243 REG_SET(DC_IP_REQUEST_CNTL, 0,
cfe4645e 1244 IP_REQUEST_EN, 0);
39902db0 1245 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
cfe4645e 1246 "Power gated front end %d\n", fe_idx);
2b13d7d3 1247
fb3466a4 1248 if (dc->debug.sanity_checks)
2b13d7d3 1249 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 1250}
1251
cfe4645e 1252static void reset_hw_ctx_wrap(
fb3466a4 1253 struct dc *dc,
608ac7bb 1254 struct dc_state *context)
70ccab60
HW		 1255{
1256 int i;
1257
cfe4645e 1258 /* Reset Front End*/
6be425f3
EY		 1259 /* Lock*/
1260 for (i = 0; i < dc->res_pool->pipe_count; i++) {
608ac7bb 1261 struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
6b670fa9 1262 struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
6be425f3
EY		 1263
1264 if (cur_pipe_ctx->stream)
1265 tg->funcs->lock(tg);
1266 }
1267 /* Disconnect*/
1268 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1269 struct pipe_ctx *pipe_ctx_old =
608ac7bb 1270 &dc->current_state->res_ctx.pipe_ctx[i];
6be425f3
EY		 1271 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1272
1273 if (!pipe_ctx->stream ||
3be5262e 1274 !pipe_ctx->plane_state ||
6be425f3
EY		 1275 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1276
1277 plane_atomic_disconnect(dc, i);
1278 }
1279 }
1280 /* Unlock*/
1281 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
608ac7bb 1282 struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
6b670fa9 1283 struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
6be425f3
EY		 1284
1285 if (cur_pipe_ctx->stream)
1286 tg->funcs->unlock(tg);
1287 }
1288
1289 /* Disable and Powerdown*/
cfe4645e
DL		 1290 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1291 struct pipe_ctx *pipe_ctx_old =
608ac7bb 1292 &dc->current_state->res_ctx.pipe_ctx[i];
cfe4645e
DL		 1293 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1294
1295 /*if (!pipe_ctx_old->stream)
1296 continue;*/
1297
3be5262e 1298 if (pipe_ctx->stream && pipe_ctx->plane_state
6be425f3
EY		 1299 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1300 continue;
1301
1302 plane_atomic_disable(dc, i);
1303
3be5262e 1304 if (!pipe_ctx->stream || !pipe_ctx->plane_state)
6be425f3 1305 plane_atomic_power_down(dc, i);
cfe4645e 1306 }
6be425f3 1307
cfe4645e 1308 /* Reset Back End*/
70ccab60
HW		 1309 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1310 struct pipe_ctx *pipe_ctx_old =
608ac7bb 1311 &dc->current_state->res_ctx.pipe_ctx[i];
70ccab60
HW		 1312 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1313
1314 if (!pipe_ctx_old->stream)
1315 continue;
1316
56e6ed45
YS		 1317 if (pipe_ctx_old->top_pipe)
1318 continue;
1319
70ccab60 1320 if (!pipe_ctx->stream ||
21e67d4d
HW		 1321 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1322 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1323
608ac7bb 1324 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
21e67d4d
HW		 1325
1326 if (old_clk)
1327 old_clk->funcs->cs_power_down(old_clk);
1328 }
70ccab60 1329 }
21e67d4d 1330
70ccab60
HW		 1331}
1332
cfe4645e
DL		 1333static bool patch_address_for_sbs_tb_stereo(
1334 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
70ccab60 1335{
3be5262e 1336 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
70ccab60 1337 bool sec_split = pipe_ctx->top_pipe &&
3be5262e
HW		 1338 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1339 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
4fa086b9 1340 (pipe_ctx->stream->timing.timing_3d_format ==
70ccab60 1341 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
4fa086b9 1342 pipe_ctx->stream->timing.timing_3d_format ==
70ccab60 1343 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
3be5262e
HW		 1344 *addr = plane_state->address.grph_stereo.left_addr;
1345 plane_state->address.grph_stereo.left_addr =
1346 plane_state->address.grph_stereo.right_addr;
70ccab60 1347 return true;
cdc5e048 1348 } else {
4fa086b9 1349 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
3be5262e
HW		 1350 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1351 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1352 plane_state->address.grph_stereo.right_addr =
1353 plane_state->address.grph_stereo.left_addr;
cdc5e048 1354 }
70ccab60
HW		 1355 }
1356 return false;
1357}
1358
9d6f264b
YS		 1359static void toggle_watermark_change_req(struct dce_hwseq *hws)
1360{
1361 uint32_t watermark_change_req;
1362
1363 REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
1364 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
1365
1366 if (watermark_change_req)
1367 watermark_change_req = 0;
1368 else
1369 watermark_change_req = 1;
1370
1371 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
1372 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
1373}
1374
fb3466a4 1375static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
70ccab60
HW		 1376{
1377 bool addr_patched = false;
1378 PHYSICAL_ADDRESS_LOC addr;
3be5262e 1379 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
70ccab60 1380
3be5262e 1381 if (plane_state == NULL)
70ccab60
HW		 1382 return;
1383 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
8feabd03
YHL		 1384 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1385 pipe_ctx->plane_res.hubp,
3be5262e
HW		 1386 &plane_state->address,
1387 plane_state->flip_immediate);
1388 plane_state->status.requested_address = plane_state->address;
70ccab60 1389 if (addr_patched)
3be5262e 1390 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
70ccab60
HW		 1391}
1392
1393static bool dcn10_set_input_transfer_func(
3be5262e 1394 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
70ccab60 1395{
d94585a0 1396 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
7b0c470f 1397 const struct dc_transfer_func *tf = NULL;
70ccab60
HW		 1398 bool result = true;
1399
d94585a0 1400 if (dpp_base == NULL)
70ccab60
HW		 1401 return false;
1402
3be5262e
HW		 1403 if (plane_state->in_transfer_func)
1404 tf = plane_state->in_transfer_func;
70ccab60 1405
3be5262e 1406 if (plane_state->gamma_correction && dce_use_lut(plane_state))
d94585a0 1407 dpp_base->funcs->ipp_program_input_lut(dpp_base,
3be5262e 1408 plane_state->gamma_correction);
5aff86c1 1409
70ccab60 1410 if (tf == NULL)
d94585a0 1411 dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
7b0c470f
LSL		 1412 else if (tf->type == TF_TYPE_PREDEFINED) {
1413 switch (tf->tf) {
70ccab60 1414 case TRANSFER_FUNCTION_SRGB:
d94585a0 1415 dpp_base->funcs->ipp_set_degamma(dpp_base,
70ccab60
HW		 1416 IPP_DEGAMMA_MODE_HW_sRGB);
1417 break;
1418 case TRANSFER_FUNCTION_BT709:
d94585a0 1419 dpp_base->funcs->ipp_set_degamma(dpp_base,
70ccab60
HW		 1420 IPP_DEGAMMA_MODE_HW_xvYCC);
1421 break;
1422 case TRANSFER_FUNCTION_LINEAR:
d94585a0 1423 dpp_base->funcs->ipp_set_degamma(dpp_base,
70ccab60
HW		 1424 IPP_DEGAMMA_MODE_BYPASS);
1425 break;
1426 case TRANSFER_FUNCTION_PQ:
1427 result = false;
1428 break;
1429 default:
1430 result = false;
1431 break;
1432 }
7b0c470f 1433 } else if (tf->type == TF_TYPE_BYPASS) {
d94585a0 1434 dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
70ccab60
HW		 1435 } else {
1436 /*TF_TYPE_DISTRIBUTED_POINTS*/
1437 result = false;
1438 }
1439
1440 return result;
1441}
1442/*modify the method to handle rgb for arr_points*/
1443static bool convert_to_custom_float(
1444 struct pwl_result_data *rgb_resulted,
1445 struct curve_points *arr_points,
1446 uint32_t hw_points_num)
1447{
1448 struct custom_float_format fmt;
1449
1450 struct pwl_result_data *rgb = rgb_resulted;
1451
1452 uint32_t i = 0;
1453
1454 fmt.exponenta_bits = 6;
1455 fmt.mantissa_bits = 12;
1456 fmt.sign = false;
1457
1458 if (!convert_to_custom_float_format(
1459 arr_points[0].x,
1460 &fmt,
1461 &arr_points[0].custom_float_x)) {
1462 BREAK_TO_DEBUGGER();
1463 return false;
1464 }
1465
1466 if (!convert_to_custom_float_format(
1467 arr_points[0].offset,
1468 &fmt,
1469 &arr_points[0].custom_float_offset)) {
1470 BREAK_TO_DEBUGGER();
1471 return false;
1472 }
1473
1474 if (!convert_to_custom_float_format(
1475 arr_points[0].slope,
1476 &fmt,
1477 &arr_points[0].custom_float_slope)) {
1478 BREAK_TO_DEBUGGER();
1479 return false;
1480 }
1481
1482 fmt.mantissa_bits = 10;
1483 fmt.sign = false;
1484
1485 if (!convert_to_custom_float_format(
1486 arr_points[1].x,
1487 &fmt,
1488 &arr_points[1].custom_float_x)) {
1489 BREAK_TO_DEBUGGER();
1490 return false;
1491 }
1492
1493 if (!convert_to_custom_float_format(
1494 arr_points[1].y,
1495 &fmt,
1496 &arr_points[1].custom_float_y)) {
1497 BREAK_TO_DEBUGGER();
1498 return false;
1499 }
1500
1501 if (!convert_to_custom_float_format(
1502 arr_points[1].slope,
1503 &fmt,
1504 &arr_points[1].custom_float_slope)) {
1505 BREAK_TO_DEBUGGER();
1506 return false;
1507 }
1508
1509 fmt.mantissa_bits = 12;
1510 fmt.sign = true;
1511
1512 while (i != hw_points_num) {
1513 if (!convert_to_custom_float_format(
1514 rgb->red,
1515 &fmt,
1516 &rgb->red_reg)) {
1517 BREAK_TO_DEBUGGER();
1518 return false;
1519 }
1520
1521 if (!convert_to_custom_float_format(
1522 rgb->green,
1523 &fmt,
1524 &rgb->green_reg)) {
1525 BREAK_TO_DEBUGGER();
1526 return false;
1527 }
1528
1529 if (!convert_to_custom_float_format(
1530 rgb->blue,
1531 &fmt,
1532 &rgb->blue_reg)) {
1533 BREAK_TO_DEBUGGER();
1534 return false;
1535 }
1536
1537 if (!convert_to_custom_float_format(
1538 rgb->delta_red,
1539 &fmt,
1540 &rgb->delta_red_reg)) {
1541 BREAK_TO_DEBUGGER();
1542 return false;
1543 }
1544
1545 if (!convert_to_custom_float_format(
1546 rgb->delta_green,
1547 &fmt,
1548 &rgb->delta_green_reg)) {
1549 BREAK_TO_DEBUGGER();
1550 return false;
1551 }
1552
1553 if (!convert_to_custom_float_format(
1554 rgb->delta_blue,
1555 &fmt,
1556 &rgb->delta_blue_reg)) {
1557 BREAK_TO_DEBUGGER();
1558 return false;
1559 }
1560
1561 ++rgb;
1562 ++i;
1563 }
1564
1565 return true;
1566}
1567#define MAX_REGIONS_NUMBER 34
1568#define MAX_LOW_POINT 25
1569#define NUMBER_SEGMENTS 32
1570
1571static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
1572 *output_tf, struct pwl_params *regamma_params)
1573{
1574 struct curve_points *arr_points;
1575 struct pwl_result_data *rgb_resulted;
1576 struct pwl_result_data *rgb;
1577 struct pwl_result_data *rgb_plus_1;
1578 struct fixed31_32 y_r;
1579 struct fixed31_32 y_g;
1580 struct fixed31_32 y_b;
1581 struct fixed31_32 y1_min;
1582 struct fixed31_32 y3_max;
1583
1584 int32_t segment_start, segment_end;
1585 int32_t i;
1586 uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
1587
1588 if (output_tf == NULL || regamma_params == NULL ||
1589 output_tf->type == TF_TYPE_BYPASS)
1590 return false;
1591
1592 arr_points = regamma_params->arr_points;
1593 rgb_resulted = regamma_params->rgb_resulted;
1594 hw_points = 0;
1595
1596 memset(regamma_params, 0, sizeof(struct pwl_params));
1597 memset(seg_distr, 0, sizeof(seg_distr));
1598
1599 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1600 /* 32 segments
1601 * segments are from 2^-25 to 2^7
1602 */
1603 for (i = 0; i < 32 ; i++)
1604 seg_distr[i] = 3;
1605
1606 segment_start = -25;
1607 segment_end = 7;
1608 } else {
1609 /* 10 segments
1610 * segment is from 2^-10 to 2^0
1611 * There are less than 256 points, for optimization
1612 */
1613 seg_distr[0] = 3;
1614 seg_distr[1] = 4;
1615 seg_distr[2] = 4;
1616 seg_distr[3] = 4;
1617 seg_distr[4] = 4;
1618 seg_distr[5] = 4;
1619 seg_distr[6] = 4;
1620 seg_distr[7] = 4;
1621 seg_distr[8] = 5;
1622 seg_distr[9] = 5;
1623
1624 segment_start = -10;
1625 segment_end = 0;
1626 }
1627
1628 for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
1629 seg_distr[i] = -1;
1630
1631 for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
1632 if (seg_distr[k] != -1)
1633 hw_points += (1 << seg_distr[k]);
1634 }
1635
1636 j = 0;
1637 for (k = 0; k < (segment_end - segment_start); k++) {
1638 increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
1639 start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1640 for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
1641 if (j == hw_points - 1)
1642 break;
1643 rgb_resulted[j].red = output_tf->tf_pts.red[i];
1644 rgb_resulted[j].green = output_tf->tf_pts.green[i];
1645 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
1646 j++;
1647 }
1648 }
1649
1650 /* last point */
1651 start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1652 rgb_resulted[hw_points - 1].red =
1653 output_tf->tf_pts.red[start_index];
1654 rgb_resulted[hw_points - 1].green =
1655 output_tf->tf_pts.green[start_index];
1656 rgb_resulted[hw_points - 1].blue =
1657 output_tf->tf_pts.blue[start_index];
1658
1659 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1660 dal_fixed31_32_from_int(segment_start));
1661 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1662 dal_fixed31_32_from_int(segment_end));
1663 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1664 dal_fixed31_32_from_int(segment_end));
1665
1666 y_r = rgb_resulted[0].red;
1667 y_g = rgb_resulted[0].green;
1668 y_b = rgb_resulted[0].blue;
1669
1670 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
1671
1672 arr_points[0].y = y1_min;
1673 arr_points[0].slope = dal_fixed31_32_div(
1674 arr_points[0].y,
1675 arr_points[0].x);
1676 y_r = rgb_resulted[hw_points - 1].red;
1677 y_g = rgb_resulted[hw_points - 1].green;
1678 y_b = rgb_resulted[hw_points - 1].blue;
1679
1680 /* see comment above, m_arrPoints[1].y should be the Y value for the
1681 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
1682 */
1683 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
1684
1685 arr_points[1].y = y3_max;
1686 arr_points[2].y = y3_max;
1687
1688 arr_points[1].slope = dal_fixed31_32_zero;
1689 arr_points[2].slope = dal_fixed31_32_zero;
1690
1691 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1692 /* for PQ, we want to have a straight line from last HW X point,
1693 * and the slope to be such that we hit 1.0 at 10000 nits.
1694 */
1695 const struct fixed31_32 end_value =
1696 dal_fixed31_32_from_int(125);
1697
1698 arr_points[1].slope = dal_fixed31_32_div(
1699 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1700 dal_fixed31_32_sub(end_value, arr_points[1].x));
1701 arr_points[2].slope = dal_fixed31_32_div(
1702 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1703 dal_fixed31_32_sub(end_value, arr_points[1].x));
1704 }
1705
1706 regamma_params->hw_points_num = hw_points;
1707
1708 i = 1;
1709 for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
1710 if (seg_distr[k] != -1) {
1711 regamma_params->arr_curve_points[k].segments_num =
1712 seg_distr[k];
1713 regamma_params->arr_curve_points[i].offset =
1714 regamma_params->arr_curve_points[k].
1715 offset + (1 << seg_distr[k]);
1716 }
1717 i++;
1718 }
1719
1720 if (seg_distr[k] != -1)
1721 regamma_params->arr_curve_points[k].segments_num =
1722 seg_distr[k];
1723
1724 rgb = rgb_resulted;
1725 rgb_plus_1 = rgb_resulted + 1;
1726
1727 i = 1;
1728
1729 while (i != hw_points + 1) {
1730 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
1731 rgb_plus_1->red = rgb->red;
1732 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
1733 rgb_plus_1->green = rgb->green;
1734 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
1735 rgb_plus_1->blue = rgb->blue;
1736
1737 rgb->delta_red = dal_fixed31_32_sub(
1738 rgb_plus_1->red,
1739 rgb->red);
1740 rgb->delta_green = dal_fixed31_32_sub(
1741 rgb_plus_1->green,
1742 rgb->green);
1743 rgb->delta_blue = dal_fixed31_32_sub(
1744 rgb_plus_1->blue,
1745 rgb->blue);
1746
1747 ++rgb_plus_1;
1748 ++rgb;
1749 ++i;
1750 }
1751
1752 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
1753
1754 return true;
1755}
1756
1757static bool dcn10_set_output_transfer_func(
1758 struct pipe_ctx *pipe_ctx,
0971c40e 1759 const struct dc_stream_state *stream)
70ccab60 1760{
d94585a0 1761 struct dpp *dpp = pipe_ctx->plane_res.dpp;
70ccab60 1762
d94585a0 1763 if (dpp == NULL)
f46661dd
AZ		 1764 return false;
1765
d94585a0 1766 dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
70ccab60 1767
4fa086b9
LSL		 1768 if (stream->out_transfer_func &&
1769 stream->out_transfer_func->type ==
70ccab60 1770 TF_TYPE_PREDEFINED &&
4fa086b9 1771 stream->out_transfer_func->tf ==
70ccab60 1772 TRANSFER_FUNCTION_SRGB) {
d94585a0 1773 dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_SRGB);
70ccab60 1774 } else if (dcn10_translate_regamma_to_hw_format(
d94585a0
YHL		 1775 stream->out_transfer_func, &dpp->regamma_params)) {
1776 dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params);
1777 dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_USER);
70ccab60 1778 } else {
d94585a0 1779 dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_BYPASS);
70ccab60
HW		 1780 }
1781
1782 return true;
1783}
1784
1785static void dcn10_pipe_control_lock(
fb3466a4 1786 struct dc *dc,
70ccab60
HW		 1787 struct pipe_ctx *pipe,
1788 bool lock)
1789{
8feabd03
YHL		 1790 struct hubp *hubp = NULL;
1791 hubp = dc->res_pool->hubps[pipe->pipe_idx];
70ccab60
HW		 1792 /* use TG master update lock to lock everything on the TG
1793 * therefore only top pipe need to lock
1794 */
1795 if (pipe->top_pipe)
1796 return;
1797
fb3466a4 1798 if (dc->debug.sanity_checks)
2b13d7d3
TC		 1799 verify_allow_pstate_change_high(dc->hwseq);
1800
70ccab60 1801 if (lock)
6b670fa9 1802 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
70ccab60 1803 else
6b670fa9 1804 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
2b13d7d3 1805
fb3466a4 1806 if (dc->debug.sanity_checks)
2b13d7d3 1807 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 1808}
1809
1810static bool wait_for_reset_trigger_to_occur(
1811 struct dc_context *dc_ctx,
1812 struct timing_generator *tg)
1813{
1814 bool rc = false;
1815
1816 /* To avoid endless loop we wait at most
1817 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1818 const uint32_t frames_to_wait_on_triggered_reset = 10;
1819 int i;
1820
1821 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1822
1823 if (!tg->funcs->is_counter_moving(tg)) {
1824 DC_ERROR("TG counter is not moving!\n");
1825 break;
1826 }
1827
1828 if (tg->funcs->did_triggered_reset_occur(tg)) {
1829 rc = true;
1830 /* usually occurs at i=1 */
1831 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1832 i);
1833 break;
1834 }
1835
1836 /* Wait for one frame. */
1837 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1838 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1839 }
1840
1841 if (false == rc)
1842 DC_ERROR("GSL: Timeout on reset trigger!\n");
1843
1844 return rc;
1845}
1846
1847static void dcn10_enable_timing_synchronization(
fb3466a4 1848 struct dc *dc,
70ccab60
HW		 1849 int group_index,
1850 int group_size,
1851 struct pipe_ctx *grouped_pipes[])
1852{
1853 struct dc_context *dc_ctx = dc->ctx;
1854 int i;
1855
1856 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1857
1858 for (i = 1; i < group_size; i++)
6b670fa9
HW		 1859 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1860 grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst);
70ccab60
HW		 1861
1862
1863 DC_SYNC_INFO("Waiting for trigger\n");
1864
1865 /* Need to get only check 1 pipe for having reset as all the others are
1866 * synchronized. Look at last pipe programmed to reset.
1867 */
6b670fa9 1868 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
70ccab60 1869 for (i = 1; i < group_size; i++)
6b670fa9
HW		 1870 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1871 grouped_pipes[i]->stream_res.tg);
70ccab60
HW		 1872
1873 DC_SYNC_INFO("Sync complete\n");
1874}
1875
c9742685 1876static void print_rq_dlg_ttu(
fb3466a4 1877 struct dc *core_dc,
c9742685
DL		 1878 struct pipe_ctx *pipe_ctx)
1879{
1880 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1881 "\n============== DML TTU Output parameters [%d] ==============\n"
1882 "qos_level_low_wm: %d, \n"
1883 "qos_level_high_wm: %d, \n"
1884 "min_ttu_vblank: %d, \n"
1885 "qos_level_flip: %d, \n"
1886 "refcyc_per_req_delivery_l: %d, \n"
1887 "qos_level_fixed_l: %d, \n"
1888 "qos_ramp_disable_l: %d, \n"
1889 "refcyc_per_req_delivery_pre_l: %d, \n"
1890 "refcyc_per_req_delivery_c: %d, \n"
1891 "qos_level_fixed_c: %d, \n"
1892 "qos_ramp_disable_c: %d, \n"
1893 "refcyc_per_req_delivery_pre_c: %d\n"
1894 "=============================================================\n",
1895 pipe_ctx->pipe_idx,
1896 pipe_ctx->ttu_regs.qos_level_low_wm,
1897 pipe_ctx->ttu_regs.qos_level_high_wm,
1898 pipe_ctx->ttu_regs.min_ttu_vblank,
1899 pipe_ctx->ttu_regs.qos_level_flip,
1900 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1901 pipe_ctx->ttu_regs.qos_level_fixed_l,
1902 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1903 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1904 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1905 pipe_ctx->ttu_regs.qos_level_fixed_c,
1906 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1907 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1908 );
1909
1910 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1911 "\n============== DML DLG Output parameters [%d] ==============\n"
1912 "refcyc_h_blank_end: %d, \n"
1913 "dlg_vblank_end: %d, \n"
1914 "min_dst_y_next_start: %d, \n"
1915 "refcyc_per_htotal: %d, \n"
1916 "refcyc_x_after_scaler: %d, \n"
1917 "dst_y_after_scaler: %d, \n"
1918 "dst_y_prefetch: %d, \n"
1919 "dst_y_per_vm_vblank: %d, \n"
1920 "dst_y_per_row_vblank: %d, \n"
1921 "ref_freq_to_pix_freq: %d, \n"
1922 "vratio_prefetch: %d, \n"
1923 "refcyc_per_pte_group_vblank_l: %d, \n"
1924 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1925 "dst_y_per_pte_row_nom_l: %d, \n"
1926 "refcyc_per_pte_group_nom_l: %d, \n",
1927 pipe_ctx->pipe_idx,
1928 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1929 pipe_ctx->dlg_regs.dlg_vblank_end,
1930 pipe_ctx->dlg_regs.min_dst_y_next_start,
1931 pipe_ctx->dlg_regs.refcyc_per_htotal,
1932 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1933 pipe_ctx->dlg_regs.dst_y_after_scaler,
1934 pipe_ctx->dlg_regs.dst_y_prefetch,
1935 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1936 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1937 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1938 pipe_ctx->dlg_regs.vratio_prefetch,
1939 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1940 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1941 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1942 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1943 );
1944
1945 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1946 "\ndst_y_per_meta_row_nom_l: %d, \n"
1947 "refcyc_per_meta_chunk_nom_l: %d, \n"
1948 "refcyc_per_line_delivery_pre_l: %d, \n"
1949 "refcyc_per_line_delivery_l: %d, \n"
1950 "vratio_prefetch_c: %d, \n"
1951 "refcyc_per_pte_group_vblank_c: %d, \n"
1952 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1953 "dst_y_per_pte_row_nom_c: %d, \n"
1954 "refcyc_per_pte_group_nom_c: %d, \n"
1955 "dst_y_per_meta_row_nom_c: %d, \n"
1956 "refcyc_per_meta_chunk_nom_c: %d, \n"
1957 "refcyc_per_line_delivery_pre_c: %d, \n"
1958 "refcyc_per_line_delivery_c: %d \n"
1959 "========================================================\n",
1960 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1961 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1962 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1963 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1964 pipe_ctx->dlg_regs.vratio_prefetch_c,
1965 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1966 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1967 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1968 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1969 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1970 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1971 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1972 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1973 );
1974
1975 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1976 "\n============== DML RQ Output parameters [%d] ==============\n"
1977 "chunk_size: %d \n"
1978 "min_chunk_size: %d \n"
1979 "meta_chunk_size: %d \n"
1980 "min_meta_chunk_size: %d \n"
1981 "dpte_group_size: %d \n"
1982 "mpte_group_size: %d \n"
1983 "swath_height: %d \n"
1984 "pte_row_height_linear: %d \n"
1985 "========================================================\n",
1986 pipe_ctx->pipe_idx,
1987 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1988 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1989 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1990 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1991 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1992 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1993 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1994 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1995 );
1996}
1997
70ccab60 1998static void dcn10_power_on_fe(
fb3466a4 1999 struct dc *dc,
70ccab60 2000 struct pipe_ctx *pipe_ctx,
608ac7bb 2001 struct dc_state *context)
70ccab60 2002{
3be5262e 2003 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
184debdb 2004 struct dce_hwseq *hws = dc->hwseq;
70ccab60 2005
fb3466a4 2006 if (dc->debug.sanity_checks) {
665da60f
CM		 2007 verify_allow_pstate_change_high(dc->hwseq);
2008 }
2009
184debdb 2010 power_on_plane(dc->hwseq,
cfe4645e 2011 pipe_ctx->pipe_idx);
70ccab60 2012
c9742685 2013 /* enable DCFCLK current DCHUB */
d21becbe
TC		 2014 REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
2015 HUBP_CLOCK_ENABLE, 1);
2016
2017 /* make sure OPP_PIPE_CLOCK_EN = 1 */
6b670fa9 2018 REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
d21becbe 2019 OPP_PIPE_CLOCK_EN, 1);
51666631 2020 /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
c9742685 2021
3be5262e 2022 if (plane_state) {
61a44fc6 2023 dm_logger_write(dc->ctx->logger, LOG_DC,
c9742685
DL		 2024 "Pipe:%d 0x%x: addr hi:0x%x, "
2025 "addr low:0x%x, "
2026 "src: %d, %d, %d,"
2027 " %d; dst: %d, %d, %d, %d;\n",
70ccab60 2028 pipe_ctx->pipe_idx,
3be5262e
HW		 2029 plane_state,
2030 plane_state->address.grph.addr.high_part,
2031 plane_state->address.grph.addr.low_part,
2032 plane_state->src_rect.x,
2033 plane_state->src_rect.y,
2034 plane_state->src_rect.width,
2035 plane_state->src_rect.height,
2036 plane_state->dst_rect.x,
2037 plane_state->dst_rect.y,
2038 plane_state->dst_rect.width,
2039 plane_state->dst_rect.height);
c9742685 2040
61a44fc6 2041 dm_logger_write(dc->ctx->logger, LOG_DC,
3eea71e3 2042 "Pipe %d: width, height, x, y format:%d\n"
c9742685
DL		 2043 "viewport:%d, %d, %d, %d\n"
2044 "recout: %d, %d, %d, %d\n",
2045 pipe_ctx->pipe_idx,
3eea71e3 2046 plane_state->format,
6702a9ac
HW		 2047 pipe_ctx->plane_res.scl_data.viewport.width,
2048 pipe_ctx->plane_res.scl_data.viewport.height,
2049 pipe_ctx->plane_res.scl_data.viewport.x,
2050 pipe_ctx->plane_res.scl_data.viewport.y,
2051 pipe_ctx->plane_res.scl_data.recout.width,
2052 pipe_ctx->plane_res.scl_data.recout.height,
2053 pipe_ctx->plane_res.scl_data.recout.x,
2054 pipe_ctx->plane_res.scl_data.recout.y);
c9742685 2055 print_rq_dlg_ttu(dc, pipe_ctx);
70ccab60 2056 }
665da60f 2057
fb3466a4 2058 if (dc->debug.sanity_checks) {
665da60f
CM		 2059 verify_allow_pstate_change_high(dc->hwseq);
2060 }
70ccab60
HW		 2061}
2062
2063static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2064{
d94585a0 2065 struct dpp_grph_csc_adjustment adjust;
70ccab60
HW		 2066 memset(&adjust, 0, sizeof(adjust));
2067 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2068
2069
4fa086b9 2070 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
70ccab60
HW		 2071 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2072 adjust.temperature_matrix[0] =
2073 pipe_ctx->stream->
4fa086b9 2074 gamut_remap_matrix.matrix[0];
70ccab60
HW		 2075 adjust.temperature_matrix[1] =
2076 pipe_ctx->stream->
4fa086b9 2077 gamut_remap_matrix.matrix[1];
70ccab60
HW		 2078 adjust.temperature_matrix[2] =
2079 pipe_ctx->stream->
4fa086b9 2080 gamut_remap_matrix.matrix[2];
70ccab60
HW		 2081 adjust.temperature_matrix[3] =
2082 pipe_ctx->stream->
4fa086b9 2083 gamut_remap_matrix.matrix[4];
70ccab60
HW		 2084 adjust.temperature_matrix[4] =
2085 pipe_ctx->stream->
4fa086b9 2086 gamut_remap_matrix.matrix[5];
70ccab60
HW		 2087 adjust.temperature_matrix[5] =
2088 pipe_ctx->stream->
4fa086b9 2089 gamut_remap_matrix.matrix[6];
70ccab60
HW		 2090 adjust.temperature_matrix[6] =
2091 pipe_ctx->stream->
4fa086b9 2092 gamut_remap_matrix.matrix[8];
70ccab60
HW		 2093 adjust.temperature_matrix[7] =
2094 pipe_ctx->stream->
4fa086b9 2095 gamut_remap_matrix.matrix[9];
70ccab60
HW		 2096 adjust.temperature_matrix[8] =
2097 pipe_ctx->stream->
4fa086b9 2098 gamut_remap_matrix.matrix[10];
70ccab60
HW		 2099 }
2100
d94585a0 2101 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
70ccab60
HW		 2102}
2103
abe07e80
YHL		 2104
2105static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2106 enum dc_color_space colorspace,
2107 uint16_t *matrix)
2108{
2109 int i;
2110 struct out_csc_color_matrix tbl_entry;
2111
4fa086b9 2112 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
abe07e80
YHL		 2113 == true) {
2114 enum dc_color_space color_space =
4fa086b9 2115 pipe_ctx->stream->output_color_space;
abe07e80
YHL		 2116
2117 //uint16_t matrix[12];
2118 for (i = 0; i < 12; i++)
4fa086b9 2119 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
abe07e80
YHL		 2120
2121 tbl_entry.color_space = color_space;
2122 //tbl_entry.regval = matrix;
d94585a0 2123 pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
807fc072
YHL		 2124 } else {
2125 pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
abe07e80
YHL		 2126 }
2127}
4b28b76b
DL		 2128static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2129{
3be5262e 2130 if (pipe_ctx->plane_state->visible)
4b28b76b
DL		 2131 return true;
2132 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
2133 return true;
2134 return false;
2135}
2136
2137static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2138{
3be5262e 2139 if (pipe_ctx->plane_state->visible)
4b28b76b
DL		 2140 return true;
2141 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
2142 return true;
2143 return false;
2144}
2145
2146static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
2147{
3be5262e 2148 if (pipe_ctx->plane_state->visible)
4b28b76b
DL		 2149 return true;
2150 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
2151 return true;
2152 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
2153 return true;
2154 return false;
2155}
2156
ad327346
DL		 2157static bool is_rgb_cspace(enum dc_color_space output_color_space)
2158{
2159 switch (output_color_space) {
2160 case COLOR_SPACE_SRGB:
2161 case COLOR_SPACE_SRGB_LIMITED:
2162 case COLOR_SPACE_2020_RGB_FULLRANGE:
2163 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
2164 case COLOR_SPACE_ADOBERGB:
2165 return true;
2166 case COLOR_SPACE_YCBCR601:
2167 case COLOR_SPACE_YCBCR709:
2168 case COLOR_SPACE_YCBCR601_LIMITED:
2169 case COLOR_SPACE_YCBCR709_LIMITED:
2170 case COLOR_SPACE_2020_YCBCR:
2171 return false;
2172 default:
2173 /* Add a case to switch */
2174 BREAK_TO_DEBUGGER();
2175 return false;
2176 }
2177}
2178
87449a90
AK		 2179static void dcn10_get_surface_visual_confirm_color(
2180 const struct pipe_ctx *pipe_ctx,
2181 struct tg_color *color)
2182{
2183 uint32_t color_value = MAX_TG_COLOR_VALUE;
2184
6702a9ac 2185 switch (pipe_ctx->plane_res.scl_data.format) {
87449a90
AK		 2186 case PIXEL_FORMAT_ARGB8888:
2187 /* set boarder color to red */
2188 color->color_r_cr = color_value;
2189 break;
2190
2191 case PIXEL_FORMAT_ARGB2101010:
2192 /* set boarder color to blue */
2193 color->color_b_cb = color_value;
2194 break;
2195 case PIXEL_FORMAT_420BPP8:
2196 /* set boarder color to green */
2197 color->color_g_y = color_value;
2198 break;
2199 case PIXEL_FORMAT_420BPP10:
2200 /* set boarder color to yellow */
2201 color->color_g_y = color_value;
2202 color->color_r_cr = color_value;
2203 break;
2204 case PIXEL_FORMAT_FP16:
2205 /* set boarder color to white */
2206 color->color_r_cr = color_value;
2207 color->color_b_cb = color_value;
2208 color->color_g_y = color_value;
2209 break;
2210 default:
2211 break;
2212 }
2213}
2214
8feabd03 2215static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
0cb8a881
YHL		 2216 struct vm_system_aperture_param *apt,
2217 struct dce_hwseq *hws)
2218{
2219 PHYSICAL_ADDRESS_LOC physical_page_number;
2220 uint32_t logical_addr_low;
2221 uint32_t logical_addr_high;
2222
2223 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
2224 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
2225 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
2226 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
2227
2228 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2229 LOGICAL_ADDR, &logical_addr_low);
2230
2231 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2232 LOGICAL_ADDR, &logical_addr_high);
2233
2234 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
2235 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
2236 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
2237}
2238
2239/* Temporary read settings, future will get values from kmd directly */
8feabd03 2240static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
0cb8a881
YHL		 2241 struct vm_context0_param *vm0,
2242 struct dce_hwseq *hws)
2243{
2244 PHYSICAL_ADDRESS_LOC fb_base;
2245 PHYSICAL_ADDRESS_LOC fb_offset;
2246 uint32_t fb_base_value;
2247 uint32_t fb_offset_value;
2248
2249 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
2250 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
2251
2252 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
2253 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
2254 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
2255 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
2256
2257 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
2258 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
2259 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
2260 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
2261
2262 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
2263 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
2264 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
2265 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
2266
2267 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
2268 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
2269 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
2270 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
2271
2272 /*
2273 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
2274 * Therefore we need to do
2275 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
2276 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
2277 */
2278 fb_base.quad_part = (uint64_t)fb_base_value << 24;
2279 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
2280 vm0->pte_base.quad_part += fb_base.quad_part;
2281 vm0->pte_base.quad_part -= fb_offset.quad_part;
2282}
2283
8feabd03 2284static void dcn10_program_pte_vm(struct hubp *hubp,
0cb8a881
YHL		 2285 enum surface_pixel_format format,
2286 union dc_tiling_info *tiling_info,
2287 enum dc_rotation_angle rotation,
2288 struct dce_hwseq *hws)
2289{
8feabd03 2290 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
0cb8a881
YHL		 2291 struct vm_system_aperture_param apt = { {{ 0 } } };
2292 struct vm_context0_param vm0 = { { { 0 } } };
2293
2294
8feabd03
YHL		 2295 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
2296 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
0cb8a881 2297
8feabd03
YHL		 2298 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
2299 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
0cb8a881
YHL		 2300}
2301
70ccab60 2302static void update_dchubp_dpp(
fb3466a4 2303 struct dc *dc,
70ccab60 2304 struct pipe_ctx *pipe_ctx,
608ac7bb 2305 struct dc_state *context)
70ccab60 2306{
184debdb 2307 struct dce_hwseq *hws = dc->hwseq;
8feabd03 2308 struct hubp *hubp = pipe_ctx->plane_res.hubp;
d94585a0 2309 struct dpp *dpp = pipe_ctx->plane_res.dpp;
3be5262e
HW		 2310 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2311 union plane_size size = plane_state->plane_size;
cc408d72
DL		 2312 struct mpcc_cfg mpcc_cfg = {0};
2313 struct pipe_ctx *top_pipe;
3be5262e 2314 bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
cbfd33fd 2315
ba326a91 2316 /* TODO: proper fix once fpga works */
70ccab60
HW		 2317 /* depends on DML calculation, DPP clock value may change dynamically */
2318 enable_dppclk(
184debdb 2319 dc->hwseq,
70ccab60 2320 pipe_ctx->pipe_idx,
10688217 2321 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
9037d802 2322 context->bw.dcn.calc_clk.dppclk_div);
608ac7bb 2323 dc->current_state->bw.dcn.cur_clk.dppclk_div =
c66a54dc
DL		 2324 context->bw.dcn.calc_clk.dppclk_div;
2325 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
70ccab60 2326
184debdb
DL		 2327 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2328 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2329 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2330 */
6b670fa9 2331 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
70ccab60 2332
8feabd03
YHL		 2333 hubp->funcs->hubp_setup(
2334 hubp,
70ccab60
HW		 2335 &pipe_ctx->dlg_regs,
2336 &pipe_ctx->ttu_regs,
2337 &pipe_ctx->rq_regs,
2338 &pipe_ctx->pipe_dlg_param);
2339
6702a9ac 2340 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
70ccab60 2341
fb3466a4 2342 if (dc->config.gpu_vm_support)
0cb8a881 2343 dcn10_program_pte_vm(
8feabd03 2344 pipe_ctx->plane_res.hubp,
3be5262e
HW		 2345 plane_state->format,
2346 &plane_state->tiling_info,
0cb8a881
YHL		 2347 plane_state->rotation,
2348 hws
2349 );
70ccab60 2350
d94585a0 2351 dpp->funcs->ipp_setup(dpp,
3be5262e 2352 plane_state->format,
264efa31 2353 EXPANSION_MODE_ZERO);
70ccab60 2354
8feabd03 2355 mpcc_cfg.dpp_id = hubp->inst;
7f4a7253
EB		 2356 mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
2357 mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree);
cc408d72
DL		 2358 for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
2359 mpcc_cfg.z_index++;
fb3466a4 2360 if (dc->debug.surface_visual_confirm)
cc408d72
DL		 2361 dcn10_get_surface_visual_confirm_color(
2362 pipe_ctx, &mpcc_cfg.black_color);
f0558542 2363 else
cc408d72
DL		 2364 color_space_to_black_color(
2365 dc, pipe_ctx->stream->output_color_space,
2366 &mpcc_cfg.black_color);
f0558542 2367 mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
ad327346
DL		 2368 /* DCN1.0 has output CM before MPC which seems to screw with
2369 * pre-multiplied alpha.
2370 */
2371 mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
4fa086b9 2372 pipe_ctx->stream->output_color_space)
ad327346 2373 && per_pixel_alpha;
8feabd03
YHL		 2374 hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
2375 hubp->opp_id = mpcc_cfg.opp_id;
70ccab60 2376
6702a9ac
HW		 2377 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2378 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
70ccab60 2379 /* scaler configuration */
d94585a0
YHL		 2380 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2381 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2382
8feabd03 2383 hubp->funcs->mem_program_viewport(hubp,
6702a9ac 2384 &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);
70ccab60
HW		 2385
2386 /*gamut remap*/
2387 program_gamut_remap(pipe_ctx);
2388
69b516c9
S		 2389 program_csc_matrix(pipe_ctx,
2390 pipe_ctx->stream->output_color_space,
2391 pipe_ctx->stream->csc_color_matrix.matrix);
70ccab60 2392
8feabd03
YHL		 2393 hubp->funcs->hubp_program_surface_config(
2394 hubp,
3be5262e
HW		 2395 plane_state->format,
2396 &plane_state->tiling_info,
70ccab60 2397 &size,
3be5262e
HW		 2398 plane_state->rotation,
2399 &plane_state->dcc,
2400 plane_state->horizontal_mirror);
70ccab60 2401
50d4cfdc
YS		 2402 dc->hwss.update_plane_addr(dc, pipe_ctx);
2403
8eb5def9 2404 if (is_pipe_tree_visible(pipe_ctx))
8feabd03 2405 hubp->funcs->set_blank(hubp, false);
70ccab60
HW		 2406}
2407
9d6f264b 2408
70ccab60 2409static void program_all_pipe_in_tree(
fb3466a4 2410 struct dc *dc,
70ccab60 2411 struct pipe_ctx *pipe_ctx,
608ac7bb 2412 struct dc_state *context)
70ccab60
HW		 2413{
2414 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
2415
1a2c82a2 2416 if (pipe_ctx->top_pipe == NULL) {
70ccab60
HW		 2417
2418 /* lock otg_master_update to process all pipes associated with
2419 * this OTG. this is done only one time.
2420 */
1a2c82a2 2421 /* watermark is for all pipes */
08b16886 2422 program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
2b13d7d3 2423
fb3466a4 2424 if (dc->debug.sanity_checks) {
2b13d7d3
TC		 2425 /* pstate stuck check after watermark update */
2426 verify_allow_pstate_change_high(dc->hwseq);
2427 }
2428
6b670fa9 2429 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
cbfd33fd 2430
6b670fa9
HW		 2431 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2432 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2433 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2434 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2435 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
cbfd33fd 2436
6b670fa9
HW		 2437 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2438 pipe_ctx->stream_res.tg);
2439 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
1a2c82a2 2440 }
cbfd33fd 2441
3be5262e 2442 if (pipe_ctx->plane_state != NULL) {
067c878a
YS		 2443 struct dc_cursor_position position = { 0 };
2444 struct pipe_ctx *cur_pipe_ctx =
2445 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2446
1a2c82a2 2447 dcn10_power_on_fe(dc, pipe_ctx, context);
9d6f264b
YS		 2448
2449 /* temporary dcn1 wa:
5667ff5c
DA		 2450 * watermark update requires toggle after a/b/c/d sets are programmed
2451 * if hubp is pg then wm value doesn't get properaged to hubp
2452 * need to toggle after ungate to ensure wm gets to hubp.
2453 *
2454 * final solution: we need to get SMU to do the toggle as
2455 * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
2456 * both driver and fw accessing same register
2457 */
9d6f264b
YS		 2458 toggle_watermark_change_req(dc->hwseq);
2459
70ccab60 2460 update_dchubp_dpp(dc, pipe_ctx, context);
067c878a
YS		 2461
2462 /* TODO: this is a hack w/a for switching from mpo to pipe split */
2463 dc_stream_set_cursor_position(pipe_ctx->stream, &position);
2464
2465 dc_stream_set_cursor_attributes(pipe_ctx->stream,
2466 &pipe_ctx->stream->cursor_attributes);
2467
2468 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
2469 dc->hwss.set_input_transfer_func(
2470 pipe_ctx, pipe_ctx->plane_state);
2471 dc->hwss.set_output_transfer_func(
2472 pipe_ctx, pipe_ctx->stream);
2473 }
70ccab60
HW		 2474 }
2475
fb3466a4 2476 if (dc->debug.sanity_checks) {
2b13d7d3
TC		 2477 /* pstate stuck check after each pipe is programmed */
2478 verify_allow_pstate_change_high(dc->hwseq);
2479 }
2480
e1b522bf 2481 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
70ccab60
HW		 2482 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2483}
2484
2485static void dcn10_pplib_apply_display_requirements(
fb3466a4 2486 struct dc *dc,
608ac7bb 2487 struct dc_state *context)
70ccab60
HW		 2488{
2489 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2490
2491 pp_display_cfg->all_displays_in_sync = false;/*todo*/
2492 pp_display_cfg->nb_pstate_switch_disable = false;
c66a54dc
DL		 2493 pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2494 pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
2495 pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2496 pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
70ccab60 2497 pp_display_cfg->avail_mclk_switch_time_us =
c66a54dc 2498 context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
70ccab60 2499 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
c66a54dc
DL		 2500 context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
2501 pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2502 pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
70ccab60
HW		 2503 dce110_fill_display_configs(context, pp_display_cfg);
2504
2505 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2506 struct dm_pp_display_configuration)) != 0)
2507 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2508
2509 dc->prev_display_config = *pp_display_cfg;
2510}
2511
6bf52028
HW		 2512static void optimize_shared_resources(struct dc *dc)
2513{
2514 if (dc->current_state->stream_count == 0) {
2515 apply_DEGVIDCN10_253_wa(dc);
2516 /* S0i2 message */
2517 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
2518 }
441ad741
EY		 2519
2520 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2521 dcn_bw_notify_pplib_of_wm_ranges(dc);
6bf52028
HW		 2522}
2523
2524static void ready_shared_resources(struct dc *dc, struct dc_state *context)
2525{
2526 if (dc->current_state->stream_count == 0 &&
2527 !dc->debug.disable_stutter)
2528 undo_DEGVIDCN10_253_wa(dc);
2529
2530 /* S0i2 message */
2531 if (dc->current_state->stream_count == 0 &&
2532 context->stream_count != 0)
2533 dcn10_pplib_apply_display_requirements(dc, context);
2534}
2535
70ccab60 2536static void dcn10_apply_ctx_for_surface(
fb3466a4 2537 struct dc *dc,
3e9ad616
EY		 2538 const struct dc_stream_state *stream,
2539 int num_planes,
608ac7bb 2540 struct dc_state *context)
70ccab60 2541{
7f10f3c2 2542 int i, be_idx;
70ccab60 2543
fb3466a4 2544 if (dc->debug.sanity_checks)
2b13d7d3
TC		 2545 verify_allow_pstate_change_high(dc->hwseq);
2546
3e9ad616
EY		 2547 be_idx = -1;
2548 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2549 if (stream == context->res_ctx.pipe_ctx[i].stream) {
2550 be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
7f10f3c2 2551 break;
3e9ad616
EY		 2552 }
2553 }
2554
2555 ASSERT(be_idx != -1);
2556
2557 if (num_planes == 0) {
2558 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2559 struct pipe_ctx *old_pipe_ctx =
608ac7bb 2560 &dc->current_state->res_ctx.pipe_ctx[i];
3e9ad616 2561
4e772ae5
YS		 2562 if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) {
2563 old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true);
3e9ad616 2564 dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx);
4e772ae5 2565 }
3e9ad616
EY		 2566 }
2567 return;
2568 }
7f10f3c2 2569
cfe4645e 2570 /* reset unused mpcc */
71a2f23e 2571 for (i = 0; i < dc->res_pool->pipe_count; i++) {
cfe4645e
DL		 2572 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2573 struct pipe_ctx *old_pipe_ctx =
608ac7bb 2574 &dc->current_state->res_ctx.pipe_ctx[i];
7f10f3c2 2575
3be5262e 2576 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
7f10f3c2
TC		 2577 continue;
2578
4bdbab3e
EY		 2579 /*
2580 * Powergate reused pipes that are not powergated
2581 * fairly hacky right now, using opp_id as indicator
2582 */
7f10f3c2 2583
3be5262e 2584 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
8feabd03 2585 if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
4bdbab3e 2586 dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
aa985070
EY		 2587 /*
2588 * power down fe will unlock when calling reset, need
2589 * to lock it back here. Messy, need rework.
2590 */
6b670fa9 2591 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
aa985070 2592 }
4bdbab3e 2593 }
cfe4645e 2594
7f10f3c2 2595
3be5262e 2596 if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state)
cfe4645e 2597 || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
6b670fa9 2598 if (old_pipe_ctx->stream_res.tg->inst != be_idx)
7f10f3c2
TC		 2599 continue;
2600
71a2f23e
EY		 2601 if (!old_pipe_ctx->top_pipe) {
2602 ASSERT(0);
2603 continue;
2604 }
2605
4bdbab3e 2606 /* reset mpc */
cc408d72
DL		 2607 dc->res_pool->mpc->funcs->remove(
2608 dc->res_pool->mpc,
7f4a7253
EB		 2609 &(old_pipe_ctx->stream_res.opp->mpc_tree),
2610 old_pipe_ctx->stream_res.opp->inst,
cc408d72 2611 old_pipe_ctx->pipe_idx);
8feabd03 2612 old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true;
2b13d7d3 2613
6be425f3
EY		 2614 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2615 "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
2616 old_pipe_ctx->mpcc->inst);*/
2617
fb3466a4 2618 if (dc->debug.sanity_checks)
2b13d7d3
TC		 2619 verify_allow_pstate_change_high(dc->hwseq);
2620
cfe4645e
DL		 2621 old_pipe_ctx->top_pipe = NULL;
2622 old_pipe_ctx->bottom_pipe = NULL;
3be5262e 2623 old_pipe_ctx->plane_state = NULL;
50d4cfdc 2624 old_pipe_ctx->stream = NULL;
cfe4645e
DL		 2625
2626 dm_logger_write(dc->ctx->logger, LOG_DC,
2627 "Reset mpcc for pipe %d\n",
2628 old_pipe_ctx->pipe_idx);
2629 }
71a2f23e 2630 }
cfe4645e 2631
70ccab60
HW		 2632 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2633 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2634
3e9ad616 2635 if (pipe_ctx->stream != stream)
70ccab60
HW		 2636 continue;
2637
2638 /* looking for top pipe to program */
f0558542 2639 if (!pipe_ctx->top_pipe)
70ccab60
HW		 2640 program_all_pipe_in_tree(dc, pipe_ctx, context);
2641 }
2642
c9742685
DL		 2643 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2644 "\n============== Watermark parameters ==============\n"
2645 "a.urgent_ns: %d \n"
2646 "a.cstate_enter_plus_exit: %d \n"
2647 "a.cstate_exit: %d \n"
2648 "a.pstate_change: %d \n"
2649 "a.pte_meta_urgent: %d \n"
2650 "b.urgent_ns: %d \n"
2651 "b.cstate_enter_plus_exit: %d \n"
2652 "b.cstate_exit: %d \n"
2653 "b.pstate_change: %d \n"
2654 "b.pte_meta_urgent: %d \n",
2655 context->bw.dcn.watermarks.a.urgent_ns,
2656 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2657 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2658 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2659 context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2660 context->bw.dcn.watermarks.b.urgent_ns,
2661 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2662 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2663 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2664 context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2665 );
2666 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2667 "\nc.urgent_ns: %d \n"
2668 "c.cstate_enter_plus_exit: %d \n"
2669 "c.cstate_exit: %d \n"
2670 "c.pstate_change: %d \n"
2671 "c.pte_meta_urgent: %d \n"
2672 "d.urgent_ns: %d \n"
2673 "d.cstate_enter_plus_exit: %d \n"
2674 "d.cstate_exit: %d \n"
2675 "d.pstate_change: %d \n"
2676 "d.pte_meta_urgent: %d \n"
2677 "========================================================\n",
2678 context->bw.dcn.watermarks.c.urgent_ns,
2679 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2680 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2681 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2682 context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2683 context->bw.dcn.watermarks.d.urgent_ns,
2684 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2685 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2686 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2687 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2688 );
2b13d7d3 2689
fb3466a4 2690 if (dc->debug.sanity_checks)
2b13d7d3 2691 verify_allow_pstate_change_high(dc->hwseq);
70ccab60
HW		 2692}
2693
2694static void dcn10_set_bandwidth(
fb3466a4 2695 struct dc *dc,
608ac7bb 2696 struct dc_state *context,
70ccab60
HW		 2697 bool decrease_allowed)
2698{
5f06b3cf
TC		 2699 struct pp_smu_display_requirement_rv *smu_req_cur =
2700 &dc->res_pool->pp_smu_req;
2701 struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2702 struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
70ccab60 2703
fb3466a4 2704 if (dc->debug.sanity_checks) {
665da60f
CM		 2705 verify_allow_pstate_change_high(dc->hwseq);
2706 }
2707
70ccab60
HW		 2708 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2709 return;
2710
c66a54dc 2711 if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
608ac7bb 2712 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
70ccab60
HW		 2713 dc->res_pool->display_clock->funcs->set_clock(
2714 dc->res_pool->display_clock,
9037d802 2715 context->bw.dcn.calc_clk.dispclk_khz);
608ac7bb 2716 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
c66a54dc 2717 context->bw.dcn.calc_clk.dispclk_khz;
70ccab60 2718 }
c66a54dc 2719 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
608ac7bb 2720 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
5f06b3cf
TC		 2721 smu_req.hard_min_dcefclk_khz =
2722 context->bw.dcn.calc_clk.dcfclk_khz;
70ccab60 2723 }
c66a54dc 2724 if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
608ac7bb 2725 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
5f06b3cf 2726 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
c66a54dc
DL		 2727 }
2728 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
608ac7bb
JZ		 2729 > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2730 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
c66a54dc
DL		 2731 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2732 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2733 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2734 }
5f06b3cf
TC		 2735
2736 smu_req.display_count = context->stream_count;
2737
2738 if (pp_smu->set_display_requirement)
2739 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2740
2741 *smu_req_cur = smu_req;
2742
c66a54dc
DL		 2743 /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2744 if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
608ac7bb
JZ		 2745 < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2746 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
c66a54dc
DL		 2747 context->bw.dcn.calc_clk.dram_ccm_us;
2748 context->bw.dcn.cur_clk.dram_ccm_us =
2749 context->bw.dcn.calc_clk.dram_ccm_us;
2750 }
2751 if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
608ac7bb
JZ		 2752 < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2753 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
c66a54dc
DL		 2754 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2755 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2756 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
70ccab60
HW		 2757 }
2758 dcn10_pplib_apply_display_requirements(dc, context);
2b13d7d3 2759
fb3466a4 2760 if (dc->debug.sanity_checks) {
665da60f
CM		 2761 verify_allow_pstate_change_high(dc->hwseq);
2762 }
2763
2b13d7d3 2764 /* need to fix this function. not doing the right thing here */
70ccab60
HW		 2765}
2766
70ccab60
HW		 2767static void set_drr(struct pipe_ctx **pipe_ctx,
2768 int num_pipes, int vmin, int vmax)
2769{
2770 int i = 0;
2771 struct drr_params params = {0};
2772
2773 params.vertical_total_max = vmax;
2774 params.vertical_total_min = vmin;
2775
2776 /* TODO: If multiple pipes are to be supported, you need
2777 * some GSL stuff
2778 */
2779 for (i = 0; i < num_pipes; i++) {
6b670fa9 2780 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
70ccab60
HW		 2781 }
2782}
2783
2784static void get_position(struct pipe_ctx **pipe_ctx,
2785 int num_pipes,
2786 struct crtc_position *position)
2787{
2788 int i = 0;
2789
2790 /* TODO: handle pipes > 1
2791 */
2792 for (i = 0; i < num_pipes; i++)
6b670fa9 2793 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
70ccab60
HW		 2794}
2795
2796static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2797 int num_pipes, const struct dc_static_screen_events *events)
2798{
2799 unsigned int i;
2800 unsigned int value = 0;
2801
2802 if (events->surface_update)
2803 value |= 0x80;
2804 if (events->cursor_update)
2805 value |= 0x2;
2806
2807 for (i = 0; i < num_pipes; i++)
6b670fa9
HW		 2808 pipe_ctx[i]->stream_res.tg->funcs->
2809 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
70ccab60
HW		 2810}
2811
2812static void set_plane_config(
fb3466a4 2813 const struct dc *dc,
70ccab60
HW		 2814 struct pipe_ctx *pipe_ctx,
2815 struct resource_context *res_ctx)
2816{
2817 /* TODO */
2818 program_gamut_remap(pipe_ctx);
2819}
2820
4fac6da2 2821static void dcn10_config_stereo_parameters(
0971c40e 2822 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
7f5c22d1 2823{
4fa086b9 2824 enum view_3d_format view_format = stream->view_format;
7f5c22d1 2825 enum dc_timing_3d_format timing_3d_format =\
4fa086b9 2826 stream->timing.timing_3d_format;
7f5c22d1
VP		 2827 bool non_stereo_timing = false;
2828
2829 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2830 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2831 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2832 non_stereo_timing = true;
2833
2834 if (non_stereo_timing == false &&
2835 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2836
2837 flags->PROGRAM_STEREO = 1;
2838 flags->PROGRAM_POLARITY = 1;
2839 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2840 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2841 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2842 enum display_dongle_type dongle = \
d0778ebf 2843 stream->sink->link->ddc->dongle_type;
7f5c22d1
VP		 2844 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2845 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2846 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2847 flags->DISABLE_STEREO_DP_SYNC = 1;
2848 }
2849 flags->RIGHT_EYE_POLARITY =\
4fa086b9 2850 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
7f5c22d1
VP		 2851 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2852 flags->FRAME_PACKED = 1;
2853 }
2854
2855 return;
2856}
2857
fb3466a4 2858static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
7f5c22d1
VP		 2859{
2860 struct crtc_stereo_flags flags = { 0 };
0971c40e 2861 struct dc_stream_state *stream = pipe_ctx->stream;
7f5c22d1
VP		 2862
2863 dcn10_config_stereo_parameters(stream, &flags);
2864
a6a6cb34
HW		 2865 pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
2866 pipe_ctx->stream_res.opp,
7f5c22d1 2867 flags.PROGRAM_STEREO == 1 ? true:false,
4fa086b9 2868 stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
7f5c22d1 2869
6b670fa9
HW		 2870 pipe_ctx->stream_res.tg->funcs->program_stereo(
2871 pipe_ctx->stream_res.tg,
4fa086b9 2872 &stream->timing,
7f5c22d1
VP		 2873 &flags);
2874
7f5c22d1
VP		 2875 return;
2876}
2877
6be425f3 2878static void dcn10_wait_for_mpcc_disconnect(
fb3466a4 2879 struct dc *dc,
6be425f3
EY		 2880 struct resource_pool *res_pool,
2881 struct pipe_ctx *pipe_ctx)
87480687
EY		 2882{
2883 int i;
87480687 2884
fb3466a4 2885 if (dc->debug.sanity_checks) {
665da60f
CM		 2886 verify_allow_pstate_change_high(dc->hwseq);
2887 }
2888
a6a6cb34 2889 if (!pipe_ctx->stream_res.opp)
6be425f3
EY		 2890 return;
2891
2892 for (i = 0; i < MAX_PIPES; i++) {
a6a6cb34 2893 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
cc408d72 2894 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
a6a6cb34 2895 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
8feabd03 2896 res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
6be425f3
EY		 2897 /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2898 "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2899 i);*/
87480687
EY		 2900 }
2901 }
6be425f3 2902
fb3466a4 2903 if (dc->debug.sanity_checks) {
665da60f
CM		 2904 verify_allow_pstate_change_high(dc->hwseq);
2905 }
2906
87480687
EY		 2907}
2908
4fac6da2 2909static bool dcn10_dummy_display_power_gating(
fb3466a4 2910 struct dc *dc,
4fac6da2
DL		 2911 uint8_t controller_id,
2912 struct dc_bios *dcb,
2b13d7d3
TC		 2913 enum pipe_gating_control power_gating)
2914{
2915 return true;
2916}
2917
2918void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2919{
3be5262e 2920 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
6b670fa9 2921 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2b13d7d3 2922
3be5262e 2923 if (plane_state == NULL)
2b13d7d3
TC		 2924 return;
2925
3be5262e 2926 plane_state->status.is_flip_pending =
8feabd03
YHL		 2927 pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2928 pipe_ctx->plane_res.hubp);
2b13d7d3 2929
8feabd03
YHL		 2930 plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2931 if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2b13d7d3 2932 tg->funcs->is_stereo_left_eye) {
3be5262e 2933 plane_state->status.is_right_eye =
6b670fa9 2934 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2b13d7d3
TC		 2935 }
2936}
4fac6da2 2937
0cb8a881
YHL		 2938
2939
70ccab60 2940static const struct hw_sequencer_funcs dcn10_funcs = {
1bf56e62 2941 .program_gamut_remap = program_gamut_remap,
abe07e80 2942 .program_csc_matrix = program_csc_matrix,
b02c3b05 2943 .init_hw = dcn10_init_hw,
70ccab60
HW		 2944 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2945 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2946 .set_plane_config = set_plane_config,
503a7c6f 2947 .update_plane_addr = dcn10_update_plane_addr,
08b16886 2948 .update_dchub = dcn10_update_dchub,
2b13d7d3 2949 .update_pending_status = dcn10_update_pending_status,
70ccab60
HW		 2950 .set_input_transfer_func = dcn10_set_input_transfer_func,
2951 .set_output_transfer_func = dcn10_set_output_transfer_func,
2952 .power_down = dce110_power_down,
2953 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2954 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2955 .update_info_frame = dce110_update_info_frame,
2956 .enable_stream = dce110_enable_stream,
2957 .disable_stream = dce110_disable_stream,
2958 .unblank_stream = dce110_unblank_stream,
4fac6da2 2959 .enable_display_power_gating = dcn10_dummy_display_power_gating,
70ccab60
HW		 2960 .power_down_front_end = dcn10_power_down_fe,
2961 .power_on_front_end = dcn10_power_on_fe,
2962 .pipe_control_lock = dcn10_pipe_control_lock,
2963 .set_bandwidth = dcn10_set_bandwidth,
2964 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2965 .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2966 .set_drr = set_drr,
2967 .get_position = get_position,
7f5c22d1 2968 .set_static_screen_control = set_static_screen_control,
15e17335
CL		 2969 .setup_stereo = dcn10_setup_stereo,
2970 .set_avmute = dce110_set_avmute,
87480687 2971 .log_hw_state = dcn10_log_hw_state,
41f97c07
HW		 2972 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2973 .ready_shared_resources = ready_shared_resources,
2974 .optimize_shared_resources = optimize_shared_resources,
87401969
AJ		 2975 .edp_backlight_control = hwss_edp_backlight_control,
2976 .edp_power_control = hwss_edp_power_control
70ccab60
HW		 2977};
2978
2979
fb3466a4 2980void dcn10_hw_sequencer_construct(struct dc *dc)
70ccab60
HW		 2981{
2982 dc->hwss = dcn10_funcs;
70ccab60
HW		 2983}
2984
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