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70ccab60 HW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "dm_services.h" | |
27 | #include "dc.h" | |
28 | ||
29 | #include "resource.h" | |
30 | #include "include/irq_service_interface.h" | |
31 | #include "dcn10/dcn10_resource.h" | |
32 | ||
33 | #include "dcn10/dcn10_ipp.h" | |
34 | #include "dcn10/dcn10_mpc.h" | |
35 | #include "irq/dcn10/irq_service_dcn10.h" | |
587cdfe9 | 36 | #include "dcn10/dcn10_dpp.h" |
70ccab60 HW |
37 | #include "dcn10/dcn10_timing_generator.h" |
38 | #include "dcn10/dcn10_hw_sequencer.h" | |
39 | #include "dce110/dce110_hw_sequencer.h" | |
40 | #include "dcn10/dcn10_opp.h" | |
41 | #include "dce/dce_link_encoder.h" | |
42 | #include "dce/dce_stream_encoder.h" | |
43 | #include "dce/dce_clocks.h" | |
44 | #include "dce/dce_clock_source.h" | |
70ccab60 HW |
45 | #include "dce/dce_audio.h" |
46 | #include "dce/dce_hwseq.h" | |
47 | #include "../virtual/virtual_stream_encoder.h" | |
48 | #include "dce110/dce110_resource.h" | |
1dc90497 | 49 | #include "dce112/dce112_resource.h" |
86be9a04 | 50 | #include "dcn10_hubp.h" |
70ccab60 HW |
51 | |
52 | #include "vega10/soc15ip.h" | |
53 | ||
54 | #include "raven1/DCN/dcn_1_0_offset.h" | |
55 | #include "raven1/DCN/dcn_1_0_sh_mask.h" | |
56 | ||
57 | #include "raven1/NBIO/nbio_7_0_offset.h" | |
58 | ||
59 | #include "raven1/MMHUB/mmhub_9_1_offset.h" | |
60 | #include "raven1/MMHUB/mmhub_9_1_sh_mask.h" | |
61 | ||
62 | #include "reg_helper.h" | |
63 | #include "dce/dce_abm.h" | |
64 | #include "dce/dce_dmcu.h" | |
65 | ||
66 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL | |
67 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f | |
68 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
69 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f | |
70 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
71 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f | |
72 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
73 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f | |
74 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
75 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f | |
76 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
77 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f | |
78 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
79 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f | |
80 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
81 | #endif | |
82 | ||
83 | ||
84 | enum dcn10_clk_src_array_id { | |
85 | DCN10_CLK_SRC_PLL0, | |
86 | DCN10_CLK_SRC_PLL1, | |
87 | DCN10_CLK_SRC_PLL2, | |
88 | DCN10_CLK_SRC_PLL3, | |
89 | DCN10_CLK_SRC_TOTAL | |
90 | }; | |
91 | ||
92 | /* begin ********************* | |
93 | * macros to expend register list macro defined in HW object header file */ | |
94 | ||
95 | /* DCN */ | |
96 | #define BASE_INNER(seg) \ | |
97 | DCE_BASE__INST0_SEG ## seg | |
98 | ||
99 | #define BASE(seg) \ | |
100 | BASE_INNER(seg) | |
101 | ||
102 | #define SR(reg_name)\ | |
103 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
104 | mm ## reg_name | |
105 | ||
106 | #define SRI(reg_name, block, id)\ | |
107 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
108 | mm ## block ## id ## _ ## reg_name | |
109 | ||
110 | ||
111 | #define SRII(reg_name, block, id)\ | |
112 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
113 | mm ## block ## id ## _ ## reg_name | |
114 | ||
115 | /* NBIO */ | |
116 | #define NBIO_BASE_INNER(seg) \ | |
117 | NBIF_BASE__INST0_SEG ## seg | |
118 | ||
119 | #define NBIO_BASE(seg) \ | |
120 | NBIO_BASE_INNER(seg) | |
121 | ||
122 | #define NBIO_SR(reg_name)\ | |
123 | .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ | |
124 | mm ## reg_name | |
125 | ||
1f7f3aec TC |
126 | /* MMHUB */ |
127 | #define MMHUB_BASE_INNER(seg) \ | |
128 | MMHUB_BASE__INST0_SEG ## seg | |
70ccab60 | 129 | |
1f7f3aec TC |
130 | #define MMHUB_BASE(seg) \ |
131 | MMHUB_BASE_INNER(seg) | |
70ccab60 | 132 | |
1f7f3aec TC |
133 | #define MMHUB_SR(reg_name)\ |
134 | .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ | |
70ccab60 HW |
135 | mm ## reg_name |
136 | ||
137 | /* macros to expend register list macro defined in HW object header file | |
138 | * end *********************/ | |
139 | ||
70ccab60 HW |
140 | |
141 | static const struct dce_dmcu_registers dmcu_regs = { | |
142 | DMCU_DCN10_REG_LIST() | |
143 | }; | |
144 | ||
145 | static const struct dce_dmcu_shift dmcu_shift = { | |
146 | DMCU_MASK_SH_LIST_DCN10(__SHIFT) | |
147 | }; | |
148 | ||
149 | static const struct dce_dmcu_mask dmcu_mask = { | |
150 | DMCU_MASK_SH_LIST_DCN10(_MASK) | |
151 | }; | |
152 | ||
153 | static const struct dce_abm_registers abm_regs = { | |
154 | ABM_DCN10_REG_LIST(0) | |
155 | }; | |
156 | ||
157 | static const struct dce_abm_shift abm_shift = { | |
158 | ABM_MASK_SH_LIST_DCN10(__SHIFT) | |
159 | }; | |
160 | ||
161 | static const struct dce_abm_mask abm_mask = { | |
162 | ABM_MASK_SH_LIST_DCN10(_MASK) | |
163 | }; | |
164 | ||
165 | #define stream_enc_regs(id)\ | |
166 | [id] = {\ | |
167 | SE_DCN_REG_LIST(id),\ | |
168 | .TMDS_CNTL = 0,\ | |
169 | .AFMT_AVI_INFO0 = 0,\ | |
170 | .AFMT_AVI_INFO1 = 0,\ | |
171 | .AFMT_AVI_INFO2 = 0,\ | |
172 | .AFMT_AVI_INFO3 = 0,\ | |
173 | } | |
174 | ||
175 | static const struct dce110_stream_enc_registers stream_enc_regs[] = { | |
176 | stream_enc_regs(0), | |
177 | stream_enc_regs(1), | |
178 | stream_enc_regs(2), | |
179 | stream_enc_regs(3), | |
180 | }; | |
181 | ||
182 | static const struct dce_stream_encoder_shift se_shift = { | |
183 | SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) | |
184 | }; | |
185 | ||
186 | static const struct dce_stream_encoder_mask se_mask = { | |
187 | SE_COMMON_MASK_SH_LIST_DCN10(_MASK), | |
188 | .AFMT_GENERIC0_UPDATE = 0, | |
189 | .AFMT_GENERIC2_UPDATE = 0, | |
190 | .DP_DYN_RANGE = 0, | |
191 | .DP_YCBCR_RANGE = 0, | |
192 | .HDMI_AVI_INFO_SEND = 0, | |
193 | .HDMI_AVI_INFO_CONT = 0, | |
194 | .HDMI_AVI_INFO_LINE = 0, | |
195 | .DP_SEC_AVI_ENABLE = 0, | |
196 | .AFMT_AVI_INFO_VERSION = 0 | |
197 | }; | |
198 | ||
199 | #define audio_regs(id)\ | |
200 | [id] = {\ | |
201 | AUD_COMMON_REG_LIST(id)\ | |
202 | } | |
203 | ||
204 | static const struct dce_audio_registers audio_regs[] = { | |
205 | audio_regs(0), | |
206 | audio_regs(1), | |
207 | audio_regs(2), | |
208 | audio_regs(3), | |
209 | }; | |
210 | ||
211 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ | |
212 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ | |
213 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ | |
214 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) | |
215 | ||
216 | static const struct dce_audio_shift audio_shift = { | |
217 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
218 | }; | |
219 | ||
220 | static const struct dce_aduio_mask audio_mask = { | |
221 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) | |
222 | }; | |
223 | ||
224 | #define aux_regs(id)\ | |
225 | [id] = {\ | |
226 | AUX_REG_LIST(id)\ | |
227 | } | |
228 | ||
229 | static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { | |
230 | aux_regs(0), | |
231 | aux_regs(1), | |
232 | aux_regs(2), | |
233 | aux_regs(3), | |
234 | aux_regs(4), | |
235 | aux_regs(5) | |
236 | }; | |
237 | ||
238 | #define hpd_regs(id)\ | |
239 | [id] = {\ | |
240 | HPD_REG_LIST(id)\ | |
241 | } | |
242 | ||
243 | static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
244 | hpd_regs(0), | |
245 | hpd_regs(1), | |
246 | hpd_regs(2), | |
247 | hpd_regs(3), | |
248 | hpd_regs(4), | |
249 | hpd_regs(5) | |
250 | }; | |
251 | ||
252 | #define link_regs(id)\ | |
253 | [id] = {\ | |
254 | LE_DCN10_REG_LIST(id), \ | |
255 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | |
256 | } | |
257 | ||
258 | static const struct dce110_link_enc_registers link_enc_regs[] = { | |
259 | link_regs(0), | |
260 | link_regs(1), | |
261 | link_regs(2), | |
262 | link_regs(3), | |
263 | link_regs(4), | |
264 | link_regs(5), | |
265 | link_regs(6), | |
266 | }; | |
267 | ||
268 | #define ipp_regs(id)\ | |
269 | [id] = {\ | |
35ce37d6 | 270 | IPP_REG_LIST_DCN10(id),\ |
70ccab60 HW |
271 | } |
272 | ||
273 | static const struct dcn10_ipp_registers ipp_regs[] = { | |
274 | ipp_regs(0), | |
275 | ipp_regs(1), | |
276 | ipp_regs(2), | |
277 | ipp_regs(3), | |
278 | }; | |
279 | ||
280 | static const struct dcn10_ipp_shift ipp_shift = { | |
35ce37d6 | 281 | IPP_MASK_SH_LIST_DCN10(__SHIFT) |
70ccab60 HW |
282 | }; |
283 | ||
284 | static const struct dcn10_ipp_mask ipp_mask = { | |
35ce37d6 | 285 | IPP_MASK_SH_LIST_DCN10(_MASK), |
70ccab60 HW |
286 | }; |
287 | ||
288 | #define opp_regs(id)\ | |
289 | [id] = {\ | |
13066f9f | 290 | OPP_REG_LIST_DCN10(id),\ |
70ccab60 HW |
291 | } |
292 | ||
293 | static const struct dcn10_opp_registers opp_regs[] = { | |
294 | opp_regs(0), | |
295 | opp_regs(1), | |
296 | opp_regs(2), | |
297 | opp_regs(3), | |
298 | }; | |
299 | ||
300 | static const struct dcn10_opp_shift opp_shift = { | |
13066f9f | 301 | OPP_MASK_SH_LIST_DCN10(__SHIFT) |
70ccab60 HW |
302 | }; |
303 | ||
304 | static const struct dcn10_opp_mask opp_mask = { | |
13066f9f | 305 | OPP_MASK_SH_LIST_DCN10(_MASK), |
70ccab60 HW |
306 | }; |
307 | ||
308 | #define tf_regs(id)\ | |
309 | [id] = {\ | |
b1a4eb99 | 310 | TF_REG_LIST_DCN10(id),\ |
70ccab60 HW |
311 | } |
312 | ||
587cdfe9 | 313 | static const struct dcn_dpp_registers tf_regs[] = { |
70ccab60 HW |
314 | tf_regs(0), |
315 | tf_regs(1), | |
316 | tf_regs(2), | |
317 | tf_regs(3), | |
318 | }; | |
319 | ||
587cdfe9 | 320 | static const struct dcn_dpp_shift tf_shift = { |
b1a4eb99 | 321 | TF_REG_LIST_SH_MASK_DCN10(__SHIFT) |
70ccab60 HW |
322 | }; |
323 | ||
587cdfe9 | 324 | static const struct dcn_dpp_mask tf_mask = { |
b1a4eb99 | 325 | TF_REG_LIST_SH_MASK_DCN10(_MASK), |
70ccab60 HW |
326 | }; |
327 | ||
cc408d72 DL |
328 | static const struct dcn_mpc_registers mpc_regs = { |
329 | MPC_COMMON_REG_LIST_DCN1_0(0), | |
330 | MPC_COMMON_REG_LIST_DCN1_0(1), | |
331 | MPC_COMMON_REG_LIST_DCN1_0(2), | |
8534575f EB |
332 | MPC_COMMON_REG_LIST_DCN1_0(3), |
333 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), | |
334 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), | |
335 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), | |
336 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) | |
70ccab60 HW |
337 | }; |
338 | ||
cc408d72 DL |
339 | static const struct dcn_mpc_shift mpc_shift = { |
340 | MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) | |
70ccab60 HW |
341 | }; |
342 | ||
cc408d72 DL |
343 | static const struct dcn_mpc_mask mpc_mask = { |
344 | MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), | |
70ccab60 HW |
345 | }; |
346 | ||
347 | #define tg_regs(id)\ | |
348 | [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} | |
349 | ||
350 | static const struct dcn_tg_registers tg_regs[] = { | |
351 | tg_regs(0), | |
352 | tg_regs(1), | |
353 | tg_regs(2), | |
354 | tg_regs(3), | |
355 | }; | |
356 | ||
357 | static const struct dcn_tg_shift tg_shift = { | |
358 | TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) | |
359 | }; | |
360 | ||
361 | static const struct dcn_tg_mask tg_mask = { | |
362 | TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) | |
363 | }; | |
364 | ||
365 | ||
366 | static const struct bios_registers bios_regs = { | |
367 | NBIO_SR(BIOS_SCRATCH_6) | |
368 | }; | |
369 | ||
370 | #define mi_regs(id)\ | |
371 | [id] = {\ | |
db3bc050 | 372 | MI_REG_LIST_DCN10(id)\ |
70ccab60 HW |
373 | } |
374 | ||
375 | ||
376 | static const struct dcn_mi_registers mi_regs[] = { | |
377 | mi_regs(0), | |
378 | mi_regs(1), | |
379 | mi_regs(2), | |
380 | mi_regs(3), | |
381 | }; | |
382 | ||
383 | static const struct dcn_mi_shift mi_shift = { | |
db3bc050 | 384 | MI_MASK_SH_LIST_DCN10(__SHIFT) |
70ccab60 HW |
385 | }; |
386 | ||
387 | static const struct dcn_mi_mask mi_mask = { | |
db3bc050 | 388 | MI_MASK_SH_LIST_DCN10(_MASK) |
70ccab60 HW |
389 | }; |
390 | ||
391 | #define clk_src_regs(index, pllid)\ | |
392 | [index] = {\ | |
393 | CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ | |
394 | } | |
395 | ||
396 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
397 | clk_src_regs(0, A), | |
398 | clk_src_regs(1, B), | |
399 | clk_src_regs(2, C), | |
400 | clk_src_regs(3, D) | |
401 | }; | |
402 | ||
403 | static const struct dce110_clk_src_shift cs_shift = { | |
404 | CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) | |
405 | }; | |
406 | ||
407 | static const struct dce110_clk_src_mask cs_mask = { | |
408 | CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) | |
409 | }; | |
410 | ||
411 | ||
412 | static const struct resource_caps res_cap = { | |
413 | .num_timing_generator = 4, | |
414 | .num_video_plane = 4, | |
415 | .num_audio = 4, | |
416 | .num_stream_encoder = 4, | |
417 | .num_pll = 4, | |
418 | }; | |
419 | ||
420 | static const struct dc_debug debug_defaults_drv = { | |
2b13d7d3 | 421 | .sanity_checks = true, |
70ccab60 HW |
422 | .disable_dmcu = true, |
423 | .force_abm_enable = false, | |
424 | .timing_trace = false, | |
c9742685 | 425 | .clock_trace = true, |
4f4ee686 HW |
426 | |
427 | .min_disp_clk_khz = 300000, | |
428 | ||
70ccab60 | 429 | .disable_pplib_clock_request = true, |
d5c40d53 | 430 | .disable_pplib_wm_range = false, |
441ad741 | 431 | .pplib_wm_report_mode = WM_REPORT_DEFAULT, |
db64fbe7 | 432 | .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, |
e92b44fd | 433 | .force_single_disp_pipe_split = true, |
a32a7708 | 434 | .disable_dcc = DCC_ENABLE, |
6512387a | 435 | .voltage_align_fclk = true, |
73fb63e7 | 436 | .disable_stereo_support = true, |
f6cb588a | 437 | .vsr_support = true, |
215a6f05 | 438 | .performance_trace = false, |
70ccab60 HW |
439 | }; |
440 | ||
441 | static const struct dc_debug debug_defaults_diags = { | |
70ccab60 HW |
442 | .disable_dmcu = true, |
443 | .force_abm_enable = false, | |
444 | .timing_trace = true, | |
c9742685 | 445 | .clock_trace = true, |
41f97c07 | 446 | .disable_stutter = true, |
70ccab60 | 447 | .disable_pplib_clock_request = true, |
6d04ee9d | 448 | .disable_pplib_wm_range = true |
70ccab60 HW |
449 | }; |
450 | ||
d94585a0 | 451 | static void dcn10_dpp_destroy(struct dpp **dpp) |
70ccab60 | 452 | { |
d94585a0 YHL |
453 | kfree(TO_DCN10_DPP(*dpp)); |
454 | *dpp = NULL; | |
70ccab60 HW |
455 | } |
456 | ||
d94585a0 | 457 | static struct dpp *dcn10_dpp_create( |
70ccab60 HW |
458 | struct dc_context *ctx, |
459 | uint32_t inst) | |
460 | { | |
587cdfe9 | 461 | struct dcn10_dpp *dpp = |
2004f45e | 462 | kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); |
70ccab60 | 463 | |
587cdfe9 | 464 | if (!dpp) |
70ccab60 HW |
465 | return NULL; |
466 | ||
d94585a0 YHL |
467 | dpp1_construct(dpp, ctx, inst, |
468 | &tf_regs[inst], &tf_shift, &tf_mask); | |
c13b408b | 469 | return &dpp->base; |
70ccab60 HW |
470 | } |
471 | ||
472 | static struct input_pixel_processor *dcn10_ipp_create( | |
473 | struct dc_context *ctx, uint32_t inst) | |
474 | { | |
475 | struct dcn10_ipp *ipp = | |
2004f45e | 476 | kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); |
70ccab60 HW |
477 | |
478 | if (!ipp) { | |
479 | BREAK_TO_DEBUGGER(); | |
480 | return NULL; | |
481 | } | |
482 | ||
483 | dcn10_ipp_construct(ipp, ctx, inst, | |
484 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
485 | return &ipp->base; | |
486 | } | |
487 | ||
488 | ||
489 | static struct output_pixel_processor *dcn10_opp_create( | |
490 | struct dc_context *ctx, uint32_t inst) | |
491 | { | |
492 | struct dcn10_opp *opp = | |
2004f45e | 493 | kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); |
70ccab60 HW |
494 | |
495 | if (!opp) { | |
496 | BREAK_TO_DEBUGGER(); | |
497 | return NULL; | |
498 | } | |
499 | ||
500 | dcn10_opp_construct(opp, ctx, inst, | |
501 | &opp_regs[inst], &opp_shift, &opp_mask); | |
502 | return &opp->base; | |
503 | } | |
504 | ||
cc408d72 | 505 | static struct mpc *dcn10_mpc_create(struct dc_context *ctx) |
70ccab60 | 506 | { |
2004f45e HW |
507 | struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), |
508 | GFP_KERNEL); | |
70ccab60 | 509 | |
cc408d72 | 510 | if (!mpc10) |
70ccab60 HW |
511 | return NULL; |
512 | ||
cc408d72 DL |
513 | dcn10_mpc_construct(mpc10, ctx, |
514 | &mpc_regs, | |
515 | &mpc_shift, | |
516 | &mpc_mask, | |
517 | 4); | |
70ccab60 | 518 | |
cc408d72 | 519 | return &mpc10->base; |
70ccab60 HW |
520 | } |
521 | ||
522 | static struct timing_generator *dcn10_timing_generator_create( | |
523 | struct dc_context *ctx, | |
524 | uint32_t instance) | |
525 | { | |
526 | struct dcn10_timing_generator *tgn10 = | |
2004f45e | 527 | kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL); |
70ccab60 HW |
528 | |
529 | if (!tgn10) | |
530 | return NULL; | |
531 | ||
532 | tgn10->base.inst = instance; | |
533 | tgn10->base.ctx = ctx; | |
534 | ||
535 | tgn10->tg_regs = &tg_regs[instance]; | |
536 | tgn10->tg_shift = &tg_shift; | |
537 | tgn10->tg_mask = &tg_mask; | |
538 | ||
539 | dcn10_timing_generator_init(tgn10); | |
540 | ||
541 | return &tgn10->base; | |
542 | } | |
543 | ||
544 | static const struct encoder_feature_support link_enc_feature = { | |
545 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
546 | .max_hdmi_pixel_clock = 600000, | |
547 | .ycbcr420_supported = true, | |
548 | .flags.bits.IS_HBR2_CAPABLE = true, | |
549 | .flags.bits.IS_HBR3_CAPABLE = true, | |
550 | .flags.bits.IS_TPS3_CAPABLE = true, | |
551 | .flags.bits.IS_TPS4_CAPABLE = true, | |
552 | .flags.bits.IS_YCBCR_CAPABLE = true | |
553 | }; | |
554 | ||
555 | struct link_encoder *dcn10_link_encoder_create( | |
556 | const struct encoder_init_data *enc_init_data) | |
557 | { | |
558 | struct dce110_link_encoder *enc110 = | |
2004f45e | 559 | kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); |
70ccab60 HW |
560 | |
561 | if (!enc110) | |
562 | return NULL; | |
563 | ||
c60ae112 DA |
564 | dce110_link_encoder_construct(enc110, |
565 | enc_init_data, | |
566 | &link_enc_feature, | |
567 | &link_enc_regs[enc_init_data->transmitter], | |
568 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
569 | &link_enc_hpd_regs[enc_init_data->hpd_source]); | |
570 | ||
571 | return &enc110->base; | |
70ccab60 HW |
572 | } |
573 | ||
574 | struct clock_source *dcn10_clock_source_create( | |
575 | struct dc_context *ctx, | |
576 | struct dc_bios *bios, | |
577 | enum clock_source_id id, | |
578 | const struct dce110_clk_src_regs *regs, | |
579 | bool dp_clk_src) | |
580 | { | |
581 | struct dce110_clk_src *clk_src = | |
2004f45e | 582 | kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); |
70ccab60 HW |
583 | |
584 | if (!clk_src) | |
585 | return NULL; | |
586 | ||
587 | if (dce110_clk_src_construct(clk_src, ctx, bios, id, | |
588 | regs, &cs_shift, &cs_mask)) { | |
589 | clk_src->base.dp_clk_src = dp_clk_src; | |
590 | return &clk_src->base; | |
591 | } | |
592 | ||
03a8742f | 593 | kfree(clk_src); |
70ccab60 HW |
594 | BREAK_TO_DEBUGGER(); |
595 | return NULL; | |
596 | } | |
597 | ||
598 | static void read_dce_straps( | |
599 | struct dc_context *ctx, | |
600 | struct resource_straps *straps) | |
601 | { | |
6631e5a9 DL |
602 | generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), |
603 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); | |
70ccab60 HW |
604 | } |
605 | ||
606 | static struct audio *create_audio( | |
607 | struct dc_context *ctx, unsigned int inst) | |
608 | { | |
609 | return dce_audio_create(ctx, inst, | |
610 | &audio_regs[inst], &audio_shift, &audio_mask); | |
611 | } | |
612 | ||
613 | static struct stream_encoder *dcn10_stream_encoder_create( | |
614 | enum engine_id eng_id, | |
615 | struct dc_context *ctx) | |
616 | { | |
617 | struct dce110_stream_encoder *enc110 = | |
2004f45e | 618 | kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); |
70ccab60 HW |
619 | |
620 | if (!enc110) | |
621 | return NULL; | |
622 | ||
f29f918f DA |
623 | dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, |
624 | &stream_enc_regs[eng_id], | |
625 | &se_shift, &se_mask); | |
626 | return &enc110->base; | |
70ccab60 HW |
627 | } |
628 | ||
629 | static const struct dce_hwseq_registers hwseq_reg = { | |
630 | HWSEQ_DCN1_REG_LIST() | |
631 | }; | |
632 | ||
633 | static const struct dce_hwseq_shift hwseq_shift = { | |
634 | HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) | |
635 | }; | |
636 | ||
637 | static const struct dce_hwseq_mask hwseq_mask = { | |
638 | HWSEQ_DCN1_MASK_SH_LIST(_MASK) | |
639 | }; | |
640 | ||
641 | static struct dce_hwseq *dcn10_hwseq_create( | |
642 | struct dc_context *ctx) | |
643 | { | |
2004f45e | 644 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); |
70ccab60 HW |
645 | |
646 | if (hws) { | |
647 | hws->ctx = ctx; | |
648 | hws->regs = &hwseq_reg; | |
649 | hws->shifts = &hwseq_shift; | |
650 | hws->masks = &hwseq_mask; | |
651 | } | |
652 | return hws; | |
653 | } | |
654 | ||
655 | static const struct resource_create_funcs res_create_funcs = { | |
656 | .read_dce_straps = read_dce_straps, | |
657 | .create_audio = create_audio, | |
658 | .create_stream_encoder = dcn10_stream_encoder_create, | |
659 | .create_hwseq = dcn10_hwseq_create, | |
660 | }; | |
661 | ||
662 | static const struct resource_create_funcs res_create_maximus_funcs = { | |
663 | .read_dce_straps = NULL, | |
664 | .create_audio = NULL, | |
665 | .create_stream_encoder = NULL, | |
666 | .create_hwseq = dcn10_hwseq_create, | |
667 | }; | |
668 | ||
669 | void dcn10_clock_source_destroy(struct clock_source **clk_src) | |
670 | { | |
2004f45e | 671 | kfree(TO_DCE110_CLK_SRC(*clk_src)); |
70ccab60 HW |
672 | *clk_src = NULL; |
673 | } | |
674 | ||
a185048c TC |
675 | static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) |
676 | { | |
2004f45e | 677 | struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); |
a185048c TC |
678 | |
679 | if (!pp_smu) | |
680 | return pp_smu; | |
681 | ||
682 | dm_pp_get_funcs_rv(ctx, pp_smu); | |
683 | return pp_smu; | |
684 | } | |
685 | ||
70ccab60 HW |
686 | static void destruct(struct dcn10_resource_pool *pool) |
687 | { | |
688 | unsigned int i; | |
689 | ||
690 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
691 | if (pool->base.stream_enc[i] != NULL) { | |
692 | /* TODO: free dcn version of stream encoder once implemented | |
693 | * rather than using virtual stream encoder | |
694 | */ | |
2004f45e | 695 | kfree(pool->base.stream_enc[i]); |
70ccab60 HW |
696 | pool->base.stream_enc[i] = NULL; |
697 | } | |
698 | } | |
699 | ||
cc408d72 | 700 | if (pool->base.mpc != NULL) { |
2004f45e | 701 | kfree(TO_DCN10_MPC(pool->base.mpc)); |
cc408d72 DL |
702 | pool->base.mpc = NULL; |
703 | } | |
70ccab60 HW |
704 | for (i = 0; i < pool->base.pipe_count; i++) { |
705 | if (pool->base.opps[i] != NULL) | |
706 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); | |
707 | ||
d94585a0 YHL |
708 | if (pool->base.dpps[i] != NULL) |
709 | dcn10_dpp_destroy(&pool->base.dpps[i]); | |
70ccab60 HW |
710 | |
711 | if (pool->base.ipps[i] != NULL) | |
712 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); | |
713 | ||
8feabd03 YHL |
714 | if (pool->base.hubps[i] != NULL) { |
715 | kfree(TO_DCN10_HUBP(pool->base.hubps[i])); | |
716 | pool->base.hubps[i] = NULL; | |
70ccab60 HW |
717 | } |
718 | ||
719 | if (pool->base.irqs != NULL) { | |
720 | dal_irq_service_destroy(&pool->base.irqs); | |
721 | } | |
722 | ||
723 | if (pool->base.timing_generators[i] != NULL) { | |
2004f45e | 724 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); |
70ccab60 HW |
725 | pool->base.timing_generators[i] = NULL; |
726 | } | |
727 | } | |
728 | ||
620fd73e DC |
729 | for (i = 0; i < pool->base.stream_enc_count; i++) |
730 | kfree(pool->base.stream_enc[i]); | |
70ccab60 HW |
731 | |
732 | for (i = 0; i < pool->base.audio_count; i++) { | |
733 | if (pool->base.audios[i]) | |
734 | dce_aud_destroy(&pool->base.audios[i]); | |
735 | } | |
736 | ||
737 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
738 | if (pool->base.clock_sources[i] != NULL) { | |
739 | dcn10_clock_source_destroy(&pool->base.clock_sources[i]); | |
740 | pool->base.clock_sources[i] = NULL; | |
741 | } | |
742 | } | |
743 | ||
744 | if (pool->base.dp_clock_source != NULL) { | |
745 | dcn10_clock_source_destroy(&pool->base.dp_clock_source); | |
746 | pool->base.dp_clock_source = NULL; | |
747 | } | |
748 | ||
70ccab60 HW |
749 | if (pool->base.abm != NULL) |
750 | dce_abm_destroy(&pool->base.abm); | |
751 | ||
752 | if (pool->base.dmcu != NULL) | |
753 | dce_dmcu_destroy(&pool->base.dmcu); | |
754 | ||
755 | if (pool->base.display_clock != NULL) | |
756 | dce_disp_clk_destroy(&pool->base.display_clock); | |
a185048c | 757 | |
2004f45e | 758 | kfree(pool->base.pp_smu); |
70ccab60 HW |
759 | } |
760 | ||
8feabd03 | 761 | static struct hubp *dcn10_hubp_create( |
70ccab60 HW |
762 | struct dc_context *ctx, |
763 | uint32_t inst) | |
764 | { | |
8feabd03 YHL |
765 | struct dcn10_hubp *hubp1 = |
766 | kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); | |
70ccab60 | 767 | |
8feabd03 | 768 | if (!hubp1) |
70ccab60 HW |
769 | return NULL; |
770 | ||
8feabd03 YHL |
771 | dcn10_hubp_construct(hubp1, ctx, inst, |
772 | &mi_regs[inst], &mi_shift, &mi_mask); | |
773 | return &hubp1->base; | |
70ccab60 HW |
774 | } |
775 | ||
776 | static void get_pixel_clock_parameters( | |
777 | const struct pipe_ctx *pipe_ctx, | |
778 | struct pixel_clk_params *pixel_clk_params) | |
779 | { | |
0971c40e | 780 | const struct dc_stream_state *stream = pipe_ctx->stream; |
4fa086b9 | 781 | pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; |
70ccab60 HW |
782 | pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; |
783 | pixel_clk_params->signal_type = pipe_ctx->stream->signal; | |
784 | pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; | |
785 | /* TODO: un-hardcode*/ | |
786 | pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * | |
787 | LINK_RATE_REF_FREQ_IN_KHZ; | |
788 | pixel_clk_params->flags.ENABLE_SS = 0; | |
789 | pixel_clk_params->color_depth = | |
4fa086b9 | 790 | stream->timing.display_color_depth; |
70ccab60 | 791 | pixel_clk_params->flags.DISPLAY_BLANKED = 1; |
4fa086b9 | 792 | pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; |
70ccab60 | 793 | |
4fa086b9 | 794 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) |
70ccab60 HW |
795 | pixel_clk_params->color_depth = COLOR_DEPTH_888; |
796 | ||
4fa086b9 | 797 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) |
70ccab60 HW |
798 | pixel_clk_params->requested_pix_clk /= 2; |
799 | ||
70ccab60 HW |
800 | } |
801 | ||
0971c40e | 802 | static void build_clamping_params(struct dc_stream_state *stream) |
70ccab60 HW |
803 | { |
804 | stream->clamping.clamping_level = CLAMPING_FULL_RANGE; | |
4fa086b9 LSL |
805 | stream->clamping.c_depth = stream->timing.display_color_depth; |
806 | stream->clamping.pixel_encoding = stream->timing.pixel_encoding; | |
70ccab60 HW |
807 | } |
808 | ||
94de2bbd | 809 | static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) |
70ccab60 HW |
810 | { |
811 | ||
10688217 | 812 | get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); |
70ccab60 HW |
813 | |
814 | pipe_ctx->clock_source->funcs->get_pix_clk_dividers( | |
815 | pipe_ctx->clock_source, | |
10688217 | 816 | &pipe_ctx->stream_res.pix_clk_params, |
70ccab60 HW |
817 | &pipe_ctx->pll_settings); |
818 | ||
4fa086b9 | 819 | pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; |
70ccab60 HW |
820 | |
821 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, | |
822 | &pipe_ctx->stream->bit_depth_params); | |
823 | build_clamping_params(pipe_ctx->stream); | |
70ccab60 HW |
824 | } |
825 | ||
9345d987 | 826 | static enum dc_status build_mapped_resource( |
fb3466a4 | 827 | const struct dc *dc, |
608ac7bb | 828 | struct dc_state *context, |
1dc90497 | 829 | struct dc_stream_state *stream) |
70ccab60 | 830 | { |
1dc90497 | 831 | struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); |
70ccab60 | 832 | |
1dc90497 AG |
833 | /*TODO Seems unneeded anymore */ |
834 | /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { | |
430ef426 | 835 | if (stream != NULL && old_context->streams[i] != NULL) { |
1dc90497 | 836 | todo: shouldn't have to copy missing parameter here |
70ccab60 HW |
837 | resource_build_bit_depth_reduction_params(stream, |
838 | &stream->bit_depth_params); | |
839 | stream->clamping.pixel_encoding = | |
4fa086b9 | 840 | stream->timing.pixel_encoding; |
70ccab60 HW |
841 | |
842 | resource_build_bit_depth_reduction_params(stream, | |
843 | &stream->bit_depth_params); | |
844 | build_clamping_params(stream); | |
845 | ||
846 | continue; | |
847 | } | |
848 | } | |
1dc90497 | 849 | */ |
70ccab60 | 850 | |
1dc90497 AG |
851 | if (!pipe_ctx) |
852 | return DC_ERROR_UNEXPECTED; | |
70ccab60 | 853 | |
94de2bbd | 854 | build_pipe_hw_param(pipe_ctx); |
70ccab60 HW |
855 | return DC_OK; |
856 | } | |
857 | ||
1dc90497 | 858 | enum dc_status dcn10_add_stream_to_ctx( |
fb3466a4 | 859 | struct dc *dc, |
608ac7bb | 860 | struct dc_state *new_ctx, |
1dc90497 | 861 | struct dc_stream_state *dc_stream) |
70ccab60 | 862 | { |
1dc90497 | 863 | enum dc_status result = DC_ERROR_UNEXPECTED; |
70ccab60 | 864 | |
1dc90497 | 865 | result = resource_map_pool_resources(dc, new_ctx, dc_stream); |
70ccab60 | 866 | |
1dc90497 AG |
867 | if (result == DC_OK) |
868 | result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); | |
70ccab60 | 869 | |
70ccab60 | 870 | |
1dc90497 AG |
871 | if (result == DC_OK) |
872 | result = build_mapped_resource(dc, new_ctx, dc_stream); | |
70ccab60 HW |
873 | |
874 | return result; | |
875 | } | |
876 | ||
877 | enum dc_status dcn10_validate_guaranteed( | |
fb3466a4 | 878 | struct dc *dc, |
0971c40e | 879 | struct dc_stream_state *dc_stream, |
608ac7bb | 880 | struct dc_state *context) |
70ccab60 HW |
881 | { |
882 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
883 | ||
4fa086b9 LSL |
884 | context->streams[0] = dc_stream; |
885 | dc_stream_retain(context->streams[0]); | |
70ccab60 HW |
886 | context->stream_count++; |
887 | ||
1dc90497 | 888 | result = resource_map_pool_resources(dc, context, dc_stream); |
70ccab60 HW |
889 | |
890 | if (result == DC_OK) | |
1dc90497 | 891 | result = resource_map_phy_clock_resources(dc, context, dc_stream); |
70ccab60 HW |
892 | |
893 | if (result == DC_OK) | |
1dc90497 | 894 | result = build_mapped_resource(dc, context, dc_stream); |
70ccab60 HW |
895 | |
896 | if (result == DC_OK) { | |
897 | validate_guaranteed_copy_streams( | |
fb3466a4 | 898 | context, dc->caps.max_streams); |
70ccab60 HW |
899 | result = resource_build_scaling_params_for_context(dc, context); |
900 | } | |
901 | if (result == DC_OK && !dcn_validate_bandwidth(dc, context)) | |
902 | return DC_FAIL_BANDWIDTH_VALIDATE; | |
903 | ||
904 | return result; | |
905 | } | |
906 | ||
907 | static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( | |
608ac7bb | 908 | struct dc_state *context, |
70ccab60 | 909 | const struct resource_pool *pool, |
0971c40e | 910 | struct dc_stream_state *stream) |
70ccab60 HW |
911 | { |
912 | struct resource_context *res_ctx = &context->res_ctx; | |
913 | struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); | |
914 | struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool); | |
915 | ||
a8f97647 | 916 | if (!head_pipe) { |
70ccab60 | 917 | ASSERT(0); |
a8f97647 HW |
918 | return NULL; |
919 | } | |
70ccab60 HW |
920 | |
921 | if (!idle_pipe) | |
a8f97647 | 922 | return NULL; |
70ccab60 HW |
923 | |
924 | idle_pipe->stream = head_pipe->stream; | |
6b670fa9 | 925 | idle_pipe->stream_res.tg = head_pipe->stream_res.tg; |
a6a6cb34 | 926 | idle_pipe->stream_res.opp = head_pipe->stream_res.opp; |
70ccab60 | 927 | |
8feabd03 | 928 | idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; |
86a66c4e | 929 | idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; |
d94585a0 | 930 | idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; |
70ccab60 HW |
931 | |
932 | return idle_pipe; | |
933 | } | |
934 | ||
935 | enum dcc_control { | |
936 | dcc_control__256_256_xxx, | |
937 | dcc_control__128_128_xxx, | |
938 | dcc_control__256_64_64, | |
939 | }; | |
940 | ||
941 | enum segment_order { | |
942 | segment_order__na, | |
943 | segment_order__contiguous, | |
944 | segment_order__non_contiguous, | |
945 | }; | |
946 | ||
947 | static bool dcc_support_pixel_format( | |
948 | enum surface_pixel_format format, | |
949 | unsigned int *bytes_per_element) | |
950 | { | |
951 | /* DML: get_bytes_per_element */ | |
952 | switch (format) { | |
953 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: | |
954 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |
955 | *bytes_per_element = 2; | |
956 | return true; | |
957 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: | |
958 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: | |
959 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: | |
960 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: | |
961 | *bytes_per_element = 4; | |
962 | return true; | |
963 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |
964 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |
965 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |
966 | *bytes_per_element = 8; | |
967 | return true; | |
968 | default: | |
969 | return false; | |
970 | } | |
971 | } | |
972 | ||
973 | static bool dcc_support_swizzle( | |
974 | enum swizzle_mode_values swizzle, | |
975 | unsigned int bytes_per_element, | |
976 | enum segment_order *segment_order_horz, | |
977 | enum segment_order *segment_order_vert) | |
978 | { | |
979 | bool standard_swizzle = false; | |
980 | bool display_swizzle = false; | |
981 | ||
982 | switch (swizzle) { | |
983 | case DC_SW_4KB_S: | |
984 | case DC_SW_64KB_S: | |
985 | case DC_SW_VAR_S: | |
986 | case DC_SW_4KB_S_X: | |
987 | case DC_SW_64KB_S_X: | |
988 | case DC_SW_VAR_S_X: | |
989 | standard_swizzle = true; | |
990 | break; | |
991 | case DC_SW_4KB_D: | |
992 | case DC_SW_64KB_D: | |
993 | case DC_SW_VAR_D: | |
994 | case DC_SW_4KB_D_X: | |
995 | case DC_SW_64KB_D_X: | |
996 | case DC_SW_VAR_D_X: | |
997 | display_swizzle = true; | |
998 | break; | |
999 | default: | |
1000 | break; | |
2801b0a8 | 1001 | } |
70ccab60 HW |
1002 | |
1003 | if (bytes_per_element == 1 && standard_swizzle) { | |
1004 | *segment_order_horz = segment_order__contiguous; | |
1005 | *segment_order_vert = segment_order__na; | |
1006 | return true; | |
1007 | } | |
1008 | if (bytes_per_element == 2 && standard_swizzle) { | |
1009 | *segment_order_horz = segment_order__non_contiguous; | |
1010 | *segment_order_vert = segment_order__contiguous; | |
1011 | return true; | |
1012 | } | |
1013 | if (bytes_per_element == 4 && standard_swizzle) { | |
1014 | *segment_order_horz = segment_order__non_contiguous; | |
1015 | *segment_order_vert = segment_order__contiguous; | |
1016 | return true; | |
1017 | } | |
1018 | if (bytes_per_element == 8 && standard_swizzle) { | |
1019 | *segment_order_horz = segment_order__na; | |
1020 | *segment_order_vert = segment_order__contiguous; | |
1021 | return true; | |
1022 | } | |
1023 | if (bytes_per_element == 8 && display_swizzle) { | |
1024 | *segment_order_horz = segment_order__contiguous; | |
1025 | *segment_order_vert = segment_order__non_contiguous; | |
1026 | return true; | |
1027 | } | |
1028 | ||
1029 | return false; | |
1030 | } | |
1031 | ||
1032 | static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height, | |
1033 | unsigned int bytes_per_element) | |
1034 | { | |
1035 | /* copied from DML. might want to refactor DML to leverage from DML */ | |
1036 | /* DML : get_blk256_size */ | |
1037 | if (bytes_per_element == 1) { | |
1038 | *blk256_width = 16; | |
1039 | *blk256_height = 16; | |
1040 | } else if (bytes_per_element == 2) { | |
1041 | *blk256_width = 16; | |
1042 | *blk256_height = 8; | |
1043 | } else if (bytes_per_element == 4) { | |
1044 | *blk256_width = 8; | |
1045 | *blk256_height = 8; | |
1046 | } else if (bytes_per_element == 8) { | |
1047 | *blk256_width = 8; | |
1048 | *blk256_height = 4; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | static void det_request_size( | |
1053 | unsigned int height, | |
1054 | unsigned int width, | |
1055 | unsigned int bpe, | |
1056 | bool *req128_horz_wc, | |
1057 | bool *req128_vert_wc) | |
1058 | { | |
1059 | unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */ | |
1060 | ||
1061 | unsigned int blk256_height = 0; | |
1062 | unsigned int blk256_width = 0; | |
1063 | unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc; | |
1064 | ||
1065 | get_blk256_size(&blk256_width, &blk256_height, bpe); | |
1066 | ||
1067 | swath_bytes_horz_wc = height * blk256_height * bpe; | |
1068 | swath_bytes_vert_wc = width * blk256_width * bpe; | |
1069 | ||
1070 | *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? | |
1071 | false : /* full 256B request */ | |
1072 | true; /* half 128b request */ | |
1073 | ||
1074 | *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ? | |
1075 | false : /* full 256B request */ | |
1076 | true; /* half 128b request */ | |
1077 | } | |
1078 | ||
1079 | static bool get_dcc_compression_cap(const struct dc *dc, | |
1080 | const struct dc_dcc_surface_param *input, | |
1081 | struct dc_surface_dcc_cap *output) | |
1082 | { | |
1083 | /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */ | |
1084 | enum dcc_control dcc_control; | |
1085 | unsigned int bpe; | |
1086 | enum segment_order segment_order_horz, segment_order_vert; | |
1087 | bool req128_horz_wc, req128_vert_wc; | |
1088 | ||
1089 | memset(output, 0, sizeof(*output)); | |
1090 | ||
a32a7708 | 1091 | if (dc->debug.disable_dcc == DCC_DISABLE) |
70ccab60 HW |
1092 | return false; |
1093 | ||
1094 | if (!dcc_support_pixel_format(input->format, | |
1095 | &bpe)) | |
1096 | return false; | |
1097 | ||
1098 | if (!dcc_support_swizzle(input->swizzle_mode, bpe, | |
1099 | &segment_order_horz, &segment_order_vert)) | |
1100 | return false; | |
1101 | ||
1102 | det_request_size(input->surface_size.height, input->surface_size.width, | |
1103 | bpe, &req128_horz_wc, &req128_vert_wc); | |
1104 | ||
1105 | if (!req128_horz_wc && !req128_vert_wc) { | |
1106 | dcc_control = dcc_control__256_256_xxx; | |
1107 | } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) { | |
1108 | if (!req128_horz_wc) | |
1109 | dcc_control = dcc_control__256_256_xxx; | |
1110 | else if (segment_order_horz == segment_order__contiguous) | |
1111 | dcc_control = dcc_control__128_128_xxx; | |
1112 | else | |
1113 | dcc_control = dcc_control__256_64_64; | |
1114 | } else if (input->scan == SCAN_DIRECTION_VERTICAL) { | |
1115 | if (!req128_vert_wc) | |
1116 | dcc_control = dcc_control__256_256_xxx; | |
1117 | else if (segment_order_vert == segment_order__contiguous) | |
1118 | dcc_control = dcc_control__128_128_xxx; | |
1119 | else | |
1120 | dcc_control = dcc_control__256_64_64; | |
1121 | } else { | |
1122 | if ((req128_horz_wc && | |
1123 | segment_order_horz == segment_order__non_contiguous) || | |
1124 | (req128_vert_wc && | |
1125 | segment_order_vert == segment_order__non_contiguous)) | |
1126 | /* access_dir not known, must use most constraining */ | |
1127 | dcc_control = dcc_control__256_64_64; | |
1128 | else | |
1129 | /* reg128 is true for either horz and vert | |
1130 | * but segment_order is contiguous | |
1131 | */ | |
1132 | dcc_control = dcc_control__128_128_xxx; | |
1133 | } | |
1134 | ||
a32a7708 TC |
1135 | if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && |
1136 | dcc_control != dcc_control__256_256_xxx) | |
1137 | return false; | |
1138 | ||
70ccab60 HW |
1139 | switch (dcc_control) { |
1140 | case dcc_control__256_256_xxx: | |
1141 | output->grph.rgb.max_uncompressed_blk_size = 256; | |
1142 | output->grph.rgb.max_compressed_blk_size = 256; | |
1143 | output->grph.rgb.independent_64b_blks = false; | |
1144 | break; | |
1145 | case dcc_control__128_128_xxx: | |
1146 | output->grph.rgb.max_uncompressed_blk_size = 128; | |
1147 | output->grph.rgb.max_compressed_blk_size = 128; | |
1148 | output->grph.rgb.independent_64b_blks = false; | |
1149 | break; | |
1150 | case dcc_control__256_64_64: | |
1151 | output->grph.rgb.max_uncompressed_blk_size = 256; | |
1152 | output->grph.rgb.max_compressed_blk_size = 64; | |
1153 | output->grph.rgb.independent_64b_blks = true; | |
1154 | break; | |
1155 | } | |
e778915c | 1156 | |
a32a7708 TC |
1157 | output->capable = true; |
1158 | output->const_color_support = false; | |
70ccab60 HW |
1159 | |
1160 | return true; | |
1161 | } | |
1162 | ||
1163 | ||
1164 | static void dcn10_destroy_resource_pool(struct resource_pool **pool) | |
1165 | { | |
1166 | struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); | |
1167 | ||
1168 | destruct(dcn10_pool); | |
2004f45e | 1169 | kfree(dcn10_pool); |
70ccab60 HW |
1170 | *pool = NULL; |
1171 | } | |
1172 | ||
8e7095b9 | 1173 | static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) |
bac4c559 DL |
1174 | { |
1175 | if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN | |
8e7095b9 DL |
1176 | && caps->max_video_width != 0 |
1177 | && plane_state->src_rect.width > caps->max_video_width) | |
bac4c559 DL |
1178 | return DC_FAIL_SURFACE_VALIDATE; |
1179 | ||
1180 | return DC_OK; | |
1181 | } | |
70ccab60 HW |
1182 | |
1183 | static struct dc_cap_funcs cap_funcs = { | |
1184 | .get_dcc_compression_cap = get_dcc_compression_cap | |
1185 | }; | |
1186 | ||
1187 | static struct resource_funcs dcn10_res_pool_funcs = { | |
1188 | .destroy = dcn10_destroy_resource_pool, | |
1189 | .link_enc_create = dcn10_link_encoder_create, | |
70ccab60 HW |
1190 | .validate_guaranteed = dcn10_validate_guaranteed, |
1191 | .validate_bandwidth = dcn_validate_bandwidth, | |
1192 | .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, | |
bac4c559 | 1193 | .validate_plane = dcn10_validate_plane, |
1dc90497 | 1194 | .add_stream_to_ctx = dcn10_add_stream_to_ctx |
70ccab60 HW |
1195 | }; |
1196 | ||
1bb47154 HW |
1197 | static uint32_t read_pipe_fuses(struct dc_context *ctx) |
1198 | { | |
1199 | uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); | |
1200 | /* RV1 support max 4 pipes */ | |
1201 | value = value & 0xf; | |
1202 | return value; | |
1203 | } | |
1204 | ||
70ccab60 HW |
1205 | static bool construct( |
1206 | uint8_t num_virtual_links, | |
fb3466a4 | 1207 | struct dc *dc, |
70ccab60 HW |
1208 | struct dcn10_resource_pool *pool) |
1209 | { | |
1210 | int i; | |
1bb47154 | 1211 | int j; |
70ccab60 | 1212 | struct dc_context *ctx = dc->ctx; |
1bb47154 | 1213 | uint32_t pipe_fuses = read_pipe_fuses(ctx); |
70ccab60 HW |
1214 | |
1215 | ctx->dc_bios->regs = &bios_regs; | |
1216 | ||
1217 | pool->base.res_cap = &res_cap; | |
1218 | pool->base.funcs = &dcn10_res_pool_funcs; | |
1219 | ||
1220 | /* | |
1221 | * TODO fill in from actual raven resource when we create | |
1222 | * more than virtual encoder | |
1223 | */ | |
1224 | ||
1225 | /************************************************* | |
1226 | * Resource + asic cap harcoding * | |
1227 | *************************************************/ | |
1228 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; | |
1229 | ||
1bb47154 HW |
1230 | /* max pipe num for ASIC before check pipe fuses */ |
1231 | pool->base.pipe_count = pool->base.res_cap->num_timing_generator; | |
1232 | ||
8e7095b9 | 1233 | dc->caps.max_video_width = 3840; |
fb3466a4 BL |
1234 | dc->caps.max_downscale_ratio = 200; |
1235 | dc->caps.i2c_speed_in_khz = 100; | |
1236 | dc->caps.max_cursor_size = 256; | |
70ccab60 | 1237 | |
fb3466a4 | 1238 | dc->caps.max_slave_planes = 1; |
a90fbf78 | 1239 | |
70ccab60 | 1240 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) |
fb3466a4 | 1241 | dc->debug = debug_defaults_drv; |
70ccab60 | 1242 | else |
fb3466a4 | 1243 | dc->debug = debug_defaults_diags; |
70ccab60 HW |
1244 | |
1245 | /************************************************* | |
1246 | * Create resources * | |
1247 | *************************************************/ | |
1248 | ||
1249 | pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = | |
1250 | dcn10_clock_source_create(ctx, ctx->dc_bios, | |
1251 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |
1252 | &clk_src_regs[0], false); | |
1253 | pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = | |
1254 | dcn10_clock_source_create(ctx, ctx->dc_bios, | |
1255 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |
1256 | &clk_src_regs[1], false); | |
1257 | pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = | |
1258 | dcn10_clock_source_create(ctx, ctx->dc_bios, | |
1259 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |
1260 | &clk_src_regs[2], false); | |
1261 | pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = | |
1262 | dcn10_clock_source_create(ctx, ctx->dc_bios, | |
1263 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |
1264 | &clk_src_regs[3], false); | |
1265 | ||
1266 | pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; | |
1267 | ||
1268 | pool->base.dp_clock_source = | |
1269 | dcn10_clock_source_create(ctx, ctx->dc_bios, | |
1270 | CLOCK_SOURCE_ID_DP_DTO, | |
1271 | /* todo: not reuse phy_pll registers */ | |
1272 | &clk_src_regs[0], true); | |
1273 | ||
1274 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
1275 | if (pool->base.clock_sources[i] == NULL) { | |
1276 | dm_error("DC: failed to create clock sources!\n"); | |
1277 | BREAK_TO_DEBUGGER(); | |
1278 | goto clock_source_create_fail; | |
1279 | } | |
1280 | } | |
1281 | ||
1282 | if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { | |
b1a4eb99 | 1283 | pool->base.display_clock = dce120_disp_clk_create(ctx); |
70ccab60 HW |
1284 | if (pool->base.display_clock == NULL) { |
1285 | dm_error("DC: failed to create display clock!\n"); | |
1286 | BREAK_TO_DEBUGGER(); | |
1287 | goto disp_clk_create_fail; | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | pool->base.dmcu = dcn10_dmcu_create(ctx, | |
1292 | &dmcu_regs, | |
1293 | &dmcu_shift, | |
1294 | &dmcu_mask); | |
1295 | if (pool->base.dmcu == NULL) { | |
1296 | dm_error("DC: failed to create dmcu!\n"); | |
1297 | BREAK_TO_DEBUGGER(); | |
1298 | goto res_create_fail; | |
1299 | } | |
1300 | ||
1301 | pool->base.abm = dce_abm_create(ctx, | |
1302 | &abm_regs, | |
1303 | &abm_shift, | |
1304 | &abm_mask); | |
1305 | if (pool->base.abm == NULL) { | |
1306 | dm_error("DC: failed to create abm!\n"); | |
1307 | BREAK_TO_DEBUGGER(); | |
1308 | goto res_create_fail; | |
1309 | } | |
1310 | ||
1311 | dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); | |
65111f25 BL |
1312 | memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); |
1313 | memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); | |
f42485bb | 1314 | |
746e082f | 1315 | if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { |
65111f25 | 1316 | dc->dcn_soc->urgent_latency = 3; |
fb3466a4 | 1317 | dc->debug.disable_dmcu = true; |
65111f25 | 1318 | dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; |
746e082f CL |
1319 | } |
1320 | ||
1321 | ||
65111f25 BL |
1322 | dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; |
1323 | ASSERT(dc->dcn_soc->number_of_channels < 3); | |
1324 | if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ | |
1325 | dc->dcn_soc->number_of_channels = 2; | |
f42485bb | 1326 | |
65111f25 BL |
1327 | if (dc->dcn_soc->number_of_channels == 1) { |
1328 | dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; | |
1329 | dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; | |
1330 | dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; | |
1331 | dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; | |
746e082f | 1332 | if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { |
65111f25 | 1333 | dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; |
746e082f | 1334 | } |
f42485bb EY |
1335 | } |
1336 | ||
a185048c TC |
1337 | pool->base.pp_smu = dcn10_pp_smu_create(ctx); |
1338 | ||
fb3466a4 | 1339 | if (!dc->debug.disable_pplib_clock_request) |
70ccab60 HW |
1340 | dcn_bw_update_from_pplib(dc); |
1341 | dcn_bw_sync_calcs_and_dml(dc); | |
a185048c TC |
1342 | if (!dc->debug.disable_pplib_wm_range) { |
1343 | dc->res_pool = &pool->base; | |
70ccab60 | 1344 | dcn_bw_notify_pplib_of_wm_ranges(dc); |
a185048c | 1345 | } |
70ccab60 HW |
1346 | |
1347 | { | |
1348 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | |
1349 | struct irq_service_init_data init_data; | |
1350 | init_data.ctx = dc->ctx; | |
1351 | pool->base.irqs = dal_irq_service_dcn10_create(&init_data); | |
1352 | if (!pool->base.irqs) | |
1353 | goto irqs_create_fail; | |
1354 | #endif | |
1355 | } | |
1356 | ||
1bb47154 HW |
1357 | /* index to valid pipe resource */ |
1358 | j = 0; | |
587cdfe9 | 1359 | /* mem input -> ipp -> dpp -> opp -> TG */ |
70ccab60 | 1360 | for (i = 0; i < pool->base.pipe_count; i++) { |
1bb47154 HW |
1361 | /* if pipe is disabled, skip instance of HW pipe, |
1362 | * i.e, skip ASIC register instance | |
1363 | */ | |
1364 | if ((pipe_fuses & (1 << i)) != 0) | |
1365 | continue; | |
1366 | ||
8feabd03 YHL |
1367 | pool->base.hubps[j] = dcn10_hubp_create(ctx, i); |
1368 | if (pool->base.hubps[j] == NULL) { | |
70ccab60 HW |
1369 | BREAK_TO_DEBUGGER(); |
1370 | dm_error( | |
1371 | "DC: failed to create memory input!\n"); | |
1372 | goto mi_create_fail; | |
1373 | } | |
1374 | ||
1bb47154 HW |
1375 | pool->base.ipps[j] = dcn10_ipp_create(ctx, i); |
1376 | if (pool->base.ipps[j] == NULL) { | |
70ccab60 HW |
1377 | BREAK_TO_DEBUGGER(); |
1378 | dm_error( | |
1379 | "DC: failed to create input pixel processor!\n"); | |
1380 | goto ipp_create_fail; | |
1381 | } | |
1382 | ||
d94585a0 YHL |
1383 | pool->base.dpps[j] = dcn10_dpp_create(ctx, i); |
1384 | if (pool->base.dpps[j] == NULL) { | |
70ccab60 HW |
1385 | BREAK_TO_DEBUGGER(); |
1386 | dm_error( | |
587cdfe9 VP |
1387 | "DC: failed to create dpp!\n"); |
1388 | goto dpp_create_fail; | |
70ccab60 HW |
1389 | } |
1390 | ||
1bb47154 HW |
1391 | pool->base.opps[j] = dcn10_opp_create(ctx, i); |
1392 | if (pool->base.opps[j] == NULL) { | |
70ccab60 HW |
1393 | BREAK_TO_DEBUGGER(); |
1394 | dm_error( | |
1395 | "DC: failed to create output pixel processor!\n"); | |
1396 | goto opp_create_fail; | |
1397 | } | |
1398 | ||
1bb47154 | 1399 | pool->base.timing_generators[j] = dcn10_timing_generator_create( |
70ccab60 | 1400 | ctx, i); |
1bb47154 | 1401 | if (pool->base.timing_generators[j] == NULL) { |
70ccab60 HW |
1402 | BREAK_TO_DEBUGGER(); |
1403 | dm_error("DC: failed to create tg!\n"); | |
1404 | goto otg_create_fail; | |
1405 | } | |
1bb47154 HW |
1406 | /* check next valid pipe */ |
1407 | j++; | |
cc408d72 | 1408 | } |
1bb47154 HW |
1409 | |
1410 | /* valid pipe num */ | |
1411 | pool->base.pipe_count = j; | |
1412 | ||
1413 | /* within dml lib, it is hard code to 4. If ASIC pipe is fused, | |
1414 | * the value may be changed | |
1415 | */ | |
1416 | dc->dml.ip.max_num_dpp = pool->base.pipe_count; | |
1417 | dc->dcn_ip->max_num_dpp = pool->base.pipe_count; | |
1418 | ||
cc408d72 DL |
1419 | pool->base.mpc = dcn10_mpc_create(ctx); |
1420 | if (pool->base.mpc == NULL) { | |
1421 | BREAK_TO_DEBUGGER(); | |
1422 | dm_error("DC: failed to create mpc!\n"); | |
1423 | goto mpc_create_fail; | |
70ccab60 HW |
1424 | } |
1425 | ||
70ccab60 HW |
1426 | if (!resource_construct(num_virtual_links, dc, &pool->base, |
1427 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? | |
1428 | &res_create_funcs : &res_create_maximus_funcs))) | |
1429 | goto res_create_fail; | |
1430 | ||
1431 | dcn10_hw_sequencer_construct(dc); | |
fb3466a4 | 1432 | dc->caps.max_planes = pool->base.pipe_count; |
70ccab60 | 1433 | |
fb3466a4 | 1434 | dc->cap_funcs = cap_funcs; |
70ccab60 HW |
1435 | |
1436 | return true; | |
1437 | ||
1438 | disp_clk_create_fail: | |
cc408d72 | 1439 | mpc_create_fail: |
70ccab60 HW |
1440 | otg_create_fail: |
1441 | opp_create_fail: | |
587cdfe9 | 1442 | dpp_create_fail: |
70ccab60 HW |
1443 | ipp_create_fail: |
1444 | mi_create_fail: | |
1445 | irqs_create_fail: | |
1446 | res_create_fail: | |
1447 | clock_source_create_fail: | |
1448 | ||
1449 | destruct(pool); | |
1450 | ||
1451 | return false; | |
1452 | } | |
1453 | ||
1454 | struct resource_pool *dcn10_create_resource_pool( | |
1455 | uint8_t num_virtual_links, | |
fb3466a4 | 1456 | struct dc *dc) |
70ccab60 HW |
1457 | { |
1458 | struct dcn10_resource_pool *pool = | |
2004f45e | 1459 | kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); |
70ccab60 HW |
1460 | |
1461 | if (!pool) | |
1462 | return NULL; | |
1463 | ||
1464 | if (construct(num_virtual_links, dc, pool)) | |
1465 | return &pool->base; | |
1466 | ||
ce82ffa1 | 1467 | kfree(pool); |
70ccab60 HW |
1468 | BREAK_TO_DEBUGGER(); |
1469 | return NULL; | |
1470 | } |