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7ed4e635 HW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "dm_services.h" | |
27 | #include "dc.h" | |
28 | ||
29 | #include "resource.h" | |
30 | #include "include/irq_service_interface.h" | |
31 | #include "dcn20/dcn20_resource.h" | |
32 | ||
33 | #include "dcn10/dcn10_hubp.h" | |
34 | #include "dcn10/dcn10_ipp.h" | |
35 | #include "dcn20_hubbub.h" | |
36 | #include "dcn20_mpc.h" | |
37 | #include "dcn20_hubp.h" | |
38 | #include "irq/dcn20/irq_service_dcn20.h" | |
39 | #include "dcn20_dpp.h" | |
40 | #include "dcn20_optc.h" | |
41 | #include "dcn20_hwseq.h" | |
42 | #include "dce110/dce110_hw_sequencer.h" | |
43 | #include "dcn20_opp.h" | |
44 | ||
97bda032 HW |
45 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
46 | #include "dcn20_dsc.h" | |
47 | #endif | |
48 | ||
7ed4e635 HW |
49 | #include "dcn20_link_encoder.h" |
50 | #include "dcn20_stream_encoder.h" | |
51 | #include "dce/dce_clock_source.h" | |
52 | #include "dce/dce_audio.h" | |
53 | #include "dce/dce_hwseq.h" | |
54 | #include "virtual/virtual_stream_encoder.h" | |
55 | #include "dce110/dce110_resource.h" | |
56 | #include "dml/display_mode_vba.h" | |
57 | #include "dcn20_dccg.h" | |
58 | #include "dcn20_vmid.h" | |
59 | ||
60 | #include "navi10_ip_offset.h" | |
61 | ||
62 | #include "dcn/dcn_2_0_0_offset.h" | |
63 | #include "dcn/dcn_2_0_0_sh_mask.h" | |
64 | ||
65 | #include "nbio/nbio_2_3_offset.h" | |
66 | ||
bb21290f CL |
67 | #include "dcn20/dcn20_dwb.h" |
68 | #include "dcn20/dcn20_mmhubbub.h" | |
69 | ||
7ed4e635 HW |
70 | #include "mmhub/mmhub_2_0_0_offset.h" |
71 | #include "mmhub/mmhub_2_0_0_sh_mask.h" | |
72 | ||
73 | #include "reg_helper.h" | |
74 | #include "dce/dce_abm.h" | |
75 | #include "dce/dce_dmcu.h" | |
76 | #include "dce/dce_aux.h" | |
77 | #include "dce/dce_i2c.h" | |
78 | #include "vm_helper.h" | |
79 | ||
80 | #include "amdgpu_socbb.h" | |
81 | ||
82 | #define SOC_BOUNDING_BOX_VALID false | |
83 | #define DC_LOGGER_INIT(logger) | |
84 | ||
85 | struct _vcs_dpi_ip_params_st dcn2_0_ip = { | |
86 | .odm_capable = 1, | |
87 | .gpuvm_enable = 0, | |
88 | .hostvm_enable = 0, | |
89 | .gpuvm_max_page_table_levels = 4, | |
90 | .hostvm_max_page_table_levels = 4, | |
91 | .hostvm_cached_page_table_levels = 0, | |
92 | .pte_group_size_bytes = 2048, | |
97bda032 HW |
93 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
94 | .num_dsc = 6, | |
95 | #else | |
7ed4e635 | 96 | .num_dsc = 0, |
97bda032 | 97 | #endif |
7ed4e635 HW |
98 | .rob_buffer_size_kbytes = 168, |
99 | .det_buffer_size_kbytes = 164, | |
100 | .dpte_buffer_size_in_pte_reqs_luma = 84, | |
101 | .pde_proc_buffer_size_64k_reqs = 48, | |
102 | .dpp_output_buffer_pixels = 2560, | |
103 | .opp_output_buffer_lines = 1, | |
104 | .pixel_chunk_size_kbytes = 8, | |
105 | .pte_chunk_size_kbytes = 2, | |
106 | .meta_chunk_size_kbytes = 2, | |
107 | .writeback_chunk_size_kbytes = 2, | |
108 | .line_buffer_size_bits = 789504, | |
109 | .is_line_buffer_bpp_fixed = 0, | |
110 | .line_buffer_fixed_bpp = 0, | |
111 | .dcc_supported = true, | |
112 | .max_line_buffer_lines = 12, | |
113 | .writeback_luma_buffer_size_kbytes = 12, | |
114 | .writeback_chroma_buffer_size_kbytes = 8, | |
115 | .writeback_chroma_line_buffer_width_pixels = 4, | |
116 | .writeback_max_hscl_ratio = 1, | |
117 | .writeback_max_vscl_ratio = 1, | |
118 | .writeback_min_hscl_ratio = 1, | |
119 | .writeback_min_vscl_ratio = 1, | |
120 | .writeback_max_hscl_taps = 12, | |
121 | .writeback_max_vscl_taps = 12, | |
122 | .writeback_line_buffer_luma_buffer_size = 0, | |
123 | .writeback_line_buffer_chroma_buffer_size = 14643, | |
124 | .cursor_buffer_size = 8, | |
125 | .cursor_chunk_size = 2, | |
126 | .max_num_otg = 6, | |
127 | .max_num_dpp = 6, | |
128 | .max_num_wb = 1, | |
129 | .max_dchub_pscl_bw_pix_per_clk = 4, | |
130 | .max_pscl_lb_bw_pix_per_clk = 2, | |
131 | .max_lb_vscl_bw_pix_per_clk = 4, | |
132 | .max_vscl_hscl_bw_pix_per_clk = 4, | |
133 | .max_hscl_ratio = 8, | |
134 | .max_vscl_ratio = 8, | |
135 | .hscl_mults = 4, | |
136 | .vscl_mults = 4, | |
137 | .max_hscl_taps = 8, | |
138 | .max_vscl_taps = 8, | |
139 | .dispclk_ramp_margin_percent = 1, | |
140 | .underscan_factor = 1.10, | |
141 | .min_vblank_lines = 32, // | |
142 | .dppclk_delay_subtotal = 77, // | |
143 | .dppclk_delay_scl_lb_only = 16, | |
144 | .dppclk_delay_scl = 50, | |
145 | .dppclk_delay_cnvc_formatter = 8, | |
146 | .dppclk_delay_cnvc_cursor = 6, | |
147 | .dispclk_delay_subtotal = 87, // | |
148 | .dcfclk_cstate_latency = 10, // SRExitTime | |
149 | .max_inter_dcn_tile_repeaters = 8, | |
150 | ||
151 | .xfc_supported = true, | |
152 | .xfc_fill_bw_overhead_percent = 10.0, | |
153 | .xfc_fill_constant_bytes = 0, | |
154 | }; | |
155 | ||
156 | struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 }; | |
157 | ||
158 | ||
159 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL | |
160 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f | |
161 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
162 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f | |
163 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
164 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f | |
165 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
166 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f | |
167 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
168 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f | |
169 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
170 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f | |
171 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
172 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f | |
173 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
174 | #endif | |
175 | ||
176 | ||
177 | enum dcn20_clk_src_array_id { | |
178 | DCN20_CLK_SRC_PLL0, | |
179 | DCN20_CLK_SRC_PLL1, | |
180 | DCN20_CLK_SRC_PLL2, | |
181 | DCN20_CLK_SRC_PLL3, | |
182 | DCN20_CLK_SRC_PLL4, | |
183 | DCN20_CLK_SRC_PLL5, | |
184 | DCN20_CLK_SRC_TOTAL | |
185 | }; | |
186 | ||
187 | /* begin ********************* | |
188 | * macros to expend register list macro defined in HW object header file */ | |
189 | ||
190 | /* DCN */ | |
191 | /* TODO awful hack. fixup dcn20_dwb.h */ | |
192 | #undef BASE_INNER | |
193 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | |
194 | ||
195 | #define BASE(seg) BASE_INNER(seg) | |
196 | ||
197 | #define SR(reg_name)\ | |
198 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
199 | mm ## reg_name | |
200 | ||
201 | #define SRI(reg_name, block, id)\ | |
202 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
203 | mm ## block ## id ## _ ## reg_name | |
204 | ||
205 | #define SRIR(var_name, reg_name, block, id)\ | |
206 | .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
207 | mm ## block ## id ## _ ## reg_name | |
208 | ||
209 | #define SRII(reg_name, block, id)\ | |
210 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
211 | mm ## block ## id ## _ ## reg_name | |
212 | ||
213 | #define DCCG_SRII(reg_name, block, id)\ | |
214 | .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
215 | mm ## block ## id ## _ ## reg_name | |
216 | ||
217 | /* NBIO */ | |
218 | #define NBIO_BASE_INNER(seg) \ | |
219 | NBIO_BASE__INST0_SEG ## seg | |
220 | ||
221 | #define NBIO_BASE(seg) \ | |
222 | NBIO_BASE_INNER(seg) | |
223 | ||
224 | #define NBIO_SR(reg_name)\ | |
225 | .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ | |
226 | mm ## reg_name | |
227 | ||
228 | /* MMHUB */ | |
229 | #define MMHUB_BASE_INNER(seg) \ | |
230 | MMHUB_BASE__INST0_SEG ## seg | |
231 | ||
232 | #define MMHUB_BASE(seg) \ | |
233 | MMHUB_BASE_INNER(seg) | |
234 | ||
235 | #define MMHUB_SR(reg_name)\ | |
236 | .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ | |
237 | mmMM ## reg_name | |
238 | ||
239 | static const struct bios_registers bios_regs = { | |
240 | NBIO_SR(BIOS_SCRATCH_3), | |
241 | NBIO_SR(BIOS_SCRATCH_6) | |
242 | }; | |
243 | ||
244 | #define clk_src_regs(index, pllid)\ | |
245 | [index] = {\ | |
246 | CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ | |
247 | } | |
248 | ||
249 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
250 | clk_src_regs(0, A), | |
251 | clk_src_regs(1, B), | |
252 | clk_src_regs(2, C), | |
253 | clk_src_regs(3, D), | |
254 | clk_src_regs(4, E), | |
255 | clk_src_regs(5, F) | |
256 | }; | |
257 | ||
258 | static const struct dce110_clk_src_shift cs_shift = { | |
259 | CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
260 | }; | |
261 | ||
262 | static const struct dce110_clk_src_mask cs_mask = { | |
263 | CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
264 | }; | |
265 | ||
266 | static const struct dce_dmcu_registers dmcu_regs = { | |
267 | DMCU_DCN10_REG_LIST() | |
268 | }; | |
269 | ||
270 | static const struct dce_dmcu_shift dmcu_shift = { | |
271 | DMCU_MASK_SH_LIST_DCN10(__SHIFT) | |
272 | }; | |
273 | ||
274 | static const struct dce_dmcu_mask dmcu_mask = { | |
275 | DMCU_MASK_SH_LIST_DCN10(_MASK) | |
276 | }; | |
d7c29549 | 277 | |
7ed4e635 | 278 | static const struct dce_abm_registers abm_regs = { |
d7c29549 | 279 | ABM_DCN20_REG_LIST() |
7ed4e635 HW |
280 | }; |
281 | ||
282 | static const struct dce_abm_shift abm_shift = { | |
d7c29549 | 283 | ABM_MASK_SH_LIST_DCN20(__SHIFT) |
7ed4e635 HW |
284 | }; |
285 | ||
286 | static const struct dce_abm_mask abm_mask = { | |
d7c29549 | 287 | ABM_MASK_SH_LIST_DCN20(_MASK) |
7ed4e635 | 288 | }; |
d7c29549 | 289 | |
7ed4e635 HW |
290 | #define audio_regs(id)\ |
291 | [id] = {\ | |
292 | AUD_COMMON_REG_LIST(id)\ | |
293 | } | |
294 | ||
295 | static const struct dce_audio_registers audio_regs[] = { | |
296 | audio_regs(0), | |
297 | audio_regs(1), | |
298 | audio_regs(2), | |
299 | audio_regs(3), | |
300 | audio_regs(4), | |
301 | audio_regs(5), | |
302 | audio_regs(6), | |
303 | }; | |
304 | ||
305 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ | |
306 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ | |
307 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ | |
308 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) | |
309 | ||
310 | static const struct dce_audio_shift audio_shift = { | |
311 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
312 | }; | |
313 | ||
314 | static const struct dce_aduio_mask audio_mask = { | |
315 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) | |
316 | }; | |
317 | ||
318 | #define stream_enc_regs(id)\ | |
319 | [id] = {\ | |
320 | SE_DCN2_REG_LIST(id)\ | |
321 | } | |
322 | ||
323 | static const struct dcn10_stream_enc_registers stream_enc_regs[] = { | |
324 | stream_enc_regs(0), | |
325 | stream_enc_regs(1), | |
326 | stream_enc_regs(2), | |
327 | stream_enc_regs(3), | |
328 | stream_enc_regs(4), | |
329 | stream_enc_regs(5), | |
330 | }; | |
331 | ||
332 | static const struct dcn10_stream_encoder_shift se_shift = { | |
333 | SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) | |
334 | }; | |
335 | ||
336 | static const struct dcn10_stream_encoder_mask se_mask = { | |
337 | SE_COMMON_MASK_SH_LIST_DCN20(_MASK) | |
338 | }; | |
339 | ||
340 | ||
341 | #define aux_regs(id)\ | |
342 | [id] = {\ | |
343 | DCN2_AUX_REG_LIST(id)\ | |
344 | } | |
345 | ||
346 | static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { | |
347 | aux_regs(0), | |
348 | aux_regs(1), | |
349 | aux_regs(2), | |
350 | aux_regs(3), | |
351 | aux_regs(4), | |
352 | aux_regs(5) | |
353 | }; | |
354 | ||
355 | #define hpd_regs(id)\ | |
356 | [id] = {\ | |
357 | HPD_REG_LIST(id)\ | |
358 | } | |
359 | ||
360 | static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
361 | hpd_regs(0), | |
362 | hpd_regs(1), | |
363 | hpd_regs(2), | |
364 | hpd_regs(3), | |
365 | hpd_regs(4), | |
366 | hpd_regs(5) | |
367 | }; | |
368 | ||
369 | #define link_regs(id, phyid)\ | |
370 | [id] = {\ | |
371 | LE_DCN10_REG_LIST(id), \ | |
372 | UNIPHY_DCN2_REG_LIST(phyid), \ | |
373 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | |
374 | } | |
375 | ||
376 | static const struct dcn10_link_enc_registers link_enc_regs[] = { | |
377 | link_regs(0, A), | |
378 | link_regs(1, B), | |
379 | link_regs(2, C), | |
380 | link_regs(3, D), | |
381 | link_regs(4, E), | |
382 | link_regs(5, F) | |
383 | }; | |
384 | ||
385 | static const struct dcn10_link_enc_shift le_shift = { | |
386 | LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT) | |
387 | }; | |
388 | ||
389 | static const struct dcn10_link_enc_mask le_mask = { | |
390 | LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK) | |
391 | }; | |
392 | ||
393 | #define ipp_regs(id)\ | |
394 | [id] = {\ | |
395 | IPP_REG_LIST_DCN20(id),\ | |
396 | } | |
397 | ||
398 | static const struct dcn10_ipp_registers ipp_regs[] = { | |
399 | ipp_regs(0), | |
400 | ipp_regs(1), | |
401 | ipp_regs(2), | |
402 | ipp_regs(3), | |
403 | ipp_regs(4), | |
404 | ipp_regs(5), | |
405 | }; | |
406 | ||
407 | static const struct dcn10_ipp_shift ipp_shift = { | |
408 | IPP_MASK_SH_LIST_DCN20(__SHIFT) | |
409 | }; | |
410 | ||
411 | static const struct dcn10_ipp_mask ipp_mask = { | |
412 | IPP_MASK_SH_LIST_DCN20(_MASK), | |
413 | }; | |
414 | ||
415 | #define opp_regs(id)\ | |
416 | [id] = {\ | |
417 | OPP_REG_LIST_DCN20(id),\ | |
418 | } | |
419 | ||
420 | static const struct dcn20_opp_registers opp_regs[] = { | |
421 | opp_regs(0), | |
422 | opp_regs(1), | |
423 | opp_regs(2), | |
424 | opp_regs(3), | |
425 | opp_regs(4), | |
426 | opp_regs(5), | |
427 | }; | |
428 | ||
429 | static const struct dcn20_opp_shift opp_shift = { | |
430 | OPP_MASK_SH_LIST_DCN20(__SHIFT) | |
431 | }; | |
432 | ||
433 | static const struct dcn20_opp_mask opp_mask = { | |
434 | OPP_MASK_SH_LIST_DCN20(_MASK) | |
435 | }; | |
436 | ||
437 | #define aux_engine_regs(id)\ | |
438 | [id] = {\ | |
439 | AUX_COMMON_REG_LIST0(id), \ | |
440 | .AUXN_IMPCAL = 0, \ | |
441 | .AUXP_IMPCAL = 0, \ | |
442 | .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ | |
443 | } | |
444 | ||
445 | static const struct dce110_aux_registers aux_engine_regs[] = { | |
446 | aux_engine_regs(0), | |
447 | aux_engine_regs(1), | |
448 | aux_engine_regs(2), | |
449 | aux_engine_regs(3), | |
450 | aux_engine_regs(4), | |
451 | aux_engine_regs(5) | |
452 | }; | |
453 | ||
454 | #define tf_regs(id)\ | |
455 | [id] = {\ | |
456 | TF_REG_LIST_DCN20(id),\ | |
457 | } | |
458 | ||
459 | static const struct dcn2_dpp_registers tf_regs[] = { | |
460 | tf_regs(0), | |
461 | tf_regs(1), | |
462 | tf_regs(2), | |
463 | tf_regs(3), | |
464 | tf_regs(4), | |
465 | tf_regs(5), | |
466 | }; | |
467 | ||
468 | static const struct dcn2_dpp_shift tf_shift = { | |
469 | TF_REG_LIST_SH_MASK_DCN20(__SHIFT) | |
470 | }; | |
471 | ||
472 | static const struct dcn2_dpp_mask tf_mask = { | |
473 | TF_REG_LIST_SH_MASK_DCN20(_MASK) | |
474 | }; | |
475 | ||
bb21290f CL |
476 | #define dwbc_regs_dcn2(id)\ |
477 | [id] = {\ | |
478 | DWBC_COMMON_REG_LIST_DCN2_0(id),\ | |
479 | } | |
480 | ||
481 | static const struct dcn20_dwbc_registers dwbc20_regs[] = { | |
482 | dwbc_regs_dcn2(0), | |
483 | }; | |
484 | ||
485 | static const struct dcn20_dwbc_shift dwbc20_shift = { | |
486 | DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
487 | }; | |
488 | ||
489 | static const struct dcn20_dwbc_mask dwbc20_mask = { | |
490 | DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
491 | }; | |
492 | ||
493 | #define mcif_wb_regs_dcn2(id)\ | |
494 | [id] = {\ | |
495 | MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ | |
496 | } | |
497 | ||
498 | static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { | |
499 | mcif_wb_regs_dcn2(0), | |
500 | }; | |
501 | ||
502 | static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { | |
503 | MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
504 | }; | |
505 | ||
506 | static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { | |
507 | MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
508 | }; | |
509 | ||
7ed4e635 HW |
510 | static const struct dcn20_mpc_registers mpc_regs = { |
511 | MPC_REG_LIST_DCN2_0(0), | |
512 | MPC_REG_LIST_DCN2_0(1), | |
513 | MPC_REG_LIST_DCN2_0(2), | |
514 | MPC_REG_LIST_DCN2_0(3), | |
515 | MPC_REG_LIST_DCN2_0(4), | |
516 | MPC_REG_LIST_DCN2_0(5), | |
517 | MPC_OUT_MUX_REG_LIST_DCN2_0(0), | |
518 | MPC_OUT_MUX_REG_LIST_DCN2_0(1), | |
519 | MPC_OUT_MUX_REG_LIST_DCN2_0(2), | |
520 | MPC_OUT_MUX_REG_LIST_DCN2_0(3), | |
521 | MPC_OUT_MUX_REG_LIST_DCN2_0(4), | |
522 | MPC_OUT_MUX_REG_LIST_DCN2_0(5), | |
523 | }; | |
524 | ||
525 | static const struct dcn20_mpc_shift mpc_shift = { | |
526 | MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
527 | }; | |
528 | ||
529 | static const struct dcn20_mpc_mask mpc_mask = { | |
530 | MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
531 | }; | |
532 | ||
533 | #define tg_regs(id)\ | |
534 | [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} | |
535 | ||
536 | ||
537 | static const struct dcn_optc_registers tg_regs[] = { | |
538 | tg_regs(0), | |
539 | tg_regs(1), | |
540 | tg_regs(2), | |
541 | tg_regs(3), | |
542 | tg_regs(4), | |
543 | tg_regs(5) | |
544 | }; | |
545 | ||
546 | static const struct dcn_optc_shift tg_shift = { | |
547 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
548 | }; | |
549 | ||
550 | static const struct dcn_optc_mask tg_mask = { | |
551 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
552 | }; | |
553 | ||
554 | #define hubp_regs(id)\ | |
555 | [id] = {\ | |
556 | HUBP_REG_LIST_DCN20(id)\ | |
557 | } | |
558 | ||
559 | static const struct dcn_hubp2_registers hubp_regs[] = { | |
560 | hubp_regs(0), | |
561 | hubp_regs(1), | |
562 | hubp_regs(2), | |
563 | hubp_regs(3), | |
564 | hubp_regs(4), | |
565 | hubp_regs(5) | |
566 | }; | |
567 | ||
568 | static const struct dcn_hubp2_shift hubp_shift = { | |
569 | HUBP_MASK_SH_LIST_DCN20(__SHIFT) | |
570 | }; | |
571 | ||
572 | static const struct dcn_hubp2_mask hubp_mask = { | |
573 | HUBP_MASK_SH_LIST_DCN20(_MASK) | |
574 | }; | |
575 | ||
576 | static const struct dcn_hubbub_registers hubbub_reg = { | |
577 | HUBBUB_REG_LIST_DCN20(0) | |
578 | }; | |
579 | ||
580 | static const struct dcn_hubbub_shift hubbub_shift = { | |
581 | HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) | |
582 | }; | |
583 | ||
584 | static const struct dcn_hubbub_mask hubbub_mask = { | |
585 | HUBBUB_MASK_SH_LIST_DCN20(_MASK) | |
586 | }; | |
587 | ||
588 | #define vmid_regs(id)\ | |
589 | [id] = {\ | |
590 | DCN20_VMID_REG_LIST(id)\ | |
591 | } | |
592 | ||
593 | static const struct dcn_vmid_registers vmid_regs[] = { | |
594 | vmid_regs(0), | |
595 | vmid_regs(1), | |
596 | vmid_regs(2), | |
597 | vmid_regs(3), | |
598 | vmid_regs(4), | |
599 | vmid_regs(5), | |
600 | vmid_regs(6), | |
601 | vmid_regs(7), | |
602 | vmid_regs(8), | |
603 | vmid_regs(9), | |
604 | vmid_regs(10), | |
605 | vmid_regs(11), | |
606 | vmid_regs(12), | |
607 | vmid_regs(13), | |
608 | vmid_regs(14), | |
609 | vmid_regs(15) | |
610 | }; | |
611 | ||
612 | static const struct dcn20_vmid_shift vmid_shifts = { | |
613 | DCN20_VMID_MASK_SH_LIST(__SHIFT) | |
614 | }; | |
615 | ||
616 | static const struct dcn20_vmid_mask vmid_masks = { | |
617 | DCN20_VMID_MASK_SH_LIST(_MASK) | |
618 | }; | |
619 | ||
97bda032 HW |
620 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
621 | #define dsc_regsDCN20(id)\ | |
622 | [id] = {\ | |
623 | DSC_REG_LIST_DCN20(id)\ | |
624 | } | |
625 | ||
626 | static const struct dcn20_dsc_registers dsc_regs[] = { | |
627 | dsc_regsDCN20(0), | |
628 | dsc_regsDCN20(1), | |
629 | dsc_regsDCN20(2), | |
630 | dsc_regsDCN20(3), | |
631 | dsc_regsDCN20(4), | |
632 | dsc_regsDCN20(5) | |
633 | }; | |
634 | ||
635 | static const struct dcn20_dsc_shift dsc_shift = { | |
636 | DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) | |
637 | }; | |
638 | ||
639 | static const struct dcn20_dsc_mask dsc_mask = { | |
640 | DSC_REG_LIST_SH_MASK_DCN20(_MASK) | |
641 | }; | |
642 | #endif | |
7ed4e635 HW |
643 | |
644 | static const struct dccg_registers dccg_regs = { | |
645 | DCCG_REG_LIST_DCN2() | |
646 | }; | |
647 | ||
648 | static const struct dccg_shift dccg_shift = { | |
649 | DCCG_MASK_SH_LIST_DCN2(__SHIFT) | |
650 | }; | |
651 | ||
652 | static const struct dccg_mask dccg_mask = { | |
653 | DCCG_MASK_SH_LIST_DCN2(_MASK) | |
654 | }; | |
655 | ||
656 | static const struct resource_caps res_cap_nv10 = { | |
657 | .num_timing_generator = 6, | |
658 | .num_opp = 6, | |
659 | .num_video_plane = 6, | |
660 | .num_audio = 7, | |
661 | .num_stream_encoder = 6, | |
662 | .num_pll = 6, | |
0d7bd17c | 663 | .num_dwb = 0, |
7ed4e635 HW |
664 | .num_ddc = 6, |
665 | .num_vmid = 16, | |
97bda032 HW |
666 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
667 | .num_dsc = 6, | |
668 | #endif | |
7ed4e635 HW |
669 | }; |
670 | ||
671 | static const struct dc_plane_cap plane_cap = { | |
672 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, | |
673 | .blends_with_above = true, | |
674 | .blends_with_below = true, | |
7ed4e635 | 675 | .per_pixel_alpha = true, |
5b1b2f20 AD |
676 | |
677 | .pixel_format_support = { | |
678 | .argb8888 = true, | |
679 | .nv12 = true, | |
680 | .fp16 = true | |
681 | }, | |
682 | ||
683 | .max_upscale_factor = { | |
684 | .argb8888 = 16000, | |
685 | .nv12 = 16000, | |
686 | .fp16 = 1 | |
687 | }, | |
688 | ||
689 | .max_downscale_factor = { | |
690 | .argb8888 = 250, | |
691 | .nv12 = 250, | |
692 | .fp16 = 1 | |
693 | } | |
7ed4e635 HW |
694 | }; |
695 | ||
696 | static const struct dc_debug_options debug_defaults_drv = { | |
697 | .disable_dmcu = true, | |
698 | .force_abm_enable = false, | |
699 | .timing_trace = false, | |
700 | .clock_trace = true, | |
701 | .disable_pplib_clock_request = true, | |
702 | .pipe_split_policy = MPC_SPLIT_DYNAMIC, | |
703 | .force_single_disp_pipe_split = true, | |
704 | .disable_dcc = DCC_ENABLE, | |
705 | .vsr_support = true, | |
706 | .performance_trace = false, | |
707 | .max_downscale_src_width = 5120,/*upto 5K*/ | |
708 | .disable_pplib_wm_range = false, | |
709 | .scl_reset_length10 = true, | |
9e14d4f1 | 710 | .sanity_checks = false, |
7ed4e635 HW |
711 | .disable_tri_buf = true, |
712 | }; | |
713 | ||
714 | static const struct dc_debug_options debug_defaults_diags = { | |
715 | .disable_dmcu = true, | |
716 | .force_abm_enable = false, | |
717 | .timing_trace = true, | |
718 | .clock_trace = true, | |
719 | .disable_dpp_power_gate = true, | |
720 | .disable_hubp_power_gate = true, | |
721 | .disable_clock_gate = true, | |
722 | .disable_pplib_clock_request = true, | |
723 | .disable_pplib_wm_range = true, | |
724 | .disable_stutter = true, | |
725 | .scl_reset_length10 = true, | |
726 | }; | |
727 | ||
728 | void dcn20_dpp_destroy(struct dpp **dpp) | |
729 | { | |
730 | kfree(TO_DCN20_DPP(*dpp)); | |
731 | *dpp = NULL; | |
732 | } | |
733 | ||
734 | struct dpp *dcn20_dpp_create( | |
735 | struct dc_context *ctx, | |
736 | uint32_t inst) | |
737 | { | |
738 | struct dcn20_dpp *dpp = | |
739 | kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); | |
740 | ||
741 | if (!dpp) | |
742 | return NULL; | |
743 | ||
744 | if (dpp2_construct(dpp, ctx, inst, | |
745 | &tf_regs[inst], &tf_shift, &tf_mask)) | |
746 | return &dpp->base; | |
747 | ||
748 | BREAK_TO_DEBUGGER(); | |
749 | kfree(dpp); | |
750 | return NULL; | |
751 | } | |
752 | ||
753 | struct input_pixel_processor *dcn20_ipp_create( | |
754 | struct dc_context *ctx, uint32_t inst) | |
755 | { | |
756 | struct dcn10_ipp *ipp = | |
757 | kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); | |
758 | ||
759 | if (!ipp) { | |
760 | BREAK_TO_DEBUGGER(); | |
761 | return NULL; | |
762 | } | |
763 | ||
764 | dcn20_ipp_construct(ipp, ctx, inst, | |
765 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
766 | return &ipp->base; | |
767 | } | |
768 | ||
769 | ||
770 | struct output_pixel_processor *dcn20_opp_create( | |
771 | struct dc_context *ctx, uint32_t inst) | |
772 | { | |
773 | struct dcn20_opp *opp = | |
774 | kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); | |
775 | ||
776 | if (!opp) { | |
777 | BREAK_TO_DEBUGGER(); | |
778 | return NULL; | |
779 | } | |
780 | ||
781 | dcn20_opp_construct(opp, ctx, inst, | |
782 | &opp_regs[inst], &opp_shift, &opp_mask); | |
783 | return &opp->base; | |
784 | } | |
785 | ||
786 | struct dce_aux *dcn20_aux_engine_create( | |
787 | struct dc_context *ctx, | |
788 | uint32_t inst) | |
789 | { | |
790 | struct aux_engine_dce110 *aux_engine = | |
791 | kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); | |
792 | ||
793 | if (!aux_engine) | |
794 | return NULL; | |
795 | ||
796 | dce110_aux_engine_construct(aux_engine, ctx, inst, | |
797 | SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, | |
798 | &aux_engine_regs[inst]); | |
799 | ||
800 | return &aux_engine->base; | |
801 | } | |
802 | #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } | |
803 | ||
804 | static const struct dce_i2c_registers i2c_hw_regs[] = { | |
805 | i2c_inst_regs(1), | |
806 | i2c_inst_regs(2), | |
807 | i2c_inst_regs(3), | |
808 | i2c_inst_regs(4), | |
809 | i2c_inst_regs(5), | |
810 | i2c_inst_regs(6), | |
811 | }; | |
812 | ||
813 | static const struct dce_i2c_shift i2c_shifts = { | |
814 | I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) | |
815 | }; | |
816 | ||
817 | static const struct dce_i2c_mask i2c_masks = { | |
818 | I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) | |
819 | }; | |
820 | ||
821 | struct dce_i2c_hw *dcn20_i2c_hw_create( | |
822 | struct dc_context *ctx, | |
823 | uint32_t inst) | |
824 | { | |
825 | struct dce_i2c_hw *dce_i2c_hw = | |
826 | kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); | |
827 | ||
828 | if (!dce_i2c_hw) | |
829 | return NULL; | |
830 | ||
831 | dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, | |
832 | &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); | |
833 | ||
834 | return dce_i2c_hw; | |
835 | } | |
836 | struct mpc *dcn20_mpc_create(struct dc_context *ctx) | |
837 | { | |
838 | struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), | |
839 | GFP_KERNEL); | |
840 | ||
841 | if (!mpc20) | |
842 | return NULL; | |
843 | ||
844 | dcn20_mpc_construct(mpc20, ctx, | |
845 | &mpc_regs, | |
846 | &mpc_shift, | |
847 | &mpc_mask, | |
848 | 6); | |
849 | ||
850 | return &mpc20->base; | |
851 | } | |
852 | ||
853 | struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) | |
854 | { | |
855 | int i; | |
856 | struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), | |
857 | GFP_KERNEL); | |
858 | ||
859 | if (!hubbub) | |
860 | return NULL; | |
861 | ||
862 | hubbub2_construct(hubbub, ctx, | |
863 | &hubbub_reg, | |
864 | &hubbub_shift, | |
865 | &hubbub_mask); | |
866 | ||
867 | for (i = 0; i < res_cap_nv10.num_vmid; i++) { | |
868 | struct dcn20_vmid *vmid = &hubbub->vmid[i]; | |
869 | ||
870 | vmid->ctx = ctx; | |
871 | ||
872 | vmid->regs = &vmid_regs[i]; | |
873 | vmid->shifts = &vmid_shifts; | |
874 | vmid->masks = &vmid_masks; | |
875 | } | |
876 | ||
877 | return &hubbub->base; | |
878 | } | |
879 | ||
880 | struct timing_generator *dcn20_timing_generator_create( | |
881 | struct dc_context *ctx, | |
882 | uint32_t instance) | |
883 | { | |
884 | struct optc *tgn10 = | |
885 | kzalloc(sizeof(struct optc), GFP_KERNEL); | |
886 | ||
887 | if (!tgn10) | |
888 | return NULL; | |
889 | ||
890 | tgn10->base.inst = instance; | |
891 | tgn10->base.ctx = ctx; | |
892 | ||
893 | tgn10->tg_regs = &tg_regs[instance]; | |
894 | tgn10->tg_shift = &tg_shift; | |
895 | tgn10->tg_mask = &tg_mask; | |
896 | ||
897 | dcn20_timing_generator_init(tgn10); | |
898 | ||
899 | return &tgn10->base; | |
900 | } | |
901 | ||
902 | static const struct encoder_feature_support link_enc_feature = { | |
903 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
904 | .max_hdmi_pixel_clock = 600000, | |
905 | .hdmi_ycbcr420_supported = true, | |
906 | .dp_ycbcr420_supported = true, | |
907 | .flags.bits.IS_HBR2_CAPABLE = true, | |
908 | .flags.bits.IS_HBR3_CAPABLE = true, | |
909 | .flags.bits.IS_TPS3_CAPABLE = true, | |
910 | .flags.bits.IS_TPS4_CAPABLE = true | |
911 | }; | |
912 | ||
913 | struct link_encoder *dcn20_link_encoder_create( | |
914 | const struct encoder_init_data *enc_init_data) | |
915 | { | |
916 | struct dcn20_link_encoder *enc20 = | |
917 | kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); | |
918 | ||
919 | if (!enc20) | |
920 | return NULL; | |
921 | ||
922 | dcn20_link_encoder_construct(enc20, | |
923 | enc_init_data, | |
924 | &link_enc_feature, | |
925 | &link_enc_regs[enc_init_data->transmitter], | |
926 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
927 | &link_enc_hpd_regs[enc_init_data->hpd_source], | |
928 | &le_shift, | |
929 | &le_mask); | |
930 | ||
931 | return &enc20->enc10.base; | |
932 | } | |
933 | ||
934 | struct clock_source *dcn20_clock_source_create( | |
935 | struct dc_context *ctx, | |
936 | struct dc_bios *bios, | |
937 | enum clock_source_id id, | |
938 | const struct dce110_clk_src_regs *regs, | |
939 | bool dp_clk_src) | |
940 | { | |
941 | struct dce110_clk_src *clk_src = | |
942 | kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); | |
943 | ||
944 | if (!clk_src) | |
945 | return NULL; | |
946 | ||
947 | if (dcn20_clk_src_construct(clk_src, ctx, bios, id, | |
948 | regs, &cs_shift, &cs_mask)) { | |
949 | clk_src->base.dp_clk_src = dp_clk_src; | |
950 | return &clk_src->base; | |
951 | } | |
952 | ||
953 | BREAK_TO_DEBUGGER(); | |
954 | return NULL; | |
955 | } | |
956 | ||
957 | static void read_dce_straps( | |
958 | struct dc_context *ctx, | |
959 | struct resource_straps *straps) | |
960 | { | |
961 | generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), | |
962 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); | |
963 | } | |
964 | ||
965 | static struct audio *dcn20_create_audio( | |
966 | struct dc_context *ctx, unsigned int inst) | |
967 | { | |
968 | return dce_audio_create(ctx, inst, | |
969 | &audio_regs[inst], &audio_shift, &audio_mask); | |
970 | } | |
971 | ||
972 | struct stream_encoder *dcn20_stream_encoder_create( | |
973 | enum engine_id eng_id, | |
974 | struct dc_context *ctx) | |
975 | { | |
976 | struct dcn10_stream_encoder *enc1 = | |
977 | kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); | |
978 | ||
979 | if (!enc1) | |
980 | return NULL; | |
981 | ||
982 | dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, | |
983 | &stream_enc_regs[eng_id], | |
984 | &se_shift, &se_mask); | |
985 | ||
986 | return &enc1->base; | |
987 | } | |
988 | ||
989 | static const struct dce_hwseq_registers hwseq_reg = { | |
990 | HWSEQ_DCN2_REG_LIST() | |
991 | }; | |
992 | ||
993 | static const struct dce_hwseq_shift hwseq_shift = { | |
994 | HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) | |
995 | }; | |
996 | ||
997 | static const struct dce_hwseq_mask hwseq_mask = { | |
998 | HWSEQ_DCN2_MASK_SH_LIST(_MASK) | |
999 | }; | |
1000 | ||
1001 | struct dce_hwseq *dcn20_hwseq_create( | |
1002 | struct dc_context *ctx) | |
1003 | { | |
1004 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); | |
1005 | ||
1006 | if (hws) { | |
1007 | hws->ctx = ctx; | |
1008 | hws->regs = &hwseq_reg; | |
1009 | hws->shifts = &hwseq_shift; | |
1010 | hws->masks = &hwseq_mask; | |
1011 | } | |
1012 | return hws; | |
1013 | } | |
1014 | ||
1015 | static const struct resource_create_funcs res_create_funcs = { | |
1016 | .read_dce_straps = read_dce_straps, | |
1017 | .create_audio = dcn20_create_audio, | |
1018 | .create_stream_encoder = dcn20_stream_encoder_create, | |
1019 | .create_hwseq = dcn20_hwseq_create, | |
1020 | }; | |
1021 | ||
1022 | static const struct resource_create_funcs res_create_maximus_funcs = { | |
1023 | .read_dce_straps = NULL, | |
1024 | .create_audio = NULL, | |
1025 | .create_stream_encoder = NULL, | |
1026 | .create_hwseq = dcn20_hwseq_create, | |
1027 | }; | |
1028 | ||
1029 | void dcn20_clock_source_destroy(struct clock_source **clk_src) | |
1030 | { | |
1031 | kfree(TO_DCE110_CLK_SRC(*clk_src)); | |
1032 | *clk_src = NULL; | |
1033 | } | |
1034 | ||
97bda032 HW |
1035 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1036 | ||
1037 | struct display_stream_compressor *dcn20_dsc_create( | |
1038 | struct dc_context *ctx, uint32_t inst) | |
1039 | { | |
1040 | struct dcn20_dsc *dsc = | |
1041 | kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); | |
1042 | ||
1043 | if (!dsc) { | |
1044 | BREAK_TO_DEBUGGER(); | |
1045 | return NULL; | |
1046 | } | |
1047 | ||
1048 | dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); | |
1049 | return &dsc->base; | |
1050 | } | |
1051 | ||
1052 | void dcn20_dsc_destroy(struct display_stream_compressor **dsc) | |
1053 | { | |
1054 | kfree(container_of(*dsc, struct dcn20_dsc, base)); | |
1055 | *dsc = NULL; | |
1056 | } | |
1057 | ||
1058 | #endif | |
7ed4e635 HW |
1059 | |
1060 | static void destruct(struct dcn20_resource_pool *pool) | |
1061 | { | |
1062 | unsigned int i; | |
1063 | ||
1064 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
1065 | if (pool->base.stream_enc[i] != NULL) { | |
1066 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); | |
1067 | pool->base.stream_enc[i] = NULL; | |
1068 | } | |
1069 | } | |
1070 | ||
97bda032 HW |
1071 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1072 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | |
1073 | if (pool->base.dscs[i] != NULL) | |
1074 | dcn20_dsc_destroy(&pool->base.dscs[i]); | |
1075 | } | |
1076 | #endif | |
7ed4e635 HW |
1077 | |
1078 | if (pool->base.mpc != NULL) { | |
1079 | kfree(TO_DCN20_MPC(pool->base.mpc)); | |
1080 | pool->base.mpc = NULL; | |
1081 | } | |
1082 | if (pool->base.hubbub != NULL) { | |
1083 | kfree(pool->base.hubbub); | |
1084 | pool->base.hubbub = NULL; | |
1085 | } | |
1086 | for (i = 0; i < pool->base.pipe_count; i++) { | |
1087 | if (pool->base.dpps[i] != NULL) | |
1088 | dcn20_dpp_destroy(&pool->base.dpps[i]); | |
1089 | ||
1090 | if (pool->base.ipps[i] != NULL) | |
1091 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); | |
1092 | ||
1093 | if (pool->base.hubps[i] != NULL) { | |
1094 | kfree(TO_DCN20_HUBP(pool->base.hubps[i])); | |
1095 | pool->base.hubps[i] = NULL; | |
1096 | } | |
1097 | ||
1098 | if (pool->base.irqs != NULL) { | |
1099 | dal_irq_service_destroy(&pool->base.irqs); | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |
1104 | if (pool->base.engines[i] != NULL) | |
1105 | dce110_engine_destroy(&pool->base.engines[i]); | |
1106 | if (pool->base.hw_i2cs[i] != NULL) { | |
1107 | kfree(pool->base.hw_i2cs[i]); | |
1108 | pool->base.hw_i2cs[i] = NULL; | |
1109 | } | |
1110 | if (pool->base.sw_i2cs[i] != NULL) { | |
1111 | kfree(pool->base.sw_i2cs[i]); | |
1112 | pool->base.sw_i2cs[i] = NULL; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |
1117 | if (pool->base.opps[i] != NULL) | |
1118 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); | |
1119 | } | |
1120 | ||
1121 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
1122 | if (pool->base.timing_generators[i] != NULL) { | |
1123 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); | |
1124 | pool->base.timing_generators[i] = NULL; | |
1125 | } | |
1126 | } | |
1127 | ||
bb21290f CL |
1128 | for (i = 0; i < pool->base.res_cap->num_dwb; i++) { |
1129 | if (pool->base.dwbc[i] != NULL) { | |
1130 | kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); | |
1131 | pool->base.dwbc[i] = NULL; | |
1132 | } | |
1133 | if (pool->base.mcif_wb[i] != NULL) { | |
1134 | kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); | |
1135 | pool->base.mcif_wb[i] = NULL; | |
1136 | } | |
1137 | } | |
1138 | ||
7ed4e635 HW |
1139 | for (i = 0; i < pool->base.audio_count; i++) { |
1140 | if (pool->base.audios[i]) | |
1141 | dce_aud_destroy(&pool->base.audios[i]); | |
1142 | } | |
1143 | ||
1144 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
1145 | if (pool->base.clock_sources[i] != NULL) { | |
1146 | dcn20_clock_source_destroy(&pool->base.clock_sources[i]); | |
1147 | pool->base.clock_sources[i] = NULL; | |
1148 | } | |
1149 | } | |
1150 | ||
1151 | if (pool->base.dp_clock_source != NULL) { | |
1152 | dcn20_clock_source_destroy(&pool->base.dp_clock_source); | |
1153 | pool->base.dp_clock_source = NULL; | |
1154 | } | |
1155 | ||
1156 | ||
1157 | if (pool->base.abm != NULL) | |
1158 | dce_abm_destroy(&pool->base.abm); | |
1159 | ||
1160 | if (pool->base.dmcu != NULL) | |
1161 | dce_dmcu_destroy(&pool->base.dmcu); | |
1162 | ||
1163 | if (pool->base.dccg != NULL) | |
1164 | dcn_dccg_destroy(&pool->base.dccg); | |
1165 | ||
1166 | if (pool->base.pp_smu != NULL) | |
1167 | dcn20_pp_smu_destroy(&pool->base.pp_smu); | |
1168 | ||
1169 | } | |
1170 | ||
1171 | struct hubp *dcn20_hubp_create( | |
1172 | struct dc_context *ctx, | |
1173 | uint32_t inst) | |
1174 | { | |
1175 | struct dcn20_hubp *hubp2 = | |
1176 | kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); | |
1177 | ||
1178 | if (!hubp2) | |
1179 | return NULL; | |
1180 | ||
1181 | if (hubp2_construct(hubp2, ctx, inst, | |
1182 | &hubp_regs[inst], &hubp_shift, &hubp_mask)) | |
1183 | return &hubp2->base; | |
1184 | ||
1185 | BREAK_TO_DEBUGGER(); | |
1186 | kfree(hubp2); | |
1187 | return NULL; | |
1188 | } | |
1189 | ||
1190 | static void get_pixel_clock_parameters( | |
1191 | struct pipe_ctx *pipe_ctx, | |
1192 | struct pixel_clk_params *pixel_clk_params) | |
1193 | { | |
1194 | const struct dc_stream_state *stream = pipe_ctx->stream; | |
1195 | bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL; | |
1196 | ||
1197 | pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; | |
1198 | pixel_clk_params->encoder_object_id = stream->link->link_enc->id; | |
1199 | pixel_clk_params->signal_type = pipe_ctx->stream->signal; | |
1200 | pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; | |
1201 | /* TODO: un-hardcode*/ | |
1202 | pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * | |
1203 | LINK_RATE_REF_FREQ_IN_KHZ; | |
1204 | pixel_clk_params->flags.ENABLE_SS = 0; | |
1205 | pixel_clk_params->color_depth = | |
1206 | stream->timing.display_color_depth; | |
1207 | pixel_clk_params->flags.DISPLAY_BLANKED = 1; | |
1208 | pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; | |
1209 | ||
1210 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) | |
1211 | pixel_clk_params->color_depth = COLOR_DEPTH_888; | |
1212 | ||
1213 | if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine) | |
1214 | pixel_clk_params->requested_pix_clk_100hz /= 2; | |
1215 | ||
1216 | if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) | |
1217 | pixel_clk_params->requested_pix_clk_100hz *= 2; | |
1218 | ||
1219 | } | |
1220 | ||
1221 | static void build_clamping_params(struct dc_stream_state *stream) | |
1222 | { | |
1223 | stream->clamping.clamping_level = CLAMPING_FULL_RANGE; | |
1224 | stream->clamping.c_depth = stream->timing.display_color_depth; | |
1225 | stream->clamping.pixel_encoding = stream->timing.pixel_encoding; | |
1226 | } | |
1227 | ||
1228 | static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) | |
1229 | { | |
1230 | ||
1231 | get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); | |
1232 | ||
1233 | pipe_ctx->clock_source->funcs->get_pix_clk_dividers( | |
1234 | pipe_ctx->clock_source, | |
1235 | &pipe_ctx->stream_res.pix_clk_params, | |
1236 | &pipe_ctx->pll_settings); | |
1237 | ||
1238 | pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; | |
1239 | ||
1240 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, | |
1241 | &pipe_ctx->stream->bit_depth_params); | |
1242 | build_clamping_params(pipe_ctx->stream); | |
1243 | ||
1244 | return DC_OK; | |
1245 | } | |
1246 | ||
1247 | enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) | |
1248 | { | |
1249 | enum dc_status status = DC_OK; | |
1250 | struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); | |
1251 | ||
1252 | /*TODO Seems unneeded anymore */ | |
1253 | /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { | |
1254 | if (stream != NULL && old_context->streams[i] != NULL) { | |
1255 | todo: shouldn't have to copy missing parameter here | |
1256 | resource_build_bit_depth_reduction_params(stream, | |
1257 | &stream->bit_depth_params); | |
1258 | stream->clamping.pixel_encoding = | |
1259 | stream->timing.pixel_encoding; | |
1260 | ||
1261 | resource_build_bit_depth_reduction_params(stream, | |
1262 | &stream->bit_depth_params); | |
1263 | build_clamping_params(stream); | |
1264 | ||
1265 | continue; | |
1266 | } | |
1267 | } | |
1268 | */ | |
1269 | ||
1270 | if (!pipe_ctx) | |
1271 | return DC_ERROR_UNEXPECTED; | |
1272 | ||
1273 | ||
1274 | status = build_pipe_hw_param(pipe_ctx); | |
1275 | ||
1276 | return status; | |
1277 | } | |
1278 | ||
97bda032 HW |
1279 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1280 | ||
c9ae6e16 NC |
1281 | static void acquire_dsc(struct resource_context *res_ctx, |
1282 | const struct resource_pool *pool, | |
1283 | struct display_stream_compressor **dsc) | |
97bda032 HW |
1284 | { |
1285 | int i; | |
c9ae6e16 NC |
1286 | |
1287 | ASSERT(*dsc == NULL); | |
1288 | *dsc = NULL; | |
97bda032 HW |
1289 | |
1290 | /* Find first free DSC */ | |
1291 | for (i = 0; i < pool->res_cap->num_dsc; i++) | |
1292 | if (!res_ctx->is_dsc_acquired[i]) { | |
c9ae6e16 | 1293 | *dsc = pool->dscs[i]; |
97bda032 HW |
1294 | res_ctx->is_dsc_acquired[i] = true; |
1295 | break; | |
1296 | } | |
97bda032 HW |
1297 | } |
1298 | ||
1299 | static void release_dsc(struct resource_context *res_ctx, | |
1300 | const struct resource_pool *pool, | |
c9ae6e16 | 1301 | struct display_stream_compressor **dsc) |
97bda032 HW |
1302 | { |
1303 | int i; | |
1304 | ||
1305 | for (i = 0; i < pool->res_cap->num_dsc; i++) | |
c9ae6e16 | 1306 | if (pool->dscs[i] == *dsc) { |
97bda032 | 1307 | res_ctx->is_dsc_acquired[i] = false; |
c9ae6e16 | 1308 | *dsc = NULL; |
97bda032 HW |
1309 | break; |
1310 | } | |
1311 | } | |
1312 | ||
1313 | #endif | |
7ed4e635 | 1314 | |
7ed4e635 | 1315 | |
97bda032 | 1316 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
c9ae6e16 NC |
1317 | enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, |
1318 | struct dc_state *dc_ctx, | |
1319 | struct dc_stream_state *dc_stream) | |
1320 | { | |
1321 | enum dc_status result = DC_OK; | |
1322 | int i; | |
1323 | const struct resource_pool *pool = dc->res_pool; | |
97bda032 | 1324 | |
c9ae6e16 NC |
1325 | /* Get a DSC if required and available */ |
1326 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1327 | struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; | |
97bda032 | 1328 | |
c9ae6e16 NC |
1329 | if (pipe_ctx->stream != dc_stream) |
1330 | continue; | |
97bda032 | 1331 | |
c9ae6e16 | 1332 | acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc); |
97bda032 | 1333 | |
c9ae6e16 NC |
1334 | /* The number of DSCs can be less than the number of pipes */ |
1335 | if (!pipe_ctx->stream_res.dsc) { | |
1336 | dm_output_to_console("No DSCs available\n"); | |
1337 | result = DC_NO_DSC_RESOURCE; | |
97bda032 | 1338 | } |
7ed4e635 | 1339 | |
c9ae6e16 NC |
1340 | break; |
1341 | } | |
7ed4e635 HW |
1342 | |
1343 | return result; | |
1344 | } | |
1345 | ||
1346 | ||
c9ae6e16 NC |
1347 | enum dc_status dcn20_remove_dsc_from_stream_resource(struct dc *dc, |
1348 | struct dc_state *new_ctx, | |
1349 | struct dc_stream_state *dc_stream) | |
7ed4e635 HW |
1350 | { |
1351 | struct pipe_ctx *pipe_ctx = NULL; | |
1352 | int i; | |
1353 | ||
7ed4e635 HW |
1354 | for (i = 0; i < MAX_PIPES; i++) { |
1355 | if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { | |
1356 | pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; | |
1357 | break; | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | if (!pipe_ctx) | |
1362 | return DC_ERROR_UNEXPECTED; | |
1363 | ||
97bda032 HW |
1364 | if (pipe_ctx->stream_res.dsc) { |
1365 | struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); | |
1366 | ||
c9ae6e16 NC |
1367 | release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); |
1368 | if (odm_pipe) | |
1369 | release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); | |
97bda032 | 1370 | } |
7ed4e635 HW |
1371 | |
1372 | return DC_OK; | |
1373 | } | |
c9ae6e16 NC |
1374 | #endif |
1375 | ||
1376 | ||
1377 | enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) | |
1378 | { | |
1379 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
1380 | ||
1381 | result = resource_map_pool_resources(dc, new_ctx, dc_stream); | |
1382 | ||
1383 | if (result == DC_OK) | |
1384 | result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); | |
1385 | ||
1386 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | |
1387 | /* Get a DSC if required and available */ | |
1388 | if (result == DC_OK && dc_stream->timing.flags.DSC) | |
1389 | result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); | |
1390 | #endif | |
1391 | ||
1392 | if (result == DC_OK) | |
1393 | result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); | |
1394 | ||
1395 | return result; | |
1396 | } | |
1397 | ||
1398 | ||
1399 | enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) | |
1400 | { | |
1401 | enum dc_status result = DC_OK; | |
1402 | ||
1403 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | |
1404 | result = dcn20_remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); | |
1405 | #endif | |
1406 | ||
1407 | return result; | |
1408 | } | |
7ed4e635 HW |
1409 | |
1410 | ||
1411 | static void swizzle_to_dml_params( | |
1412 | enum swizzle_mode_values swizzle, | |
1413 | unsigned int *sw_mode) | |
1414 | { | |
1415 | switch (swizzle) { | |
1416 | case DC_SW_LINEAR: | |
1417 | *sw_mode = dm_sw_linear; | |
1418 | break; | |
1419 | case DC_SW_4KB_S: | |
1420 | *sw_mode = dm_sw_4kb_s; | |
1421 | break; | |
1422 | case DC_SW_4KB_S_X: | |
1423 | *sw_mode = dm_sw_4kb_s_x; | |
1424 | break; | |
1425 | case DC_SW_4KB_D: | |
1426 | *sw_mode = dm_sw_4kb_d; | |
1427 | break; | |
1428 | case DC_SW_4KB_D_X: | |
1429 | *sw_mode = dm_sw_4kb_d_x; | |
1430 | break; | |
1431 | case DC_SW_64KB_S: | |
1432 | *sw_mode = dm_sw_64kb_s; | |
1433 | break; | |
1434 | case DC_SW_64KB_S_X: | |
1435 | *sw_mode = dm_sw_64kb_s_x; | |
1436 | break; | |
1437 | case DC_SW_64KB_S_T: | |
1438 | *sw_mode = dm_sw_64kb_s_t; | |
1439 | break; | |
1440 | case DC_SW_64KB_D: | |
1441 | *sw_mode = dm_sw_64kb_d; | |
1442 | break; | |
1443 | case DC_SW_64KB_D_X: | |
1444 | *sw_mode = dm_sw_64kb_d_x; | |
1445 | break; | |
1446 | case DC_SW_64KB_D_T: | |
1447 | *sw_mode = dm_sw_64kb_d_t; | |
1448 | break; | |
1449 | case DC_SW_64KB_R_X: | |
1450 | *sw_mode = dm_sw_64kb_r_x; | |
1451 | break; | |
1452 | case DC_SW_VAR_S: | |
1453 | *sw_mode = dm_sw_var_s; | |
1454 | break; | |
1455 | case DC_SW_VAR_S_X: | |
1456 | *sw_mode = dm_sw_var_s_x; | |
1457 | break; | |
1458 | case DC_SW_VAR_D: | |
1459 | *sw_mode = dm_sw_var_d; | |
1460 | break; | |
1461 | case DC_SW_VAR_D_X: | |
1462 | *sw_mode = dm_sw_var_d_x; | |
1463 | break; | |
1464 | ||
1465 | default: | |
1466 | ASSERT(0); /* Not supported */ | |
1467 | break; | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | static bool dcn20_split_stream_for_combine( | |
1472 | struct resource_context *res_ctx, | |
1473 | const struct resource_pool *pool, | |
1474 | struct pipe_ctx *primary_pipe, | |
1475 | struct pipe_ctx *secondary_pipe, | |
1476 | bool is_odm_combine) | |
1477 | { | |
1478 | int pipe_idx = secondary_pipe->pipe_idx; | |
1479 | struct scaler_data *sd = &primary_pipe->plane_res.scl_data; | |
1480 | struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; | |
1481 | int new_width; | |
1482 | ||
1483 | *secondary_pipe = *primary_pipe; | |
1484 | secondary_pipe->bottom_pipe = sec_bot_pipe; | |
1485 | ||
1486 | secondary_pipe->pipe_idx = pipe_idx; | |
1487 | secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; | |
1488 | secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; | |
1489 | secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; | |
1490 | secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; | |
1491 | secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; | |
1492 | secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; | |
c92b4c46 NC |
1493 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1494 | secondary_pipe->stream_res.dsc = NULL; | |
1495 | #endif | |
7ed4e635 HW |
1496 | if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { |
1497 | ASSERT(!secondary_pipe->bottom_pipe); | |
1498 | secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; | |
1499 | secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; | |
1500 | } | |
1501 | primary_pipe->bottom_pipe = secondary_pipe; | |
1502 | secondary_pipe->top_pipe = primary_pipe; | |
1503 | ||
1504 | if (is_odm_combine) { | |
7ed4e635 HW |
1505 | if (primary_pipe->plane_state) { |
1506 | /* HACTIVE halved for odm combine */ | |
1507 | sd->h_active /= 2; | |
1508 | /* Copy scl_data to secondary pipe */ | |
1509 | secondary_pipe->plane_res.scl_data = *sd; | |
1510 | ||
1511 | /* Calculate new vp and recout for left pipe */ | |
1512 | /* Need at least 16 pixels width per side */ | |
1513 | if (sd->recout.x + 16 >= sd->h_active) | |
1514 | return false; | |
1515 | new_width = sd->h_active - sd->recout.x; | |
1516 | sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1517 | sd->ratios.horz, sd->recout.width - new_width)); | |
1518 | sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1519 | sd->ratios.horz_c, sd->recout.width - new_width)); | |
1520 | sd->recout.width = new_width; | |
1521 | ||
1522 | /* Calculate new vp and recout for right pipe */ | |
1523 | sd = &secondary_pipe->plane_res.scl_data; | |
1524 | new_width = sd->recout.width + sd->recout.x - sd->h_active; | |
1525 | /* Need at least 16 pixels width per side */ | |
1526 | if (new_width <= 16) | |
1527 | return false; | |
1528 | sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1529 | sd->ratios.horz, sd->recout.width - new_width)); | |
1530 | sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1531 | sd->ratios.horz_c, sd->recout.width - new_width)); | |
1532 | sd->recout.width = new_width; | |
1533 | sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( | |
1534 | sd->ratios.horz, sd->h_active - sd->recout.x)); | |
1535 | sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( | |
1536 | sd->ratios.horz_c, sd->h_active - sd->recout.x)); | |
1537 | sd->recout.x = 0; | |
1538 | } | |
1539 | secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx]; | |
97bda032 | 1540 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
c9ae6e16 NC |
1541 | if (secondary_pipe->stream->timing.flags.DSC == 1) { |
1542 | acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc); | |
97bda032 HW |
1543 | ASSERT(secondary_pipe->stream_res.dsc); |
1544 | if (secondary_pipe->stream_res.dsc == NULL) | |
1545 | return false; | |
1546 | } | |
1547 | #endif | |
7ed4e635 HW |
1548 | } else { |
1549 | ASSERT(primary_pipe->plane_state); | |
1550 | resource_build_scaling_params(primary_pipe); | |
1551 | resource_build_scaling_params(secondary_pipe); | |
1552 | } | |
1553 | ||
1554 | return true; | |
1555 | } | |
1556 | ||
1557 | void dcn20_populate_dml_writeback_from_context( | |
1558 | struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) | |
1559 | { | |
1560 | int pipe_cnt, i; | |
1561 | ||
1562 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { | |
1563 | struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; | |
1564 | ||
1565 | if (!res_ctx->pipe_ctx[i].stream) | |
1566 | continue; | |
1567 | ||
1568 | /* Set writeback information */ | |
1569 | pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; | |
1570 | pipes[pipe_cnt].dout.num_active_wb++; | |
1571 | pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; | |
1572 | pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; | |
1573 | pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; | |
1574 | pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; | |
1575 | pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; | |
1576 | pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; | |
1577 | pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; | |
1578 | pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; | |
1579 | pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; | |
1580 | pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; | |
1581 | if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { | |
1582 | if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) | |
1583 | pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; | |
1584 | else | |
1585 | pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; | |
1586 | } else | |
1587 | pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; | |
1588 | ||
1589 | pipe_cnt++; | |
1590 | } | |
1591 | ||
1592 | } | |
1593 | ||
1594 | int dcn20_populate_dml_pipes_from_context( | |
1595 | struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) | |
1596 | { | |
1597 | int pipe_cnt, i; | |
1598 | bool synchronized_vblank = true; | |
1599 | ||
1600 | for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { | |
1601 | if (!res_ctx->pipe_ctx[i].stream) | |
1602 | continue; | |
1603 | ||
1604 | if (pipe_cnt < 0) { | |
1605 | pipe_cnt = i; | |
1606 | continue; | |
1607 | } | |
1608 | if (!resource_are_streams_timing_synchronizable( | |
1609 | res_ctx->pipe_ctx[pipe_cnt].stream, | |
1610 | res_ctx->pipe_ctx[i].stream)) { | |
1611 | synchronized_vblank = false; | |
1612 | break; | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { | |
1617 | struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; | |
1618 | struct dc_link *link; | |
1619 | ||
1620 | if (!res_ctx->pipe_ctx[i].stream) | |
1621 | continue; | |
1622 | /* todo: | |
1623 | pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; | |
1624 | pipes[pipe_cnt].pipe.src.dcc = 0; | |
1625 | pipes[pipe_cnt].pipe.src.vm = 0;*/ | |
1626 | ||
97bda032 HW |
1627 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1628 | pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; | |
1629 | /* todo: rotation?*/ | |
1630 | pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; | |
1631 | #endif | |
7ed4e635 HW |
1632 | if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { |
1633 | pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; | |
1634 | /* 1/2 vblank */ | |
1635 | pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = | |
1636 | (timing->v_total - timing->v_addressable | |
1637 | - timing->v_border_top - timing->v_border_bottom) / 2; | |
1638 | /* 36 bytes dp, 32 hdmi */ | |
1639 | pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = | |
1640 | dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; | |
1641 | } | |
1642 | pipes[pipe_cnt].pipe.src.dcc = false; | |
1643 | pipes[pipe_cnt].pipe.src.dcc_rate = 1; | |
1644 | pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; | |
1645 | pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; | |
1646 | pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start | |
1647 | - timing->h_addressable | |
1648 | - timing->h_border_left | |
1649 | - timing->h_border_right; | |
1650 | pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch; | |
1651 | pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start | |
1652 | - timing->v_addressable | |
1653 | - timing->v_border_top | |
1654 | - timing->v_border_bottom; | |
1655 | pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; | |
1656 | pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; | |
1657 | pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; | |
1658 | pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; | |
1659 | pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; | |
1660 | pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; | |
1661 | if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) | |
1662 | pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; | |
1663 | pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; | |
1664 | ||
1665 | link = res_ctx->pipe_ctx[i].stream->link; | |
1666 | if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) { | |
1667 | pipes[pipe_cnt].dout.dp_lanes = link->cur_link_settings.lane_count; | |
1668 | } else if (link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) { | |
1669 | pipes[pipe_cnt].dout.dp_lanes = link->verified_link_cap.lane_count; | |
1670 | } else { | |
1671 | /* Unknown link capabilities, so assume max */ | |
1672 | pipes[pipe_cnt].dout.dp_lanes = 4; | |
1673 | } | |
1674 | ||
1675 | pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth; | |
1676 | switch (res_ctx->pipe_ctx[i].stream->signal) { | |
1677 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
1678 | case SIGNAL_TYPE_DISPLAY_PORT: | |
1679 | pipes[pipe_cnt].dout.output_type = dm_dp; | |
1680 | break; | |
1681 | case SIGNAL_TYPE_EDP: | |
1682 | pipes[pipe_cnt].dout.output_type = dm_edp; | |
1683 | break; | |
1684 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
1685 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
1686 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
1687 | pipes[pipe_cnt].dout.output_type = dm_hdmi; | |
1688 | break; | |
1689 | default: | |
1690 | /* In case there is no signal, set dp with 4 lanes to allow max config */ | |
1691 | pipes[pipe_cnt].dout.output_type = dm_dp; | |
1692 | pipes[pipe_cnt].dout.dp_lanes = 4; | |
1693 | } | |
1694 | switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { | |
1695 | case PIXEL_ENCODING_RGB: | |
1696 | case PIXEL_ENCODING_YCBCR444: | |
1697 | pipes[pipe_cnt].dout.output_format = dm_444; | |
1698 | break; | |
1699 | case PIXEL_ENCODING_YCBCR420: | |
1700 | pipes[pipe_cnt].dout.output_format = dm_420; | |
1701 | break; | |
1702 | case PIXEL_ENCODING_YCBCR422: | |
1703 | if (true) /* todo */ | |
1704 | pipes[pipe_cnt].dout.output_format = dm_s422; | |
1705 | else | |
1706 | pipes[pipe_cnt].dout.output_format = dm_n422; | |
1707 | break; | |
1708 | default: | |
1709 | pipes[pipe_cnt].dout.output_format = dm_444; | |
1710 | } | |
1711 | pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; | |
1712 | if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state | |
1713 | == res_ctx->pipe_ctx[i].plane_state) | |
1714 | pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; | |
1715 | ||
1716 | /* todo: default max for now, until there is logic reflecting this in dc*/ | |
1717 | pipes[pipe_cnt].dout.output_bpc = 12; | |
1718 | /* | |
1719 | * Use max cursor settings for calculations to minimize | |
1720 | * bw calculations due to cursor on/off | |
1721 | */ | |
1722 | pipes[pipe_cnt].pipe.src.num_cursors = 2; | |
ed07237c IB |
1723 | pipes[pipe_cnt].pipe.src.cur0_src_width = 256; |
1724 | pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; | |
1725 | pipes[pipe_cnt].pipe.src.cur1_src_width = 256; | |
1726 | pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit; | |
7ed4e635 HW |
1727 | |
1728 | if (!res_ctx->pipe_ctx[i].plane_state) { | |
1729 | pipes[pipe_cnt].pipe.src.source_scan = dm_horz; | |
1730 | pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; | |
1731 | pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; | |
1732 | pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; | |
1733 | if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) | |
1734 | pipes[pipe_cnt].pipe.src.viewport_width = 1920; | |
1735 | pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; | |
1736 | if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) | |
1737 | pipes[pipe_cnt].pipe.src.viewport_height = 1080; | |
1738 | pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */ | |
1739 | pipes[pipe_cnt].pipe.src.source_format = dm_444_32; | |
1740 | pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ | |
1741 | pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ | |
1742 | pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ | |
1743 | pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ | |
1744 | pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; | |
1745 | pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; | |
1746 | pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; | |
1747 | pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ | |
1748 | pipes[pipe_cnt].pipe.scale_taps.htaps = 1; | |
1749 | pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; | |
1750 | pipes[pipe_cnt].pipe.src.is_hsplit = 0; | |
1751 | pipes[pipe_cnt].pipe.dest.odm_combine = 0; | |
1752 | } else { | |
1753 | struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; | |
1754 | struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; | |
1755 | ||
7ed4e635 HW |
1756 | pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; |
1757 | pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe | |
1758 | && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) | |
1759 | || (res_ctx->pipe_ctx[i].top_pipe | |
1760 | && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln); | |
1761 | pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe | |
1762 | && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln | |
1763 | && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp | |
1764 | != res_ctx->pipe_ctx[i].stream_res.opp) | |
1765 | || (res_ctx->pipe_ctx[i].top_pipe | |
1766 | && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln | |
1767 | && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp | |
1768 | != res_ctx->pipe_ctx[i].stream_res.opp); | |
1769 | pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 | |
1770 | || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; | |
1771 | pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; | |
1772 | pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; | |
1773 | pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; | |
1774 | pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; | |
1775 | pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; | |
1776 | pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; | |
1777 | if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { | |
1778 | pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch; | |
1779 | pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch; | |
1780 | pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l; | |
1781 | pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c; | |
1782 | } else { | |
1783 | pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch; | |
1784 | pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch; | |
1785 | } | |
1786 | pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; | |
1787 | pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; | |
1788 | pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; | |
1789 | pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; | |
1790 | pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; | |
1791 | if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) { | |
1792 | pipes[pipe_cnt].pipe.dest.full_recout_width += | |
1793 | res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width; | |
1794 | pipes[pipe_cnt].pipe.dest.full_recout_height += | |
1795 | res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height; | |
1796 | } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) { | |
1797 | pipes[pipe_cnt].pipe.dest.full_recout_width += | |
1798 | res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; | |
1799 | pipes[pipe_cnt].pipe.dest.full_recout_height += | |
1800 | res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height; | |
1801 | } | |
1802 | ||
ed07237c | 1803 | pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; |
7ed4e635 HW |
1804 | pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); |
1805 | pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); | |
1806 | pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); | |
1807 | pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); | |
1808 | pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = | |
1809 | scl->ratios.vert.value != dc_fixpt_one.value | |
1810 | || scl->ratios.horz.value != dc_fixpt_one.value | |
1811 | || scl->ratios.vert_c.value != dc_fixpt_one.value | |
1812 | || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ | |
1813 | || dc->debug.always_scale; /*support always scale*/ | |
1814 | pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; | |
1815 | pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; | |
1816 | pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; | |
1817 | pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; | |
1818 | ||
b964e790 DL |
1819 | pipes[pipe_cnt].pipe.src.macro_tile_size = |
1820 | swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); | |
7ed4e635 HW |
1821 | swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, |
1822 | &pipes[pipe_cnt].pipe.src.sw_mode); | |
1823 | ||
1824 | switch (pln->format) { | |
1825 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: | |
1826 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: | |
1827 | pipes[pipe_cnt].pipe.src.source_format = dm_420_8; | |
1828 | break; | |
1829 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: | |
1830 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: | |
1831 | pipes[pipe_cnt].pipe.src.source_format = dm_420_10; | |
1832 | break; | |
1833 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |
1834 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |
1835 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |
1836 | pipes[pipe_cnt].pipe.src.source_format = dm_444_64; | |
1837 | break; | |
1838 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: | |
1839 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |
1840 | pipes[pipe_cnt].pipe.src.source_format = dm_444_16; | |
1841 | break; | |
1842 | case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: | |
1843 | pipes[pipe_cnt].pipe.src.source_format = dm_444_8; | |
1844 | break; | |
1845 | default: | |
1846 | pipes[pipe_cnt].pipe.src.source_format = dm_444_32; | |
1847 | break; | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | pipe_cnt++; | |
1852 | } | |
1853 | ||
1854 | /* populate writeback information */ | |
1855 | dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); | |
1856 | ||
1857 | return pipe_cnt; | |
1858 | } | |
1859 | ||
1860 | unsigned int dcn20_calc_max_scaled_time( | |
1861 | unsigned int time_per_pixel, | |
1862 | enum mmhubbub_wbif_mode mode, | |
1863 | unsigned int urgent_watermark) | |
1864 | { | |
1865 | unsigned int time_per_byte = 0; | |
1866 | unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ | |
1867 | unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ | |
1868 | unsigned int small_free_entry, max_free_entry; | |
1869 | unsigned int buf_lh_capability; | |
1870 | unsigned int max_scaled_time; | |
1871 | ||
1872 | if (mode == PACKED_444) /* packed mode */ | |
1873 | time_per_byte = time_per_pixel/4; | |
1874 | else if (mode == PLANAR_420_8BPC) | |
1875 | time_per_byte = time_per_pixel; | |
1876 | else if (mode == PLANAR_420_10BPC) /* p010 */ | |
1877 | time_per_byte = time_per_pixel * 819/1024; | |
1878 | ||
1879 | if (time_per_byte == 0) | |
1880 | time_per_byte = 1; | |
1881 | ||
1882 | small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; | |
1883 | max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; | |
1884 | buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ | |
1885 | max_scaled_time = buf_lh_capability - urgent_watermark; | |
1886 | return max_scaled_time; | |
1887 | } | |
1888 | ||
1889 | void dcn20_set_mcif_arb_params( | |
1890 | struct dc *dc, | |
1891 | struct dc_state *context, | |
1892 | display_e2e_pipe_params_st *pipes, | |
1893 | int pipe_cnt) | |
1894 | { | |
1895 | enum mmhubbub_wbif_mode wbif_mode; | |
1896 | struct mcif_arb_params *wb_arb_params; | |
1897 | int i, j, k, dwb_pipe; | |
1898 | ||
1899 | /* Writeback MCIF_WB arbitration parameters */ | |
1900 | dwb_pipe = 0; | |
1901 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1902 | ||
1903 | if (!context->res_ctx.pipe_ctx[i].stream) | |
1904 | continue; | |
1905 | ||
1906 | for (j = 0; j < MAX_DWB_PIPES; j++) { | |
1907 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) | |
1908 | continue; | |
1909 | ||
1910 | //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; | |
1911 | wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; | |
1912 | ||
1913 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { | |
1914 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) | |
1915 | wbif_mode = PLANAR_420_8BPC; | |
1916 | else | |
1917 | wbif_mode = PLANAR_420_10BPC; | |
1918 | } else | |
1919 | wbif_mode = PACKED_444; | |
1920 | ||
1921 | for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { | |
1922 | wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
1923 | wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
1924 | } | |
1925 | wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ | |
1926 | wb_arb_params->slice_lines = 32; | |
1927 | wb_arb_params->arbitration_slice = 2; | |
1928 | wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, | |
1929 | wbif_mode, | |
1930 | wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ | |
1931 | ||
1932 | dwb_pipe++; | |
1933 | ||
1934 | if (dwb_pipe >= MAX_DWB_PIPES) | |
1935 | return; | |
1936 | } | |
1937 | if (dwb_pipe >= MAX_DWB_PIPES) | |
1938 | return; | |
1939 | } | |
1940 | } | |
1941 | ||
0ba37b20 DL |
1942 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1943 | static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) | |
1944 | { | |
1945 | int i; | |
1946 | ||
1947 | /* Validate DSC config, dsc count validation is already done */ | |
1948 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1949 | struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; | |
1950 | struct dc_stream_state *stream = pipe_ctx->stream; | |
1951 | struct dsc_config dsc_cfg; | |
1952 | ||
1953 | /* Only need to validate top pipe */ | |
1954 | if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC) | |
1955 | continue; | |
1956 | ||
1957 | dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left | |
1958 | + stream->timing.h_border_right; | |
1959 | dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top | |
1960 | + stream->timing.v_border_bottom; | |
1961 | if (dc_res_get_odm_bottom_pipe(pipe_ctx)) | |
1962 | dsc_cfg.pic_width /= 2; | |
1963 | dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; | |
1964 | dsc_cfg.color_depth = stream->timing.display_color_depth; | |
1965 | dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; | |
1966 | ||
1967 | if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) | |
1968 | return false; | |
1969 | } | |
1970 | return true; | |
1971 | } | |
1972 | #endif | |
1973 | ||
254eb07c JA |
1974 | bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, |
1975 | bool fast_validate) | |
7ed4e635 | 1976 | { |
254eb07c JA |
1977 | bool out = false; |
1978 | ||
42351c66 JA |
1979 | BW_VAL_TRACE_SETUP(); |
1980 | ||
7ed4e635 HW |
1981 | int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit; |
1982 | int pipe_split_from[MAX_PIPES]; | |
1983 | bool odm_capable = context->bw_ctx.dml.ip.odm_capable; | |
1984 | bool force_split = false; | |
0ba37b20 DL |
1985 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
1986 | bool failed_non_odm_dsc = false; | |
1987 | #endif | |
7ed4e635 HW |
1988 | int split_threshold = dc->res_pool->pipe_count / 2; |
1989 | bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC; | |
1990 | display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); | |
00999d99 | 1991 | DC_LOGGER_INIT(dc->ctx->logger); |
7ed4e635 | 1992 | |
42351c66 JA |
1993 | BW_VAL_TRACE_COUNT(); |
1994 | ||
7ed4e635 HW |
1995 | ASSERT(pipes); |
1996 | if (!pipes) | |
1997 | return false; | |
1998 | ||
1999 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
2000 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
2001 | struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; | |
2002 | ||
2003 | if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) | |
2004 | continue; | |
2005 | ||
2006 | /* merge previously split pipe since mode support needs to make the decision */ | |
2007 | pipe->bottom_pipe = hsplit_pipe->bottom_pipe; | |
2008 | if (hsplit_pipe->bottom_pipe) | |
2009 | hsplit_pipe->bottom_pipe->top_pipe = pipe; | |
2010 | hsplit_pipe->plane_state = NULL; | |
2011 | hsplit_pipe->stream = NULL; | |
2012 | hsplit_pipe->top_pipe = NULL; | |
2013 | hsplit_pipe->bottom_pipe = NULL; | |
97bda032 HW |
2014 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
2015 | if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc) | |
c9ae6e16 | 2016 | release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc); |
97bda032 | 2017 | #endif |
7ed4e635 HW |
2018 | /* Clear plane_res and stream_res */ |
2019 | memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); | |
2020 | memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); | |
2021 | if (pipe->plane_state) | |
2022 | resource_build_scaling_params(pipe); | |
2023 | } | |
2024 | ||
ed07237c IB |
2025 | if (dc->res_pool->funcs->populate_dml_pipes) |
2026 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, | |
2027 | &context->res_ctx, pipes); | |
2028 | else | |
2029 | pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, | |
2030 | &context->res_ctx, pipes); | |
254eb07c JA |
2031 | |
2032 | if (!pipe_cnt) { | |
42351c66 | 2033 | BW_VAL_TRACE_SKIP(pass); |
254eb07c JA |
2034 | out = true; |
2035 | goto validate_out; | |
2036 | } | |
7ed4e635 HW |
2037 | |
2038 | context->bw_ctx.dml.ip.odm_capable = 0; | |
254eb07c | 2039 | |
7ed4e635 | 2040 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); |
254eb07c | 2041 | |
7ed4e635 HW |
2042 | context->bw_ctx.dml.ip.odm_capable = odm_capable; |
2043 | ||
0ba37b20 DL |
2044 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
2045 | /* 1 dsc per stream dsc validation */ | |
2046 | if (vlevel <= context->bw_ctx.dml.soc.num_states) | |
2047 | if (!dcn20_validate_dsc(dc, context)) { | |
2048 | failed_non_odm_dsc = true; | |
2049 | vlevel = context->bw_ctx.dml.soc.num_states + 1; | |
2050 | } | |
2051 | #endif | |
2052 | ||
7ed4e635 HW |
2053 | if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable) |
2054 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); | |
2055 | ||
2056 | if (vlevel > context->bw_ctx.dml.soc.num_states) | |
2057 | goto validate_fail; | |
2058 | ||
2059 | if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold) | |
2060 | || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold)) | |
2061 | context->commit_hints.full_update_needed = true; | |
2062 | ||
2063 | /*initialize pipe_just_split_from to invalid idx*/ | |
2064 | for (i = 0; i < MAX_PIPES; i++) | |
2065 | pipe_split_from[i] = -1; | |
2066 | ||
2067 | /* Single display only conditionals get set here */ | |
2068 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
2069 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
2070 | bool exit_loop = false; | |
2071 | ||
2072 | if (!pipe->stream || pipe->top_pipe) | |
2073 | continue; | |
2074 | ||
2075 | if (dc->debug.force_single_disp_pipe_split) { | |
2076 | if (!force_split) | |
2077 | force_split = true; | |
2078 | else { | |
2079 | force_split = false; | |
2080 | exit_loop = true; | |
2081 | } | |
2082 | } | |
2083 | if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) { | |
2084 | if (avoid_split) | |
2085 | avoid_split = false; | |
2086 | else { | |
2087 | avoid_split = true; | |
2088 | exit_loop = true; | |
2089 | } | |
2090 | } | |
2091 | if (exit_loop) | |
2092 | break; | |
2093 | } | |
2094 | ||
2095 | if (context->stream_count > split_threshold) | |
2096 | avoid_split = true; | |
2097 | ||
2098 | vlevel_unsplit = vlevel; | |
2099 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |
2100 | if (!context->res_ctx.pipe_ctx[i].stream) | |
2101 | continue; | |
2102 | for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++) | |
2103 | if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1) | |
2104 | break; | |
2105 | pipe_idx++; | |
2106 | } | |
2107 | ||
2108 | for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { | |
2109 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
2110 | struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; | |
2111 | bool need_split = true; | |
2112 | bool need_split3d; | |
2113 | ||
2114 | if (!pipe->stream || pipe_split_from[i] >= 0) | |
2115 | continue; | |
2116 | ||
2117 | pipe_idx++; | |
2118 | ||
2119 | if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { | |
2120 | force_split = true; | |
2121 | context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true; | |
2122 | context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true; | |
2123 | } | |
2124 | if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) | |
2125 | context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; | |
2126 | ||
2127 | if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { | |
2128 | hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); | |
2129 | ASSERT(hsplit_pipe); | |
2130 | if (!dcn20_split_stream_for_combine( | |
2131 | &context->res_ctx, dc->res_pool, | |
2132 | pipe, hsplit_pipe, | |
2133 | true)) | |
2134 | goto validate_fail; | |
2135 | pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; | |
2136 | dcn20_build_mapped_resource(dc, context, pipe->stream); | |
2137 | } | |
2138 | ||
2139 | if (!pipe->plane_state) | |
2140 | continue; | |
2141 | /* Skip 2nd half of already split pipe */ | |
2142 | if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) | |
2143 | continue; | |
2144 | ||
2145 | need_split3d = ((pipe->stream->view_format == | |
2146 | VIEW_3D_FORMAT_SIDE_BY_SIDE || | |
2147 | pipe->stream->view_format == | |
2148 | VIEW_3D_FORMAT_TOP_AND_BOTTOM) && | |
2149 | (pipe->stream->timing.timing_3d_format == | |
2150 | TIMING_3D_FORMAT_TOP_AND_BOTTOM || | |
2151 | pipe->stream->timing.timing_3d_format == | |
2152 | TIMING_3D_FORMAT_SIDE_BY_SIDE)); | |
2153 | ||
2154 | if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) { | |
2155 | need_split = false; | |
2156 | vlevel = vlevel_unsplit; | |
2157 | context->bw_ctx.dml.vba.maxMpcComb = 0; | |
2158 | } else | |
be67de35 | 2159 | need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2; |
7ed4e635 | 2160 | |
02ce5a79 DL |
2161 | /* We do not support mpo + odm at the moment */ |
2162 | if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state | |
2163 | && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) | |
2164 | goto validate_fail; | |
2165 | ||
7ed4e635 HW |
2166 | if (need_split3d || need_split || force_split) { |
2167 | if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { | |
2168 | /* pipe not split previously needs split */ | |
2169 | hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); | |
2170 | ASSERT(hsplit_pipe || force_split); | |
2171 | if (!hsplit_pipe) | |
2172 | continue; | |
2173 | ||
2174 | if (!dcn20_split_stream_for_combine( | |
2175 | &context->res_ctx, dc->res_pool, | |
2176 | pipe, hsplit_pipe, | |
2177 | context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])) | |
2178 | goto validate_fail; | |
2179 | pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; | |
2180 | } | |
02ce5a79 | 2181 | } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { |
7ed4e635 HW |
2182 | /* merge should already have been done */ |
2183 | ASSERT(0); | |
2184 | } | |
2185 | } | |
0ba37b20 DL |
2186 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
2187 | /* Actual dsc count per stream dsc validation*/ | |
2188 | if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) { | |
2189 | context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = | |
2190 | DML_FAIL_DSC_VALIDATION_FAILURE; | |
2191 | goto validate_fail; | |
2192 | } | |
2193 | #endif | |
7ed4e635 | 2194 | |
42351c66 JA |
2195 | BW_VAL_TRACE_END_VOLTAGE_LEVEL(); |
2196 | ||
254eb07c | 2197 | if (fast_validate) { |
42351c66 | 2198 | BW_VAL_TRACE_SKIP(fast); |
254eb07c JA |
2199 | out = true; |
2200 | goto validate_out; | |
2201 | } | |
2202 | ||
7ed4e635 HW |
2203 | for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { |
2204 | if (!context->res_ctx.pipe_ctx[i].stream) | |
2205 | continue; | |
2206 | ||
2207 | pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; | |
2208 | pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; | |
2209 | ||
2210 | if (pipe_split_from[i] < 0) { | |
2211 | pipes[pipe_cnt].clks_cfg.dppclk_mhz = | |
2212 | context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; | |
2213 | if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) | |
2214 | pipes[pipe_cnt].pipe.dest.odm_combine = | |
2215 | context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; | |
2216 | else | |
2217 | pipes[pipe_cnt].pipe.dest.odm_combine = 0; | |
2218 | pipe_idx++; | |
2219 | } else { | |
2220 | pipes[pipe_cnt].clks_cfg.dppclk_mhz = | |
2221 | context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; | |
2222 | if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) | |
2223 | pipes[pipe_cnt].pipe.dest.odm_combine = | |
2224 | context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]]; | |
2225 | else | |
2226 | pipes[pipe_cnt].pipe.dest.odm_combine = 0; | |
2227 | } | |
2228 | pipe_cnt++; | |
2229 | } | |
2230 | ||
ed07237c IB |
2231 | if (pipe_cnt != pipe_idx) { |
2232 | if (dc->res_pool->funcs->populate_dml_pipes) | |
2233 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, | |
2234 | &context->res_ctx, pipes); | |
2235 | else | |
2236 | pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, | |
2237 | &context->res_ctx, pipes); | |
2238 | } | |
7ed4e635 | 2239 | |
8e27a2d4 IB |
2240 | pipes[0].clks_cfg.voltage = vlevel; |
2241 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; | |
2242 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; | |
2243 | ||
7ed4e635 HW |
2244 | /* only pipe 0 is read for voltage and dcf/soc clocks */ |
2245 | if (vlevel < 1) { | |
2246 | pipes[0].clks_cfg.voltage = 1; | |
2247 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; | |
2248 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; | |
2249 | } | |
2250 | context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2251 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2252 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2253 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2254 | context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2255 | ||
2256 | if (vlevel < 2) { | |
2257 | pipes[0].clks_cfg.voltage = 2; | |
2258 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; | |
2259 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; | |
2260 | } | |
2261 | context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2262 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2263 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2264 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2265 | context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2266 | ||
2267 | if (vlevel < 3) { | |
2268 | pipes[0].clks_cfg.voltage = 3; | |
2269 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; | |
2270 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; | |
2271 | } | |
2272 | context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2273 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2274 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2275 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2276 | context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2277 | ||
2278 | pipes[0].clks_cfg.voltage = vlevel; | |
2279 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; | |
2280 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; | |
2281 | context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2282 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2283 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2284 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2285 | context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |
2286 | /* Writeback MCIF_WB arbitration parameters */ | |
2287 | dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); | |
2288 | ||
2289 | context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; | |
2290 | context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; | |
2291 | context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; | |
173932de | 2292 | context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; |
7ed4e635 HW |
2293 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; |
2294 | context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; | |
2295 | context->bw_ctx.bw.dcn.clk.p_state_change_support = | |
2296 | context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] | |
2297 | != dm_dram_clock_change_unsupported; | |
2298 | context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; | |
2299 | ||
42351c66 JA |
2300 | BW_VAL_TRACE_END_WATERMARKS(); |
2301 | ||
7ed4e635 HW |
2302 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { |
2303 | if (!context->res_ctx.pipe_ctx[i].stream) | |
2304 | continue; | |
2305 | pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx]; | |
2306 | pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx]; | |
2307 | pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx]; | |
2308 | pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx]; | |
2309 | if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) | |
2310 | context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | |
2311 | context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = | |
2312 | pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | |
97bda032 | 2313 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
b7d39c58 | 2314 | context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz = |
97bda032 HW |
2315 | context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000; |
2316 | #endif | |
7ed4e635 HW |
2317 | context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; |
2318 | pipe_idx++; | |
2319 | } | |
2320 | ||
2321 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |
2322 | bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; | |
2323 | ||
2324 | if (!context->res_ctx.pipe_ctx[i].stream) | |
2325 | continue; | |
2326 | ||
2327 | context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, | |
2328 | &context->res_ctx.pipe_ctx[i].dlg_regs, | |
2329 | &context->res_ctx.pipe_ctx[i].ttu_regs, | |
2330 | pipes, | |
2331 | pipe_cnt, | |
2332 | pipe_idx, | |
2333 | cstate_en, | |
2334 | context->bw_ctx.bw.dcn.clk.p_state_change_support); | |
254eb07c | 2335 | |
7ed4e635 HW |
2336 | context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, |
2337 | &context->res_ctx.pipe_ctx[i].rq_regs, | |
2338 | pipes[pipe_idx].pipe); | |
254eb07c | 2339 | |
7ed4e635 HW |
2340 | pipe_idx++; |
2341 | } | |
2342 | ||
254eb07c JA |
2343 | out = true; |
2344 | goto validate_out; | |
7ed4e635 HW |
2345 | |
2346 | validate_fail: | |
00999d99 DL |
2347 | DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", |
2348 | dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); | |
254eb07c | 2349 | |
42351c66 | 2350 | BW_VAL_TRACE_SKIP(fail); |
254eb07c JA |
2351 | out = false; |
2352 | ||
2353 | validate_out: | |
7ed4e635 | 2354 | kfree(pipes); |
254eb07c | 2355 | |
42351c66 JA |
2356 | BW_VAL_TRACE_FINISH(); |
2357 | ||
254eb07c | 2358 | return out; |
7ed4e635 HW |
2359 | } |
2360 | ||
7ed4e635 HW |
2361 | struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( |
2362 | struct dc_state *state, | |
2363 | const struct resource_pool *pool, | |
2364 | struct dc_stream_state *stream) | |
2365 | { | |
2366 | struct resource_context *res_ctx = &state->res_ctx; | |
2367 | struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); | |
2368 | struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); | |
2369 | ||
2370 | if (!head_pipe) | |
2371 | ASSERT(0); | |
2372 | ||
2373 | if (!idle_pipe) | |
2374 | return false; | |
2375 | ||
2376 | idle_pipe->stream = head_pipe->stream; | |
2377 | idle_pipe->stream_res.tg = head_pipe->stream_res.tg; | |
2378 | idle_pipe->stream_res.opp = head_pipe->stream_res.opp; | |
2379 | ||
2380 | idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; | |
2381 | idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; | |
2382 | idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; | |
2383 | idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; | |
2384 | ||
2385 | return idle_pipe; | |
2386 | } | |
2387 | ||
2388 | bool dcn20_get_dcc_compression_cap(const struct dc *dc, | |
2389 | const struct dc_dcc_surface_param *input, | |
2390 | struct dc_surface_dcc_cap *output) | |
2391 | { | |
2392 | return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( | |
2393 | dc->res_pool->hubbub, | |
2394 | input, | |
2395 | output); | |
2396 | } | |
2397 | ||
2398 | static void dcn20_destroy_resource_pool(struct resource_pool **pool) | |
2399 | { | |
2400 | struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); | |
2401 | ||
2402 | destruct(dcn20_pool); | |
2403 | kfree(dcn20_pool); | |
2404 | *pool = NULL; | |
2405 | } | |
2406 | ||
2407 | ||
2408 | static struct dc_cap_funcs cap_funcs = { | |
2409 | .get_dcc_compression_cap = dcn20_get_dcc_compression_cap | |
2410 | }; | |
2411 | ||
2412 | ||
2413 | enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state) | |
2414 | { | |
2415 | enum dc_status result = DC_OK; | |
2416 | ||
2417 | enum surface_pixel_format surf_pix_format = plane_state->format; | |
2418 | unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); | |
2419 | ||
2420 | enum swizzle_mode_values swizzle = DC_SW_LINEAR; | |
2421 | ||
2422 | if (bpp == 64) | |
2423 | swizzle = DC_SW_64KB_D; | |
2424 | else | |
2425 | swizzle = DC_SW_64KB_S; | |
2426 | ||
2427 | plane_state->tiling_info.gfx9.swizzle = swizzle; | |
2428 | return result; | |
2429 | } | |
2430 | ||
2431 | static struct resource_funcs dcn20_res_pool_funcs = { | |
2432 | .destroy = dcn20_destroy_resource_pool, | |
2433 | .link_enc_create = dcn20_link_encoder_create, | |
2434 | .validate_bandwidth = dcn20_validate_bandwidth, | |
7ed4e635 HW |
2435 | .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, |
2436 | .add_stream_to_ctx = dcn20_add_stream_to_ctx, | |
2437 | .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, | |
2438 | .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, | |
2439 | .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, | |
c9ae6e16 NC |
2440 | .set_mcif_arb_params = dcn20_set_mcif_arb_params, |
2441 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | |
2442 | .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, | |
2443 | .remove_dsc_from_stream_resource = dcn20_remove_dsc_from_stream_resource | |
2444 | #endif | |
7ed4e635 HW |
2445 | }; |
2446 | ||
bb21290f CL |
2447 | bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) |
2448 | { | |
2449 | int i; | |
2450 | uint32_t pipe_count = pool->res_cap->num_dwb; | |
2451 | ||
2452 | ASSERT(pipe_count > 0); | |
2453 | ||
2454 | for (i = 0; i < pipe_count; i++) { | |
2455 | struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), | |
2456 | GFP_KERNEL); | |
2457 | ||
2458 | if (!dwbc20) { | |
2459 | dm_error("DC: failed to create dwbc20!\n"); | |
2460 | return false; | |
2461 | } | |
2462 | dcn20_dwbc_construct(dwbc20, ctx, | |
2463 | &dwbc20_regs[i], | |
2464 | &dwbc20_shift, | |
2465 | &dwbc20_mask, | |
2466 | i); | |
2467 | pool->dwbc[i] = &dwbc20->base; | |
2468 | } | |
2469 | return true; | |
2470 | } | |
2471 | ||
2472 | bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) | |
2473 | { | |
2474 | int i; | |
2475 | uint32_t pipe_count = pool->res_cap->num_dwb; | |
2476 | ||
2477 | ASSERT(pipe_count > 0); | |
2478 | ||
2479 | for (i = 0; i < pipe_count; i++) { | |
2480 | struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), | |
2481 | GFP_KERNEL); | |
2482 | ||
2483 | if (!mcif_wb20) { | |
2484 | dm_error("DC: failed to create mcif_wb20!\n"); | |
2485 | return false; | |
2486 | } | |
2487 | ||
2488 | dcn20_mmhubbub_construct(mcif_wb20, ctx, | |
2489 | &mcif_wb20_regs[i], | |
2490 | &mcif_wb20_shift, | |
2491 | &mcif_wb20_mask, | |
2492 | i); | |
2493 | ||
2494 | pool->mcif_wb[i] = &mcif_wb20->base; | |
2495 | } | |
2496 | return true; | |
2497 | } | |
2498 | ||
7ed4e635 HW |
2499 | struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) |
2500 | { | |
2501 | struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); | |
2502 | ||
2503 | if (!pp_smu) | |
2504 | return pp_smu; | |
2505 | ||
2506 | dm_pp_get_funcs(ctx, pp_smu); | |
2507 | ||
2508 | if (pp_smu->ctx.ver != PP_SMU_VER_NV) | |
2509 | pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); | |
2510 | ||
2511 | return pp_smu; | |
2512 | } | |
2513 | ||
2514 | void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) | |
2515 | { | |
2516 | if (pp_smu && *pp_smu) { | |
2517 | kfree(*pp_smu); | |
2518 | *pp_smu = NULL; | |
2519 | } | |
2520 | } | |
2521 | ||
2522 | static void cap_soc_clocks( | |
2523 | struct _vcs_dpi_soc_bounding_box_st *bb, | |
2524 | struct pp_smu_nv_clock_table max_clocks) | |
2525 | { | |
2526 | int i; | |
2527 | ||
2528 | // First pass - cap all clocks higher than the reported max | |
2529 | for (i = 0; i < bb->num_states; i++) { | |
2530 | if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) | |
2531 | && max_clocks.dcfClockInKhz != 0) | |
2532 | bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); | |
2533 | ||
2534 | if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) | |
2535 | && max_clocks.uClockInKhz != 0) | |
2536 | bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; | |
2537 | ||
2538 | if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) | |
2539 | && max_clocks.fabricClockInKhz != 0) | |
2540 | bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); | |
2541 | ||
2542 | if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) | |
2543 | && max_clocks.displayClockInKhz != 0) | |
2544 | bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); | |
2545 | ||
2546 | if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) | |
2547 | && max_clocks.dppClockInKhz != 0) | |
2548 | bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); | |
2549 | ||
2550 | if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) | |
2551 | && max_clocks.phyClockInKhz != 0) | |
2552 | bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); | |
2553 | ||
2554 | if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) | |
2555 | && max_clocks.socClockInKhz != 0) | |
2556 | bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); | |
2557 | ||
2558 | if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) | |
2559 | && max_clocks.dscClockInKhz != 0) | |
2560 | bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); | |
2561 | } | |
2562 | ||
2563 | // Second pass - remove all duplicate clock states | |
2564 | for (i = bb->num_states - 1; i > 1; i--) { | |
2565 | bool duplicate = true; | |
2566 | ||
2567 | if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) | |
2568 | duplicate = false; | |
2569 | if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) | |
2570 | duplicate = false; | |
2571 | if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) | |
2572 | duplicate = false; | |
2573 | if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) | |
2574 | duplicate = false; | |
2575 | if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) | |
2576 | duplicate = false; | |
2577 | if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) | |
2578 | duplicate = false; | |
2579 | if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) | |
2580 | duplicate = false; | |
2581 | if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) | |
2582 | duplicate = false; | |
2583 | ||
2584 | if (duplicate) | |
2585 | bb->num_states--; | |
2586 | } | |
2587 | } | |
2588 | ||
2589 | static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, | |
2590 | struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) | |
2591 | { | |
2592 | struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0}; | |
f18bc4e5 | 2593 | int i; |
7ed4e635 | 2594 | int num_calculated_states = 0; |
f18bc4e5 | 2595 | int min_dcfclk = 0; |
7ed4e635 HW |
2596 | |
2597 | if (num_states == 0) | |
2598 | return; | |
2599 | ||
f18bc4e5 JL |
2600 | if (dc->bb_overrides.min_dcfclk_mhz > 0) |
2601 | min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; | |
2602 | ||
7ed4e635 | 2603 | for (i = 0; i < num_states; i++) { |
f18bc4e5 JL |
2604 | int min_fclk_required_by_uclk; |
2605 | calculated_states[i].state = i; | |
2606 | calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; | |
7ed4e635 | 2607 | |
f18bc4e5 | 2608 | min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1008 / 1000000; |
7ed4e635 | 2609 | |
f18bc4e5 JL |
2610 | calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? |
2611 | min_dcfclk : min_fclk_required_by_uclk; | |
7ed4e635 | 2612 | |
f18bc4e5 JL |
2613 | calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? |
2614 | max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; | |
7ed4e635 | 2615 | |
f18bc4e5 JL |
2616 | calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? |
2617 | max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; | |
7ed4e635 | 2618 | |
f18bc4e5 JL |
2619 | calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; |
2620 | calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; | |
2621 | calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); | |
7ed4e635 | 2622 | |
f18bc4e5 | 2623 | calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; |
7ed4e635 | 2624 | |
f18bc4e5 | 2625 | num_calculated_states++; |
7ed4e635 HW |
2626 | } |
2627 | ||
7ed4e635 HW |
2628 | memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); |
2629 | bb->num_states = num_calculated_states; | |
f18bc4e5 JL |
2630 | |
2631 | // Duplicate the last state, DML always an extra state identical to max state to work | |
2632 | memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); | |
2633 | bb->clock_limits[num_calculated_states].state = bb->num_states; | |
7ed4e635 HW |
2634 | } |
2635 | ||
2636 | static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) | |
2637 | { | |
2638 | kernel_fpu_begin(); | |
2639 | if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns | |
2640 | && dc->bb_overrides.sr_exit_time_ns) { | |
2641 | bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; | |
2642 | } | |
2643 | ||
2644 | if ((int)(bb->sr_enter_plus_exit_time_us * 1000) | |
2645 | != dc->bb_overrides.sr_enter_plus_exit_time_ns | |
2646 | && dc->bb_overrides.sr_enter_plus_exit_time_ns) { | |
2647 | bb->sr_enter_plus_exit_time_us = | |
2648 | dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; | |
2649 | } | |
2650 | ||
2651 | if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns | |
2652 | && dc->bb_overrides.urgent_latency_ns) { | |
2653 | bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; | |
2654 | } | |
2655 | ||
2656 | if ((int)(bb->dram_clock_change_latency_us * 1000) | |
2657 | != dc->bb_overrides.dram_clock_change_latency_ns | |
2658 | && dc->bb_overrides.dram_clock_change_latency_ns) { | |
2659 | bb->dram_clock_change_latency_us = | |
2660 | dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; | |
2661 | } | |
2662 | kernel_fpu_end(); | |
2663 | } | |
2664 | ||
2665 | #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) | |
2666 | #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) | |
2667 | ||
2668 | static bool init_soc_bounding_box(struct dc *dc, | |
2669 | struct dcn20_resource_pool *pool) | |
2670 | { | |
2671 | const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; | |
2672 | DC_LOGGER_INIT(dc->ctx->logger); | |
2673 | ||
2674 | if (!bb && !SOC_BOUNDING_BOX_VALID) { | |
2675 | DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); | |
2676 | return false; | |
2677 | } | |
2678 | ||
2679 | if (bb && !SOC_BOUNDING_BOX_VALID) { | |
2680 | int i; | |
2681 | ||
2682 | dcn2_0_soc.sr_exit_time_us = | |
2683 | fixed16_to_double_to_cpu(bb->sr_exit_time_us); | |
2684 | dcn2_0_soc.sr_enter_plus_exit_time_us = | |
2685 | fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); | |
2686 | dcn2_0_soc.urgent_latency_us = | |
2687 | fixed16_to_double_to_cpu(bb->urgent_latency_us); | |
2688 | dcn2_0_soc.urgent_latency_pixel_data_only_us = | |
2689 | fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); | |
2690 | dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = | |
2691 | fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); | |
2692 | dcn2_0_soc.urgent_latency_vm_data_only_us = | |
2693 | fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); | |
2694 | dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = | |
2695 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); | |
2696 | dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = | |
2697 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); | |
2698 | dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = | |
2699 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); | |
2700 | dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = | |
2701 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); | |
2702 | dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = | |
2703 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); | |
2704 | dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = | |
2705 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); | |
2706 | dcn2_0_soc.max_avg_sdp_bw_use_normal_percent = | |
2707 | fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); | |
2708 | dcn2_0_soc.max_avg_dram_bw_use_normal_percent = | |
2709 | fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); | |
2710 | dcn2_0_soc.writeback_latency_us = | |
2711 | fixed16_to_double_to_cpu(bb->writeback_latency_us); | |
2712 | dcn2_0_soc.ideal_dram_bw_after_urgent_percent = | |
2713 | fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); | |
2714 | dcn2_0_soc.max_request_size_bytes = | |
2715 | le32_to_cpu(bb->max_request_size_bytes); | |
2716 | dcn2_0_soc.dram_channel_width_bytes = | |
2717 | le32_to_cpu(bb->dram_channel_width_bytes); | |
2718 | dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes = | |
2719 | le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); | |
2720 | dcn2_0_soc.dcn_downspread_percent = | |
2721 | fixed16_to_double_to_cpu(bb->dcn_downspread_percent); | |
2722 | dcn2_0_soc.downspread_percent = | |
2723 | fixed16_to_double_to_cpu(bb->downspread_percent); | |
2724 | dcn2_0_soc.dram_page_open_time_ns = | |
2725 | fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); | |
2726 | dcn2_0_soc.dram_rw_turnaround_time_ns = | |
2727 | fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); | |
2728 | dcn2_0_soc.dram_return_buffer_per_channel_bytes = | |
2729 | le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); | |
2730 | dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles = | |
2731 | le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); | |
2732 | dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes = | |
2733 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); | |
2734 | dcn2_0_soc.channel_interleave_bytes = | |
2735 | le32_to_cpu(bb->channel_interleave_bytes); | |
2736 | dcn2_0_soc.num_banks = | |
2737 | le32_to_cpu(bb->num_banks); | |
2738 | dcn2_0_soc.num_chans = | |
2739 | le32_to_cpu(bb->num_chans); | |
2740 | dcn2_0_soc.vmm_page_size_bytes = | |
2741 | le32_to_cpu(bb->vmm_page_size_bytes); | |
2742 | dcn2_0_soc.dram_clock_change_latency_us = | |
2743 | fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); | |
2744 | dcn2_0_soc.writeback_dram_clock_change_latency_us = | |
2745 | fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); | |
2746 | dcn2_0_soc.return_bus_width_bytes = | |
2747 | le32_to_cpu(bb->return_bus_width_bytes); | |
2748 | dcn2_0_soc.dispclk_dppclk_vco_speed_mhz = | |
2749 | le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); | |
2750 | dcn2_0_soc.xfc_bus_transport_time_us = | |
2751 | le32_to_cpu(bb->xfc_bus_transport_time_us); | |
2752 | dcn2_0_soc.xfc_xbuf_latency_tolerance_us = | |
2753 | le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); | |
2754 | dcn2_0_soc.use_urgent_burst_bw = | |
2755 | le32_to_cpu(bb->use_urgent_burst_bw); | |
2756 | dcn2_0_soc.num_states = | |
2757 | le32_to_cpu(bb->num_states); | |
2758 | ||
2759 | for (i = 0; i < dcn2_0_soc.num_states; i++) { | |
2760 | dcn2_0_soc.clock_limits[i].state = | |
2761 | le32_to_cpu(bb->clock_limits[i].state); | |
2762 | dcn2_0_soc.clock_limits[i].dcfclk_mhz = | |
2763 | fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); | |
2764 | dcn2_0_soc.clock_limits[i].fabricclk_mhz = | |
2765 | fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); | |
2766 | dcn2_0_soc.clock_limits[i].dispclk_mhz = | |
2767 | fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); | |
2768 | dcn2_0_soc.clock_limits[i].dppclk_mhz = | |
2769 | fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); | |
2770 | dcn2_0_soc.clock_limits[i].phyclk_mhz = | |
2771 | fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); | |
2772 | dcn2_0_soc.clock_limits[i].socclk_mhz = | |
2773 | fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); | |
2774 | dcn2_0_soc.clock_limits[i].dscclk_mhz = | |
2775 | fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); | |
2776 | dcn2_0_soc.clock_limits[i].dram_speed_mts = | |
2777 | fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); | |
2778 | } | |
2779 | } | |
2780 | ||
2781 | if (pool->base.pp_smu) { | |
2782 | struct pp_smu_nv_clock_table max_clocks = {0}; | |
2783 | unsigned int uclk_states[8] = {0}; | |
2784 | unsigned int num_states = 0; | |
2785 | enum pp_smu_status status; | |
2786 | bool clock_limits_available = false; | |
2787 | bool uclk_states_available = false; | |
2788 | ||
2789 | if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { | |
2790 | status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) | |
2791 | (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); | |
2792 | ||
2793 | uclk_states_available = (status == PP_SMU_RESULT_OK); | |
2794 | } | |
2795 | ||
2796 | if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { | |
2797 | status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) | |
2798 | (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); | |
c2ad17c3 AW |
2799 | /* SMU cannot set DCF clock to anything equal to or higher than SOC clock |
2800 | */ | |
2801 | if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) | |
2802 | max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; | |
7ed4e635 HW |
2803 | clock_limits_available = (status == PP_SMU_RESULT_OK); |
2804 | } | |
2805 | ||
c2ad17c3 | 2806 | if (clock_limits_available && uclk_states_available && num_states) |
7ed4e635 HW |
2807 | update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states); |
2808 | else if (clock_limits_available) | |
2809 | cap_soc_clocks(&dcn2_0_soc, max_clocks); | |
2810 | } | |
2811 | ||
2812 | dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator; | |
2813 | dcn2_0_ip.max_num_dpp = pool->base.pipe_count; | |
2814 | patch_bounding_box(dc, &dcn2_0_soc); | |
2815 | ||
2816 | return true; | |
2817 | } | |
2818 | ||
2819 | static bool construct( | |
2820 | uint8_t num_virtual_links, | |
2821 | struct dc *dc, | |
2822 | struct dcn20_resource_pool *pool) | |
2823 | { | |
2824 | int i; | |
2825 | struct dc_context *ctx = dc->ctx; | |
2826 | struct irq_service_init_data init_data; | |
2827 | ||
2828 | ctx->dc_bios->regs = &bios_regs; | |
2829 | ||
2830 | pool->base.res_cap = &res_cap_nv10; | |
2831 | pool->base.funcs = &dcn20_res_pool_funcs; | |
2832 | ||
2833 | /************************************************* | |
2834 | * Resource + asic cap harcoding * | |
2835 | *************************************************/ | |
2836 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; | |
2837 | ||
2838 | pool->base.pipe_count = 6; | |
2839 | pool->base.mpcc_count = 6; | |
2840 | dc->caps.max_downscale_ratio = 200; | |
2841 | dc->caps.i2c_speed_in_khz = 100; | |
2842 | dc->caps.max_cursor_size = 256; | |
2843 | dc->caps.dmdata_alloc_size = 2048; | |
2844 | ||
2845 | dc->caps.max_slave_planes = 1; | |
2846 | dc->caps.post_blend_color_processing = true; | |
2847 | dc->caps.force_dp_tps4_for_cp2520 = true; | |
2848 | dc->caps.hw_3d_lut = true; | |
2849 | ||
2850 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) | |
2851 | dc->debug = debug_defaults_drv; | |
2852 | else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { | |
2853 | pool->base.pipe_count = 4; | |
2854 | ||
2855 | pool->base.mpcc_count = pool->base.pipe_count; | |
2856 | dc->debug = debug_defaults_diags; | |
2857 | } else | |
2858 | dc->debug = debug_defaults_diags; | |
2859 | //dcn2.0x | |
2860 | dc->work_arounds.dedcn20_305_wa = true; | |
2861 | ||
2862 | // Init the vm_helper | |
2863 | if (dc->vm_helper) | |
2864 | init_vm_helper(dc->vm_helper, 16, pool->base.pipe_count); | |
2865 | ||
2866 | /************************************************* | |
2867 | * Create resources * | |
2868 | *************************************************/ | |
2869 | ||
2870 | pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = | |
2871 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2872 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |
2873 | &clk_src_regs[0], false); | |
2874 | pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = | |
2875 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2876 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |
2877 | &clk_src_regs[1], false); | |
2878 | pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = | |
2879 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2880 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |
2881 | &clk_src_regs[2], false); | |
2882 | pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = | |
2883 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2884 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |
2885 | &clk_src_regs[3], false); | |
2886 | pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = | |
2887 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2888 | CLOCK_SOURCE_COMBO_PHY_PLL4, | |
2889 | &clk_src_regs[4], false); | |
2890 | pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = | |
2891 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2892 | CLOCK_SOURCE_COMBO_PHY_PLL5, | |
2893 | &clk_src_regs[5], false); | |
2894 | pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; | |
2895 | /* todo: not reuse phy_pll registers */ | |
2896 | pool->base.dp_clock_source = | |
2897 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2898 | CLOCK_SOURCE_ID_DP_DTO, | |
2899 | &clk_src_regs[0], true); | |
2900 | ||
2901 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
2902 | if (pool->base.clock_sources[i] == NULL) { | |
2903 | dm_error("DC: failed to create clock sources!\n"); | |
2904 | BREAK_TO_DEBUGGER(); | |
2905 | goto create_fail; | |
2906 | } | |
2907 | } | |
2908 | ||
2909 | pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); | |
2910 | if (pool->base.dccg == NULL) { | |
2911 | dm_error("DC: failed to create dccg!\n"); | |
2912 | BREAK_TO_DEBUGGER(); | |
2913 | goto create_fail; | |
2914 | } | |
2915 | ||
2916 | pool->base.dmcu = dcn20_dmcu_create(ctx, | |
2917 | &dmcu_regs, | |
2918 | &dmcu_shift, | |
2919 | &dmcu_mask); | |
2920 | if (pool->base.dmcu == NULL) { | |
2921 | dm_error("DC: failed to create dmcu!\n"); | |
2922 | BREAK_TO_DEBUGGER(); | |
2923 | goto create_fail; | |
2924 | } | |
2925 | ||
d7c29549 | 2926 | pool->base.abm = dce_abm_create(ctx, |
7ed4e635 HW |
2927 | &abm_regs, |
2928 | &abm_shift, | |
2929 | &abm_mask); | |
2930 | if (pool->base.abm == NULL) { | |
2931 | dm_error("DC: failed to create abm!\n"); | |
2932 | BREAK_TO_DEBUGGER(); | |
2933 | goto create_fail; | |
d7c29549 | 2934 | } |
7ed4e635 HW |
2935 | |
2936 | pool->base.pp_smu = dcn20_pp_smu_create(ctx); | |
2937 | ||
2938 | ||
2939 | if (!init_soc_bounding_box(dc, pool)) { | |
2940 | dm_error("DC: failed to initialize soc bounding box!\n"); | |
2941 | BREAK_TO_DEBUGGER(); | |
2942 | goto create_fail; | |
2943 | } | |
2944 | ||
2945 | dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10); | |
2946 | ||
2947 | if (!dc->debug.disable_pplib_wm_range) { | |
2948 | struct pp_smu_wm_range_sets ranges = {0}; | |
2949 | int i = 0; | |
2950 | ||
2951 | ranges.num_reader_wm_sets = 0; | |
2952 | ||
2953 | if (dcn2_0_soc.num_states == 1) { | |
2954 | ranges.reader_wm_sets[0].wm_inst = i; | |
2955 | ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2956 | ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2957 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2958 | ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2959 | ||
2960 | ranges.num_reader_wm_sets = 1; | |
2961 | } else if (dcn2_0_soc.num_states > 1) { | |
2962 | for (i = 0; i < 4 && i < dcn2_0_soc.num_states - 1; i++) { | |
2963 | ranges.reader_wm_sets[i].wm_inst = i; | |
2964 | ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2965 | ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2966 | ranges.reader_wm_sets[i].min_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16; | |
2967 | ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i + 1].dram_speed_mts / 16; | |
2968 | ||
2969 | ranges.num_reader_wm_sets = i + 1; | |
2970 | } | |
2971 | } | |
2972 | ||
2973 | ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2974 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2975 | ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2976 | ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2977 | ||
2978 | ranges.num_writer_wm_sets = 1; | |
2979 | ||
2980 | ranges.writer_wm_sets[0].wm_inst = 0; | |
2981 | ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2982 | ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2983 | ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2984 | ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2985 | ||
2986 | /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ | |
2987 | if (pool->base.pp_smu->nv_funcs.set_wm_ranges) | |
2988 | pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); | |
2989 | } | |
2990 | ||
2991 | init_data.ctx = dc->ctx; | |
2992 | pool->base.irqs = dal_irq_service_dcn20_create(&init_data); | |
2993 | if (!pool->base.irqs) | |
2994 | goto create_fail; | |
2995 | ||
2996 | /* mem input -> ipp -> dpp -> opp -> TG */ | |
2997 | for (i = 0; i < pool->base.pipe_count; i++) { | |
2998 | pool->base.hubps[i] = dcn20_hubp_create(ctx, i); | |
2999 | if (pool->base.hubps[i] == NULL) { | |
3000 | BREAK_TO_DEBUGGER(); | |
3001 | dm_error( | |
3002 | "DC: failed to create memory input!\n"); | |
3003 | goto create_fail; | |
3004 | } | |
3005 | ||
3006 | pool->base.ipps[i] = dcn20_ipp_create(ctx, i); | |
3007 | if (pool->base.ipps[i] == NULL) { | |
3008 | BREAK_TO_DEBUGGER(); | |
3009 | dm_error( | |
3010 | "DC: failed to create input pixel processor!\n"); | |
3011 | goto create_fail; | |
3012 | } | |
3013 | ||
3014 | pool->base.dpps[i] = dcn20_dpp_create(ctx, i); | |
3015 | if (pool->base.dpps[i] == NULL) { | |
3016 | BREAK_TO_DEBUGGER(); | |
3017 | dm_error( | |
3018 | "DC: failed to create dpps!\n"); | |
3019 | goto create_fail; | |
3020 | } | |
3021 | } | |
3022 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |
3023 | pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); | |
3024 | if (pool->base.engines[i] == NULL) { | |
3025 | BREAK_TO_DEBUGGER(); | |
3026 | dm_error( | |
3027 | "DC:failed to create aux engine!!\n"); | |
3028 | goto create_fail; | |
3029 | } | |
3030 | pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); | |
3031 | if (pool->base.hw_i2cs[i] == NULL) { | |
3032 | BREAK_TO_DEBUGGER(); | |
3033 | dm_error( | |
3034 | "DC:failed to create hw i2c!!\n"); | |
3035 | goto create_fail; | |
3036 | } | |
3037 | pool->base.sw_i2cs[i] = NULL; | |
3038 | } | |
3039 | ||
3040 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |
3041 | pool->base.opps[i] = dcn20_opp_create(ctx, i); | |
3042 | if (pool->base.opps[i] == NULL) { | |
3043 | BREAK_TO_DEBUGGER(); | |
3044 | dm_error( | |
3045 | "DC: failed to create output pixel processor!\n"); | |
3046 | goto create_fail; | |
3047 | } | |
3048 | } | |
3049 | ||
3050 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
3051 | pool->base.timing_generators[i] = dcn20_timing_generator_create( | |
3052 | ctx, i); | |
3053 | if (pool->base.timing_generators[i] == NULL) { | |
3054 | BREAK_TO_DEBUGGER(); | |
3055 | dm_error("DC: failed to create tg!\n"); | |
3056 | goto create_fail; | |
3057 | } | |
3058 | } | |
3059 | ||
3060 | pool->base.timing_generator_count = i; | |
3061 | ||
3062 | pool->base.mpc = dcn20_mpc_create(ctx); | |
3063 | if (pool->base.mpc == NULL) { | |
3064 | BREAK_TO_DEBUGGER(); | |
3065 | dm_error("DC: failed to create mpc!\n"); | |
3066 | goto create_fail; | |
3067 | } | |
3068 | ||
3069 | pool->base.hubbub = dcn20_hubbub_create(ctx); | |
3070 | if (pool->base.hubbub == NULL) { | |
3071 | BREAK_TO_DEBUGGER(); | |
3072 | dm_error("DC: failed to create hubbub!\n"); | |
3073 | goto create_fail; | |
3074 | } | |
3075 | ||
97bda032 HW |
3076 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
3077 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | |
3078 | pool->base.dscs[i] = dcn20_dsc_create(ctx, i); | |
3079 | if (pool->base.dscs[i] == NULL) { | |
3080 | BREAK_TO_DEBUGGER(); | |
3081 | dm_error("DC: failed to create display stream compressor %d!\n", i); | |
3082 | goto create_fail; | |
3083 | } | |
3084 | } | |
3085 | #endif | |
7ed4e635 | 3086 | |
bb21290f CL |
3087 | if (!dcn20_dwbc_create(ctx, &pool->base)) { |
3088 | BREAK_TO_DEBUGGER(); | |
3089 | dm_error("DC: failed to create dwbc!\n"); | |
3090 | goto create_fail; | |
3091 | } | |
3092 | if (!dcn20_mmhubbub_create(ctx, &pool->base)) { | |
3093 | BREAK_TO_DEBUGGER(); | |
3094 | dm_error("DC: failed to create mcif_wb!\n"); | |
3095 | goto create_fail; | |
3096 | } | |
3097 | ||
7ed4e635 HW |
3098 | if (!resource_construct(num_virtual_links, dc, &pool->base, |
3099 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? | |
3100 | &res_create_funcs : &res_create_maximus_funcs))) | |
3101 | goto create_fail; | |
3102 | ||
3103 | dcn20_hw_sequencer_construct(dc); | |
3104 | ||
3105 | dc->caps.max_planes = pool->base.pipe_count; | |
3106 | ||
3107 | for (i = 0; i < dc->caps.max_planes; ++i) | |
3108 | dc->caps.planes[i] = plane_cap; | |
3109 | ||
3110 | dc->cap_funcs = cap_funcs; | |
3111 | ||
3112 | return true; | |
3113 | ||
3114 | create_fail: | |
3115 | ||
3116 | destruct(pool); | |
3117 | ||
3118 | return false; | |
3119 | } | |
3120 | ||
3121 | struct resource_pool *dcn20_create_resource_pool( | |
3122 | const struct dc_init_data *init_data, | |
3123 | struct dc *dc) | |
3124 | { | |
3125 | struct dcn20_resource_pool *pool = | |
3126 | kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); | |
3127 | ||
3128 | if (!pool) | |
3129 | return NULL; | |
3130 | ||
3131 | if (construct(init_data->num_virtual_links, dc, pool)) | |
3132 | return &pool->base; | |
3133 | ||
3134 | BREAK_TO_DEBUGGER(); | |
3135 | kfree(pool); | |
3136 | return NULL; | |
3137 | } |