[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / i2caux / i2caux.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"

/*
 * Pre-requisites: headers required by header of this unit
 */
#include "include/i2caux_interface.h"
#include "dc_bios_types.h"

/*
 * Header of this unit
 */

#include "i2caux.h"

/*
 * Post-requisites: headers required by this unit
 */

#include "engine.h"
#include "i2c_engine.h"
#include "aux_engine.h"

/*
 * This unit
 */

#include "dce80/i2caux_dce80.h"

#include "dce100/i2caux_dce100.h"

#include "dce110/i2caux_dce110.h"

#include "dce112/i2caux_dce112.h"

#include "dce120/i2caux_dce120.h"

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/i2caux_dcn10.h"
#endif

#include "diagnostics/i2caux_diag.h"

/*
 * @brief
 * Plain API, available publicly
 */

struct i2caux *dal_i2caux_create(
	struct dc_context *ctx)
{
	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
		return dal_i2caux_diag_fpga_create(ctx);
	}

	switch (ctx->dce_version) {
	case DCE_VERSION_8_0:
		return dal_i2caux_dce80_create(ctx);
	case DCE_VERSION_11_2:
		return dal_i2caux_dce112_create(ctx);
	case DCE_VERSION_11_0:
		return dal_i2caux_dce110_create(ctx);
	case DCE_VERSION_10_0:
		return dal_i2caux_dce100_create(ctx);
	case DCE_VERSION_12_0:
		return dal_i2caux_dce120_create(ctx);
	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
	case DCN_VERSION_1_0:
		return dal_i2caux_dcn10_create(ctx);
	#endif
	default:
		BREAK_TO_DEBUGGER();
		return NULL;
	}
}

bool dal_i2caux_submit_i2c_command(
	struct i2caux *i2caux,
	struct ddc *ddc,
	struct i2c_command *cmd)
{
	struct i2c_engine *engine;
	uint8_t index_of_payload = 0;
	bool result;

	if (!ddc) {
		BREAK_TO_DEBUGGER();
		return false;
	}

	if (!cmd) {
		BREAK_TO_DEBUGGER();
		return false;
	}

	/*
	 * default will be SW, however there is a feature flag in adapter
	 * service that determines whether SW i2c_engine will be available or
	 * not, if sw i2c is not available we will fallback to hw. This feature
	 * flag is set to not creating sw i2c engine for every dce except dce80
	 * currently
	 */
	switch (cmd->engine) {
	case I2C_COMMAND_ENGINE_DEFAULT:
	case I2C_COMMAND_ENGINE_SW:
		/* try to acquire SW engine first,
		 * acquire HW engine if SW engine not available */
		engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);

		if (!engine)
			engine = i2caux->funcs->acquire_i2c_hw_engine(
				i2caux, ddc);
	break;
	case I2C_COMMAND_ENGINE_HW:
	default:
		/* try to acquire HW engine first,
		 * acquire SW engine if HW engine not available */
		engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);

		if (!engine)
			engine = i2caux->funcs->acquire_i2c_sw_engine(
				i2caux, ddc);
	}

	if (!engine)
		return false;

	engine->funcs->set_speed(engine, cmd->speed);

	result = true;

	while (index_of_payload < cmd->number_of_payloads) {
		bool mot = (index_of_payload != cmd->number_of_payloads - 1);

		struct i2c_payload *payload = cmd->payloads + index_of_payload;

		struct i2caux_transaction_request request = { 0 };

		request.operation = payload->write ?
			I2CAUX_TRANSACTION_WRITE :
			I2CAUX_TRANSACTION_READ;

		request.payload.address_space =
			I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
		request.payload.address = (payload->address << 1) |
			!payload->write;
		request.payload.length = payload->length;
		request.payload.data = payload->data;

		if (!engine->base.funcs->submit_request(
			&engine->base, &request, mot)) {
			result = false;
			break;
		}

		++index_of_payload;
	}

	i2caux->funcs->release_engine(i2caux, &engine->base);

	return result;
}

bool dal_i2caux_submit_aux_command(
	struct i2caux *i2caux,
	struct ddc *ddc,
	struct aux_command *cmd)
{
	struct aux_engine *engine;
	uint8_t index_of_payload = 0;
	bool result;
	bool mot;

	if (!ddc) {
		BREAK_TO_DEBUGGER();
		return false;
	}

	if (!cmd) {
		BREAK_TO_DEBUGGER();
		return false;
	}

	engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);

	if (!engine)
		return false;

	engine->delay = cmd->defer_delay;
	engine->max_defer_write_retry = cmd->max_defer_write_retry;

	result = true;

	while (index_of_payload < cmd->number_of_payloads) {
		struct aux_payload *payload = cmd->payloads + index_of_payload;
		struct i2caux_transaction_request request = { 0 };

		if (cmd->mot == I2C_MOT_UNDEF)
			mot = (index_of_payload != cmd->number_of_payloads - 1);
		else
			mot = (cmd->mot == I2C_MOT_TRUE);

		request.operation = payload->write ?
			I2CAUX_TRANSACTION_WRITE :
			I2CAUX_TRANSACTION_READ;

		if (payload->i2c_over_aux) {
			request.payload.address_space =
				I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;

			request.payload.address = (payload->address << 1) |
				!payload->write;
		} else {
			request.payload.address_space =
				I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD;

			request.payload.address = payload->address;
		}

		request.payload.length = payload->length;
		request.payload.data = payload->data;

		if (!engine->base.funcs->submit_request(
			&engine->base, &request, mot)) {
			result = false;
			break;
		}

		++index_of_payload;
	}

	i2caux->funcs->release_engine(i2caux, &engine->base);

	return result;
}

static bool get_hw_supported_ddc_line(
	struct ddc *ddc,
	enum gpio_ddc_line *line)
{
	enum gpio_ddc_line line_found;

	if (!ddc) {
		BREAK_TO_DEBUGGER();
		return false;
	}

	if (!ddc->hw_info.hw_supported)
		return false;

	line_found = dal_ddc_get_line(ddc);

	if (line_found >= GPIO_DDC_LINE_COUNT)
		return false;

	*line = line_found;

	return true;
}

void dal_i2caux_configure_aux(
	struct i2caux *i2caux,
	struct ddc *ddc,
	union aux_config cfg)
{
	struct aux_engine *engine =
		i2caux->funcs->acquire_aux_engine(i2caux, ddc);

	if (!engine)
		return;

	engine->funcs->configure(engine, cfg);

	i2caux->funcs->release_engine(i2caux, &engine->base);
}

void dal_i2caux_destroy(
	struct i2caux **i2caux)
{
	if (!i2caux || !*i2caux) {
		BREAK_TO_DEBUGGER();
		return;
	}

	(*i2caux)->funcs->destroy(i2caux);

	*i2caux = NULL;
}

/*
 * @brief
 * An utility function used by 'struct i2caux' and its descendants
 */

uint32_t dal_i2caux_get_reference_clock(
		struct dc_bios *bios)
{
	struct firmware_info info = { { 0 } };

	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
		return 0;

	return info.pll_info.crystal_frequency;
}

/*
 * @brief
 * i2caux
 */

enum {
	/* following are expressed in KHz */
	DEFAULT_I2C_SW_SPEED = 50,
	DEFAULT_I2C_HW_SPEED = 50,

	/* This is the timeout as defined in DP 1.2a,
	 * 2.3.4 "Detailed uPacket TX AUX CH State Description". */
	AUX_TIMEOUT_PERIOD = 400,

	/* Ideally, the SW timeout should be just above 550usec
	 * which is programmed in HW.
	 * But the SW timeout of 600usec is not reliable,
	 * because on some systems, delay_in_microseconds()
	 * returns faster than it should.
	 * EPR #379763: by trial-and-error on different systems,
	 * 700usec is the minimum reliable SW timeout for polling
	 * the AUX_SW_STATUS.AUX_SW_DONE bit.
	 * This timeout expires *only* when there is
	 * AUX Error or AUX Timeout conditions - not during normal operation.
	 * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
	 * at most within ~240usec. That means,
	 * increasing this timeout will not affect normal operation,
	 * and we'll timeout after
	 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
	 * This timeout is especially important for
	 * resume from S3 and CTS. */
	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
};

struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
	struct i2caux *i2caux,
	struct ddc *ddc)
{
	enum gpio_ddc_line line;
	struct i2c_engine *engine = NULL;

	if (get_hw_supported_ddc_line(ddc, &line))
		engine = i2caux->i2c_sw_engines[line];

	if (!engine)
		engine = i2caux->i2c_generic_sw_engine;

	if (!engine)
		return NULL;

	if (!engine->base.funcs->acquire(&engine->base, ddc))
		return NULL;

	return engine;
}

struct aux_engine *dal_i2caux_acquire_aux_engine(
	struct i2caux *i2caux,
	struct ddc *ddc)
{
	enum gpio_ddc_line line;
	struct aux_engine *engine;

	if (!get_hw_supported_ddc_line(ddc, &line))
		return NULL;

	engine = i2caux->aux_engines[line];

	if (!engine)
		return NULL;

	if (!engine->base.funcs->acquire(&engine->base, ddc))
		return NULL;

	return engine;
}

void dal_i2caux_release_engine(
	struct i2caux *i2caux,
	struct engine *engine)
{
	engine->funcs->release_engine(engine);

	dal_ddc_close(engine->ddc);

	engine->ddc = NULL;
}

bool dal_i2caux_construct(
	struct i2caux *i2caux,
	struct dc_context *ctx)
{
	uint32_t i = 0;

	i2caux->ctx = ctx;
	do {
		i2caux->i2c_sw_engines[i] = NULL;
		i2caux->i2c_hw_engines[i] = NULL;
		i2caux->aux_engines[i] = NULL;

		++i;
	} while (i < GPIO_DDC_LINE_COUNT);

	i2caux->i2c_generic_sw_engine = NULL;
	i2caux->i2c_generic_hw_engine = NULL;

	i2caux->aux_timeout_period =
		SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD;

	i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED;
	i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED;

	return true;
}

void dal_i2caux_destruct(
	struct i2caux *i2caux)
{
	uint32_t i = 0;

	if (i2caux->i2c_generic_hw_engine)
		i2caux->i2c_generic_hw_engine->funcs->destroy(
			&i2caux->i2c_generic_hw_engine);

	if (i2caux->i2c_generic_sw_engine)
		i2caux->i2c_generic_sw_engine->funcs->destroy(
			&i2caux->i2c_generic_sw_engine);

	do {
		if (i2caux->aux_engines[i])
			i2caux->aux_engines[i]->funcs->destroy(
				&i2caux->aux_engines[i]);

		if (i2caux->i2c_hw_engines[i])
			i2caux->i2c_hw_engines[i]->funcs->destroy(
				&i2caux->i2c_hw_engines[i]);

		if (i2caux->i2c_sw_engines[i])
			i2caux->i2c_sw_engines[i]->funcs->destroy(
				&i2caux->i2c_sw_engines[i]);

		++i;
	} while (i < GPIO_DDC_LINE_COUNT);
}
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dm_services.h"
	27
	28	/*
	29	* Pre-requisites: headers required by header of this unit
	30	*/
	31	#include "include/i2caux_interface.h"
	32	#include "dc_bios_types.h"
	33
	34	/*
	35	* Header of this unit
	36	*/
	37
	38	#include "i2caux.h"
	39
	40	/*
	41	* Post-requisites: headers required by this unit
	42	*/
	43
	44	#include "engine.h"
	45	#include "i2c_engine.h"
	46	#include "aux_engine.h"
	47
	48	/*
	49	* This unit
	50	*/
	51
	52	#include "dce80/i2caux_dce80.h"
	53
	54	#include "dce100/i2caux_dce100.h"
	55
	56	#include "dce110/i2caux_dce110.h"
	57
	58	#include "dce112/i2caux_dce112.h"
	59
2c8ad2d5	60	#include "dce120/i2caux_dce120.h"
2c8ad2d5	61
ff5ef992 AD	62	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
	63	#include "dcn10/i2caux_dcn10.h"
	64	#endif
	65
4562236b HW	66	#include "diagnostics/i2caux_diag.h"
	67
	68	/*
	69	* @brief
	70	* Plain API, available publicly
	71	*/
	72
	73	struct i2caux *dal_i2caux_create(
	74	struct dc_context *ctx)
	75	{
	76	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
	77	return dal_i2caux_diag_fpga_create(ctx);
	78	}
	79
	80	switch (ctx->dce_version) {
	81	case DCE_VERSION_8_0:
	82	return dal_i2caux_dce80_create(ctx);
	83	case DCE_VERSION_11_2:
	84	return dal_i2caux_dce112_create(ctx);
	85	case DCE_VERSION_11_0:
	86	return dal_i2caux_dce110_create(ctx);
	87	case DCE_VERSION_10_0:
	88	return dal_i2caux_dce100_create(ctx);
2c8ad2d5 AD	89	case DCE_VERSION_12_0:
2c8ad2d5 AD	90	return dal_i2caux_dce120_create(ctx);
ff5ef992 AD	91	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
	92	case DCN_VERSION_1_0:
	93	return dal_i2caux_dcn10_create(ctx);
	94	#endif
4562236b HW	95	default:
	96	BREAK_TO_DEBUGGER();
	97	return NULL;
	98	}
	99	}
	100
	101	bool dal_i2caux_submit_i2c_command(
	102	struct i2caux *i2caux,
	103	struct ddc *ddc,
	104	struct i2c_command *cmd)
	105	{
	106	struct i2c_engine *engine;
	107	uint8_t index_of_payload = 0;
	108	bool result;
	109
	110	if (!ddc) {
	111	BREAK_TO_DEBUGGER();
	112	return false;
	113	}
	114
	115	if (!cmd) {
	116	BREAK_TO_DEBUGGER();
	117	return false;
	118	}
	119
	120	/*
	121	* default will be SW, however there is a feature flag in adapter
	122	* service that determines whether SW i2c_engine will be available or
	123	* not, if sw i2c is not available we will fallback to hw. This feature
	124	* flag is set to not creating sw i2c engine for every dce except dce80
	125	* currently
	126	*/
	127	switch (cmd->engine) {
	128	case I2C_COMMAND_ENGINE_DEFAULT:
	129	case I2C_COMMAND_ENGINE_SW:
	130	/* try to acquire SW engine first,
	131	* acquire HW engine if SW engine not available */
	132	engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);
	133
	134	if (!engine)
	135	engine = i2caux->funcs->acquire_i2c_hw_engine(
	136	i2caux, ddc);
	137	break;
	138	case I2C_COMMAND_ENGINE_HW:
	139	default:
	140	/* try to acquire HW engine first,
	141	* acquire SW engine if HW engine not available */
	142	engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);
	143
	144	if (!engine)
	145	engine = i2caux->funcs->acquire_i2c_sw_engine(
	146	i2caux, ddc);
	147	}
	148
	149	if (!engine)
	150	return false;
	151
	152	engine->funcs->set_speed(engine, cmd->speed);
	153
	154	result = true;
	155
	156	while (index_of_payload < cmd->number_of_payloads) {
	157	bool mot = (index_of_payload != cmd->number_of_payloads - 1);
	158
159	struct i2c_payload *payload = cmd->payloads + index_of_payload;
160
161	struct i2caux_transaction_request request = { 0 };
162
163	request.operation = payload->write ?
164	I2CAUX_TRANSACTION_WRITE :
165	I2CAUX_TRANSACTION_READ;
166
167	request.payload.address_space =
168	I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
169	request.payload.address = (payload->address << 1) \|
170	!payload->write;
171	request.payload.length = payload->length;
172	request.payload.data = payload->data;
173
174	if (!engine->base.funcs->submit_request(
175	&engine->base, &request, mot)) {
176	result = false;
177	break;
178	}
179
180	++index_of_payload;
181	}
182
183	i2caux->funcs->release_engine(i2caux, &engine->base);
184
185	return result;
186	}
187
188	bool dal_i2caux_submit_aux_command(
189	struct i2caux *i2caux,
190	struct ddc *ddc,
191	struct aux_command *cmd)
192	{
193	struct aux_engine *engine;
194	uint8_t index_of_payload = 0;
195	bool result;
7c7f5b15	196	bool mot;
4562236b HW	197
	198	if (!ddc) {
	199	BREAK_TO_DEBUGGER();
	200	return false;
	201	}
	202
	203	if (!cmd) {
	204	BREAK_TO_DEBUGGER();
	205	return false;
	206	}
	207
	208	engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);
	209
	210	if (!engine)
	211	return false;
	212
	213	engine->delay = cmd->defer_delay;
	214	engine->max_defer_write_retry = cmd->max_defer_write_retry;
	215
	216	result = true;
	217
	218	while (index_of_payload < cmd->number_of_payloads) {
4562236b	219	struct aux_payload *payload = cmd->payloads + index_of_payload;
4562236b HW	220	struct i2caux_transaction_request request = { 0 };
4562236b HW	221
7c7f5b15 AG	222	if (cmd->mot == I2C_MOT_UNDEF)
	223	mot = (index_of_payload != cmd->number_of_payloads - 1);
	224	else
	225	mot = (cmd->mot == I2C_MOT_TRUE);
	226
4562236b HW	227	request.operation = payload->write ?
	228	I2CAUX_TRANSACTION_WRITE :
	229	I2CAUX_TRANSACTION_READ;
	230
	231	if (payload->i2c_over_aux) {
	232	request.payload.address_space =
	233	I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
	234
	235	request.payload.address = (payload->address << 1) \|
	236	!payload->write;
	237	} else {
	238	request.payload.address_space =
	239	I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD;
	240
	241	request.payload.address = payload->address;
	242	}
	243
	244	request.payload.length = payload->length;
	245	request.payload.data = payload->data;
	246
	247	if (!engine->base.funcs->submit_request(
	248	&engine->base, &request, mot)) {
	249	result = false;
	250	break;
	251	}
	252
	253	++index_of_payload;
	254	}
	255
	256	i2caux->funcs->release_engine(i2caux, &engine->base);
	257
	258	return result;
	259	}
	260
	261	static bool get_hw_supported_ddc_line(
	262	struct ddc *ddc,
	263	enum gpio_ddc_line *line)
	264	{
	265	enum gpio_ddc_line line_found;
	266
	267	if (!ddc) {
	268	BREAK_TO_DEBUGGER();
	269	return false;
	270	}
	271
	272	if (!ddc->hw_info.hw_supported)
	273	return false;
	274
	275	line_found = dal_ddc_get_line(ddc);
	276
	277	if (line_found >= GPIO_DDC_LINE_COUNT)
	278	return false;
	279
	280	*line = line_found;
	281
	282	return true;
	283	}
	284
	285	void dal_i2caux_configure_aux(
	286	struct i2caux *i2caux,
	287	struct ddc *ddc,
	288	union aux_config cfg)
	289	{
	290	struct aux_engine *engine =
291	i2caux->funcs->acquire_aux_engine(i2caux, ddc);
292
293	if (!engine)
294	return;
295
296	engine->funcs->configure(engine, cfg);
297
298	i2caux->funcs->release_engine(i2caux, &engine->base);
299	}
300
301	void dal_i2caux_destroy(
302	struct i2caux **i2caux)
303	{
304	if (!i2caux \|\| !*i2caux) {
305	BREAK_TO_DEBUGGER();
306	return;
307	}
308
309	(*i2caux)->funcs->destroy(i2caux);
310
311	*i2caux = NULL;
312	}
313
314	/*
315	* @brief
316	* An utility function used by 'struct i2caux' and its descendants
317	*/
318
319	uint32_t dal_i2caux_get_reference_clock(
320	struct dc_bios *bios)
321	{
322	struct firmware_info info = { { 0 } };
323
324	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
325	return 0;
326
327	return info.pll_info.crystal_frequency;
328	}
329
330	/*
331	* @brief
332	* i2caux
333	*/
334
335	enum {
336	/* following are expressed in KHz */
337	DEFAULT_I2C_SW_SPEED = 50,
338	DEFAULT_I2C_HW_SPEED = 50,
339
340	/* This is the timeout as defined in DP 1.2a,
341	* 2.3.4 "Detailed uPacket TX AUX CH State Description". */
342	AUX_TIMEOUT_PERIOD = 400,
343
344	/* Ideally, the SW timeout should be just above 550usec
345	* which is programmed in HW.
346	* But the SW timeout of 600usec is not reliable,
347	* because on some systems, delay_in_microseconds()
348	* returns faster than it should.
349	* EPR #379763: by trial-and-error on different systems,
350	* 700usec is the minimum reliable SW timeout for polling
351	* the AUX_SW_STATUS.AUX_SW_DONE bit.
352	* This timeout expires only when there is
353	* AUX Error or AUX Timeout conditions - not during normal operation.
354	* During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
355	* at most within ~240usec. That means,
356	* increasing this timeout will not affect normal operation,
357	* and we'll timeout after
358	* SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
359	* This timeout is especially important for
360	* resume from S3 and CTS. */
361	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
362	};
363
364	struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
365	struct i2caux *i2caux,
366	struct ddc *ddc)
367	{
368	enum gpio_ddc_line line;
369	struct i2c_engine *engine = NULL;
370
371	if (get_hw_supported_ddc_line(ddc, &line))
372	engine = i2caux->i2c_sw_engines[line];
373
374	if (!engine)
375	engine = i2caux->i2c_generic_sw_engine;
376
377	if (!engine)
378	return NULL;
379
380	if (!engine->base.funcs->acquire(&engine->base, ddc))
381	return NULL;
382
383	return engine;
384	}
385
386	struct aux_engine *dal_i2caux_acquire_aux_engine(
387	struct i2caux *i2caux,
388	struct ddc *ddc)
389	{
390	enum gpio_ddc_line line;
391	struct aux_engine *engine;
392
393	if (!get_hw_supported_ddc_line(ddc, &line))
394	return NULL;
395
396	engine = i2caux->aux_engines[line];
397
398	if (!engine)
399	return NULL;
400
401	if (!engine->base.funcs->acquire(&engine->base, ddc))
402	return NULL;
403
404	return engine;
405	}
406
407	void dal_i2caux_release_engine(
408	struct i2caux *i2caux,
409	struct engine *engine)
410	{
411	engine->funcs->release_engine(engine);
412
413	dal_ddc_close(engine->ddc);
414
415	engine->ddc = NULL;
416	}
417
418	bool dal_i2caux_construct(
419	struct i2caux *i2caux,
420	struct dc_context *ctx)
421	{
422	uint32_t i = 0;
423
424	i2caux->ctx = ctx;
425	do {
426	i2caux->i2c_sw_engines[i] = NULL;
427	i2caux->i2c_hw_engines[i] = NULL;
428	i2caux->aux_engines[i] = NULL;
429
430	++i;
431	} while (i < GPIO_DDC_LINE_COUNT);
432
433	i2caux->i2c_generic_sw_engine = NULL;
434	i2caux->i2c_generic_hw_engine = NULL;
435
436	i2caux->aux_timeout_period =
437	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD;
438
439	i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED;
440	i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED;
441
442	return true;
443	}
444
445	void dal_i2caux_destruct(
446	struct i2caux *i2caux)
447	{
448	uint32_t i = 0;
449
450	if (i2caux->i2c_generic_hw_engine)
451	i2caux->i2c_generic_hw_engine->funcs->destroy(
452	&i2caux->i2c_generic_hw_engine);
453
454	if (i2caux->i2c_generic_sw_engine)
455	i2caux->i2c_generic_sw_engine->funcs->destroy(
456	&i2caux->i2c_generic_sw_engine);
457
458	do {
459	if (i2caux->aux_engines[i])
460	i2caux->aux_engines[i]->funcs->destroy(
461	&i2caux->aux_engines[i]);
462
463	if (i2caux->i2c_hw_engines[i])
464	i2caux->i2c_hw_engines[i]->funcs->destroy(
465	&i2caux->i2c_hw_engines[i]);
466
467	if (i2caux->i2c_sw_engines[i])
468	i2caux->i2c_sw_engines[i]->funcs->destroy(
469	&i2caux->i2c_sw_engines[i]);
470
471	++i;
472	} while (i < GPIO_DDC_LINE_COUNT);
473	}
474