]>
Commit | Line | Data |
---|---|---|
4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef _CORE_TYPES_H_ | |
27 | #define _CORE_TYPES_H_ | |
28 | ||
29 | #include "dc.h" | |
5e141de4 | 30 | #include "dce_calcs.h" |
ff5ef992 | 31 | #include "dcn_calcs.h" |
4562236b HW |
32 | #include "ddc_service_types.h" |
33 | #include "dc_bios_types.h" | |
ff5ef992 AD |
34 | #include "mem_input.h" |
35 | #include "mpc.h" | |
4562236b | 36 | |
4562236b HW |
37 | #define MAX_CLOCK_SOURCES 7 |
38 | ||
3be5262e | 39 | void enable_surface_flip_reporting(struct dc_plane_state *plane_state, |
4562236b HW |
40 | uint32_t controller_id); |
41 | ||
4562236b HW |
42 | #include "grph_object_id.h" |
43 | #include "link_encoder.h" | |
44 | #include "stream_encoder.h" | |
45 | #include "clock_source.h" | |
46 | #include "audio.h" | |
47 | #include "hw_sequencer_types.h" | |
4562236b | 48 | |
4562236b | 49 | |
4562236b | 50 | /************ link *****************/ |
4562236b HW |
51 | struct link_init_data { |
52 | const struct core_dc *dc; | |
53 | struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ | |
54 | uint32_t connector_index; /* this will be mapped to the HPD pins */ | |
55 | uint32_t link_index; /* this is mapped to DAL display_index | |
56 | TODO: remove it when DC is complete. */ | |
57 | }; | |
58 | ||
d0778ebf HW |
59 | struct dc_link *link_create(const struct link_init_data *init_params); |
60 | void link_destroy(struct dc_link **link); | |
4562236b HW |
61 | |
62 | enum dc_status dc_link_validate_mode_timing( | |
0971c40e | 63 | const struct dc_stream_state *stream, |
d0778ebf | 64 | struct dc_link *link, |
4562236b HW |
65 | const struct dc_crtc_timing *timing); |
66 | ||
d0778ebf | 67 | void core_link_resume(struct dc_link *link); |
4562236b HW |
68 | |
69 | void core_link_enable_stream(struct pipe_ctx *pipe_ctx); | |
70 | ||
71 | void core_link_disable_stream(struct pipe_ctx *pipe_ctx); | |
72 | ||
15e17335 | 73 | void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); |
4562236b | 74 | /********** DAL Core*********************/ |
e11b86ad | 75 | #include "display_clock.h" |
4562236b HW |
76 | #include "transform.h" |
77 | ||
78 | struct resource_pool; | |
79 | struct validate_context; | |
80 | struct resource_context; | |
81 | ||
82 | struct resource_funcs { | |
83 | void (*destroy)(struct resource_pool **pool); | |
84 | struct link_encoder *(*link_enc_create)( | |
85 | const struct encoder_init_data *init); | |
86 | enum dc_status (*validate_with_context)( | |
87 | const struct core_dc *dc, | |
88 | const struct dc_validation_set set[], | |
89 | int set_count, | |
430ef426 DL |
90 | struct validate_context *context, |
91 | struct validate_context *old_context); | |
4562236b HW |
92 | |
93 | enum dc_status (*validate_guaranteed)( | |
94 | const struct core_dc *dc, | |
0971c40e | 95 | struct dc_stream_state *stream, |
4562236b HW |
96 | struct validate_context *context); |
97 | ||
45209ef7 | 98 | bool (*validate_bandwidth)( |
4562236b HW |
99 | const struct core_dc *dc, |
100 | struct validate_context *context); | |
101 | ||
102 | struct pipe_ctx *(*acquire_idle_pipe_for_layer)( | |
745cc746 | 103 | struct validate_context *context, |
a2b8659d | 104 | const struct resource_pool *pool, |
0971c40e | 105 | struct dc_stream_state *stream); |
c9614aeb | 106 | enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); |
4562236b HW |
107 | }; |
108 | ||
109 | struct audio_support{ | |
110 | bool dp_audio; | |
111 | bool hdmi_audio_on_dongle; | |
112 | bool hdmi_audio_native; | |
113 | }; | |
114 | ||
f0e3db90 HW |
115 | #define NO_UNDERLAY_PIPE -1 |
116 | ||
4562236b HW |
117 | struct resource_pool { |
118 | struct mem_input *mis[MAX_PIPES]; | |
119 | struct input_pixel_processor *ipps[MAX_PIPES]; | |
120 | struct transform *transforms[MAX_PIPES]; | |
121 | struct output_pixel_processor *opps[MAX_PIPES]; | |
122 | struct timing_generator *timing_generators[MAX_PIPES]; | |
123 | struct stream_encoder *stream_enc[MAX_PIPES * 2]; | |
f0558542 | 124 | #ifdef CONFIG_DRM_AMD_DC_DCN1_0 |
cc408d72 | 125 | struct mpc *mpc; |
f0558542 | 126 | #endif |
4562236b HW |
127 | |
128 | unsigned int pipe_count; | |
129 | unsigned int underlay_pipe_index; | |
130 | unsigned int stream_enc_count; | |
5ac3d3c9 | 131 | unsigned int ref_clock_inKhz; |
4562236b HW |
132 | |
133 | /* | |
134 | * reserved clock source for DP | |
135 | */ | |
136 | struct clock_source *dp_clock_source; | |
137 | ||
138 | struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; | |
139 | unsigned int clk_src_count; | |
140 | ||
141 | struct audio *audios[MAX_PIPES]; | |
142 | unsigned int audio_count; | |
143 | struct audio_support audio_support; | |
144 | ||
145 | struct display_clock *display_clock; | |
146 | struct irq_service *irqs; | |
147 | ||
5e7773a2 AK |
148 | struct abm *abm; |
149 | struct dmcu *dmcu; | |
150 | ||
4562236b HW |
151 | const struct resource_funcs *funcs; |
152 | const struct resource_caps *res_cap; | |
153 | }; | |
154 | ||
79b06f0c HW |
155 | struct stream_resource { |
156 | int stub; | |
157 | }; | |
158 | ||
159 | struct plane_resource { | |
160 | int stub; | |
161 | }; | |
162 | ||
4562236b | 163 | struct pipe_ctx { |
3be5262e | 164 | struct dc_plane_state *plane_state; |
0971c40e | 165 | struct dc_stream_state *stream; |
4562236b | 166 | |
79b06f0c HW |
167 | struct plane_resource plane_res; |
168 | struct stream_resource stream_res; | |
169 | ||
4562236b HW |
170 | struct mem_input *mi; |
171 | struct input_pixel_processor *ipp; | |
172 | struct transform *xfm; | |
173 | struct output_pixel_processor *opp; | |
174 | struct timing_generator *tg; | |
175 | ||
176 | struct scaler_data scl_data; | |
177 | ||
178 | struct stream_encoder *stream_enc; | |
179 | struct display_clock *dis_clk; | |
180 | struct clock_source *clock_source; | |
181 | ||
182 | struct audio *audio; | |
183 | ||
184 | struct pixel_clk_params pix_clk_params; | |
185 | struct pll_settings pll_settings; | |
186 | ||
187 | /*fmt*/ | |
188 | struct encoder_info_frame encoder_info_frame; | |
189 | ||
190 | uint8_t pipe_idx; | |
191 | ||
192 | struct pipe_ctx *top_pipe; | |
193 | struct pipe_ctx *bottom_pipe; | |
f0558542 | 194 | |
ff5ef992 | 195 | #ifdef CONFIG_DRM_AMD_DC_DCN1_0 |
ff5ef992 AD |
196 | struct _vcs_dpi_display_dlg_regs_st dlg_regs; |
197 | struct _vcs_dpi_display_ttu_regs_st ttu_regs; | |
198 | struct _vcs_dpi_display_rq_regs_st rq_regs; | |
199 | struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; | |
200 | #endif | |
4562236b HW |
201 | }; |
202 | ||
203 | struct resource_context { | |
4562236b HW |
204 | struct pipe_ctx pipe_ctx[MAX_PIPES]; |
205 | bool is_stream_enc_acquired[MAX_PIPES * 2]; | |
206 | bool is_audio_acquired[MAX_PIPES]; | |
207 | uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; | |
208 | uint8_t dp_clock_source_ref_count; | |
9037d802 DL |
209 | }; |
210 | ||
211 | struct dce_bw_output { | |
212 | bool cpuc_state_change_enable; | |
213 | bool cpup_state_change_enable; | |
214 | bool stutter_mode_enable; | |
215 | bool nbp_state_change_enable; | |
216 | bool all_displays_in_sync; | |
217 | struct dce_watermarks urgent_wm_ns[MAX_PIPES]; | |
218 | struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; | |
219 | struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; | |
220 | int sclk_khz; | |
221 | int sclk_deep_sleep_khz; | |
222 | int yclk_khz; | |
223 | int dispclk_khz; | |
224 | int blackout_recovery_time_us; | |
225 | }; | |
226 | ||
227 | #ifdef CONFIG_DRM_AMD_DC_DCN1_0 | |
228 | struct dcn_bw_clocks { | |
229 | int dispclk_khz; | |
230 | bool dppclk_div; | |
231 | int dcfclk_khz; | |
232 | int dcfclk_deep_sleep_khz; | |
233 | int fclk_khz; | |
234 | int dram_ccm_us; | |
235 | int min_active_dram_ccm_us; | |
236 | }; | |
237 | ||
238 | struct dcn_bw_output { | |
239 | struct dcn_bw_clocks cur_clk; | |
240 | struct dcn_bw_clocks calc_clk; | |
241 | struct dcn_watermark_set watermarks; | |
242 | }; | |
243 | #endif | |
244 | ||
245 | union bw_context { | |
246 | #ifdef CONFIG_DRM_AMD_DC_DCN1_0 | |
247 | struct dcn_bw_output dcn; | |
248 | #endif | |
249 | struct dce_bw_output dce; | |
250 | }; | |
4562236b HW |
251 | |
252 | struct validate_context { | |
0971c40e | 253 | struct dc_stream_state *streams[MAX_PIPES]; |
ab2541b6 AC |
254 | struct dc_stream_status stream_status[MAX_PIPES]; |
255 | uint8_t stream_count; | |
4562236b HW |
256 | |
257 | struct resource_context res_ctx; | |
258 | ||
259 | /* The output from BW and WM calculations. */ | |
9037d802 DL |
260 | union bw_context bw; |
261 | ||
5ea81b91 | 262 | /* Note: these are big structures, do *not* put on stack! */ |
4562236b | 263 | struct dm_pp_display_configuration pp_display_cfg; |
ff5ef992 | 264 | #ifdef CONFIG_DRM_AMD_DC_DCN1_0 |
ff5ef992 AD |
265 | struct dcn_bw_internal_vars dcn_bw_vars; |
266 | #endif | |
8a76708e AG |
267 | |
268 | int ref_count; | |
4562236b HW |
269 | }; |
270 | ||
271 | #endif /* _CORE_TYPES_H_ */ |