[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / inc / core_types.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef _CORE_TYPES_H_
#define _CORE_TYPES_H_

#include "dc.h"
#include "dce_calcs.h"
#include "dcn_calcs.h"
#include "ddc_service_types.h"
#include "dc_bios_types.h"
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "mem_input.h"
#include "mpc.h"
#endif

struct core_stream;

#define MAX_PIPES 6
#define MAX_CLOCK_SOURCES 7


/********* core_surface **********/
#define DC_SURFACE_TO_CORE(dc_surface) \
	container_of(dc_surface, struct core_surface, public)

#define DC_GAMMA_TO_CORE(dc_gamma) \
	container_of(dc_gamma, struct core_gamma, public)

#define DC_TRANSFER_FUNC_TO_CORE(dc_transfer_func) \
	container_of(dc_transfer_func, struct core_transfer_func, public)

struct core_surface {
	struct dc_surface public;
	struct dc_surface_status status;
	struct dc_context *ctx;
};

struct core_gamma {
	struct dc_gamma public;
	struct dc_context *ctx;
};

struct core_transfer_func {
	struct dc_transfer_func public;
	struct dc_context *ctx;
};

void enable_surface_flip_reporting(struct dc_surface *dc_surface,
		uint32_t controller_id);

/********* core_stream ************/
#include "grph_object_id.h"
#include "link_encoder.h"
#include "stream_encoder.h"
#include "clock_source.h"
#include "audio.h"
#include "hw_sequencer_types.h"
#include "opp.h"

#define DC_STREAM_TO_CORE(dc_stream) container_of( \
	dc_stream, struct core_stream, public)

struct core_stream {
	struct dc_stream public;

	/* field internal to DC */
	struct dc_context *ctx;
	const struct core_sink *sink;

	/* used by DCP and FMT */
	struct bit_depth_reduction_params bit_depth_params;
	struct clamping_and_pixel_encoding_params clamping;

	int phy_pix_clk;
	enum signal_type signal;

	struct dc_stream_status status;
};

/************ core_sink *****************/

#define DC_SINK_TO_CORE(dc_sink) \
	container_of(dc_sink, struct core_sink, public)

struct core_sink {
	/** The public, read-only (for DM) area of sink. **/
	struct dc_sink public;
	/** End-of-public area. **/

	/** The 'protected' area - read/write access, for use only inside DC **/
	/* not used for now */
	struct core_link *link;
	struct dc_context *ctx;
};

/************ link *****************/
#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public)

struct link_init_data {
	const struct core_dc *dc;
	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
	uint32_t connector_index; /* this will be mapped to the HPD pins */
	uint32_t link_index; /* this is mapped to DAL display_index
				TODO: remove it when DC is complete. */
};

/* DP MST stream allocation (payload bandwidth number) */
struct link_mst_stream_allocation {
	/* DIG front */
	const struct stream_encoder *stream_enc;
	/* associate DRM payload table with DC stream encoder */
	uint8_t vcp_id;
	/* number of slots required for the DP stream in transport packet */
	uint8_t slot_count;
};

/* DP MST stream allocation table */
struct link_mst_stream_allocation_table {
	/* number of DP video streams */
	int stream_count;
	/* array of stream allocations */
	struct link_mst_stream_allocation
	stream_allocations[MAX_CONTROLLER_NUM];
};

struct core_link {
	struct dc_link public;
	const struct core_dc *dc;

	struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/

	struct link_encoder *link_enc;
	struct graphics_object_id link_id;
	union ddi_channel_mapping ddi_channel_mapping;
	struct connector_device_tag_info device_tag;
	struct dpcd_caps dpcd_caps;
	unsigned int dpcd_sink_count;

	enum edp_revision edp_revision;
	bool psr_enabled;

	/* MST record stream using this link */
	struct link_flags {
		bool dp_keep_receiver_powered;
	} wa_flags;
	struct link_mst_stream_allocation_table mst_stream_alloc_table;

	struct dc_link_status link_status;
};

#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)

struct core_link *link_create(const struct link_init_data *init_params);
void link_destroy(struct core_link **link);

enum dc_status dc_link_validate_mode_timing(
		const struct core_stream *stream,
		struct core_link *link,
		const struct dc_crtc_timing *timing);

void core_link_resume(struct core_link *link);

void core_link_enable_stream(struct pipe_ctx *pipe_ctx);

void core_link_disable_stream(struct pipe_ctx *pipe_ctx);

/********** DAL Core*********************/
#include "display_clock.h"
#include "transform.h"

struct resource_pool;
struct validate_context;
struct resource_context;

struct resource_funcs {
	void (*destroy)(struct resource_pool **pool);
	struct link_encoder *(*link_enc_create)(
			const struct encoder_init_data *init);
	enum dc_status (*validate_with_context)(
					const struct core_dc *dc,
					const struct dc_validation_set set[],
					int set_count,
					struct validate_context *context);

	enum dc_status (*validate_guaranteed)(
					const struct core_dc *dc,
					const struct dc_stream *stream,
					struct validate_context *context);

	bool (*validate_bandwidth)(
					const struct core_dc *dc,
					struct validate_context *context);

	struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
			struct validate_context *context,
			const struct resource_pool *pool,
			struct core_stream *stream);
};

struct audio_support{
	bool dp_audio;
	bool hdmi_audio_on_dongle;
	bool hdmi_audio_native;
};

#define NO_UNDERLAY_PIPE -1

struct resource_pool {
	struct mem_input *mis[MAX_PIPES];
	struct input_pixel_processor *ipps[MAX_PIPES];
	struct transform *transforms[MAX_PIPES];
	struct output_pixel_processor *opps[MAX_PIPES];
	struct timing_generator *timing_generators[MAX_PIPES];
	struct stream_encoder *stream_enc[MAX_PIPES * 2];

	unsigned int pipe_count;
	unsigned int underlay_pipe_index;
	unsigned int stream_enc_count;
	unsigned int ref_clock_inKhz;

	/*
	 * reserved clock source for DP
	 */
	struct clock_source *dp_clock_source;

	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
	unsigned int clk_src_count;

	struct audio *audios[MAX_PIPES];
	unsigned int audio_count;
	struct audio_support audio_support;

	struct display_clock *display_clock;
	struct irq_service *irqs;

	struct abm *abm;
	struct dmcu *dmcu;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
	struct mpc *mpc;
#endif

	const struct resource_funcs *funcs;
	const struct resource_caps *res_cap;
};

struct pipe_ctx {
	struct core_surface *surface;
	struct core_stream *stream;

	struct mem_input *mi;
	struct input_pixel_processor *ipp;
	struct transform *xfm;
	struct output_pixel_processor *opp;
	struct timing_generator *tg;

	struct scaler_data scl_data;

	struct stream_encoder *stream_enc;
	struct display_clock *dis_clk;
	struct clock_source *clock_source;

	struct audio *audio;

	struct pixel_clk_params pix_clk_params;
	struct pll_settings pll_settings;

	/*fmt*/
	struct encoder_info_frame encoder_info_frame;

	uint8_t pipe_idx;

	struct pipe_ctx *top_pipe;
	struct pipe_ctx *bottom_pipe;
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	uint8_t mpc_idx;
	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
	struct _vcs_dpi_display_rq_regs_st rq_regs;
	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
#endif
};

struct resource_context {
	struct pipe_ctx pipe_ctx[MAX_PIPES];
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	struct mpc_tree_cfg mpc_tree[MAX_PIPES];
#endif
	bool is_stream_enc_acquired[MAX_PIPES * 2];
	bool is_audio_acquired[MAX_PIPES];
	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
	uint8_t dp_clock_source_ref_count;
 };

struct validate_context {
	struct core_stream *streams[MAX_PIPES];
	struct dc_stream_status stream_status[MAX_PIPES];
	uint8_t stream_count;

	struct resource_context res_ctx;

	/* The output from BW and WM calculations. */
	struct bw_calcs_output bw_results;
	/* Note: these are big structures, do *not* put on stack! */
	struct dm_pp_display_configuration pp_display_cfg;
	int dispclk_khz;
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	int dppclk_khz;
	bool dppclk_div;
	int dcfclk_khz;
	int dcfclk_deep_sleep_khz;
	int socclk_khz;
	int fclk_khz;
	int dram_ccm_us;
	int min_active_dram_ccm_us;
	struct dcn_watermark_set watermarks;
	struct dcn_bw_internal_vars dcn_bw_vars;
#endif
};

#endif /* _CORE_TYPES_H_ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef _CORE_TYPES_H_
	27	#define _CORE_TYPES_H_
	28
	29	#include "dc.h"
5e141de4	30	#include "dce_calcs.h"
ff5ef992	31	#include "dcn_calcs.h"
4562236b HW	32	#include "ddc_service_types.h"
4562236b HW	33	#include "dc_bios_types.h"
f3e43418	34	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992 AD	35	#include "mem_input.h"
ff5ef992 AD	36	#include "mpc.h"
f3e43418	37	#endif
4562236b HW	38
4562236b HW	39	struct core_stream;
4562236b HW	40
	41	#define MAX_PIPES 6
	42	#define MAX_CLOCK_SOURCES 7
	43
4562236b HW	44
	45	/******* core_surface ********/
	46	#define DC_SURFACE_TO_CORE(dc_surface) \
	47	container_of(dc_surface, struct core_surface, public)
	48
	49	#define DC_GAMMA_TO_CORE(dc_gamma) \
	50	container_of(dc_gamma, struct core_gamma, public)
	51
90e508ba AK	52	#define DC_TRANSFER_FUNC_TO_CORE(dc_transfer_func) \
	53	container_of(dc_transfer_func, struct core_transfer_func, public)
	54
4562236b HW	55	struct core_surface {
	56	struct dc_surface public;
	57	struct dc_surface_status status;
	58	struct dc_context *ctx;
	59	};
	60
	61	struct core_gamma {
	62	struct dc_gamma public;
	63	struct dc_context *ctx;
	64	};
	65
fb735a9f AK	66	struct core_transfer_func {
	67	struct dc_transfer_func public;
	68	struct dc_context *ctx;
	69	};
	70
4562236b HW	71	void enable_surface_flip_reporting(struct dc_surface *dc_surface,
	72	uint32_t controller_id);
	73
	74	/******* core_stream **********/
	75	#include "grph_object_id.h"
	76	#include "link_encoder.h"
	77	#include "stream_encoder.h"
	78	#include "clock_source.h"
	79	#include "audio.h"
	80	#include "hw_sequencer_types.h"
	81	#include "opp.h"
	82
	83	#define DC_STREAM_TO_CORE(dc_stream) container_of( \
	84	dc_stream, struct core_stream, public)
	85
	86	struct core_stream {
	87	struct dc_stream public;
	88
	89	/* field internal to DC */
	90	struct dc_context *ctx;
	91	const struct core_sink *sink;
	92
	93	/* used by DCP and FMT */
	94	struct bit_depth_reduction_params bit_depth_params;
	95	struct clamping_and_pixel_encoding_params clamping;
	96
	97	int phy_pix_clk;
	98	enum signal_type signal;
	99
	100	struct dc_stream_status status;
	101	};
	102
	103	/********** core_sink ***************/
	104
	105	#define DC_SINK_TO_CORE(dc_sink) \
	106	container_of(dc_sink, struct core_sink, public)
	107
	108	struct core_sink {
	109	/ The public, read-only (for DM) area of sink. /
	110	struct dc_sink public;
	111	/ End-of-public area. /
	112
	113	/ The 'protected' area - read/write access, for use only inside DC /
	114	/* not used for now */
	115	struct core_link *link;
	116	struct dc_context *ctx;
4562236b HW	117	};
	118
	119	/********** link ***************/
	120	#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public)
	121
	122	struct link_init_data {
	123	const struct core_dc *dc;
	124	struct dc_context ctx; / TODO: remove 'dal' when DC is complete. */
	125	uint32_t connector_index; /* this will be mapped to the HPD pins */
	126	uint32_t link_index; /* this is mapped to DAL display_index
	127	TODO: remove it when DC is complete. */
	128	};
	129
	130	/* DP MST stream allocation (payload bandwidth number) */
	131	struct link_mst_stream_allocation {
	132	/* DIG front */
	133	const struct stream_encoder *stream_enc;
	134	/* associate DRM payload table with DC stream encoder */
	135	uint8_t vcp_id;
	136	/* number of slots required for the DP stream in transport packet */
	137	uint8_t slot_count;
	138	};
	139
	140	/* DP MST stream allocation table */
	141	struct link_mst_stream_allocation_table {
	142	/* number of DP video streams */
	143	int stream_count;
	144	/* array of stream allocations */
	145	struct link_mst_stream_allocation
	146	stream_allocations[MAX_CONTROLLER_NUM];
	147	};
	148
	149	struct core_link {
	150	struct dc_link public;
	151	const struct core_dc *dc;
	152
	153	struct dc_context ctx; / TODO: AUTO remove 'dal' when DC is complete*/
	154
	155	struct link_encoder *link_enc;
4562236b HW	156	struct graphics_object_id link_id;
	157	union ddi_channel_mapping ddi_channel_mapping;
	158	struct connector_device_tag_info device_tag;
	159	struct dpcd_caps dpcd_caps;
	160	unsigned int dpcd_sink_count;
	161
	162	enum edp_revision edp_revision;
94267b3d	163	bool psr_enabled;
4562236b HW	164
	165	/* MST record stream using this link */
	166	struct link_flags {
	167	bool dp_keep_receiver_powered;
	168	} wa_flags;
	169	struct link_mst_stream_allocation_table mst_stream_alloc_table;
	170
	171	struct dc_link_status link_status;
	172	};
	173
	174	#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
	175
	176	struct core_link link_create(const struct link_init_data init_params);
	177	void link_destroy(struct core_link **link);
	178
	179	enum dc_status dc_link_validate_mode_timing(
	180	const struct core_stream *stream,
	181	struct core_link *link,
	182	const struct dc_crtc_timing *timing);
	183
	184	void core_link_resume(struct core_link *link);
	185
	186	void core_link_enable_stream(struct pipe_ctx *pipe_ctx);
	187
	188	void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
	189
	190	/******** DAL Core*******************/
e11b86ad	191	#include "display_clock.h"
4562236b HW	192	#include "transform.h"
	193
	194	struct resource_pool;
	195	struct validate_context;
	196	struct resource_context;
	197
	198	struct resource_funcs {
	199	void (destroy)(struct resource_pool *pool);
	200	struct link_encoder (link_enc_create)(
	201	const struct encoder_init_data *init);
	202	enum dc_status (*validate_with_context)(
	203	const struct core_dc *dc,
	204	const struct dc_validation_set set[],
	205	int set_count,
	206	struct validate_context *context);
	207
	208	enum dc_status (*validate_guaranteed)(
	209	const struct core_dc *dc,
ab2541b6	210	const struct dc_stream *stream,
4562236b HW	211	struct validate_context *context);
4562236b HW	212
45209ef7	213	bool (*validate_bandwidth)(
4562236b HW	214	const struct core_dc *dc,
	215	struct validate_context *context);
	216
	217	struct pipe_ctx (acquire_idle_pipe_for_layer)(
745cc746	218	struct validate_context *context,
a2b8659d	219	const struct resource_pool *pool,
4562236b	220	struct core_stream *stream);
4562236b HW	221	};
	222
	223	struct audio_support{
	224	bool dp_audio;
	225	bool hdmi_audio_on_dongle;
	226	bool hdmi_audio_native;
	227	};
	228
f0e3db90 HW	229	#define NO_UNDERLAY_PIPE -1
f0e3db90 HW	230
4562236b HW	231	struct resource_pool {
	232	struct mem_input *mis[MAX_PIPES];
	233	struct input_pixel_processor *ipps[MAX_PIPES];
	234	struct transform *transforms[MAX_PIPES];
	235	struct output_pixel_processor *opps[MAX_PIPES];
	236	struct timing_generator *timing_generators[MAX_PIPES];
	237	struct stream_encoder stream_enc[MAX_PIPES 2];
	238
	239	unsigned int pipe_count;
	240	unsigned int underlay_pipe_index;
	241	unsigned int stream_enc_count;
5ac3d3c9	242	unsigned int ref_clock_inKhz;
4562236b HW	243
	244	/*
	245	* reserved clock source for DP
	246	*/
	247	struct clock_source *dp_clock_source;
	248
	249	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
	250	unsigned int clk_src_count;
	251
	252	struct audio *audios[MAX_PIPES];
	253	unsigned int audio_count;
	254	struct audio_support audio_support;
	255
	256	struct display_clock *display_clock;
	257	struct irq_service *irqs;
	258
5e7773a2 AK	259	struct abm *abm;
5e7773a2 AK	260	struct dmcu *dmcu;
f3e43418	261	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992	262	struct mpc *mpc;
f3e43418	263	#endif
5e7773a2	264
4562236b HW	265	const struct resource_funcs *funcs;
	266	const struct resource_caps *res_cap;
	267	};
	268
	269	struct pipe_ctx {
	270	struct core_surface *surface;
	271	struct core_stream *stream;
	272
	273	struct mem_input *mi;
	274	struct input_pixel_processor *ipp;
	275	struct transform *xfm;
	276	struct output_pixel_processor *opp;
	277	struct timing_generator *tg;
	278
	279	struct scaler_data scl_data;
	280
	281	struct stream_encoder *stream_enc;
	282	struct display_clock *dis_clk;
	283	struct clock_source *clock_source;
	284
	285	struct audio *audio;
	286
	287	struct pixel_clk_params pix_clk_params;
	288	struct pll_settings pll_settings;
	289
	290	/fmt/
	291	struct encoder_info_frame encoder_info_frame;
	292
	293	uint8_t pipe_idx;
	294
	295	struct pipe_ctx *top_pipe;
	296	struct pipe_ctx *bottom_pipe;
ff5ef992 AD	297	#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	298	uint8_t mpc_idx;
	299	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
	300	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
	301	struct _vcs_dpi_display_rq_regs_st rq_regs;
	302	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
	303	#endif
4562236b HW	304	};
	305
	306	struct resource_context {
4562236b	307	struct pipe_ctx pipe_ctx[MAX_PIPES];
ff5ef992 AD	308	#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	309	struct mpc_tree_cfg mpc_tree[MAX_PIPES];
	310	#endif
4562236b HW	311	bool is_stream_enc_acquired[MAX_PIPES * 2];
	312	bool is_audio_acquired[MAX_PIPES];
	313	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
	314	uint8_t dp_clock_source_ref_count;
	315	};
	316
	317	struct validate_context {
ab2541b6 AC	318	struct core_stream *streams[MAX_PIPES];
	319	struct dc_stream_status stream_status[MAX_PIPES];
	320	uint8_t stream_count;
4562236b HW	321
	322	struct resource_context res_ctx;
	323
	324	/* The output from BW and WM calculations. */
	325	struct bw_calcs_output bw_results;
5ea81b91	326	/* Note: these are big structures, do not put on stack! */
4562236b	327	struct dm_pp_display_configuration pp_display_cfg;
0f56b418	328	int dispclk_khz;
ff5ef992 AD	329	#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	330	int dppclk_khz;
	331	bool dppclk_div;
	332	int dcfclk_khz;
	333	int dcfclk_deep_sleep_khz;
	334	int socclk_khz;
	335	int fclk_khz;
	336	int dram_ccm_us;
	337	int min_active_dram_ccm_us;
	338	struct dcn_watermark_set watermarks;
	339	struct dcn_bw_internal_vars dcn_bw_vars;
	340	#endif
4562236b HW	341	};
	342
	343	#endif /* _CORE_TYPES_H_ */