[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / inc / hw / clk_mgr.h

/*
 * Copyright 2012-16 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DAL_CLK_MGR_H__
#define __DAL_CLK_MGR_H__

#include "dc.h"

#define DCN_MINIMUM_DISPCLK_Khz 100000
#define DCN_MINIMUM_DPPCLK_Khz 100000

#ifdef CONFIG_DRM_AMD_DC_DCN2_1
/* Constants */
#define DDR4_DRAM_WIDTH   64
#define WM_A 0
#define WM_B 1
#define WM_C 2
#define WM_D 3
#define WM_SET_COUNT 4
#endif

#define DCN_MINIMUM_DISPCLK_Khz 100000
#define DCN_MINIMUM_DPPCLK_Khz 100000

#ifdef CONFIG_DRM_AMD_DC_DCN2_1
/* Will these bw structures be ASIC specific? */

#define MAX_NUM_DPM_LVL		8
#define WM_SET_COUNT 		4


struct clk_limit_table_entry {
	unsigned int voltage; /* milivolts withh 2 fractional bits */
	unsigned int dcfclk_mhz;
	unsigned int fclk_mhz;
	unsigned int memclk_mhz;
	unsigned int socclk_mhz;
};

/* This table is contiguous */
struct clk_limit_table {
	struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
	unsigned int num_entries;
};

struct wm_range_table_entry {
	unsigned int wm_inst;
	unsigned int wm_type;
	double pstate_latency_us;
	double sr_exit_time_us;
	double sr_enter_plus_exit_time_us;
	bool valid;
};


struct clk_log_info {
	bool enabled;
	char *pBuf;
	unsigned int bufSize;
	unsigned int *sum_chars_printed;
};

struct clk_state_registers_and_bypass {
	uint32_t dcfclk;
	uint32_t dcf_deep_sleep_divider;
	uint32_t dcf_deep_sleep_allow;
	uint32_t dprefclk;
	uint32_t dispclk;
	uint32_t dppclk;

	uint32_t dppclk_bypass;
	uint32_t dcfclk_bypass;
	uint32_t dprefclk_bypass;
	uint32_t dispclk_bypass;
};

struct rv1_clk_internal {
	uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
	uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
	uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
	uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
	uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk

	uint32_t CLK0_CLK8_BYPASS_CNTL;  //dcfclk bypass
	uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
};

struct rn_clk_internal {
	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
	uint32_t CLK1_CLK3_DS_CNTL;		//dcf_deep_sleep_divider
	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow

	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

};

/* For dtn logging and debugging */
struct clk_state_registers {
		uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
		uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
		uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
		uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
		uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
};

/* TODO: combine this with the above */
struct clk_bypass {
	uint32_t dcfclk_bypass;
	uint32_t dispclk_pypass;
	uint32_t dprefclk_bypass;
};
/*
 * This table is not contiguous, can have holes, each
 * entry correspond to one set of WM. For example if
 * we have 2 DPM and LPDDR, we will WM set A, B and
 * D occupied, C will be emptry.
 */
struct wm_table {
	struct wm_range_table_entry entries[WM_SET_COUNT];
};

struct clk_bw_params {
	unsigned int vram_type;
	unsigned int num_channels;
	struct clk_limit_table clk_table;
	struct wm_table wm_table;
};
#endif
/* Public interfaces */

struct clk_states {
	uint32_t dprefclk_khz;
};

struct clk_mgr_funcs {
	/*
	 * This function should set new clocks based on the input "safe_to_lower".
	 * If safe_to_lower == false, then only clocks which are to be increased
	 * should changed.
	 * If safe_to_lower == true, then only clocks which are to be decreased
	 * should be changed.
	 */
	void (*update_clocks)(struct clk_mgr *clk_mgr,
			struct dc_state *context,
			bool safe_to_lower);

	int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);

	void (*init_clocks)(struct clk_mgr *clk_mgr);

	void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
	void (*get_clock)(struct clk_mgr *clk_mgr,
			struct dc_state *context,
			enum dc_clock_type clock_type,
			struct dc_clock_config *clock_cfg);

	bool (*are_clock_states_equal) (struct dc_clocks *a,
			struct dc_clocks *b);
	void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
};

struct clk_mgr {
	struct dc_context *ctx;
	struct clk_mgr_funcs *funcs;
	struct dc_clocks clks;
	bool psr_allow_active_cache;
	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
	int dentist_vco_freq_khz;
#ifdef CONFIG_DRM_AMD_DC_DCN2_1
	struct clk_bw_params *bw_params;
#endif
};

/* forward declarations */
struct dccg;

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);

void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

#endif /* __DAL_CLK_MGR_H__ */
Commit	Line	Data
4562236b	1	/*
e11b86ad	2	* Copyright 2012-16 Advanced Micro Devices, Inc.
4562236b HW	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
84e7fc05 DL	26	#ifndef __DAL_CLK_MGR_H__
84e7fc05 DL	27	#define __DAL_CLK_MGR_H__
4562236b	28
765b2683	29	#include "dc.h"
fd8cc371	30
925f566c CL	31	#define DCN_MINIMUM_DISPCLK_Khz 100000
	32	#define DCN_MINIMUM_DPPCLK_Khz 100000
	33
4edb6fc9 BL	34	#ifdef CONFIG_DRM_AMD_DC_DCN2_1
	35	/* Constants */
	36	#define DDR4_DRAM_WIDTH 64
	37	#define WM_A 0
	38	#define WM_B 1
	39	#define WM_C 2
	40	#define WM_D 3
	41	#define WM_SET_COUNT 4
	42	#endif
	43
	44	#define DCN_MINIMUM_DISPCLK_Khz 100000
	45	#define DCN_MINIMUM_DPPCLK_Khz 100000
	46
	47	#ifdef CONFIG_DRM_AMD_DC_DCN2_1
	48	/* Will these bw structures be ASIC specific? */
	49
976035dd	50	#define MAX_NUM_DPM_LVL 8
4edb6fc9 BL	51	#define WM_SET_COUNT 4
	52
	53
	54	struct clk_limit_table_entry {
	55	unsigned int voltage; /* milivolts withh 2 fractional bits */
	56	unsigned int dcfclk_mhz;
	57	unsigned int fclk_mhz;
	58	unsigned int memclk_mhz;
	59	unsigned int socclk_mhz;
	60	};
	61
	62	/* This table is contiguous */
	63	struct clk_limit_table {
	64	struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
	65	unsigned int num_entries;
	66	};
	67
	68	struct wm_range_table_entry {
	69	unsigned int wm_inst;
	70	unsigned int wm_type;
	71	double pstate_latency_us;
9d9de889 EY	72	double sr_exit_time_us;
9d9de889 EY	73	double sr_enter_plus_exit_time_us;
4edb6fc9 BL	74	bool valid;
	75	};
	76
	77
	78	struct clk_log_info {
	79	bool enabled;
	80	char *pBuf;
	81	unsigned int bufSize;
	82	unsigned int *sum_chars_printed;
	83	};
	84
	85	struct clk_state_registers_and_bypass {
	86	uint32_t dcfclk;
	87	uint32_t dcf_deep_sleep_divider;
	88	uint32_t dcf_deep_sleep_allow;
	89	uint32_t dprefclk;
	90	uint32_t dispclk;
	91	uint32_t dppclk;
	92
	93	uint32_t dppclk_bypass;
	94	uint32_t dcfclk_bypass;
	95	uint32_t dprefclk_bypass;
	96	uint32_t dispclk_bypass;
	97	};
	98
	99	struct rv1_clk_internal {
	100	uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
	101	uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
	102	uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
	103	uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
	104	uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
	105
	106	uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
	107	uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
	108	uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
	109	};
	110
	111	struct rn_clk_internal {
	112	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
	113	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
	114	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
	115	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
	116	uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
	117	uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
	118
	119	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
	120	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
	121	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
	122	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
	123
	124	};
	125
	126	/* For dtn logging and debugging */
	127	struct clk_state_registers {
	128	uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
	129	uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
	130	uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
	131	uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
	132	uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
	133	};
	134
	135	/* TODO: combine this with the above */
	136	struct clk_bypass {
	137	uint32_t dcfclk_bypass;
138	uint32_t dispclk_pypass;
139	uint32_t dprefclk_bypass;
140	};
141	/*
142	* This table is not contiguous, can have holes, each
143	* entry correspond to one set of WM. For example if
144	* we have 2 DPM and LPDDR, we will WM set A, B and
145	* D occupied, C will be emptry.
146	*/
147	struct wm_table {
148	struct wm_range_table_entry entries[WM_SET_COUNT];
149	};
150
151	struct clk_bw_params {
152	unsigned int vram_type;
153	unsigned int num_channels;
154	struct clk_limit_table clk_table;
155	struct wm_table wm_table;
156	};
157	#endif
dc88b4a6	158	/* Public interfaces */
1a687574	159
baa1fd7f EY	160	struct clk_states {
	161	uint32_t dprefclk_khz;
	162	};
	163
84e7fc05	164	struct clk_mgr_funcs {
dc88b4a6 EY	165	/*
	166	* This function should set new clocks based on the input "safe_to_lower".
	167	* If safe_to_lower == false, then only clocks which are to be increased
	168	* should changed.
	169	* If safe_to_lower == true, then only clocks which are to be decreased
	170	* should be changed.
	171	*/
84e7fc05	172	void (update_clocks)(struct clk_mgr clk_mgr,
24f7dd7e	173	struct dc_state *context,
fab55d61	174	bool safe_to_lower);
e11b86ad	175
84e7fc05	176	int (get_dp_ref_clk_frequency)(struct clk_mgr clk_mgr);
3a66541c EB	177
3a66541c EB	178	void (init_clocks)(struct clk_mgr clk_mgr);
21e471f0	179
baa1fd7f	180	void (enable_pme_wa) (struct clk_mgr clk_mgr);
925f566c CL	181	void (get_clock)(struct clk_mgr clk_mgr,
	182	struct dc_state *context,
	183	enum dc_clock_type clock_type,
	184	struct dc_clock_config *clock_cfg);
deb79818 JL	185
	186	bool (are_clock_states_equal) (struct dc_clocks a,
	187	struct dc_clocks *b);
622a88c8	188	void (notify_wm_ranges)(struct clk_mgr clk_mgr);
e11b86ad	189	};
9a70eba7	190
dc88b4a6 EY	191	struct clk_mgr {
	192	struct dc_context *ctx;
	193	struct clk_mgr_funcs *funcs;
	194	struct dc_clocks clks;
ab4a4072	195	bool psr_allow_active_cache;
dc88b4a6	196	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
44ce0cd3	197	int dentist_vco_freq_khz;
4edb6fc9 BL	198	#ifdef CONFIG_DRM_AMD_DC_DCN2_1
	199	struct clk_bw_params *bw_params;
	200	#endif
dc88b4a6 EY	201	};
	202
	203	/* forward declarations */
	204	struct dccg;
	205
	206	struct clk_mgr dc_clk_mgr_create(struct dc_context ctx, struct pp_smu_funcs pp_smu, struct dccg dccg);
21e471f0	207
dc88b4a6	208	void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
21e471f0	209
ab4a4072 EY	210	void clk_mgr_exit_optimized_pwr_state(const struct dc dc, struct clk_mgr clk_mgr);
	211
	212	void clk_mgr_optimize_pwr_state(const struct dc dc, struct clk_mgr clk_mgr);
	213
84e7fc05	214	#endif /* __DAL_CLK_MGR_H__ */