[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / inc / hw / timing_generator.h

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
#define __DAL_TIMING_GENERATOR_TYPES_H__

struct dc_bios;

/* Contains CRTC vertical/horizontal pixel counters */
struct crtc_position {
	int32_t vertical_count;
	int32_t horizontal_count;
	int32_t nominal_vcount;
};

struct dcp_gsl_params {
	int gsl_group;
	int gsl_master;
};

/* define the structure of Dynamic Refresh Mode */
struct drr_params {
	uint32_t vertical_total_min;
	uint32_t vertical_total_max;
	bool immediate_flip;
};

#define LEFT_EYE_3D_PRIMARY_SURFACE 1
#define RIGHT_EYE_3D_PRIMARY_SURFACE 0

enum test_pattern_dyn_range {
	TEST_PATTERN_DYN_RANGE_VESA = 0,
	TEST_PATTERN_DYN_RANGE_CEA
};

enum test_pattern_mode {
	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
	TEST_PATTERN_MODE_VERTICALBARS,
	TEST_PATTERN_MODE_HORIZONTALBARS,
	TEST_PATTERN_MODE_SINGLERAMP_RGB,
	TEST_PATTERN_MODE_DUALRAMP_RGB
};

enum test_pattern_color_format {
	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
	TEST_PATTERN_COLOR_FORMAT_BPC_8,
	TEST_PATTERN_COLOR_FORMAT_BPC_10,
	TEST_PATTERN_COLOR_FORMAT_BPC_12
};

enum controller_dp_test_pattern {
	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
	CONTROLLER_DP_TEST_PATTERN_PRBS7,
	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
};

enum crtc_state {
	CRTC_STATE_VBLANK = 0,
	CRTC_STATE_VACTIVE
};

struct _dlg_otg_param {
	int vstartup_start;
	int vupdate_offset;
	int vupdate_width;
	int vready_offset;
	enum signal_type signal;
};

struct crtc_stereo_flags {
	uint8_t PROGRAM_STEREO         : 1;
	uint8_t PROGRAM_POLARITY       : 1;
	uint8_t RIGHT_EYE_POLARITY     : 1;
	uint8_t FRAME_PACKED           : 1;
	uint8_t DISABLE_STEREO_DP_SYNC : 1;
};

struct timing_generator {
	const struct timing_generator_funcs *funcs;
	struct dc_bios *bp;
	struct dc_context *ctx;
	struct _dlg_otg_param dlg_otg_param;
	int inst;
};

struct dc_crtc_timing;

struct drr_params;

struct timing_generator_funcs {
	bool (*validate_timing)(struct timing_generator *tg,
							const struct dc_crtc_timing *timing);
	void (*program_timing)(struct timing_generator *tg,
							const struct dc_crtc_timing *timing,
							bool use_vbios);
	bool (*enable_crtc)(struct timing_generator *tg);
	bool (*disable_crtc)(struct timing_generator *tg);
	bool (*is_counter_moving)(struct timing_generator *tg);
	void (*get_position)(struct timing_generator *tg,
				struct crtc_position *position);

	uint32_t (*get_frame_count)(struct timing_generator *tg);
	void (*get_scanoutpos)(
		struct timing_generator *tg,
		uint32_t *v_blank_start,
		uint32_t *v_blank_end,
		uint32_t *h_position,
		uint32_t *v_position);
	void (*set_early_control)(struct timing_generator *tg,
							   uint32_t early_cntl);
	void (*wait_for_state)(struct timing_generator *tg,
							enum crtc_state state);
	void (*set_blank)(struct timing_generator *tg,
					bool enable_blanking);
	bool (*is_blanked)(struct timing_generator *tg);
	void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
	void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
	void (*set_colors)(struct timing_generator *tg,
						const struct tg_color *blank_color,
						const struct tg_color *overscan_color);

	void (*disable_vga)(struct timing_generator *tg);
	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
	void (*setup_global_swap_lock)(struct timing_generator *tg,
							const struct dcp_gsl_params *gsl_params);
	void (*unlock)(struct timing_generator *tg);
	void (*lock)(struct timing_generator *tg);
	void (*enable_reset_trigger)(struct timing_generator *tg,
				     int source_tg_inst);
	void (*enable_crtc_reset)(struct timing_generator *tg,
				  int source_tg_inst,
				  struct crtc_trigger_info *crtc_tp);
	void (*disable_reset_trigger)(struct timing_generator *tg);
	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
	void (*enable_advanced_request)(struct timing_generator *tg,
					bool enable, const struct dc_crtc_timing *timing);
	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
	void (*set_static_screen_control)(struct timing_generator *tg,
							uint32_t value);
	void (*set_test_pattern)(
		struct timing_generator *tg,
		enum controller_dp_test_pattern test_pattern,
		enum dc_color_depth color_depth);

	bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);

	void (*program_global_sync)(struct timing_generator *tg);
	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
	void (*program_stereo)(struct timing_generator *tg,
		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
	bool (*is_stereo_left_eye)(struct timing_generator *tg);
};

#endif
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
	27	#define __DAL_TIMING_GENERATOR_TYPES_H__
	28
	29	struct dc_bios;
	30
4562236b HW	31	/* Contains CRTC vertical/horizontal pixel counters */
4562236b HW	32	struct crtc_position {
72ada5f7 EC	33	int32_t vertical_count;
	34	int32_t horizontal_count;
	35	int32_t nominal_vcount;
4562236b HW	36	};
	37
	38	struct dcp_gsl_params {
	39	int gsl_group;
	40	int gsl_master;
	41	};
	42
9c3b2b50 TC	43	/* define the structure of Dynamic Refresh Mode */
	44	struct drr_params {
	45	uint32_t vertical_total_min;
	46	uint32_t vertical_total_max;
	47	bool immediate_flip;
	48	};
	49
4562236b HW	50	#define LEFT_EYE_3D_PRIMARY_SURFACE 1
	51	#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
	52
	53	enum test_pattern_dyn_range {
	54	TEST_PATTERN_DYN_RANGE_VESA = 0,
	55	TEST_PATTERN_DYN_RANGE_CEA
	56	};
	57
	58	enum test_pattern_mode {
	59	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
	60	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
	61	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
	62	TEST_PATTERN_MODE_VERTICALBARS,
	63	TEST_PATTERN_MODE_HORIZONTALBARS,
	64	TEST_PATTERN_MODE_SINGLERAMP_RGB,
	65	TEST_PATTERN_MODE_DUALRAMP_RGB
	66	};
	67
	68	enum test_pattern_color_format {
	69	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
	70	TEST_PATTERN_COLOR_FORMAT_BPC_8,
	71	TEST_PATTERN_COLOR_FORMAT_BPC_10,
	72	TEST_PATTERN_COLOR_FORMAT_BPC_12
	73	};
	74
	75	enum controller_dp_test_pattern {
	76	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
	77	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
	78	CONTROLLER_DP_TEST_PATTERN_PRBS7,
	79	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
	80	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
	81	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
	82	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
	83	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
	84	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
	85	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
	86	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
	87	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
	88	};
	89
	90	enum crtc_state {
	91	CRTC_STATE_VBLANK = 0,
	92	CRTC_STATE_VACTIVE
	93	};
43193c79	94
ff5ef992 AD	95	struct _dlg_otg_param {
	96	int vstartup_start;
	97	int vupdate_offset;
	98	int vupdate_width;
	99	int vready_offset;
	100	enum signal_type signal;
	101	};
9edba557 VP	102
	103	struct crtc_stereo_flags {
	104	uint8_t PROGRAM_STEREO : 1;
	105	uint8_t PROGRAM_POLARITY : 1;
	106	uint8_t RIGHT_EYE_POLARITY : 1;
	107	uint8_t FRAME_PACKED : 1;
	108	uint8_t DISABLE_STEREO_DP_SYNC : 1;
	109	};
	110
4562236b HW	111	struct timing_generator {
	112	const struct timing_generator_funcs *funcs;
	113	struct dc_bios *bp;
	114	struct dc_context *ctx;
ff5ef992	115	struct _dlg_otg_param dlg_otg_param;
4562236b HW	116	int inst;
	117	};
	118
	119	struct dc_crtc_timing;
	120
	121	struct drr_params;
	122
	123	struct timing_generator_funcs {
	124	bool (validate_timing)(struct timing_generator tg,
	125	const struct dc_crtc_timing *timing);
	126	void (program_timing)(struct timing_generator tg,
	127	const struct dc_crtc_timing *timing,
	128	bool use_vbios);
	129	bool (enable_crtc)(struct timing_generator tg);
	130	bool (disable_crtc)(struct timing_generator tg);
	131	bool (is_counter_moving)(struct timing_generator tg);
	132	void (get_position)(struct timing_generator tg,
72ada5f7 EC	133	struct crtc_position *position);
72ada5f7 EC	134
4562236b	135	uint32_t (get_frame_count)(struct timing_generator tg);
81c50963	136	void (*get_scanoutpos)(
4562236b	137	struct timing_generator *tg,
81c50963 ST	138	uint32_t *v_blank_start,
	139	uint32_t *v_blank_end,
	140	uint32_t *h_position,
	141	uint32_t *v_position);
4562236b HW	142	void (set_early_control)(struct timing_generator tg,
	143	uint32_t early_cntl);
	144	void (wait_for_state)(struct timing_generator tg,
	145	enum crtc_state state);
4b5e7d62	146	void (set_blank)(struct timing_generator tg,
4562236b HW	147	bool enable_blanking);
	148	bool (is_blanked)(struct timing_generator tg);
	149	void (set_overscan_blank_color) (struct timing_generator tg, const struct tg_color *color);
	150	void (set_blank_color)(struct timing_generator tg, const struct tg_color *color);
	151	void (set_colors)(struct timing_generator tg,
	152	const struct tg_color *blank_color,
	153	const struct tg_color *overscan_color);
	154
	155	void (disable_vga)(struct timing_generator tg);
	156	bool (did_triggered_reset_occur)(struct timing_generator tg);
	157	void (setup_global_swap_lock)(struct timing_generator tg,
	158	const struct dcp_gsl_params *gsl_params);
	159	void (unlock)(struct timing_generator tg);
	160	void (lock)(struct timing_generator tg);
fa2123db ML	161	void (enable_reset_trigger)(struct timing_generator tg,
	162	int source_tg_inst);
	163	void (enable_crtc_reset)(struct timing_generator tg,
	164	int source_tg_inst,
	165	struct crtc_trigger_info *crtc_tp);
4562236b HW	166	void (disable_reset_trigger)(struct timing_generator tg);
	167	void (tear_down_global_swap_lock)(struct timing_generator tg);
	168	void (enable_advanced_request)(struct timing_generator tg,
	169	bool enable, const struct dc_crtc_timing *timing);
	170	void (set_drr)(struct timing_generator tg, const struct drr_params *params);
	171	void (set_static_screen_control)(struct timing_generator tg,
	172	uint32_t value);
	173	void (*set_test_pattern)(
	174	struct timing_generator *tg,
	175	enum controller_dp_test_pattern test_pattern,
	176	enum dc_color_depth color_depth);
	177
667e1498 AG	178	bool (arm_vert_intr)(struct timing_generator tg, uint8_t width);
667e1498 AG	179
ff5ef992 AD	180	void (program_global_sync)(struct timing_generator tg);
ff5ef992 AD	181	void (enable_optc_clock)(struct timing_generator tg, bool enable);
9edba557 VP	182	void (program_stereo)(struct timing_generator tg,
	183	const struct dc_crtc_timing timing, struct crtc_stereo_flags flags);
	184	bool (is_stereo_left_eye)(struct timing_generator tg);
4562236b HW	185	};
	186
	187	#endif