[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / display / dc / irq / dce110 / irq_service_dce110.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"

#include "include/logger_interface.h"

#include "irq_service_dce110.h"

#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"

#include "ivsrcid/ivsrcid_vislands30.h"

#include "dc.h"
#include "core_types.h"
static bool hpd_ack(
	struct irq_service *irq_service,
	const struct irq_source_info *info)
{
	uint32_t addr = info->status_reg;
	uint32_t value = dm_read_reg(irq_service->ctx, addr);
	uint32_t current_status =
		get_reg_field_value(
			value,
			DC_HPD_INT_STATUS,
			DC_HPD_SENSE_DELAYED);

	dal_irq_service_ack_generic(irq_service, info);

	value = dm_read_reg(irq_service->ctx, info->enable_reg);

	set_reg_field_value(
		value,
		current_status ? 0 : 1,
		DC_HPD_INT_CONTROL,
		DC_HPD_INT_POLARITY);

	dm_write_reg(irq_service->ctx, info->enable_reg, value);

	return true;
}

static const struct irq_source_info_funcs hpd_irq_info_funcs = {
	.set = NULL,
	.ack = hpd_ack
};

static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
	.set = NULL,
	.ack = NULL
};

static const struct irq_source_info_funcs pflip_irq_info_funcs = {
	.set = NULL,
	.ack = NULL
};

static const struct irq_source_info_funcs vblank_irq_info_funcs = {
	.set = dce110_vblank_set,
	.ack = NULL
};

#define hpd_int_entry(reg_num)\
	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
		.enable_value = {\
			DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
			~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
		},\
		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
		.funcs = &hpd_irq_info_funcs\
	}

#define hpd_rx_int_entry(reg_num)\
	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
		.enable_value = {\
			DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
			~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
		.funcs = &hpd_rx_irq_info_funcs\
	}
#define pflip_int_entry(reg_num)\
	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
		.enable_mask =\
		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
		.enable_value = {\
			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
		.funcs = &pflip_irq_info_funcs\
	}

#define vupdate_int_entry(reg_num)\
	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
		.enable_mask =\
		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
		.enable_value = {\
			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
		.ack_mask =\
		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
		.ack_value =\
		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
		.funcs = &vblank_irq_info_funcs\
	}

#define vblank_int_entry(reg_num)\
	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
		.enable_mask =\
		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
		.enable_value = {\
			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
		.ack_mask =\
		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
		.ack_value =\
		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
		.funcs = &vblank_irq_info_funcs,\
		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
	}

#define dummy_irq_entry() \
	{\
		.funcs = &dummy_irq_info_funcs\
	}

#define i2c_int_entry(reg_num) \
	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

#define dp_sink_int_entry(reg_num) \
	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

#define gpio_pad_int_entry(reg_num) \
	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

#define dc_underflow_int_entry(reg_num) \
	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

bool dal_irq_service_dummy_set(
	struct irq_service *irq_service,
	const struct irq_source_info *info,
	bool enable)
{
	dm_logger_write(
		irq_service->ctx->logger, LOG_ERROR,
		"%s: called for non-implemented irq source\n",
		__func__);
	return false;
}

bool dal_irq_service_dummy_ack(
	struct irq_service *irq_service,
	const struct irq_source_info *info)
{
	dm_logger_write(
		irq_service->ctx->logger, LOG_ERROR,
		"%s: called for non-implemented irq source\n",
		__func__);
	return false;
}


bool dce110_vblank_set(
		struct irq_service *irq_service,
		const struct irq_source_info *info,
		bool enable)
{
	struct dc_context *dc_ctx = irq_service->ctx;
	struct dc *core_dc = irq_service->ctx->dc;
	enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source(
										irq_service->ctx->dc,
										info->src_id,
										info->ext_id);
	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;

	struct timing_generator *tg =
			core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

	if (enable) {
		if (!tg->funcs->arm_vert_intr(tg, 2)) {
			DC_ERROR("Failed to get VBLANK!\n");
			return false;
		}
	}

	dal_irq_service_set_generic(irq_service, info, enable);
	return true;

}

static const struct irq_source_info_funcs dummy_irq_info_funcs = {
	.set = dal_irq_service_dummy_set,
	.ack = dal_irq_service_dummy_ack
};

static const struct irq_source_info
irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
	hpd_int_entry(0),
	hpd_int_entry(1),
	hpd_int_entry(2),
	hpd_int_entry(3),
	hpd_int_entry(4),
	hpd_int_entry(5),
	hpd_rx_int_entry(0),
	hpd_rx_int_entry(1),
	hpd_rx_int_entry(2),
	hpd_rx_int_entry(3),
	hpd_rx_int_entry(4),
	hpd_rx_int_entry(5),
	i2c_int_entry(1),
	i2c_int_entry(2),
	i2c_int_entry(3),
	i2c_int_entry(4),
	i2c_int_entry(5),
	i2c_int_entry(6),
	dp_sink_int_entry(1),
	dp_sink_int_entry(2),
	dp_sink_int_entry(3),
	dp_sink_int_entry(4),
	dp_sink_int_entry(5),
	dp_sink_int_entry(6),
	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
	pflip_int_entry(0),
	pflip_int_entry(1),
	pflip_int_entry(2),
	pflip_int_entry(3),
	pflip_int_entry(4),
	pflip_int_entry(5),
	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
	gpio_pad_int_entry(0),
	gpio_pad_int_entry(1),
	gpio_pad_int_entry(2),
	gpio_pad_int_entry(3),
	gpio_pad_int_entry(4),
	gpio_pad_int_entry(5),
	gpio_pad_int_entry(6),
	gpio_pad_int_entry(7),
	gpio_pad_int_entry(8),
	gpio_pad_int_entry(9),
	gpio_pad_int_entry(10),
	gpio_pad_int_entry(11),
	gpio_pad_int_entry(12),
	gpio_pad_int_entry(13),
	gpio_pad_int_entry(14),
	gpio_pad_int_entry(15),
	gpio_pad_int_entry(16),
	gpio_pad_int_entry(17),
	gpio_pad_int_entry(18),
	gpio_pad_int_entry(19),
	gpio_pad_int_entry(20),
	gpio_pad_int_entry(21),
	gpio_pad_int_entry(22),
	gpio_pad_int_entry(23),
	gpio_pad_int_entry(24),
	gpio_pad_int_entry(25),
	gpio_pad_int_entry(26),
	gpio_pad_int_entry(27),
	gpio_pad_int_entry(28),
	gpio_pad_int_entry(29),
	gpio_pad_int_entry(30),
	dc_underflow_int_entry(1),
	dc_underflow_int_entry(2),
	dc_underflow_int_entry(3),
	dc_underflow_int_entry(4),
	dc_underflow_int_entry(5),
	dc_underflow_int_entry(6),
	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
	vupdate_int_entry(0),
	vupdate_int_entry(1),
	vupdate_int_entry(2),
	vupdate_int_entry(3),
	vupdate_int_entry(4),
	vupdate_int_entry(5),
	vblank_int_entry(0),
	vblank_int_entry(1),
	vblank_int_entry(2),
	vblank_int_entry(3),
	vblank_int_entry(4),
	vblank_int_entry(5),

};

enum dc_irq_source to_dal_irq_source_dce110(
		struct irq_service *irq_service,
		uint32_t src_id,
		uint32_t ext_id)
{
	switch (src_id) {
	case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
		return DC_IRQ_SOURCE_VBLANK1;
	case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
		return DC_IRQ_SOURCE_VBLANK2;
	case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
		return DC_IRQ_SOURCE_VBLANK3;
	case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
		return DC_IRQ_SOURCE_VBLANK4;
	case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
		return DC_IRQ_SOURCE_VBLANK5;
	case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
		return DC_IRQ_SOURCE_VBLANK6;
	case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
		return DC_IRQ_SOURCE_VUPDATE1;
	case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
		return DC_IRQ_SOURCE_VUPDATE2;
	case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
		return DC_IRQ_SOURCE_VUPDATE3;
	case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
		return DC_IRQ_SOURCE_VUPDATE4;
	case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
		return DC_IRQ_SOURCE_VUPDATE5;
	case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
		return DC_IRQ_SOURCE_VUPDATE6;
	case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
		return DC_IRQ_SOURCE_PFLIP1;
	case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
		return DC_IRQ_SOURCE_PFLIP2;
	case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
		return DC_IRQ_SOURCE_PFLIP3;
	case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
		return DC_IRQ_SOURCE_PFLIP4;
	case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
		return DC_IRQ_SOURCE_PFLIP5;
	case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
		return DC_IRQ_SOURCE_PFLIP6;

	case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
		/* generic src_id for all HPD and HPDRX interrupts */
		switch (ext_id) {
		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
			return DC_IRQ_SOURCE_HPD1;
		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
			return DC_IRQ_SOURCE_HPD2;
		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
			return DC_IRQ_SOURCE_HPD3;
		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
			return DC_IRQ_SOURCE_HPD4;
		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
			return DC_IRQ_SOURCE_HPD5;
		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
			return DC_IRQ_SOURCE_HPD6;
		case VISLANDS30_IV_EXTID_HPD_RX_A:
			return DC_IRQ_SOURCE_HPD1RX;
		case VISLANDS30_IV_EXTID_HPD_RX_B:
			return DC_IRQ_SOURCE_HPD2RX;
		case VISLANDS30_IV_EXTID_HPD_RX_C:
			return DC_IRQ_SOURCE_HPD3RX;
		case VISLANDS30_IV_EXTID_HPD_RX_D:
			return DC_IRQ_SOURCE_HPD4RX;
		case VISLANDS30_IV_EXTID_HPD_RX_E:
			return DC_IRQ_SOURCE_HPD5RX;
		case VISLANDS30_IV_EXTID_HPD_RX_F:
			return DC_IRQ_SOURCE_HPD6RX;
		default:
			return DC_IRQ_SOURCE_INVALID;
		}
		break;

	default:
		return DC_IRQ_SOURCE_INVALID;
	}
}

static const struct irq_service_funcs irq_service_funcs_dce110 = {
		.to_dal_irq_source = to_dal_irq_source_dce110
};

bool construct(
	struct irq_service *irq_service,
	struct irq_service_init_data *init_data)
{
	if (!dal_irq_service_construct(irq_service, init_data))
		return false;

	irq_service->info = irq_source_info_dce110;
	irq_service->funcs = &irq_service_funcs_dce110;

	return true;
}

struct irq_service *dal_irq_service_dce110_create(
	struct irq_service_init_data *init_data)
{
	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
						  GFP_KERNEL);

	if (!irq_service)
		return NULL;

	if (construct(irq_service, init_data))
		return irq_service;

	kfree(irq_service);
	return NULL;
}
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dm_services.h"
	27
	28	#include "include/logger_interface.h"
	29
	30	#include "irq_service_dce110.h"
	31
	32	#include "dce/dce_11_0_d.h"
	33	#include "dce/dce_11_0_sh_mask.h"
667e1498	34
4562236b HW	35	#include "ivsrcid/ivsrcid_vislands30.h"
4562236b HW	36
fb3466a4 BL	37	#include "dc.h"
fb3466a4 BL	38	#include "core_types.h"
4562236b HW	39	static bool hpd_ack(
	40	struct irq_service *irq_service,
	41	const struct irq_source_info *info)
	42	{
	43	uint32_t addr = info->status_reg;
	44	uint32_t value = dm_read_reg(irq_service->ctx, addr);
	45	uint32_t current_status =
	46	get_reg_field_value(
	47	value,
	48	DC_HPD_INT_STATUS,
	49	DC_HPD_SENSE_DELAYED);
	50
	51	dal_irq_service_ack_generic(irq_service, info);
	52
	53	value = dm_read_reg(irq_service->ctx, info->enable_reg);
	54
	55	set_reg_field_value(
	56	value,
	57	current_status ? 0 : 1,
	58	DC_HPD_INT_CONTROL,
	59	DC_HPD_INT_POLARITY);
	60
	61	dm_write_reg(irq_service->ctx, info->enable_reg, value);
	62
	63	return true;
	64	}
	65
	66	static const struct irq_source_info_funcs hpd_irq_info_funcs = {
	67	.set = NULL,
	68	.ack = hpd_ack
	69	};
	70
	71	static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
	72	.set = NULL,
	73	.ack = NULL
	74	};
	75
	76	static const struct irq_source_info_funcs pflip_irq_info_funcs = {
	77	.set = NULL,
	78	.ack = NULL
	79	};
	80
	81	static const struct irq_source_info_funcs vblank_irq_info_funcs = {
667e1498	82	.set = dce110_vblank_set,
4562236b HW	83	.ack = NULL
	84	};
	85
	86	#define hpd_int_entry(reg_num)\
	87	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
	88	.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
	89	.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
	90	.enable_value = {\
	91	DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
	92	~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
	93	},\
	94	.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
	95	.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
	96	.ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
	97	.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
	98	.funcs = &hpd_irq_info_funcs\
	99	}
	100
	101	#define hpd_rx_int_entry(reg_num)\
	102	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
	103	.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
	104	.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
	105	.enable_value = {\
	106	DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
	107	~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
	108	.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
	109	.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
	110	.ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
	111	.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
	112	.funcs = &hpd_rx_irq_info_funcs\
	113	}
	114	#define pflip_int_entry(reg_num)\
	115	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
	116	.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
	117	.enable_mask =\
	118	GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
	119	.enable_value = {\
	120	GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
	121	~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
	122	.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
	123	.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
	124	.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
	125	.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
	126	.funcs = &pflip_irq_info_funcs\
	127	}
	128
	129	#define vupdate_int_entry(reg_num)\
	130	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
	131	.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
	132	.enable_mask =\
	133	CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
	134	.enable_value = {\
	135	CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
	136	~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
	137	.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
	138	.ack_mask =\
	139	CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
	140	.ack_value =\
	141	CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
	142	.funcs = &vblank_irq_info_funcs\
	143	}
	144
b10d51f8 AG	145	#define vblank_int_entry(reg_num)\
b10d51f8 AG	146	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
667e1498	147	.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
b10d51f8	148	.enable_mask =\
667e1498	149	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
b10d51f8	150	.enable_value = {\
667e1498 AG	151	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
	152	~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
	153	.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
b10d51f8	154	.ack_mask =\
667e1498	155	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
b10d51f8	156	.ack_value =\
667e1498 AG	157	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
	158	.funcs = &vblank_irq_info_funcs,\
	159	.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
b10d51f8 AG	160	}
b10d51f8 AG	161
4562236b HW	162	#define dummy_irq_entry() \
	163	{\
	164	.funcs = &dummy_irq_info_funcs\
	165	}
	166
	167	#define i2c_int_entry(reg_num) \
	168	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
	169
	170	#define dp_sink_int_entry(reg_num) \
	171	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
	172
	173	#define gpio_pad_int_entry(reg_num) \
	174	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
	175
	176	#define dc_underflow_int_entry(reg_num) \
	177	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
	178
	179	bool dal_irq_service_dummy_set(
	180	struct irq_service *irq_service,
	181	const struct irq_source_info *info,
	182	bool enable)
	183	{
	184	dm_logger_write(
	185	irq_service->ctx->logger, LOG_ERROR,
	186	"%s: called for non-implemented irq source\n",
	187	__func__);
	188	return false;
	189	}
	190
	191	bool dal_irq_service_dummy_ack(
	192	struct irq_service *irq_service,
	193	const struct irq_source_info *info)
	194	{
	195	dm_logger_write(
	196	irq_service->ctx->logger, LOG_ERROR,
	197	"%s: called for non-implemented irq source\n",
	198	__func__);
	199	return false;
	200	}
	201
667e1498 AG	202
	203	bool dce110_vblank_set(
	204	struct irq_service *irq_service,
	205	const struct irq_source_info *info,
	206	bool enable)
	207	{
	208	struct dc_context *dc_ctx = irq_service->ctx;
fb3466a4	209	struct dc *core_dc = irq_service->ctx->dc;
667e1498 AG	210	enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source(
	211	irq_service->ctx->dc,
	212	info->src_id,
	213	info->ext_id);
	214	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
	215
	216	struct timing_generator *tg =
608ac7bb	217	core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
667e1498 AG	218
	219	if (enable) {
	220	if (!tg->funcs->arm_vert_intr(tg, 2)) {
	221	DC_ERROR("Failed to get VBLANK!\n");
	222	return false;
	223	}
	224	}
	225
	226	dal_irq_service_set_generic(irq_service, info, enable);
	227	return true;
	228
	229	}
	230
4562236b HW	231	static const struct irq_source_info_funcs dummy_irq_info_funcs = {
	232	.set = dal_irq_service_dummy_set,
	233	.ack = dal_irq_service_dummy_ack
	234	};
	235
	236	static const struct irq_source_info
	237	irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
	238	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
	239	hpd_int_entry(0),
	240	hpd_int_entry(1),
	241	hpd_int_entry(2),
	242	hpd_int_entry(3),
	243	hpd_int_entry(4),
	244	hpd_int_entry(5),
	245	hpd_rx_int_entry(0),
	246	hpd_rx_int_entry(1),
	247	hpd_rx_int_entry(2),
	248	hpd_rx_int_entry(3),
	249	hpd_rx_int_entry(4),
	250	hpd_rx_int_entry(5),
	251	i2c_int_entry(1),
	252	i2c_int_entry(2),
	253	i2c_int_entry(3),
	254	i2c_int_entry(4),
	255	i2c_int_entry(5),
	256	i2c_int_entry(6),
	257	dp_sink_int_entry(1),
	258	dp_sink_int_entry(2),
	259	dp_sink_int_entry(3),
	260	dp_sink_int_entry(4),
	261	dp_sink_int_entry(5),
	262	dp_sink_int_entry(6),
	263	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
	264	pflip_int_entry(0),
	265	pflip_int_entry(1),
	266	pflip_int_entry(2),
	267	pflip_int_entry(3),
	268	pflip_int_entry(4),
	269	pflip_int_entry(5),
	270	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
	271	gpio_pad_int_entry(0),
	272	gpio_pad_int_entry(1),
	273	gpio_pad_int_entry(2),
	274	gpio_pad_int_entry(3),
	275	gpio_pad_int_entry(4),
	276	gpio_pad_int_entry(5),
	277	gpio_pad_int_entry(6),
	278	gpio_pad_int_entry(7),
	279	gpio_pad_int_entry(8),
	280	gpio_pad_int_entry(9),
	281	gpio_pad_int_entry(10),
	282	gpio_pad_int_entry(11),
	283	gpio_pad_int_entry(12),
	284	gpio_pad_int_entry(13),
	285	gpio_pad_int_entry(14),
	286	gpio_pad_int_entry(15),
	287	gpio_pad_int_entry(16),
	288	gpio_pad_int_entry(17),
	289	gpio_pad_int_entry(18),
	290	gpio_pad_int_entry(19),
	291	gpio_pad_int_entry(20),
	292	gpio_pad_int_entry(21),
	293	gpio_pad_int_entry(22),
	294	gpio_pad_int_entry(23),
295	gpio_pad_int_entry(24),
296	gpio_pad_int_entry(25),
297	gpio_pad_int_entry(26),
298	gpio_pad_int_entry(27),
299	gpio_pad_int_entry(28),
300	gpio_pad_int_entry(29),
301	gpio_pad_int_entry(30),
302	dc_underflow_int_entry(1),
303	dc_underflow_int_entry(2),
304	dc_underflow_int_entry(3),
305	dc_underflow_int_entry(4),
306	dc_underflow_int_entry(5),
307	dc_underflow_int_entry(6),
308	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
309	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
310	vupdate_int_entry(0),
311	vupdate_int_entry(1),
312	vupdate_int_entry(2),
313	vupdate_int_entry(3),
314	vupdate_int_entry(4),
315	vupdate_int_entry(5),
b10d51f8 AG	316	vblank_int_entry(0),
	317	vblank_int_entry(1),
	318	vblank_int_entry(2),
	319	vblank_int_entry(3),
	320	vblank_int_entry(4),
	321	vblank_int_entry(5),
	322
4562236b HW	323	};
	324
	325	enum dc_irq_source to_dal_irq_source_dce110(
	326	struct irq_service *irq_service,
	327	uint32_t src_id,
	328	uint32_t ext_id)
	329	{
	330	switch (src_id) {
667e1498	331	case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
b10d51f8	332	return DC_IRQ_SOURCE_VBLANK1;
667e1498	333	case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
b10d51f8	334	return DC_IRQ_SOURCE_VBLANK2;
667e1498	335	case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
b10d51f8	336	return DC_IRQ_SOURCE_VBLANK3;
667e1498	337	case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
b10d51f8	338	return DC_IRQ_SOURCE_VBLANK4;
667e1498	339	case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
b10d51f8	340	return DC_IRQ_SOURCE_VBLANK5;
667e1498	341	case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
b10d51f8	342	return DC_IRQ_SOURCE_VBLANK6;
4562236b HW	343	case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
	344	return DC_IRQ_SOURCE_VUPDATE1;
	345	case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
	346	return DC_IRQ_SOURCE_VUPDATE2;
	347	case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
	348	return DC_IRQ_SOURCE_VUPDATE3;
	349	case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
	350	return DC_IRQ_SOURCE_VUPDATE4;
	351	case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
	352	return DC_IRQ_SOURCE_VUPDATE5;
	353	case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
	354	return DC_IRQ_SOURCE_VUPDATE6;
	355	case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
	356	return DC_IRQ_SOURCE_PFLIP1;
	357	case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
	358	return DC_IRQ_SOURCE_PFLIP2;
	359	case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
	360	return DC_IRQ_SOURCE_PFLIP3;
	361	case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
	362	return DC_IRQ_SOURCE_PFLIP4;
	363	case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
	364	return DC_IRQ_SOURCE_PFLIP5;
	365	case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
	366	return DC_IRQ_SOURCE_PFLIP6;
	367
	368	case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
	369	/* generic src_id for all HPD and HPDRX interrupts */
	370	switch (ext_id) {
	371	case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
	372	return DC_IRQ_SOURCE_HPD1;
	373	case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
	374	return DC_IRQ_SOURCE_HPD2;
	375	case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
	376	return DC_IRQ_SOURCE_HPD3;
	377	case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
	378	return DC_IRQ_SOURCE_HPD4;
	379	case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
	380	return DC_IRQ_SOURCE_HPD5;
	381	case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
	382	return DC_IRQ_SOURCE_HPD6;
	383	case VISLANDS30_IV_EXTID_HPD_RX_A:
	384	return DC_IRQ_SOURCE_HPD1RX;
	385	case VISLANDS30_IV_EXTID_HPD_RX_B:
	386	return DC_IRQ_SOURCE_HPD2RX;
	387	case VISLANDS30_IV_EXTID_HPD_RX_C:
	388	return DC_IRQ_SOURCE_HPD3RX;
	389	case VISLANDS30_IV_EXTID_HPD_RX_D:
	390	return DC_IRQ_SOURCE_HPD4RX;
	391	case VISLANDS30_IV_EXTID_HPD_RX_E:
	392	return DC_IRQ_SOURCE_HPD5RX;
	393	case VISLANDS30_IV_EXTID_HPD_RX_F:
	394	return DC_IRQ_SOURCE_HPD6RX;
	395	default:
	396	return DC_IRQ_SOURCE_INVALID;
	397	}
	398	break;
	399
	400	default:
	401	return DC_IRQ_SOURCE_INVALID;
	402	}
	403	}
	404
	405	static const struct irq_service_funcs irq_service_funcs_dce110 = {
	406	.to_dal_irq_source = to_dal_irq_source_dce110
407	};
408
409	bool construct(
410	struct irq_service *irq_service,
411	struct irq_service_init_data *init_data)
412	{
413	if (!dal_irq_service_construct(irq_service, init_data))
414	return false;
415
416	irq_service->info = irq_source_info_dce110;
417	irq_service->funcs = &irq_service_funcs_dce110;
418
419	return true;
420	}
421
422	struct irq_service *dal_irq_service_dce110_create(
423	struct irq_service_init_data *init_data)
424	{
2004f45e HW	425	struct irq_service irq_service = kzalloc(sizeof(irq_service),
2004f45e HW	426	GFP_KERNEL);
4562236b HW	427
	428	if (!irq_service)
	429	return NULL;
	430
	431	if (construct(irq_service, init_data))
	432	return irq_service;
	433
2004f45e	434	kfree(irq_service);
4562236b HW	435	return NULL;
4562236b HW	436	}