[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / display / dc / irq / dce120 / irq_service_dce120.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"

#include "include/logger_interface.h"

#include "irq_service_dce120.h"
#include "../dce110/irq_service_dce110.h"

#include "vega10/DC/dce_12_0_offset.h"
#include "vega10/DC/dce_12_0_sh_mask.h"
#include "vega10/soc15ip.h"

#include "ivsrcid/ivsrcid_vislands30.h"

static bool hpd_ack(
	struct irq_service *irq_service,
	const struct irq_source_info *info)
{
	uint32_t addr = info->status_reg;
	uint32_t value = dm_read_reg(irq_service->ctx, addr);
	uint32_t current_status =
		get_reg_field_value(
			value,
			HPD0_DC_HPD_INT_STATUS,
			DC_HPD_SENSE_DELAYED);

	dal_irq_service_ack_generic(irq_service, info);

	value = dm_read_reg(irq_service->ctx, info->enable_reg);

	set_reg_field_value(
		value,
		current_status ? 0 : 1,
		HPD0_DC_HPD_INT_CONTROL,
		DC_HPD_INT_POLARITY);

	dm_write_reg(irq_service->ctx, info->enable_reg, value);

	return true;
}

static const struct irq_source_info_funcs hpd_irq_info_funcs = {
	.set = NULL,
	.ack = hpd_ack
};

static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
	.set = NULL,
	.ack = NULL
};

static const struct irq_source_info_funcs pflip_irq_info_funcs = {
	.set = NULL,
	.ack = NULL
};

static const struct irq_source_info_funcs vblank_irq_info_funcs = {
	.set = dce110_vblank_set,
	.ack = NULL
};

#define BASE_INNER(seg) \
	DCE_BASE__INST0_SEG ## seg

#define BASE(seg) \
	BASE_INNER(seg)

#define SRI(reg_name, block, id)\
	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
			mm ## block ## id ## _ ## reg_name


#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
	.enable_reg = SRI(reg1, block, reg_num),\
	.enable_mask = \
		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
	.enable_value = {\
		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
	},\
	.ack_reg = SRI(reg2, block, reg_num),\
	.ack_mask = \
		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
	.ack_value = \
		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

#define hpd_int_entry(reg_num)\
	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
		IRQ_REG_ENTRY(HPD, reg_num,\
			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
		.funcs = &hpd_irq_info_funcs\
	}

#define hpd_rx_int_entry(reg_num)\
	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
		IRQ_REG_ENTRY(HPD, reg_num,\
			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
		.funcs = &hpd_rx_irq_info_funcs\
	}
#define pflip_int_entry(reg_num)\
	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
		IRQ_REG_ENTRY(DCP, reg_num, \
			GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
			GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
		.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
		.funcs = &pflip_irq_info_funcs\
	}

#define vupdate_int_entry(reg_num)\
	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
		IRQ_REG_ENTRY(CRTC, reg_num,\
			CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
			CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
		.funcs = &vblank_irq_info_funcs\
	}

#define vblank_int_entry(reg_num)\
	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
		IRQ_REG_ENTRY(CRTC, reg_num,\
				CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
				CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
		.funcs = &vblank_irq_info_funcs,\
		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
	}

#define dummy_irq_entry() \
	{\
		.funcs = &dummy_irq_info_funcs\
	}

#define i2c_int_entry(reg_num) \
	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

#define dp_sink_int_entry(reg_num) \
	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

#define gpio_pad_int_entry(reg_num) \
	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

#define dc_underflow_int_entry(reg_num) \
	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

static const struct irq_source_info_funcs dummy_irq_info_funcs = {
	.set = dal_irq_service_dummy_set,
	.ack = dal_irq_service_dummy_ack
};

static const struct irq_source_info
irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
	hpd_int_entry(0),
	hpd_int_entry(1),
	hpd_int_entry(2),
	hpd_int_entry(3),
	hpd_int_entry(4),
	hpd_int_entry(5),
	hpd_rx_int_entry(0),
	hpd_rx_int_entry(1),
	hpd_rx_int_entry(2),
	hpd_rx_int_entry(3),
	hpd_rx_int_entry(4),
	hpd_rx_int_entry(5),
	i2c_int_entry(1),
	i2c_int_entry(2),
	i2c_int_entry(3),
	i2c_int_entry(4),
	i2c_int_entry(5),
	i2c_int_entry(6),
	dp_sink_int_entry(1),
	dp_sink_int_entry(2),
	dp_sink_int_entry(3),
	dp_sink_int_entry(4),
	dp_sink_int_entry(5),
	dp_sink_int_entry(6),
	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
	pflip_int_entry(0),
	pflip_int_entry(1),
	pflip_int_entry(2),
	pflip_int_entry(3),
	pflip_int_entry(4),
	pflip_int_entry(5),
	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
	gpio_pad_int_entry(0),
	gpio_pad_int_entry(1),
	gpio_pad_int_entry(2),
	gpio_pad_int_entry(3),
	gpio_pad_int_entry(4),
	gpio_pad_int_entry(5),
	gpio_pad_int_entry(6),
	gpio_pad_int_entry(7),
	gpio_pad_int_entry(8),
	gpio_pad_int_entry(9),
	gpio_pad_int_entry(10),
	gpio_pad_int_entry(11),
	gpio_pad_int_entry(12),
	gpio_pad_int_entry(13),
	gpio_pad_int_entry(14),
	gpio_pad_int_entry(15),
	gpio_pad_int_entry(16),
	gpio_pad_int_entry(17),
	gpio_pad_int_entry(18),
	gpio_pad_int_entry(19),
	gpio_pad_int_entry(20),
	gpio_pad_int_entry(21),
	gpio_pad_int_entry(22),
	gpio_pad_int_entry(23),
	gpio_pad_int_entry(24),
	gpio_pad_int_entry(25),
	gpio_pad_int_entry(26),
	gpio_pad_int_entry(27),
	gpio_pad_int_entry(28),
	gpio_pad_int_entry(29),
	gpio_pad_int_entry(30),
	dc_underflow_int_entry(1),
	dc_underflow_int_entry(2),
	dc_underflow_int_entry(3),
	dc_underflow_int_entry(4),
	dc_underflow_int_entry(5),
	dc_underflow_int_entry(6),
	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
	vupdate_int_entry(0),
	vupdate_int_entry(1),
	vupdate_int_entry(2),
	vupdate_int_entry(3),
	vupdate_int_entry(4),
	vupdate_int_entry(5),
	vblank_int_entry(0),
	vblank_int_entry(1),
	vblank_int_entry(2),
	vblank_int_entry(3),
	vblank_int_entry(4),
	vblank_int_entry(5),
};

static const struct irq_service_funcs irq_service_funcs_dce120 = {
		.to_dal_irq_source = to_dal_irq_source_dce110
};

static bool construct(
	struct irq_service *irq_service,
	struct irq_service_init_data *init_data)
{
	if (!dal_irq_service_construct(irq_service, init_data))
		return false;

	irq_service->info = irq_source_info_dce120;
	irq_service->funcs = &irq_service_funcs_dce120;

	return true;
}

struct irq_service *dal_irq_service_dce120_create(
	struct irq_service_init_data *init_data)
{
	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
						  GFP_KERNEL);

	if (!irq_service)
		return NULL;

	if (construct(irq_service, init_data))
		return irq_service;

	kfree(irq_service);
	return NULL;
}
Commit	Line	Data
9a48d684 HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dm_services.h"
	27
	28	#include "include/logger_interface.h"
	29
	30	#include "irq_service_dce120.h"
	31	#include "../dce110/irq_service_dce110.h"
	32
	33	#include "vega10/DC/dce_12_0_offset.h"
	34	#include "vega10/DC/dce_12_0_sh_mask.h"
	35	#include "vega10/soc15ip.h"
	36
	37	#include "ivsrcid/ivsrcid_vislands30.h"
	38
	39	static bool hpd_ack(
	40	struct irq_service *irq_service,
	41	const struct irq_source_info *info)
	42	{
	43	uint32_t addr = info->status_reg;
	44	uint32_t value = dm_read_reg(irq_service->ctx, addr);
	45	uint32_t current_status =
	46	get_reg_field_value(
	47	value,
	48	HPD0_DC_HPD_INT_STATUS,
	49	DC_HPD_SENSE_DELAYED);
	50
	51	dal_irq_service_ack_generic(irq_service, info);
	52
	53	value = dm_read_reg(irq_service->ctx, info->enable_reg);
	54
	55	set_reg_field_value(
	56	value,
	57	current_status ? 0 : 1,
	58	HPD0_DC_HPD_INT_CONTROL,
	59	DC_HPD_INT_POLARITY);
	60
	61	dm_write_reg(irq_service->ctx, info->enable_reg, value);
	62
	63	return true;
	64	}
65
66	static const struct irq_source_info_funcs hpd_irq_info_funcs = {
67	.set = NULL,
68	.ack = hpd_ack
69	};
70
71	static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
72	.set = NULL,
73	.ack = NULL
74	};
75
76	static const struct irq_source_info_funcs pflip_irq_info_funcs = {
77	.set = NULL,
78	.ack = NULL
79	};
80
81	static const struct irq_source_info_funcs vblank_irq_info_funcs = {
667e1498	82	.set = dce110_vblank_set,
9a48d684 HW	83	.ack = NULL
	84	};
	85
	86	#define BASE_INNER(seg) \
	87	DCE_BASE__INST0_SEG ## seg
	88
	89	#define BASE(seg) \
	90	BASE_INNER(seg)
	91
	92	#define SRI(reg_name, block, id)\
	93	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
	94	mm ## block ## id ## _ ## reg_name
	95
	96
	97	#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
	98	.enable_reg = SRI(reg1, block, reg_num),\
	99	.enable_mask = \
	100	block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
	101	.enable_value = {\
	102	block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
	103	~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
	104	},\
	105	.ack_reg = SRI(reg2, block, reg_num),\
	106	.ack_mask = \
	107	block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
	108	.ack_value = \
	109	block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
	110
	111	#define hpd_int_entry(reg_num)\
	112	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
	113	IRQ_REG_ENTRY(HPD, reg_num,\
	114	DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
	115	DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
	116	.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
	117	.funcs = &hpd_irq_info_funcs\
	118	}
	119
	120	#define hpd_rx_int_entry(reg_num)\
	121	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
	122	IRQ_REG_ENTRY(HPD, reg_num,\
	123	DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
	124	DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
	125	.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
	126	.funcs = &hpd_rx_irq_info_funcs\
	127	}
	128	#define pflip_int_entry(reg_num)\
	129	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
	130	IRQ_REG_ENTRY(DCP, reg_num, \
	131	GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
	132	GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
	133	.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
	134	.funcs = &pflip_irq_info_funcs\
	135	}
	136
	137	#define vupdate_int_entry(reg_num)\
	138	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
	139	IRQ_REG_ENTRY(CRTC, reg_num,\
	140	CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
	141	CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
	142	.funcs = &vblank_irq_info_funcs\
	143	}
	144
	145	#define vblank_int_entry(reg_num)\
	146	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
667e1498 AG	147	IRQ_REG_ENTRY(CRTC, reg_num,\
	148	CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
	149	CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
	150	.funcs = &vblank_irq_info_funcs,\
	151	.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
9a48d684 HW	152	}
	153
	154	#define dummy_irq_entry() \
	155	{\
	156	.funcs = &dummy_irq_info_funcs\
	157	}
	158
	159	#define i2c_int_entry(reg_num) \
	160	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
	161
	162	#define dp_sink_int_entry(reg_num) \
	163	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
	164
	165	#define gpio_pad_int_entry(reg_num) \
	166	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
	167
	168	#define dc_underflow_int_entry(reg_num) \
	169	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
	170
	171	static const struct irq_source_info_funcs dummy_irq_info_funcs = {
	172	.set = dal_irq_service_dummy_set,
	173	.ack = dal_irq_service_dummy_ack
	174	};
	175
	176	static const struct irq_source_info
	177	irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
	178	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
	179	hpd_int_entry(0),
	180	hpd_int_entry(1),
	181	hpd_int_entry(2),
	182	hpd_int_entry(3),
	183	hpd_int_entry(4),
	184	hpd_int_entry(5),
	185	hpd_rx_int_entry(0),
	186	hpd_rx_int_entry(1),
	187	hpd_rx_int_entry(2),
	188	hpd_rx_int_entry(3),
	189	hpd_rx_int_entry(4),
	190	hpd_rx_int_entry(5),
	191	i2c_int_entry(1),
	192	i2c_int_entry(2),
	193	i2c_int_entry(3),
	194	i2c_int_entry(4),
	195	i2c_int_entry(5),
	196	i2c_int_entry(6),
	197	dp_sink_int_entry(1),
	198	dp_sink_int_entry(2),
	199	dp_sink_int_entry(3),
	200	dp_sink_int_entry(4),
	201	dp_sink_int_entry(5),
	202	dp_sink_int_entry(6),
	203	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
	204	pflip_int_entry(0),
	205	pflip_int_entry(1),
	206	pflip_int_entry(2),
	207	pflip_int_entry(3),
	208	pflip_int_entry(4),
	209	pflip_int_entry(5),
	210	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
	211	gpio_pad_int_entry(0),
	212	gpio_pad_int_entry(1),
	213	gpio_pad_int_entry(2),
	214	gpio_pad_int_entry(3),
	215	gpio_pad_int_entry(4),
216	gpio_pad_int_entry(5),
217	gpio_pad_int_entry(6),
218	gpio_pad_int_entry(7),
219	gpio_pad_int_entry(8),
220	gpio_pad_int_entry(9),
221	gpio_pad_int_entry(10),
222	gpio_pad_int_entry(11),
223	gpio_pad_int_entry(12),
224	gpio_pad_int_entry(13),
225	gpio_pad_int_entry(14),
226	gpio_pad_int_entry(15),
227	gpio_pad_int_entry(16),
228	gpio_pad_int_entry(17),
229	gpio_pad_int_entry(18),
230	gpio_pad_int_entry(19),
231	gpio_pad_int_entry(20),
232	gpio_pad_int_entry(21),
233	gpio_pad_int_entry(22),
234	gpio_pad_int_entry(23),
235	gpio_pad_int_entry(24),
236	gpio_pad_int_entry(25),
237	gpio_pad_int_entry(26),
238	gpio_pad_int_entry(27),
239	gpio_pad_int_entry(28),
240	gpio_pad_int_entry(29),
241	gpio_pad_int_entry(30),
242	dc_underflow_int_entry(1),
243	dc_underflow_int_entry(2),
244	dc_underflow_int_entry(3),
245	dc_underflow_int_entry(4),
246	dc_underflow_int_entry(5),
247	dc_underflow_int_entry(6),
248	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
249	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
250	vupdate_int_entry(0),
251	vupdate_int_entry(1),
252	vupdate_int_entry(2),
253	vupdate_int_entry(3),
254	vupdate_int_entry(4),
255	vupdate_int_entry(5),
256	vblank_int_entry(0),
257	vblank_int_entry(1),
258	vblank_int_entry(2),
259	vblank_int_entry(3),
260	vblank_int_entry(4),
261	vblank_int_entry(5),
262	};
263
264	static const struct irq_service_funcs irq_service_funcs_dce120 = {
265	.to_dal_irq_source = to_dal_irq_source_dce110
266	};
267
268	static bool construct(
269	struct irq_service *irq_service,
270	struct irq_service_init_data *init_data)
271	{
272	if (!dal_irq_service_construct(irq_service, init_data))
273	return false;
274
275	irq_service->info = irq_source_info_dce120;
276	irq_service->funcs = &irq_service_funcs_dce120;
277
278	return true;
279	}
280
281	struct irq_service *dal_irq_service_dce120_create(
282	struct irq_service_init_data *init_data)
283	{
2004f45e HW	284	struct irq_service irq_service = kzalloc(sizeof(irq_service),
2004f45e HW	285	GFP_KERNEL);
9a48d684 HW	286
	287	if (!irq_service)
	288	return NULL;
	289
	290	if (construct(irq_service, init_data))
	291	return irq_service;
	292
2004f45e	293	kfree(irq_service);
9a48d684 HW	294	return NULL;
9a48d684 HW	295	}