[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / display / dc / irq / dce80 / irq_service_dce80.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"

#include "include/logger_interface.h"

#include "irq_service_dce80.h"
#include "../dce110/irq_service_dce110.h"

#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"

#include "ivsrcid/ivsrcid_vislands30.h"

#include "dc_types.h"

static bool hpd_ack(
	struct irq_service *irq_service,
	const struct irq_source_info *info)
{
	uint32_t addr = info->status_reg;
	uint32_t value = dm_read_reg(irq_service->ctx, addr);
	uint32_t current_status =
		get_reg_field_value(
			value,
			DC_HPD1_INT_STATUS,
			DC_HPD1_SENSE_DELAYED);

	dal_irq_service_ack_generic(irq_service, info);

	value = dm_read_reg(irq_service->ctx, info->enable_reg);

	set_reg_field_value(
		value,
		current_status ? 0 : 1,
		DC_HPD1_INT_CONTROL,
		DC_HPD1_INT_POLARITY);

	dm_write_reg(irq_service->ctx, info->enable_reg, value);

	return true;
}

static const struct irq_source_info_funcs hpd_irq_info_funcs = {
	.set = NULL,
	.ack = hpd_ack
};

static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
	.set = NULL,
	.ack = NULL
};

static const struct irq_source_info_funcs pflip_irq_info_funcs = {
	.set = NULL,
	.ack = NULL
};

static const struct irq_source_info_funcs vblank_irq_info_funcs = {
	.set = dce110_vblank_set,
	.ack = NULL
};


#define hpd_int_entry(reg_num)\
	[DC_IRQ_SOURCE_INVALID + reg_num] = {\
		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
		.enable_value = {\
			DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
			~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
		},\
		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
		.funcs = &hpd_irq_info_funcs\
	}

#define hpd_rx_int_entry(reg_num)\
	[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
		.enable_value = {\
				DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
			~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
		.funcs = &hpd_rx_irq_info_funcs\
	}

#define pflip_int_entry(reg_num)\
	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
		.enable_mask =\
		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
		.enable_value = {\
			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
		.funcs = &pflip_irq_info_funcs\
 	}

#define vupdate_int_entry(reg_num)\
	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
		.enable_mask =\
		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
		.enable_value = {\
			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
		.ack_mask =\
		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
		.ack_value =\
		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
		.funcs = &vblank_irq_info_funcs\
	}

#define vblank_int_entry(reg_num)\
	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
		.enable_mask =\
		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
		.enable_value = {\
			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
		.ack_mask =\
		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
		.ack_value =\
		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
		.funcs = &vblank_irq_info_funcs,\
		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
	}

#define dummy_irq_entry() \
	{\
		.funcs = &dummy_irq_info_funcs\
	}

#define i2c_int_entry(reg_num) \
	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

#define dp_sink_int_entry(reg_num) \
	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

#define gpio_pad_int_entry(reg_num) \
	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

#define dc_underflow_int_entry(reg_num) \
	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()


static const struct irq_source_info_funcs dummy_irq_info_funcs = {
	.set = dal_irq_service_dummy_set,
	.ack = dal_irq_service_dummy_ack
};

static const struct irq_source_info
irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
	hpd_int_entry(1),
	hpd_int_entry(2),
	hpd_int_entry(3),
	hpd_int_entry(4),
	hpd_int_entry(5),
	hpd_int_entry(6),
	hpd_rx_int_entry(1),
	hpd_rx_int_entry(2),
	hpd_rx_int_entry(3),
	hpd_rx_int_entry(4),
	hpd_rx_int_entry(5),
	hpd_rx_int_entry(6),
	i2c_int_entry(1),
	i2c_int_entry(2),
	i2c_int_entry(3),
	i2c_int_entry(4),
	i2c_int_entry(5),
	i2c_int_entry(6),
	dp_sink_int_entry(1),
	dp_sink_int_entry(2),
	dp_sink_int_entry(3),
	dp_sink_int_entry(4),
	dp_sink_int_entry(5),
	dp_sink_int_entry(6),
	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
	pflip_int_entry(0),
	pflip_int_entry(1),
	pflip_int_entry(2),
	pflip_int_entry(3),
	pflip_int_entry(4),
	pflip_int_entry(5),
	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
	gpio_pad_int_entry(0),
	gpio_pad_int_entry(1),
	gpio_pad_int_entry(2),
	gpio_pad_int_entry(3),
	gpio_pad_int_entry(4),
	gpio_pad_int_entry(5),
	gpio_pad_int_entry(6),
	gpio_pad_int_entry(7),
	gpio_pad_int_entry(8),
	gpio_pad_int_entry(9),
	gpio_pad_int_entry(10),
	gpio_pad_int_entry(11),
	gpio_pad_int_entry(12),
	gpio_pad_int_entry(13),
	gpio_pad_int_entry(14),
	gpio_pad_int_entry(15),
	gpio_pad_int_entry(16),
	gpio_pad_int_entry(17),
	gpio_pad_int_entry(18),
	gpio_pad_int_entry(19),
	gpio_pad_int_entry(20),
	gpio_pad_int_entry(21),
	gpio_pad_int_entry(22),
	gpio_pad_int_entry(23),
	gpio_pad_int_entry(24),
	gpio_pad_int_entry(25),
	gpio_pad_int_entry(26),
	gpio_pad_int_entry(27),
	gpio_pad_int_entry(28),
	gpio_pad_int_entry(29),
	gpio_pad_int_entry(30),
	dc_underflow_int_entry(1),
	dc_underflow_int_entry(2),
	dc_underflow_int_entry(3),
	dc_underflow_int_entry(4),
	dc_underflow_int_entry(5),
	dc_underflow_int_entry(6),
	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
	vupdate_int_entry(0),
	vupdate_int_entry(1),
	vupdate_int_entry(2),
	vupdate_int_entry(3),
	vupdate_int_entry(4),
	vupdate_int_entry(5),
	vblank_int_entry(0),
	vblank_int_entry(1),
	vblank_int_entry(2),
	vblank_int_entry(3),
	vblank_int_entry(4),
	vblank_int_entry(5),
};

static const struct irq_service_funcs irq_service_funcs_dce80 = {
		.to_dal_irq_source = to_dal_irq_source_dce110
};

static bool construct(
	struct irq_service *irq_service,
	struct irq_service_init_data *init_data)
{
	if (!dal_irq_service_construct(irq_service, init_data))
		return false;

	irq_service->info = irq_source_info_dce80;
	irq_service->funcs = &irq_service_funcs_dce80;

	return true;
}

struct irq_service *dal_irq_service_dce80_create(
	struct irq_service_init_data *init_data)
{
	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
						  GFP_KERNEL);

	if (!irq_service)
		return NULL;

	if (construct(irq_service, init_data))
		return irq_service;

	kfree(irq_service);
	return NULL;
}
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dm_services.h"
	27
	28	#include "include/logger_interface.h"
	29
	30	#include "irq_service_dce80.h"
	31	#include "../dce110/irq_service_dce110.h"
	32
	33	#include "dce/dce_8_0_d.h"
	34	#include "dce/dce_8_0_sh_mask.h"
	35
	36	#include "ivsrcid/ivsrcid_vislands30.h"
	37
667e1498	38	#include "dc_types.h"
667e1498	39
4562236b HW	40	static bool hpd_ack(
	41	struct irq_service *irq_service,
	42	const struct irq_source_info *info)
	43	{
	44	uint32_t addr = info->status_reg;
	45	uint32_t value = dm_read_reg(irq_service->ctx, addr);
	46	uint32_t current_status =
	47	get_reg_field_value(
	48	value,
	49	DC_HPD1_INT_STATUS,
	50	DC_HPD1_SENSE_DELAYED);
	51
	52	dal_irq_service_ack_generic(irq_service, info);
	53
	54	value = dm_read_reg(irq_service->ctx, info->enable_reg);
	55
	56	set_reg_field_value(
	57	value,
	58	current_status ? 0 : 1,
	59	DC_HPD1_INT_CONTROL,
	60	DC_HPD1_INT_POLARITY);
	61
	62	dm_write_reg(irq_service->ctx, info->enable_reg, value);
	63
	64	return true;
	65	}
	66
	67	static const struct irq_source_info_funcs hpd_irq_info_funcs = {
	68	.set = NULL,
	69	.ack = hpd_ack
	70	};
	71
	72	static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
	73	.set = NULL,
	74	.ack = NULL
	75	};
	76
	77	static const struct irq_source_info_funcs pflip_irq_info_funcs = {
	78	.set = NULL,
	79	.ack = NULL
	80	};
	81
	82	static const struct irq_source_info_funcs vblank_irq_info_funcs = {
667e1498	83	.set = dce110_vblank_set,
4562236b HW	84	.ack = NULL
	85	};
	86
	87
	88	#define hpd_int_entry(reg_num)\
	89	[DC_IRQ_SOURCE_INVALID + reg_num] = {\
	90	.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
	91	.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
	92	.enable_value = {\
	93	DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
	94	~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
	95	},\
	96	.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
	97	.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
	98	.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
	99	.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
	100	.funcs = &hpd_irq_info_funcs\
	101	}
	102
	103	#define hpd_rx_int_entry(reg_num)\
	104	[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
	105	.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
	106	.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
	107	.enable_value = {\
	108	DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
	109	~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
	110	.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
	111	.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
	112	.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
	113	.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
	114	.funcs = &hpd_rx_irq_info_funcs\
	115	}
	116
	117	#define pflip_int_entry(reg_num)\
	118	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
	119	.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
	120	.enable_mask =\
	121	GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
	122	.enable_value = {\
	123	GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
	124	~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
	125	.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
	126	.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
	127	.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
	128	.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
	129	.funcs = &pflip_irq_info_funcs\
	130	}
	131
	132	#define vupdate_int_entry(reg_num)\
	133	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
	134	.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
	135	.enable_mask =\
	136	CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
	137	.enable_value = {\
	138	CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
	139	~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
	140	.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
	141	.ack_mask =\
	142	CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
	143	.ack_value =\
	144	CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
	145	.funcs = &vblank_irq_info_funcs\
	146	}
	147
b10d51f8 AG	148	#define vblank_int_entry(reg_num)\
b10d51f8 AG	149	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
667e1498	150	.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
b10d51f8	151	.enable_mask =\
667e1498	152	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
b10d51f8	153	.enable_value = {\
667e1498 AG	154	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
	155	~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
	156	.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
b10d51f8	157	.ack_mask =\
667e1498	158	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
b10d51f8	159	.ack_value =\
667e1498 AG	160	CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
	161	.funcs = &vblank_irq_info_funcs,\
	162	.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
b10d51f8 AG	163	}
b10d51f8 AG	164
4562236b HW	165	#define dummy_irq_entry() \
	166	{\
	167	.funcs = &dummy_irq_info_funcs\
	168	}
	169
	170	#define i2c_int_entry(reg_num) \
	171	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
	172
	173	#define dp_sink_int_entry(reg_num) \
	174	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
	175
	176	#define gpio_pad_int_entry(reg_num) \
	177	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
	178
	179	#define dc_underflow_int_entry(reg_num) \
	180	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
	181
	182
	183	static const struct irq_source_info_funcs dummy_irq_info_funcs = {
	184	.set = dal_irq_service_dummy_set,
	185	.ack = dal_irq_service_dummy_ack
	186	};
	187
	188	static const struct irq_source_info
	189	irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
	190	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
	191	hpd_int_entry(1),
	192	hpd_int_entry(2),
	193	hpd_int_entry(3),
	194	hpd_int_entry(4),
	195	hpd_int_entry(5),
	196	hpd_int_entry(6),
	197	hpd_rx_int_entry(1),
	198	hpd_rx_int_entry(2),
	199	hpd_rx_int_entry(3),
	200	hpd_rx_int_entry(4),
	201	hpd_rx_int_entry(5),
	202	hpd_rx_int_entry(6),
	203	i2c_int_entry(1),
	204	i2c_int_entry(2),
	205	i2c_int_entry(3),
	206	i2c_int_entry(4),
	207	i2c_int_entry(5),
	208	i2c_int_entry(6),
	209	dp_sink_int_entry(1),
	210	dp_sink_int_entry(2),
	211	dp_sink_int_entry(3),
	212	dp_sink_int_entry(4),
	213	dp_sink_int_entry(5),
	214	dp_sink_int_entry(6),
	215	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
	216	pflip_int_entry(0),
	217	pflip_int_entry(1),
	218	pflip_int_entry(2),
	219	pflip_int_entry(3),
	220	pflip_int_entry(4),
	221	pflip_int_entry(5),
	222	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
	223	gpio_pad_int_entry(0),
	224	gpio_pad_int_entry(1),
	225	gpio_pad_int_entry(2),
	226	gpio_pad_int_entry(3),
	227	gpio_pad_int_entry(4),
	228	gpio_pad_int_entry(5),
229	gpio_pad_int_entry(6),
230	gpio_pad_int_entry(7),
231	gpio_pad_int_entry(8),
232	gpio_pad_int_entry(9),
233	gpio_pad_int_entry(10),
234	gpio_pad_int_entry(11),
235	gpio_pad_int_entry(12),
236	gpio_pad_int_entry(13),
237	gpio_pad_int_entry(14),
238	gpio_pad_int_entry(15),
239	gpio_pad_int_entry(16),
240	gpio_pad_int_entry(17),
241	gpio_pad_int_entry(18),
242	gpio_pad_int_entry(19),
243	gpio_pad_int_entry(20),
244	gpio_pad_int_entry(21),
245	gpio_pad_int_entry(22),
246	gpio_pad_int_entry(23),
247	gpio_pad_int_entry(24),
248	gpio_pad_int_entry(25),
249	gpio_pad_int_entry(26),
250	gpio_pad_int_entry(27),
251	gpio_pad_int_entry(28),
252	gpio_pad_int_entry(29),
253	gpio_pad_int_entry(30),
254	dc_underflow_int_entry(1),
255	dc_underflow_int_entry(2),
256	dc_underflow_int_entry(3),
257	dc_underflow_int_entry(4),
258	dc_underflow_int_entry(5),
259	dc_underflow_int_entry(6),
260	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
261	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
262	vupdate_int_entry(0),
263	vupdate_int_entry(1),
264	vupdate_int_entry(2),
265	vupdate_int_entry(3),
266	vupdate_int_entry(4),
267	vupdate_int_entry(5),
b10d51f8 AG	268	vblank_int_entry(0),
	269	vblank_int_entry(1),
	270	vblank_int_entry(2),
	271	vblank_int_entry(3),
	272	vblank_int_entry(4),
	273	vblank_int_entry(5),
4562236b HW	274	};
	275
	276	static const struct irq_service_funcs irq_service_funcs_dce80 = {
	277	.to_dal_irq_source = to_dal_irq_source_dce110
	278	};
	279
	280	static bool construct(
	281	struct irq_service *irq_service,
	282	struct irq_service_init_data *init_data)
	283	{
	284	if (!dal_irq_service_construct(irq_service, init_data))
	285	return false;
	286
	287	irq_service->info = irq_source_info_dce80;
	288	irq_service->funcs = &irq_service_funcs_dce80;
	289
	290	return true;
	291	}
	292
	293	struct irq_service *dal_irq_service_dce80_create(
	294	struct irq_service_init_data *init_data)
	295	{
2004f45e HW	296	struct irq_service irq_service = kzalloc(sizeof(irq_service),
2004f45e HW	297	GFP_KERNEL);
4562236b HW	298
	299	if (!irq_service)
	300	return NULL;
	301
	302	if (construct(irq_service, init_data))
	303	return irq_service;
	304
2004f45e	305	kfree(irq_service);
4562236b HW	306	return NULL;
	307	}
	308
	309