[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / irq_types.h

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DAL_IRQ_TYPES_H__
#define __DAL_IRQ_TYPES_H__

struct dc_context;

typedef void (*interrupt_handler)(void *);

typedef void *irq_handler_idx;
#define DAL_INVALID_IRQ_HANDLER_IDX NULL

/* The order of the IRQ sources is important and MUST match the one's
of base driver */
enum dc_irq_source {
	/* Use as mask to specify invalid irq source */
	DC_IRQ_SOURCE_INVALID = 0,

	DC_IRQ_SOURCE_HPD1,
	DC_IRQ_SOURCE_HPD2,
	DC_IRQ_SOURCE_HPD3,
	DC_IRQ_SOURCE_HPD4,
	DC_IRQ_SOURCE_HPD5,
	DC_IRQ_SOURCE_HPD6,

	DC_IRQ_SOURCE_HPD1RX,
	DC_IRQ_SOURCE_HPD2RX,
	DC_IRQ_SOURCE_HPD3RX,
	DC_IRQ_SOURCE_HPD4RX,
	DC_IRQ_SOURCE_HPD5RX,
	DC_IRQ_SOURCE_HPD6RX,

	DC_IRQ_SOURCE_I2C_DDC1,
	DC_IRQ_SOURCE_I2C_DDC2,
	DC_IRQ_SOURCE_I2C_DDC3,
	DC_IRQ_SOURCE_I2C_DDC4,
	DC_IRQ_SOURCE_I2C_DDC5,
	DC_IRQ_SOURCE_I2C_DDC6,

	DC_IRQ_SOURCE_DPSINK1,
	DC_IRQ_SOURCE_DPSINK2,
	DC_IRQ_SOURCE_DPSINK3,
	DC_IRQ_SOURCE_DPSINK4,
	DC_IRQ_SOURCE_DPSINK5,
	DC_IRQ_SOURCE_DPSINK6,

	DC_IRQ_SOURCE_TIMER,

	DC_IRQ_SOURCE_PFLIP_FIRST,
	DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST,
	DC_IRQ_SOURCE_PFLIP2,
	DC_IRQ_SOURCE_PFLIP3,
	DC_IRQ_SOURCE_PFLIP4,
	DC_IRQ_SOURCE_PFLIP5,
	DC_IRQ_SOURCE_PFLIP6,
	DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
	DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0,

	DC_IRQ_SOURCE_GPIOPAD0,
	DC_IRQ_SOURCE_GPIOPAD1,
	DC_IRQ_SOURCE_GPIOPAD2,
	DC_IRQ_SOURCE_GPIOPAD3,
	DC_IRQ_SOURCE_GPIOPAD4,
	DC_IRQ_SOURCE_GPIOPAD5,
	DC_IRQ_SOURCE_GPIOPAD6,
	DC_IRQ_SOURCE_GPIOPAD7,
	DC_IRQ_SOURCE_GPIOPAD8,
	DC_IRQ_SOURCE_GPIOPAD9,
	DC_IRQ_SOURCE_GPIOPAD10,
	DC_IRQ_SOURCE_GPIOPAD11,
	DC_IRQ_SOURCE_GPIOPAD12,
	DC_IRQ_SOURCE_GPIOPAD13,
	DC_IRQ_SOURCE_GPIOPAD14,
	DC_IRQ_SOURCE_GPIOPAD15,
	DC_IRQ_SOURCE_GPIOPAD16,
	DC_IRQ_SOURCE_GPIOPAD17,
	DC_IRQ_SOURCE_GPIOPAD18,
	DC_IRQ_SOURCE_GPIOPAD19,
	DC_IRQ_SOURCE_GPIOPAD20,
	DC_IRQ_SOURCE_GPIOPAD21,
	DC_IRQ_SOURCE_GPIOPAD22,
	DC_IRQ_SOURCE_GPIOPAD23,
	DC_IRQ_SOURCE_GPIOPAD24,
	DC_IRQ_SOURCE_GPIOPAD25,
	DC_IRQ_SOURCE_GPIOPAD26,
	DC_IRQ_SOURCE_GPIOPAD27,
	DC_IRQ_SOURCE_GPIOPAD28,
	DC_IRQ_SOURCE_GPIOPAD29,
	DC_IRQ_SOURCE_GPIOPAD30,

	DC_IRQ_SOURCE_DC1UNDERFLOW,
	DC_IRQ_SOURCE_DC2UNDERFLOW,
	DC_IRQ_SOURCE_DC3UNDERFLOW,
	DC_IRQ_SOURCE_DC4UNDERFLOW,
	DC_IRQ_SOURCE_DC5UNDERFLOW,
	DC_IRQ_SOURCE_DC6UNDERFLOW,

	DC_IRQ_SOURCE_DMCU_SCP,
	DC_IRQ_SOURCE_VBIOS_SW,

	DC_IRQ_SOURCE_VUPDATE1,
	DC_IRQ_SOURCE_VUPDATE2,
	DC_IRQ_SOURCE_VUPDATE3,
	DC_IRQ_SOURCE_VUPDATE4,
	DC_IRQ_SOURCE_VUPDATE5,
	DC_IRQ_SOURCE_VUPDATE6,

	DC_IRQ_SOURCE_VBLANK1,
	DC_IRQ_SOURCE_VBLANK2,
	DC_IRQ_SOURCE_VBLANK3,
	DC_IRQ_SOURCE_VBLANK4,
	DC_IRQ_SOURCE_VBLANK5,
	DC_IRQ_SOURCE_VBLANK6,

	DAL_IRQ_SOURCES_NUMBER
};

enum irq_type
{
	IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
	IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
};

#define DAL_VALID_IRQ_SRC_NUM(src) \
	((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID)

/* Number of Page Flip IRQ Sources. */
#define DAL_PFLIP_IRQ_SRC_NUM \
	(DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1)

/* the number of contexts may be expanded in the future based on needs */
enum dc_interrupt_context {
	INTERRUPT_LOW_IRQ_CONTEXT = 0,
	INTERRUPT_HIGH_IRQ_CONTEXT,
	INTERRUPT_CONTEXT_NUMBER
};

enum dc_interrupt_porlarity {
	INTERRUPT_POLARITY_DEFAULT = 0,
	INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
	INTERRUPT_POLARITY_HIGH,
	INTERRUPT_POLARITY_BOTH
};

#define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \
	(int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
	(int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"

struct dc_timer_interrupt_params {
	uint32_t micro_sec_interval;
	enum dc_interrupt_context int_context;
};

struct dc_interrupt_params {
	/* The polarity *change* which will trigger an interrupt.
	 * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
	 * 'current_polarity' must be initialised. */
	enum dc_interrupt_porlarity requested_polarity;
	/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
	 * 'current_polarity' should contain the current state, which means
	 * the interrupt will be triggered when state changes from what is,
	 * in 'current_polarity'. */
	enum dc_interrupt_porlarity current_polarity;
	enum dc_irq_source irq_source;
	enum dc_interrupt_context int_context;
};

#endif
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DAL_IRQ_TYPES_H__
	27	#define __DAL_IRQ_TYPES_H__
	28
	29	struct dc_context;
	30
	31	typedef void (interrupt_handler)(void );
	32
	33	typedef void *irq_handler_idx;
	34	#define DAL_INVALID_IRQ_HANDLER_IDX NULL
	35
	36	/* The order of the IRQ sources is important and MUST match the one's
	37	of base driver */
	38	enum dc_irq_source {
	39	/* Use as mask to specify invalid irq source */
	40	DC_IRQ_SOURCE_INVALID = 0,
	41
	42	DC_IRQ_SOURCE_HPD1,
	43	DC_IRQ_SOURCE_HPD2,
	44	DC_IRQ_SOURCE_HPD3,
	45	DC_IRQ_SOURCE_HPD4,
	46	DC_IRQ_SOURCE_HPD5,
	47	DC_IRQ_SOURCE_HPD6,
	48
	49	DC_IRQ_SOURCE_HPD1RX,
	50	DC_IRQ_SOURCE_HPD2RX,
	51	DC_IRQ_SOURCE_HPD3RX,
	52	DC_IRQ_SOURCE_HPD4RX,
	53	DC_IRQ_SOURCE_HPD5RX,
	54	DC_IRQ_SOURCE_HPD6RX,
	55
	56	DC_IRQ_SOURCE_I2C_DDC1,
	57	DC_IRQ_SOURCE_I2C_DDC2,
	58	DC_IRQ_SOURCE_I2C_DDC3,
	59	DC_IRQ_SOURCE_I2C_DDC4,
	60	DC_IRQ_SOURCE_I2C_DDC5,
	61	DC_IRQ_SOURCE_I2C_DDC6,
	62
	63	DC_IRQ_SOURCE_DPSINK1,
	64	DC_IRQ_SOURCE_DPSINK2,
65	DC_IRQ_SOURCE_DPSINK3,
66	DC_IRQ_SOURCE_DPSINK4,
67	DC_IRQ_SOURCE_DPSINK5,
68	DC_IRQ_SOURCE_DPSINK6,
69
70	DC_IRQ_SOURCE_TIMER,
71
72	DC_IRQ_SOURCE_PFLIP_FIRST,
73	DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST,
74	DC_IRQ_SOURCE_PFLIP2,
75	DC_IRQ_SOURCE_PFLIP3,
76	DC_IRQ_SOURCE_PFLIP4,
77	DC_IRQ_SOURCE_PFLIP5,
78	DC_IRQ_SOURCE_PFLIP6,
79	DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
80	DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
81
82	DC_IRQ_SOURCE_GPIOPAD0,
83	DC_IRQ_SOURCE_GPIOPAD1,
84	DC_IRQ_SOURCE_GPIOPAD2,
85	DC_IRQ_SOURCE_GPIOPAD3,
86	DC_IRQ_SOURCE_GPIOPAD4,
87	DC_IRQ_SOURCE_GPIOPAD5,
88	DC_IRQ_SOURCE_GPIOPAD6,
89	DC_IRQ_SOURCE_GPIOPAD7,
90	DC_IRQ_SOURCE_GPIOPAD8,
91	DC_IRQ_SOURCE_GPIOPAD9,
92	DC_IRQ_SOURCE_GPIOPAD10,
93	DC_IRQ_SOURCE_GPIOPAD11,
94	DC_IRQ_SOURCE_GPIOPAD12,
95	DC_IRQ_SOURCE_GPIOPAD13,
96	DC_IRQ_SOURCE_GPIOPAD14,
97	DC_IRQ_SOURCE_GPIOPAD15,
98	DC_IRQ_SOURCE_GPIOPAD16,
99	DC_IRQ_SOURCE_GPIOPAD17,
100	DC_IRQ_SOURCE_GPIOPAD18,
101	DC_IRQ_SOURCE_GPIOPAD19,
102	DC_IRQ_SOURCE_GPIOPAD20,
103	DC_IRQ_SOURCE_GPIOPAD21,
104	DC_IRQ_SOURCE_GPIOPAD22,
105	DC_IRQ_SOURCE_GPIOPAD23,
106	DC_IRQ_SOURCE_GPIOPAD24,
107	DC_IRQ_SOURCE_GPIOPAD25,
108	DC_IRQ_SOURCE_GPIOPAD26,
109	DC_IRQ_SOURCE_GPIOPAD27,
110	DC_IRQ_SOURCE_GPIOPAD28,
111	DC_IRQ_SOURCE_GPIOPAD29,
112	DC_IRQ_SOURCE_GPIOPAD30,
113
114	DC_IRQ_SOURCE_DC1UNDERFLOW,
115	DC_IRQ_SOURCE_DC2UNDERFLOW,
116	DC_IRQ_SOURCE_DC3UNDERFLOW,
117	DC_IRQ_SOURCE_DC4UNDERFLOW,
118	DC_IRQ_SOURCE_DC5UNDERFLOW,
119	DC_IRQ_SOURCE_DC6UNDERFLOW,
120
121	DC_IRQ_SOURCE_DMCU_SCP,
122	DC_IRQ_SOURCE_VBIOS_SW,
123
124	DC_IRQ_SOURCE_VUPDATE1,
125	DC_IRQ_SOURCE_VUPDATE2,
126	DC_IRQ_SOURCE_VUPDATE3,
127	DC_IRQ_SOURCE_VUPDATE4,
128	DC_IRQ_SOURCE_VUPDATE5,
129	DC_IRQ_SOURCE_VUPDATE6,
130
b10d51f8 AG	131	DC_IRQ_SOURCE_VBLANK1,
	132	DC_IRQ_SOURCE_VBLANK2,
	133	DC_IRQ_SOURCE_VBLANK3,
	134	DC_IRQ_SOURCE_VBLANK4,
	135	DC_IRQ_SOURCE_VBLANK5,
	136	DC_IRQ_SOURCE_VBLANK6,
	137
4562236b HW	138	DAL_IRQ_SOURCES_NUMBER
	139	};
	140
	141	enum irq_type
	142	{
	143	IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
	144	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
b10d51f8	145	IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
4562236b HW	146	};
	147
	148	#define DAL_VALID_IRQ_SRC_NUM(src) \
	149	((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID)
	150
	151	/* Number of Page Flip IRQ Sources. */
	152	#define DAL_PFLIP_IRQ_SRC_NUM \
	153	(DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1)
	154
	155	/* the number of contexts may be expanded in the future based on needs */
	156	enum dc_interrupt_context {
	157	INTERRUPT_LOW_IRQ_CONTEXT = 0,
	158	INTERRUPT_HIGH_IRQ_CONTEXT,
	159	INTERRUPT_CONTEXT_NUMBER
	160	};
	161
	162	enum dc_interrupt_porlarity {
	163	INTERRUPT_POLARITY_DEFAULT = 0,
	164	INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
	165	INTERRUPT_POLARITY_HIGH,
	166	INTERRUPT_POLARITY_BOTH
	167	};
	168
	169	#define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \
	170	(int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
	171	(int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
	172	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
	173
	174	struct dc_timer_interrupt_params {
	175	uint32_t micro_sec_interval;
	176	enum dc_interrupt_context int_context;
	177	};
	178
	179	struct dc_interrupt_params {
	180	/* The polarity change which will trigger an interrupt.
	181	* If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
	182	* 'current_polarity' must be initialised. */
	183	enum dc_interrupt_porlarity requested_polarity;
	184	/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
	185	* 'current_polarity' should contain the current state, which means
	186	* the interrupt will be triggered when state changes from what is,
	187	* in 'current_polarity'. */
	188	enum dc_interrupt_porlarity current_polarity;
	189	enum dc_irq_source irq_source;
	190	enum dc_interrupt_context int_context;
	191	};
	192
	193	#endif