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5fc3aeeb | 1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #ifndef __AMD_SHARED_H__ | |
24 | #define __AMD_SHARED_H__ | |
25 | ||
0b2daf09 JZ |
26 | #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
27 | ||
28 | /* | |
29 | * Supported GPU families (aligned with amdgpu_drm.h) | |
30 | */ | |
31 | #define AMD_FAMILY_UNKNOWN 0 | |
32 | #define AMD_FAMILY_CI 120 /* Bonaire, Hawaii */ | |
33 | #define AMD_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
34 | #define AMD_FAMILY_VI 130 /* Iceland, Tonga */ | |
35 | #define AMD_FAMILY_CZ 135 /* Carrizo */ | |
36 | ||
2f7d10b3 JZ |
37 | /* |
38 | * Supported ASIC types | |
39 | */ | |
40 | enum amd_asic_type { | |
41 | CHIP_BONAIRE = 0, | |
42 | CHIP_KAVERI, | |
43 | CHIP_KABINI, | |
44 | CHIP_HAWAII, | |
45 | CHIP_MULLINS, | |
46 | CHIP_TOPAZ, | |
47 | CHIP_TONGA, | |
48299f95 | 48 | CHIP_FIJI, |
2f7d10b3 | 49 | CHIP_CARRIZO, |
139f4917 | 50 | CHIP_STONEY, |
2f7d10b3 JZ |
51 | CHIP_LAST, |
52 | }; | |
53 | ||
54 | /* | |
55 | * Chip flags | |
56 | */ | |
57 | enum amd_chip_flags { | |
58 | AMD_ASIC_MASK = 0x0000ffffUL, | |
59 | AMD_FLAGS_MASK = 0xffff0000UL, | |
60 | AMD_IS_MOBILITY = 0x00010000UL, | |
61 | AMD_IS_APU = 0x00020000UL, | |
62 | AMD_IS_PX = 0x00040000UL, | |
63 | AMD_EXP_HW_SUPPORT = 0x00080000UL, | |
64 | }; | |
65 | ||
5fc3aeeb | 66 | enum amd_ip_block_type { |
67 | AMD_IP_BLOCK_TYPE_COMMON, | |
68 | AMD_IP_BLOCK_TYPE_GMC, | |
69 | AMD_IP_BLOCK_TYPE_IH, | |
70 | AMD_IP_BLOCK_TYPE_SMC, | |
71 | AMD_IP_BLOCK_TYPE_DCE, | |
72 | AMD_IP_BLOCK_TYPE_GFX, | |
73 | AMD_IP_BLOCK_TYPE_SDMA, | |
74 | AMD_IP_BLOCK_TYPE_UVD, | |
75 | AMD_IP_BLOCK_TYPE_VCE, | |
a8fe58ce | 76 | AMD_IP_BLOCK_TYPE_ACP, |
5fc3aeeb | 77 | }; |
78 | ||
79 | enum amd_clockgating_state { | |
80 | AMD_CG_STATE_GATE = 0, | |
81 | AMD_CG_STATE_UNGATE, | |
82 | }; | |
83 | ||
84 | enum amd_powergating_state { | |
85 | AMD_PG_STATE_GATE = 0, | |
86 | AMD_PG_STATE_UNGATE, | |
87 | }; | |
88 | ||
e3b04bc7 AD |
89 | /* CG flags */ |
90 | #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) | |
91 | #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) | |
92 | #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) | |
93 | #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) | |
94 | #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) | |
95 | #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) | |
96 | #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) | |
97 | #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) | |
98 | #define AMD_CG_SUPPORT_MC_LS (1 << 8) | |
99 | #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) | |
100 | #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) | |
101 | #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) | |
102 | #define AMD_CG_SUPPORT_BIF_LS (1 << 12) | |
103 | #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) | |
104 | #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) | |
105 | #define AMD_CG_SUPPORT_HDP_LS (1 << 15) | |
106 | #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) | |
107 | ||
108 | /* PG flags */ | |
109 | #define AMD_PG_SUPPORT_GFX_PG (1 << 0) | |
110 | #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) | |
111 | #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) | |
112 | #define AMD_PG_SUPPORT_UVD (1 << 3) | |
113 | #define AMD_PG_SUPPORT_VCE (1 << 4) | |
114 | #define AMD_PG_SUPPORT_CP (1 << 5) | |
115 | #define AMD_PG_SUPPORT_GDS (1 << 6) | |
116 | #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) | |
117 | #define AMD_PG_SUPPORT_SDMA (1 << 8) | |
118 | #define AMD_PG_SUPPORT_ACP (1 << 9) | |
119 | #define AMD_PG_SUPPORT_SAMU (1 << 10) | |
120 | ||
3a2c788d RZ |
121 | enum amd_pm_state_type { |
122 | /* not used for dpm */ | |
123 | POWER_STATE_TYPE_DEFAULT, | |
124 | POWER_STATE_TYPE_POWERSAVE, | |
125 | /* user selectable states */ | |
126 | POWER_STATE_TYPE_BATTERY, | |
127 | POWER_STATE_TYPE_BALANCED, | |
128 | POWER_STATE_TYPE_PERFORMANCE, | |
129 | /* internal states */ | |
130 | POWER_STATE_TYPE_INTERNAL_UVD, | |
131 | POWER_STATE_TYPE_INTERNAL_UVD_SD, | |
132 | POWER_STATE_TYPE_INTERNAL_UVD_HD, | |
133 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, | |
134 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, | |
135 | POWER_STATE_TYPE_INTERNAL_BOOT, | |
136 | POWER_STATE_TYPE_INTERNAL_THERMAL, | |
137 | POWER_STATE_TYPE_INTERNAL_ACPI, | |
138 | POWER_STATE_TYPE_INTERNAL_ULV, | |
139 | POWER_STATE_TYPE_INTERNAL_3DPERF, | |
140 | }; | |
141 | ||
5fc3aeeb | 142 | struct amd_ip_funcs { |
143 | /* sets up early driver state (pre sw_init), does not configure hw - Optional */ | |
144 | int (*early_init)(void *handle); | |
145 | /* sets up late driver/hw state (post hw_init) - Optional */ | |
146 | int (*late_init)(void *handle); | |
147 | /* sets up driver state, does not configure hw */ | |
148 | int (*sw_init)(void *handle); | |
149 | /* tears down driver state, does not configure hw */ | |
150 | int (*sw_fini)(void *handle); | |
151 | /* sets up the hw state */ | |
152 | int (*hw_init)(void *handle); | |
153 | /* tears down the hw state */ | |
154 | int (*hw_fini)(void *handle); | |
155 | /* handles IP specific hw/sw changes for suspend */ | |
156 | int (*suspend)(void *handle); | |
157 | /* handles IP specific hw/sw changes for resume */ | |
158 | int (*resume)(void *handle); | |
159 | /* returns current IP block idle status */ | |
160 | bool (*is_idle)(void *handle); | |
161 | /* poll for idle */ | |
162 | int (*wait_for_idle)(void *handle); | |
163 | /* soft reset the IP block */ | |
164 | int (*soft_reset)(void *handle); | |
165 | /* dump the IP block status registers */ | |
166 | void (*print_status)(void *handle); | |
167 | /* enable/disable cg for the IP block */ | |
168 | int (*set_clockgating_state)(void *handle, | |
169 | enum amd_clockgating_state state); | |
170 | /* enable/disable pg for the IP block */ | |
171 | int (*set_powergating_state)(void *handle, | |
172 | enum amd_powergating_state state); | |
173 | }; | |
174 | ||
175 | #endif /* __AMD_SHARED_H__ */ |