[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / amd / include / amd_shared.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef __AMD_SHARED_H__
#define __AMD_SHARED_H__

#define AMD_MAX_USEC_TIMEOUT		200000  /* 200 ms */

/*
 * Supported ASIC types
 */
enum amd_asic_type {
	CHIP_TAHITI = 0,
	CHIP_PITCAIRN,
	CHIP_VERDE,
	CHIP_OLAND,
	CHIP_HAINAN,
	CHIP_BONAIRE,
	CHIP_KAVERI,
	CHIP_KABINI,
	CHIP_HAWAII,
	CHIP_MULLINS,
	CHIP_TOPAZ,
	CHIP_TONGA,
	CHIP_FIJI,
	CHIP_CARRIZO,
	CHIP_STONEY,
	CHIP_POLARIS10,
	CHIP_POLARIS11,
	CHIP_POLARIS12,
	CHIP_LAST,
};

/*
 * Chip flags
 */
enum amd_chip_flags {
	AMD_ASIC_MASK = 0x0000ffffUL,
	AMD_FLAGS_MASK  = 0xffff0000UL,
	AMD_IS_MOBILITY = 0x00010000UL,
	AMD_IS_APU      = 0x00020000UL,
	AMD_IS_PX       = 0x00040000UL,
	AMD_EXP_HW_SUPPORT = 0x00080000UL,
};

enum amd_ip_block_type {
	AMD_IP_BLOCK_TYPE_COMMON,
	AMD_IP_BLOCK_TYPE_GMC,
	AMD_IP_BLOCK_TYPE_IH,
	AMD_IP_BLOCK_TYPE_SMC,
	AMD_IP_BLOCK_TYPE_DCE,
	AMD_IP_BLOCK_TYPE_GFX,
	AMD_IP_BLOCK_TYPE_SDMA,
	AMD_IP_BLOCK_TYPE_UVD,
	AMD_IP_BLOCK_TYPE_VCE,
	AMD_IP_BLOCK_TYPE_ACP,
};

enum amd_clockgating_state {
	AMD_CG_STATE_GATE = 0,
	AMD_CG_STATE_UNGATE,
};

enum amd_powergating_state {
	AMD_PG_STATE_GATE = 0,
	AMD_PG_STATE_UNGATE,
};

struct amd_vce_state {
	/* vce clocks */
	u32 evclk;
	u32 ecclk;
	/* gpu clocks */
	u32 sclk;
	u32 mclk;
	u8 clk_idx;
	u8 pstate;
};


#define AMD_MAX_VCE_LEVELS 6

enum amd_vce_level {
	AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
	AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
	AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
	AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
	AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
	AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
};

/* CG flags */
#define AMD_CG_SUPPORT_GFX_MGCG			(1 << 0)
#define AMD_CG_SUPPORT_GFX_MGLS			(1 << 1)
#define AMD_CG_SUPPORT_GFX_CGCG			(1 << 2)
#define AMD_CG_SUPPORT_GFX_CGLS			(1 << 3)
#define AMD_CG_SUPPORT_GFX_CGTS			(1 << 4)
#define AMD_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
#define AMD_CG_SUPPORT_GFX_CP_LS		(1 << 6)
#define AMD_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
#define AMD_CG_SUPPORT_MC_LS			(1 << 8)
#define AMD_CG_SUPPORT_MC_MGCG			(1 << 9)
#define AMD_CG_SUPPORT_SDMA_LS			(1 << 10)
#define AMD_CG_SUPPORT_SDMA_MGCG		(1 << 11)
#define AMD_CG_SUPPORT_BIF_LS			(1 << 12)
#define AMD_CG_SUPPORT_UVD_MGCG			(1 << 13)
#define AMD_CG_SUPPORT_VCE_MGCG			(1 << 14)
#define AMD_CG_SUPPORT_HDP_LS			(1 << 15)
#define AMD_CG_SUPPORT_HDP_MGCG			(1 << 16)
#define AMD_CG_SUPPORT_ROM_MGCG			(1 << 17)
#define AMD_CG_SUPPORT_DRM_LS			(1 << 18)
#define AMD_CG_SUPPORT_BIF_MGCG			(1 << 19)
#define AMD_CG_SUPPORT_GFX_3D_CGCG		(1 << 20)
#define AMD_CG_SUPPORT_GFX_3D_CGLS		(1 << 21)

/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
#define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
#define AMD_PG_SUPPORT_GFX_DMG			(1 << 2)
#define AMD_PG_SUPPORT_UVD			(1 << 3)
#define AMD_PG_SUPPORT_VCE			(1 << 4)
#define AMD_PG_SUPPORT_CP			(1 << 5)
#define AMD_PG_SUPPORT_GDS			(1 << 6)
#define AMD_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
#define AMD_PG_SUPPORT_SDMA			(1 << 8)
#define AMD_PG_SUPPORT_ACP			(1 << 9)
#define AMD_PG_SUPPORT_SAMU			(1 << 10)
#define AMD_PG_SUPPORT_GFX_QUICK_MG		(1 << 11)
#define AMD_PG_SUPPORT_GFX_PIPELINE		(1 << 12)

enum amd_pm_state_type {
	/* not used for dpm */
	POWER_STATE_TYPE_DEFAULT,
	POWER_STATE_TYPE_POWERSAVE,
	/* user selectable states */
	POWER_STATE_TYPE_BATTERY,
	POWER_STATE_TYPE_BALANCED,
	POWER_STATE_TYPE_PERFORMANCE,
	/* internal states */
	POWER_STATE_TYPE_INTERNAL_UVD,
	POWER_STATE_TYPE_INTERNAL_UVD_SD,
	POWER_STATE_TYPE_INTERNAL_UVD_HD,
	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
	POWER_STATE_TYPE_INTERNAL_BOOT,
	POWER_STATE_TYPE_INTERNAL_THERMAL,
	POWER_STATE_TYPE_INTERNAL_ACPI,
	POWER_STATE_TYPE_INTERNAL_ULV,
	POWER_STATE_TYPE_INTERNAL_3DPERF,
};

struct amd_ip_funcs {
	/* Name of IP block */
	char *name;
	/* sets up early driver state (pre sw_init), does not configure hw - Optional */
	int (*early_init)(void *handle);
	/* sets up late driver/hw state (post hw_init) - Optional */
	int (*late_init)(void *handle);
	/* sets up driver state, does not configure hw */
	int (*sw_init)(void *handle);
	/* tears down driver state, does not configure hw */
	int (*sw_fini)(void *handle);
	/* sets up the hw state */
	int (*hw_init)(void *handle);
	/* tears down the hw state */
	int (*hw_fini)(void *handle);
	void (*late_fini)(void *handle);
	/* handles IP specific hw/sw changes for suspend */
	int (*suspend)(void *handle);
	/* handles IP specific hw/sw changes for resume */
	int (*resume)(void *handle);
	/* returns current IP block idle status */
	bool (*is_idle)(void *handle);
	/* poll for idle */
	int (*wait_for_idle)(void *handle);
	/* check soft reset the IP block */
	bool (*check_soft_reset)(void *handle);
	/* pre soft reset the IP block */
	int (*pre_soft_reset)(void *handle);
	/* soft reset the IP block */
	int (*soft_reset)(void *handle);
	/* post soft reset the IP block */
	int (*post_soft_reset)(void *handle);
	/* enable/disable cg for the IP block */
	int (*set_clockgating_state)(void *handle,
				     enum amd_clockgating_state state);
	/* enable/disable pg for the IP block */
	int (*set_powergating_state)(void *handle,
				     enum amd_powergating_state state);
};

#endif /* __AMD_SHARED_H__ */
Commit	Line	Data
5fc3aeeb	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#ifndef __AMD_SHARED_H__
	24	#define __AMD_SHARED_H__
	25
70fd80d6	26	#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
0b2daf09	27
2f7d10b3 JZ	28	/*
	29	* Supported ASIC types
	30	*/
	31	enum amd_asic_type {
26d721c5 KW	32	CHIP_TAHITI = 0,
	33	CHIP_PITCAIRN,
	34	CHIP_VERDE,
	35	CHIP_OLAND,
	36	CHIP_HAINAN,
	37	CHIP_BONAIRE,
2f7d10b3 JZ	38	CHIP_KAVERI,
	39	CHIP_KABINI,
	40	CHIP_HAWAII,
	41	CHIP_MULLINS,
	42	CHIP_TOPAZ,
	43	CHIP_TONGA,
48299f95	44	CHIP_FIJI,
2f7d10b3	45	CHIP_CARRIZO,
139f4917	46	CHIP_STONEY,
2cc0c0b5 FC	47	CHIP_POLARIS10,
2cc0c0b5 FC	48	CHIP_POLARIS11,
c4642a47	49	CHIP_POLARIS12,
2f7d10b3 JZ	50	CHIP_LAST,
	51	};
	52
	53	/*
	54	* Chip flags
	55	*/
	56	enum amd_chip_flags {
	57	AMD_ASIC_MASK = 0x0000ffffUL,
	58	AMD_FLAGS_MASK = 0xffff0000UL,
	59	AMD_IS_MOBILITY = 0x00010000UL,
	60	AMD_IS_APU = 0x00020000UL,
	61	AMD_IS_PX = 0x00040000UL,
	62	AMD_EXP_HW_SUPPORT = 0x00080000UL,
	63	};
	64
5fc3aeeb	65	enum amd_ip_block_type {
	66	AMD_IP_BLOCK_TYPE_COMMON,
	67	AMD_IP_BLOCK_TYPE_GMC,
	68	AMD_IP_BLOCK_TYPE_IH,
	69	AMD_IP_BLOCK_TYPE_SMC,
	70	AMD_IP_BLOCK_TYPE_DCE,
	71	AMD_IP_BLOCK_TYPE_GFX,
	72	AMD_IP_BLOCK_TYPE_SDMA,
	73	AMD_IP_BLOCK_TYPE_UVD,
	74	AMD_IP_BLOCK_TYPE_VCE,
a8fe58ce	75	AMD_IP_BLOCK_TYPE_ACP,
5fc3aeeb	76	};
	77
	78	enum amd_clockgating_state {
	79	AMD_CG_STATE_GATE = 0,
	80	AMD_CG_STATE_UNGATE,
	81	};
	82
	83	enum amd_powergating_state {
	84	AMD_PG_STATE_GATE = 0,
	85	AMD_PG_STATE_UNGATE,
	86	};
	87
0d8de7ca RZ	88	struct amd_vce_state {
	89	/* vce clocks */
	90	u32 evclk;
	91	u32 ecclk;
	92	/* gpu clocks */
	93	u32 sclk;
	94	u32 mclk;
	95	u8 clk_idx;
	96	u8 pstate;
	97	};
	98
	99
	100	#define AMD_MAX_VCE_LEVELS 6
	101
	102	enum amd_vce_level {
	103	AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
	104	AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
	105	AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
	106	AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
	107	AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
	108	AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
	109	};
	110
e3b04bc7 AD	111	/* CG flags */
	112	#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
	113	#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
	114	#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
	115	#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
	116	#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
	117	#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
	118	#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
	119	#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
	120	#define AMD_CG_SUPPORT_MC_LS (1 << 8)
	121	#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
	122	#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
	123	#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
	124	#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
	125	#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
	126	#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
	127	#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
	128	#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
4fae91c5	129	#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
398d82cc RZ	130	#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
	131	#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
	132	#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
	133	#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
e3b04bc7 AD	134
	135	/* PG flags */
	136	#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
	137	#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
	138	#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
	139	#define AMD_PG_SUPPORT_UVD (1 << 3)
	140	#define AMD_PG_SUPPORT_VCE (1 << 4)
	141	#define AMD_PG_SUPPORT_CP (1 << 5)
	142	#define AMD_PG_SUPPORT_GDS (1 << 6)
	143	#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
	144	#define AMD_PG_SUPPORT_SDMA (1 << 8)
	145	#define AMD_PG_SUPPORT_ACP (1 << 9)
	146	#define AMD_PG_SUPPORT_SAMU (1 << 10)
6b0432b7 AD	147	#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
6b0432b7 AD	148	#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
e3b04bc7	149
3a2c788d RZ	150	enum amd_pm_state_type {
	151	/* not used for dpm */
	152	POWER_STATE_TYPE_DEFAULT,
	153	POWER_STATE_TYPE_POWERSAVE,
	154	/* user selectable states */
	155	POWER_STATE_TYPE_BATTERY,
	156	POWER_STATE_TYPE_BALANCED,
	157	POWER_STATE_TYPE_PERFORMANCE,
	158	/* internal states */
	159	POWER_STATE_TYPE_INTERNAL_UVD,
	160	POWER_STATE_TYPE_INTERNAL_UVD_SD,
	161	POWER_STATE_TYPE_INTERNAL_UVD_HD,
	162	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
	163	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
	164	POWER_STATE_TYPE_INTERNAL_BOOT,
	165	POWER_STATE_TYPE_INTERNAL_THERMAL,
	166	POWER_STATE_TYPE_INTERNAL_ACPI,
	167	POWER_STATE_TYPE_INTERNAL_ULV,
	168	POWER_STATE_TYPE_INTERNAL_3DPERF,
	169	};
	170
5fc3aeeb	171	struct amd_ip_funcs {
88a907d6 TSD	172	/* Name of IP block */
88a907d6 TSD	173	char *name;
5fc3aeeb	174	/* sets up early driver state (pre sw_init), does not configure hw - Optional */
	175	int (early_init)(void handle);
	176	/* sets up late driver/hw state (post hw_init) - Optional */
	177	int (late_init)(void handle);
	178	/* sets up driver state, does not configure hw */
	179	int (sw_init)(void handle);
	180	/* tears down driver state, does not configure hw */
	181	int (sw_fini)(void handle);
	182	/* sets up the hw state */
	183	int (hw_init)(void handle);
	184	/* tears down the hw state */
	185	int (hw_fini)(void handle);
212cb3b6	186	void (late_fini)(void handle);
5fc3aeeb	187	/* handles IP specific hw/sw changes for suspend */
	188	int (suspend)(void handle);
	189	/* handles IP specific hw/sw changes for resume */
	190	int (resume)(void handle);
	191	/* returns current IP block idle status */
	192	bool (is_idle)(void handle);
	193	/* poll for idle */
	194	int (wait_for_idle)(void handle);
63fbf42f	195	/* check soft reset the IP block */
da146d3b	196	bool (check_soft_reset)(void handle);
d31a501e CZ	197	/* pre soft reset the IP block */
d31a501e CZ	198	int (pre_soft_reset)(void handle);
5fc3aeeb	199	/* soft reset the IP block */
5fc3aeeb	200	int (soft_reset)(void handle);
35d782fe CZ	201	/* post soft reset the IP block */
35d782fe CZ	202	int (post_soft_reset)(void handle);
5fc3aeeb	203	/* enable/disable cg for the IP block */
	204	int (set_clockgating_state)(void handle,
	205	enum amd_clockgating_state state);
	206	/* enable/disable pg for the IP block */
	207	int (set_powergating_state)(void handle,
	208	enum amd_powergating_state state);
	209	};
	210
	211	#endif /* __AMD_SHARED_H__ */