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1f7371b2 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/types.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/gfp.h> | |
ac885b3a | 26 | #include <linux/slab.h> |
1f7371b2 AD |
27 | #include "amd_shared.h" |
28 | #include "amd_powerplay.h" | |
ac885b3a | 29 | #include "pp_instance.h" |
577bbe01 RZ |
30 | #include "power_state.h" |
31 | #include "eventmanager.h" | |
e273b041 | 32 | #include "pp_debug.h" |
1f7371b2 | 33 | |
a969e163 RZ |
34 | #define PP_CHECK(handle) \ |
35 | do { \ | |
36 | if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \ | |
37 | return -EINVAL; \ | |
38 | } while (0) | |
39 | ||
7383bcb9 RZ |
40 | #define PP_CHECK_HW(hwmgr) \ |
41 | do { \ | |
42 | if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ | |
43 | return -EINVAL; \ | |
44 | } while (0) | |
45 | ||
1f7371b2 AD |
46 | static int pp_early_init(void *handle) |
47 | { | |
48 | return 0; | |
49 | } | |
50 | ||
51 | static int pp_sw_init(void *handle) | |
52 | { | |
3bace359 JZ |
53 | struct pp_instance *pp_handle; |
54 | struct pp_hwmgr *hwmgr; | |
55 | int ret = 0; | |
56 | ||
57 | if (handle == NULL) | |
58 | return -EINVAL; | |
59 | ||
60 | pp_handle = (struct pp_instance *)handle; | |
61 | hwmgr = pp_handle->hwmgr; | |
62 | ||
7383bcb9 RZ |
63 | PP_CHECK_HW(hwmgr); |
64 | ||
65 | if (hwmgr->pptable_func == NULL || | |
3bace359 JZ |
66 | hwmgr->pptable_func->pptable_init == NULL || |
67 | hwmgr->hwmgr_func->backend_init == NULL) | |
68 | return -EINVAL; | |
69 | ||
70 | ret = hwmgr->pptable_func->pptable_init(hwmgr); | |
e92a0370 | 71 | |
3bace359 JZ |
72 | if (ret == 0) |
73 | ret = hwmgr->hwmgr_func->backend_init(hwmgr); | |
74 | ||
9441f964 | 75 | if (ret) |
7383bcb9 | 76 | printk(KERN_ERR "amdgpu: powerplay initialization failed\n"); |
9441f964 | 77 | else |
7383bcb9 | 78 | printk(KERN_INFO "amdgpu: powerplay initialized\n"); |
9441f964 | 79 | |
3bace359 | 80 | return ret; |
1f7371b2 AD |
81 | } |
82 | ||
83 | static int pp_sw_fini(void *handle) | |
84 | { | |
3bace359 JZ |
85 | struct pp_instance *pp_handle; |
86 | struct pp_hwmgr *hwmgr; | |
87 | int ret = 0; | |
88 | ||
89 | if (handle == NULL) | |
90 | return -EINVAL; | |
91 | ||
92 | pp_handle = (struct pp_instance *)handle; | |
93 | hwmgr = pp_handle->hwmgr; | |
94 | ||
7383bcb9 RZ |
95 | PP_CHECK_HW(hwmgr); |
96 | ||
97 | if (hwmgr->hwmgr_func->backend_fini != NULL) | |
3bace359 JZ |
98 | ret = hwmgr->hwmgr_func->backend_fini(hwmgr); |
99 | ||
100 | return ret; | |
1f7371b2 AD |
101 | } |
102 | ||
103 | static int pp_hw_init(void *handle) | |
104 | { | |
ac885b3a JZ |
105 | struct pp_instance *pp_handle; |
106 | struct pp_smumgr *smumgr; | |
e92a0370 | 107 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
108 | int ret = 0; |
109 | ||
110 | if (handle == NULL) | |
111 | return -EINVAL; | |
112 | ||
113 | pp_handle = (struct pp_instance *)handle; | |
114 | smumgr = pp_handle->smu_mgr; | |
115 | ||
116 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
117 | smumgr->smumgr_funcs->smu_init == NULL || | |
118 | smumgr->smumgr_funcs->start_smu == NULL) | |
119 | return -EINVAL; | |
120 | ||
121 | ret = smumgr->smumgr_funcs->smu_init(smumgr); | |
122 | if (ret) { | |
123 | printk(KERN_ERR "[ powerplay ] smc initialization failed\n"); | |
124 | return ret; | |
125 | } | |
126 | ||
127 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
128 | if (ret) { | |
129 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
130 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
131 | return ret; | |
132 | } | |
e92a0370 | 133 | |
3bace359 | 134 | hw_init_power_state_table(pp_handle->hwmgr); |
e92a0370 | 135 | eventmgr = pp_handle->eventmgr; |
3bace359 | 136 | |
e92a0370 RZ |
137 | if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) |
138 | return -EINVAL; | |
139 | ||
140 | ret = eventmgr->pp_eventmgr_init(eventmgr); | |
1f7371b2 AD |
141 | return 0; |
142 | } | |
143 | ||
144 | static int pp_hw_fini(void *handle) | |
145 | { | |
ac885b3a JZ |
146 | struct pp_instance *pp_handle; |
147 | struct pp_smumgr *smumgr; | |
e92a0370 | 148 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
149 | |
150 | if (handle == NULL) | |
151 | return -EINVAL; | |
152 | ||
153 | pp_handle = (struct pp_instance *)handle; | |
e92a0370 RZ |
154 | eventmgr = pp_handle->eventmgr; |
155 | ||
156 | if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL) | |
157 | eventmgr->pp_eventmgr_fini(eventmgr); | |
158 | ||
ac885b3a JZ |
159 | smumgr = pp_handle->smu_mgr; |
160 | ||
161 | if (smumgr != NULL || smumgr->smumgr_funcs != NULL || | |
162 | smumgr->smumgr_funcs->smu_fini != NULL) | |
163 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
164 | ||
1f7371b2 AD |
165 | return 0; |
166 | } | |
167 | ||
168 | static bool pp_is_idle(void *handle) | |
169 | { | |
170 | return 0; | |
171 | } | |
172 | ||
173 | static int pp_wait_for_idle(void *handle) | |
174 | { | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static int pp_sw_reset(void *handle) | |
179 | { | |
180 | return 0; | |
181 | } | |
182 | ||
1f7371b2 AD |
183 | |
184 | static int pp_set_clockgating_state(void *handle, | |
185 | enum amd_clockgating_state state) | |
186 | { | |
03e3905f EH |
187 | struct pp_hwmgr *hwmgr; |
188 | uint32_t msg_id, pp_state; | |
189 | ||
190 | if (handle == NULL) | |
191 | return -EINVAL; | |
192 | ||
193 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
194 | ||
7383bcb9 | 195 | PP_CHECK_HW(hwmgr); |
03e3905f | 196 | |
7383bcb9 RZ |
197 | if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { |
198 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
538333f0 | 199 | return 0; |
7383bcb9 | 200 | } |
538333f0 | 201 | |
03e3905f EH |
202 | if (state == AMD_CG_STATE_UNGATE) |
203 | pp_state = 0; | |
204 | else | |
205 | pp_state = PP_STATE_CG | PP_STATE_LS; | |
206 | ||
207 | /* Enable/disable GFX blocks clock gating through SMU */ | |
208 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
209 | PP_BLOCK_GFX_CG, | |
210 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
211 | pp_state); | |
212 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
213 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
214 | PP_BLOCK_GFX_3D, | |
215 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
216 | pp_state); | |
217 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
218 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
219 | PP_BLOCK_GFX_RLC, | |
220 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
221 | pp_state); | |
222 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
223 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
224 | PP_BLOCK_GFX_CP, | |
225 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
226 | pp_state); | |
227 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
228 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
229 | PP_BLOCK_GFX_MG, | |
230 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
231 | pp_state); | |
232 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
233 | ||
234 | /* Enable/disable System blocks clock gating through SMU */ | |
235 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
236 | PP_BLOCK_SYS_BIF, | |
237 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
238 | pp_state); | |
239 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
240 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
241 | PP_BLOCK_SYS_BIF, | |
242 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
243 | pp_state); | |
244 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
245 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
246 | PP_BLOCK_SYS_MC, | |
247 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
248 | pp_state); | |
249 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
250 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
251 | PP_BLOCK_SYS_ROM, | |
252 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
253 | pp_state); | |
254 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
255 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
256 | PP_BLOCK_SYS_DRM, | |
257 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
258 | pp_state); | |
259 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
260 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
261 | PP_BLOCK_SYS_HDP, | |
262 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
263 | pp_state); | |
264 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
265 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
266 | PP_BLOCK_SYS_SDMA, | |
267 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
268 | pp_state); | |
269 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
270 | ||
1f7371b2 AD |
271 | return 0; |
272 | } | |
273 | ||
274 | static int pp_set_powergating_state(void *handle, | |
275 | enum amd_powergating_state state) | |
276 | { | |
65f85e7d EH |
277 | struct pp_hwmgr *hwmgr; |
278 | ||
279 | if (handle == NULL) | |
280 | return -EINVAL; | |
281 | ||
282 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
283 | ||
7383bcb9 RZ |
284 | PP_CHECK_HW(hwmgr); |
285 | ||
286 | if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) { | |
287 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
288 | return 0; | |
289 | } | |
65f85e7d EH |
290 | |
291 | /* Enable/disable GFX per cu powergating through SMU */ | |
292 | return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr, | |
293 | state == AMD_PG_STATE_GATE ? true : false); | |
1f7371b2 AD |
294 | } |
295 | ||
296 | static int pp_suspend(void *handle) | |
297 | { | |
577bbe01 RZ |
298 | struct pp_instance *pp_handle; |
299 | struct pp_eventmgr *eventmgr; | |
300 | struct pem_event_data event_data = { {0} }; | |
301 | ||
302 | if (handle == NULL) | |
303 | return -EINVAL; | |
304 | ||
305 | pp_handle = (struct pp_instance *)handle; | |
306 | eventmgr = pp_handle->eventmgr; | |
307 | pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); | |
1f7371b2 AD |
308 | return 0; |
309 | } | |
310 | ||
311 | static int pp_resume(void *handle) | |
312 | { | |
577bbe01 RZ |
313 | struct pp_instance *pp_handle; |
314 | struct pp_eventmgr *eventmgr; | |
315 | struct pem_event_data event_data = { {0} }; | |
e0b71a7e RZ |
316 | struct pp_smumgr *smumgr; |
317 | int ret; | |
577bbe01 RZ |
318 | |
319 | if (handle == NULL) | |
320 | return -EINVAL; | |
321 | ||
322 | pp_handle = (struct pp_instance *)handle; | |
e0b71a7e RZ |
323 | smumgr = pp_handle->smu_mgr; |
324 | ||
325 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
326 | smumgr->smumgr_funcs->start_smu == NULL) | |
327 | return -EINVAL; | |
328 | ||
329 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
330 | if (ret) { | |
331 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
332 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
333 | return ret; | |
334 | } | |
335 | ||
577bbe01 RZ |
336 | eventmgr = pp_handle->eventmgr; |
337 | pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); | |
e0b71a7e | 338 | |
1f7371b2 AD |
339 | return 0; |
340 | } | |
341 | ||
342 | const struct amd_ip_funcs pp_ip_funcs = { | |
88a907d6 | 343 | .name = "powerplay", |
1f7371b2 AD |
344 | .early_init = pp_early_init, |
345 | .late_init = NULL, | |
346 | .sw_init = pp_sw_init, | |
347 | .sw_fini = pp_sw_fini, | |
348 | .hw_init = pp_hw_init, | |
349 | .hw_fini = pp_hw_fini, | |
350 | .suspend = pp_suspend, | |
351 | .resume = pp_resume, | |
352 | .is_idle = pp_is_idle, | |
353 | .wait_for_idle = pp_wait_for_idle, | |
354 | .soft_reset = pp_sw_reset, | |
1f7371b2 AD |
355 | .set_clockgating_state = pp_set_clockgating_state, |
356 | .set_powergating_state = pp_set_powergating_state, | |
357 | }; | |
358 | ||
359 | static int pp_dpm_load_fw(void *handle) | |
360 | { | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int pp_dpm_fw_loading_complete(void *handle) | |
365 | { | |
366 | return 0; | |
367 | } | |
368 | ||
369 | static int pp_dpm_force_performance_level(void *handle, | |
370 | enum amd_dpm_forced_level level) | |
371 | { | |
577bbe01 RZ |
372 | struct pp_instance *pp_handle; |
373 | struct pp_hwmgr *hwmgr; | |
374 | ||
375 | if (handle == NULL) | |
376 | return -EINVAL; | |
377 | ||
378 | pp_handle = (struct pp_instance *)handle; | |
379 | ||
380 | hwmgr = pp_handle->hwmgr; | |
381 | ||
7383bcb9 RZ |
382 | PP_CHECK_HW(hwmgr); |
383 | ||
384 | if (hwmgr->hwmgr_func->force_dpm_level == NULL) { | |
385 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
386 | return 0; | |
387 | } | |
577bbe01 RZ |
388 | |
389 | hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); | |
390 | ||
1f7371b2 AD |
391 | return 0; |
392 | } | |
577bbe01 | 393 | |
1f7371b2 AD |
394 | static enum amd_dpm_forced_level pp_dpm_get_performance_level( |
395 | void *handle) | |
396 | { | |
577bbe01 RZ |
397 | struct pp_hwmgr *hwmgr; |
398 | ||
399 | if (handle == NULL) | |
400 | return -EINVAL; | |
401 | ||
402 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
403 | ||
404 | if (hwmgr == NULL) | |
405 | return -EINVAL; | |
406 | ||
407 | return (((struct pp_instance *)handle)->hwmgr->dpm_level); | |
1f7371b2 | 408 | } |
577bbe01 | 409 | |
1f7371b2 AD |
410 | static int pp_dpm_get_sclk(void *handle, bool low) |
411 | { | |
577bbe01 RZ |
412 | struct pp_hwmgr *hwmgr; |
413 | ||
414 | if (handle == NULL) | |
415 | return -EINVAL; | |
416 | ||
417 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
418 | ||
7383bcb9 RZ |
419 | PP_CHECK_HW(hwmgr); |
420 | ||
421 | if (hwmgr->hwmgr_func->get_sclk == NULL) { | |
422 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
423 | return 0; | |
424 | } | |
577bbe01 RZ |
425 | |
426 | return hwmgr->hwmgr_func->get_sclk(hwmgr, low); | |
1f7371b2 | 427 | } |
577bbe01 | 428 | |
1f7371b2 AD |
429 | static int pp_dpm_get_mclk(void *handle, bool low) |
430 | { | |
577bbe01 RZ |
431 | struct pp_hwmgr *hwmgr; |
432 | ||
433 | if (handle == NULL) | |
434 | return -EINVAL; | |
435 | ||
436 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
437 | ||
7383bcb9 RZ |
438 | PP_CHECK_HW(hwmgr); |
439 | ||
440 | if (hwmgr->hwmgr_func->get_mclk == NULL) { | |
441 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
442 | return 0; | |
443 | } | |
577bbe01 RZ |
444 | |
445 | return hwmgr->hwmgr_func->get_mclk(hwmgr, low); | |
1f7371b2 | 446 | } |
577bbe01 | 447 | |
1f7371b2 AD |
448 | static int pp_dpm_powergate_vce(void *handle, bool gate) |
449 | { | |
577bbe01 RZ |
450 | struct pp_hwmgr *hwmgr; |
451 | ||
452 | if (handle == NULL) | |
453 | return -EINVAL; | |
454 | ||
455 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
456 | ||
7383bcb9 RZ |
457 | PP_CHECK_HW(hwmgr); |
458 | ||
459 | if (hwmgr->hwmgr_func->powergate_vce == NULL) { | |
460 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
461 | return 0; | |
462 | } | |
577bbe01 RZ |
463 | |
464 | return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); | |
1f7371b2 | 465 | } |
577bbe01 | 466 | |
1f7371b2 AD |
467 | static int pp_dpm_powergate_uvd(void *handle, bool gate) |
468 | { | |
577bbe01 RZ |
469 | struct pp_hwmgr *hwmgr; |
470 | ||
471 | if (handle == NULL) | |
472 | return -EINVAL; | |
473 | ||
474 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
475 | ||
7383bcb9 RZ |
476 | PP_CHECK_HW(hwmgr); |
477 | ||
478 | if (hwmgr->hwmgr_func->powergate_uvd == NULL) { | |
479 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
480 | return 0; | |
481 | } | |
577bbe01 RZ |
482 | |
483 | return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); | |
484 | } | |
485 | ||
486 | static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) | |
487 | { | |
488 | switch (state) { | |
489 | case POWER_STATE_TYPE_BATTERY: | |
490 | return PP_StateUILabel_Battery; | |
491 | case POWER_STATE_TYPE_BALANCED: | |
492 | return PP_StateUILabel_Balanced; | |
493 | case POWER_STATE_TYPE_PERFORMANCE: | |
494 | return PP_StateUILabel_Performance; | |
495 | default: | |
496 | return PP_StateUILabel_None; | |
497 | } | |
1f7371b2 AD |
498 | } |
499 | ||
500 | int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) | |
501 | { | |
577bbe01 RZ |
502 | int ret = 0; |
503 | struct pp_instance *pp_handle; | |
504 | struct pem_event_data data = { {0} }; | |
505 | ||
506 | pp_handle = (struct pp_instance *)handle; | |
507 | ||
508 | if (pp_handle == NULL) | |
509 | return -EINVAL; | |
510 | ||
511 | switch (event_id) { | |
512 | case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: | |
513 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
514 | break; | |
515 | case AMD_PP_EVENT_ENABLE_USER_STATE: | |
516 | { | |
517 | enum amd_pm_state_type ps; | |
518 | ||
519 | if (input == NULL) | |
520 | return -EINVAL; | |
521 | ps = *(unsigned long *)input; | |
522 | ||
523 | data.requested_ui_label = power_state_convert(ps); | |
524 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
dc26a2a2 | 525 | break; |
577bbe01 | 526 | } |
dc26a2a2 RZ |
527 | case AMD_PP_EVENT_COMPLETE_INIT: |
528 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
529 | break; | |
577bbe01 RZ |
530 | default: |
531 | break; | |
532 | } | |
533 | return ret; | |
1f7371b2 | 534 | } |
577bbe01 | 535 | |
1f7371b2 AD |
536 | enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) |
537 | { | |
577bbe01 RZ |
538 | struct pp_hwmgr *hwmgr; |
539 | struct pp_power_state *state; | |
540 | ||
541 | if (handle == NULL) | |
542 | return -EINVAL; | |
543 | ||
544 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
545 | ||
546 | if (hwmgr == NULL || hwmgr->current_ps == NULL) | |
547 | return -EINVAL; | |
548 | ||
549 | state = hwmgr->current_ps; | |
550 | ||
551 | switch (state->classification.ui_label) { | |
552 | case PP_StateUILabel_Battery: | |
553 | return POWER_STATE_TYPE_BATTERY; | |
554 | case PP_StateUILabel_Balanced: | |
555 | return POWER_STATE_TYPE_BALANCED; | |
556 | case PP_StateUILabel_Performance: | |
557 | return POWER_STATE_TYPE_PERFORMANCE; | |
558 | default: | |
f3898ea1 EH |
559 | if (state->classification.flags & PP_StateClassificationFlag_Boot) |
560 | return POWER_STATE_TYPE_INTERNAL_BOOT; | |
561 | else | |
562 | return POWER_STATE_TYPE_DEFAULT; | |
577bbe01 | 563 | } |
1f7371b2 | 564 | } |
577bbe01 | 565 | |
1f7371b2 AD |
566 | static void |
567 | pp_debugfs_print_current_performance_level(void *handle, | |
568 | struct seq_file *m) | |
569 | { | |
577bbe01 RZ |
570 | struct pp_hwmgr *hwmgr; |
571 | ||
572 | if (handle == NULL) | |
573 | return; | |
574 | ||
575 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
576 | ||
7383bcb9 RZ |
577 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL) |
578 | return; | |
579 | ||
580 | if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) { | |
581 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
577bbe01 | 582 | return; |
7383bcb9 | 583 | } |
577bbe01 RZ |
584 | |
585 | hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); | |
1f7371b2 | 586 | } |
3bace359 | 587 | |
cac9a199 RZ |
588 | static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) |
589 | { | |
590 | struct pp_hwmgr *hwmgr; | |
591 | ||
592 | if (handle == NULL) | |
593 | return -EINVAL; | |
594 | ||
595 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
596 | ||
7383bcb9 RZ |
597 | PP_CHECK_HW(hwmgr); |
598 | ||
599 | if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { | |
600 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
601 | return 0; | |
602 | } | |
cac9a199 RZ |
603 | |
604 | return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); | |
605 | } | |
606 | ||
607 | static int pp_dpm_get_fan_control_mode(void *handle) | |
608 | { | |
609 | struct pp_hwmgr *hwmgr; | |
610 | ||
611 | if (handle == NULL) | |
612 | return -EINVAL; | |
613 | ||
614 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
615 | ||
7383bcb9 RZ |
616 | PP_CHECK_HW(hwmgr); |
617 | ||
618 | if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) { | |
619 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
620 | return 0; | |
621 | } | |
cac9a199 RZ |
622 | |
623 | return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); | |
624 | } | |
625 | ||
626 | static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) | |
627 | { | |
628 | struct pp_hwmgr *hwmgr; | |
629 | ||
630 | if (handle == NULL) | |
631 | return -EINVAL; | |
632 | ||
633 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
634 | ||
7383bcb9 RZ |
635 | PP_CHECK_HW(hwmgr); |
636 | ||
637 | if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) { | |
638 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
639 | return 0; | |
640 | } | |
cac9a199 RZ |
641 | |
642 | return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); | |
643 | } | |
644 | ||
645 | static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) | |
646 | { | |
647 | struct pp_hwmgr *hwmgr; | |
648 | ||
649 | if (handle == NULL) | |
650 | return -EINVAL; | |
651 | ||
652 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
653 | ||
7383bcb9 RZ |
654 | PP_CHECK_HW(hwmgr); |
655 | ||
656 | if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) { | |
657 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
658 | return 0; | |
659 | } | |
cac9a199 RZ |
660 | |
661 | return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); | |
662 | } | |
663 | ||
664 | static int pp_dpm_get_temperature(void *handle) | |
665 | { | |
666 | struct pp_hwmgr *hwmgr; | |
667 | ||
668 | if (handle == NULL) | |
669 | return -EINVAL; | |
670 | ||
671 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
672 | ||
7383bcb9 RZ |
673 | PP_CHECK_HW(hwmgr); |
674 | ||
675 | if (hwmgr->hwmgr_func->get_temperature == NULL) { | |
676 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
677 | return 0; | |
678 | } | |
cac9a199 RZ |
679 | |
680 | return hwmgr->hwmgr_func->get_temperature(hwmgr); | |
681 | } | |
577bbe01 | 682 | |
f3898ea1 EH |
683 | static int pp_dpm_get_pp_num_states(void *handle, |
684 | struct pp_states_info *data) | |
685 | { | |
686 | struct pp_hwmgr *hwmgr; | |
687 | int i; | |
688 | ||
689 | if (!handle) | |
690 | return -EINVAL; | |
691 | ||
692 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
693 | ||
694 | if (hwmgr == NULL || hwmgr->ps == NULL) | |
695 | return -EINVAL; | |
696 | ||
697 | data->nums = hwmgr->num_ps; | |
698 | ||
699 | for (i = 0; i < hwmgr->num_ps; i++) { | |
700 | struct pp_power_state *state = (struct pp_power_state *) | |
701 | ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); | |
702 | switch (state->classification.ui_label) { | |
703 | case PP_StateUILabel_Battery: | |
704 | data->states[i] = POWER_STATE_TYPE_BATTERY; | |
705 | break; | |
706 | case PP_StateUILabel_Balanced: | |
707 | data->states[i] = POWER_STATE_TYPE_BALANCED; | |
708 | break; | |
709 | case PP_StateUILabel_Performance: | |
710 | data->states[i] = POWER_STATE_TYPE_PERFORMANCE; | |
711 | break; | |
712 | default: | |
713 | if (state->classification.flags & PP_StateClassificationFlag_Boot) | |
714 | data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; | |
715 | else | |
716 | data->states[i] = POWER_STATE_TYPE_DEFAULT; | |
717 | } | |
718 | } | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static int pp_dpm_get_pp_table(void *handle, char **table) | |
724 | { | |
725 | struct pp_hwmgr *hwmgr; | |
726 | ||
727 | if (!handle) | |
728 | return -EINVAL; | |
729 | ||
730 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
731 | ||
7383bcb9 RZ |
732 | PP_CHECK_HW(hwmgr); |
733 | ||
734 | if (hwmgr->hwmgr_func->get_pp_table == NULL) { | |
735 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
736 | return 0; | |
737 | } | |
f3898ea1 EH |
738 | |
739 | return hwmgr->hwmgr_func->get_pp_table(hwmgr, table); | |
740 | } | |
741 | ||
742 | static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) | |
743 | { | |
744 | struct pp_hwmgr *hwmgr; | |
745 | ||
746 | if (!handle) | |
747 | return -EINVAL; | |
748 | ||
749 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
750 | ||
7383bcb9 RZ |
751 | PP_CHECK_HW(hwmgr); |
752 | ||
753 | if (hwmgr->hwmgr_func->set_pp_table == NULL) { | |
754 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
755 | return 0; | |
756 | } | |
f3898ea1 EH |
757 | |
758 | return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size); | |
759 | } | |
760 | ||
761 | static int pp_dpm_force_clock_level(void *handle, | |
5632708f | 762 | enum pp_clock_type type, uint32_t mask) |
f3898ea1 EH |
763 | { |
764 | struct pp_hwmgr *hwmgr; | |
765 | ||
766 | if (!handle) | |
767 | return -EINVAL; | |
768 | ||
769 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
770 | ||
7383bcb9 RZ |
771 | PP_CHECK_HW(hwmgr); |
772 | ||
773 | if (hwmgr->hwmgr_func->force_clock_level == NULL) { | |
774 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
775 | return 0; | |
776 | } | |
f3898ea1 | 777 | |
5632708f | 778 | return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); |
f3898ea1 EH |
779 | } |
780 | ||
781 | static int pp_dpm_print_clock_levels(void *handle, | |
782 | enum pp_clock_type type, char *buf) | |
783 | { | |
784 | struct pp_hwmgr *hwmgr; | |
785 | ||
786 | if (!handle) | |
787 | return -EINVAL; | |
788 | ||
789 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
790 | ||
7383bcb9 | 791 | PP_CHECK_HW(hwmgr); |
f3898ea1 | 792 | |
7383bcb9 RZ |
793 | if (hwmgr->hwmgr_func->print_clock_levels == NULL) { |
794 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
795 | return 0; | |
796 | } | |
f3898ea1 EH |
797 | return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); |
798 | } | |
799 | ||
1f7371b2 | 800 | const struct amd_powerplay_funcs pp_dpm_funcs = { |
cac9a199 | 801 | .get_temperature = pp_dpm_get_temperature, |
1f7371b2 AD |
802 | .load_firmware = pp_dpm_load_fw, |
803 | .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, | |
804 | .force_performance_level = pp_dpm_force_performance_level, | |
805 | .get_performance_level = pp_dpm_get_performance_level, | |
806 | .get_current_power_state = pp_dpm_get_current_power_state, | |
807 | .get_sclk = pp_dpm_get_sclk, | |
808 | .get_mclk = pp_dpm_get_mclk, | |
809 | .powergate_vce = pp_dpm_powergate_vce, | |
810 | .powergate_uvd = pp_dpm_powergate_uvd, | |
811 | .dispatch_tasks = pp_dpm_dispatch_tasks, | |
812 | .print_current_performance_level = pp_debugfs_print_current_performance_level, | |
cac9a199 RZ |
813 | .set_fan_control_mode = pp_dpm_set_fan_control_mode, |
814 | .get_fan_control_mode = pp_dpm_get_fan_control_mode, | |
815 | .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, | |
816 | .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, | |
f3898ea1 EH |
817 | .get_pp_num_states = pp_dpm_get_pp_num_states, |
818 | .get_pp_table = pp_dpm_get_pp_table, | |
819 | .set_pp_table = pp_dpm_set_pp_table, | |
820 | .force_clock_level = pp_dpm_force_clock_level, | |
821 | .print_clock_levels = pp_dpm_print_clock_levels, | |
1f7371b2 AD |
822 | }; |
823 | ||
ac885b3a JZ |
824 | static int amd_pp_instance_init(struct amd_pp_init *pp_init, |
825 | struct amd_powerplay *amd_pp) | |
826 | { | |
827 | int ret; | |
828 | struct pp_instance *handle; | |
829 | ||
830 | handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); | |
831 | if (handle == NULL) | |
832 | return -ENOMEM; | |
833 | ||
a969e163 RZ |
834 | handle->pp_valid = PP_VALID; |
835 | ||
ac885b3a JZ |
836 | ret = smum_init(pp_init, handle); |
837 | if (ret) | |
3bace359 JZ |
838 | goto fail_smum; |
839 | ||
840 | ret = hwmgr_init(pp_init, handle); | |
841 | if (ret) | |
842 | goto fail_hwmgr; | |
ac885b3a | 843 | |
e92a0370 RZ |
844 | ret = eventmgr_init(handle); |
845 | if (ret) | |
846 | goto fail_eventmgr; | |
847 | ||
ac885b3a JZ |
848 | amd_pp->pp_handle = handle; |
849 | return 0; | |
3bace359 | 850 | |
e92a0370 RZ |
851 | fail_eventmgr: |
852 | hwmgr_fini(handle->hwmgr); | |
3bace359 JZ |
853 | fail_hwmgr: |
854 | smum_fini(handle->smu_mgr); | |
855 | fail_smum: | |
856 | kfree(handle); | |
857 | return ret; | |
ac885b3a JZ |
858 | } |
859 | ||
860 | static int amd_pp_instance_fini(void *handle) | |
861 | { | |
862 | struct pp_instance *instance = (struct pp_instance *)handle; | |
e92a0370 | 863 | |
ac885b3a JZ |
864 | if (instance == NULL) |
865 | return -EINVAL; | |
866 | ||
e92a0370 RZ |
867 | eventmgr_fini(instance->eventmgr); |
868 | ||
3bace359 JZ |
869 | hwmgr_fini(instance->hwmgr); |
870 | ||
ac885b3a JZ |
871 | smum_fini(instance->smu_mgr); |
872 | ||
873 | kfree(handle); | |
874 | return 0; | |
875 | } | |
876 | ||
1f7371b2 AD |
877 | int amd_powerplay_init(struct amd_pp_init *pp_init, |
878 | struct amd_powerplay *amd_pp) | |
879 | { | |
ac885b3a JZ |
880 | int ret; |
881 | ||
1f7371b2 AD |
882 | if (pp_init == NULL || amd_pp == NULL) |
883 | return -EINVAL; | |
884 | ||
ac885b3a JZ |
885 | ret = amd_pp_instance_init(pp_init, amd_pp); |
886 | ||
887 | if (ret) | |
888 | return ret; | |
889 | ||
1f7371b2 AD |
890 | amd_pp->ip_funcs = &pp_ip_funcs; |
891 | amd_pp->pp_funcs = &pp_dpm_funcs; | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | int amd_powerplay_fini(void *handle) | |
897 | { | |
ac885b3a JZ |
898 | amd_pp_instance_fini(handle); |
899 | ||
1f7371b2 AD |
900 | return 0; |
901 | } | |
7fb72a1f RZ |
902 | |
903 | /* export this function to DAL */ | |
904 | ||
155f1127 DR |
905 | int amd_powerplay_display_configuration_change(void *handle, |
906 | const struct amd_pp_display_configuration *display_config) | |
7fb72a1f RZ |
907 | { |
908 | struct pp_hwmgr *hwmgr; | |
7fb72a1f | 909 | |
a969e163 | 910 | PP_CHECK((struct pp_instance *)handle); |
7fb72a1f RZ |
911 | |
912 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
913 | ||
914 | phm_store_dal_configuration_data(hwmgr, display_config); | |
e0b71a7e | 915 | |
7fb72a1f RZ |
916 | return 0; |
917 | } | |
c4dd206b | 918 | |
1c9a9082 | 919 | int amd_powerplay_get_display_power_level(void *handle, |
47329134 | 920 | struct amd_pp_simple_clock_info *output) |
c4dd206b VP |
921 | { |
922 | struct pp_hwmgr *hwmgr; | |
923 | ||
a969e163 RZ |
924 | PP_CHECK((struct pp_instance *)handle); |
925 | ||
926 | if (output == NULL) | |
c4dd206b VP |
927 | return -EINVAL; |
928 | ||
929 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
930 | ||
1c9a9082 | 931 | return phm_get_dal_power_level(hwmgr, output); |
c4dd206b | 932 | } |
e273b041 RZ |
933 | |
934 | int amd_powerplay_get_current_clocks(void *handle, | |
155f1127 | 935 | struct amd_pp_clock_info *clocks) |
e273b041 RZ |
936 | { |
937 | struct pp_hwmgr *hwmgr; | |
938 | struct amd_pp_simple_clock_info simple_clocks; | |
939 | struct pp_clock_info hw_clocks; | |
e273b041 | 940 | |
fa9e6991 RZ |
941 | PP_CHECK((struct pp_instance *)handle); |
942 | ||
943 | if (clocks == NULL) | |
e273b041 RZ |
944 | return -EINVAL; |
945 | ||
946 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
947 | ||
948 | phm_get_dal_power_level(hwmgr, &simple_clocks); | |
949 | ||
950 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { | |
951 | if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment)) | |
952 | PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1); | |
953 | } else { | |
954 | if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity)) | |
955 | PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1); | |
956 | } | |
957 | ||
958 | clocks->min_engine_clock = hw_clocks.min_eng_clk; | |
959 | clocks->max_engine_clock = hw_clocks.max_eng_clk; | |
960 | clocks->min_memory_clock = hw_clocks.min_mem_clk; | |
961 | clocks->max_memory_clock = hw_clocks.max_mem_clk; | |
962 | clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; | |
963 | clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; | |
964 | ||
965 | clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; | |
966 | clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; | |
967 | ||
968 | clocks->max_clocks_state = simple_clocks.level; | |
969 | ||
970 | if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { | |
971 | clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; | |
972 | clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; | |
973 | } | |
974 | ||
975 | return 0; | |
976 | ||
977 | } | |
978 | ||
979 | int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) | |
980 | { | |
981 | int result = -1; | |
982 | ||
983 | struct pp_hwmgr *hwmgr; | |
984 | ||
fa9e6991 RZ |
985 | PP_CHECK((struct pp_instance *)handle); |
986 | ||
987 | if (clocks == NULL) | |
e273b041 RZ |
988 | return -EINVAL; |
989 | ||
990 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
991 | ||
992 | result = phm_get_clock_by_type(hwmgr, type, clocks); | |
993 | ||
994 | return result; | |
995 | } | |
996 | ||
155f1127 DR |
997 | int amd_powerplay_get_display_mode_validation_clocks(void *handle, |
998 | struct amd_pp_simple_clock_info *clocks) | |
e273b041 RZ |
999 | { |
1000 | int result = -1; | |
e273b041 RZ |
1001 | struct pp_hwmgr *hwmgr; |
1002 | ||
fa9e6991 RZ |
1003 | PP_CHECK((struct pp_instance *)handle); |
1004 | ||
1005 | if (clocks == NULL) | |
e273b041 RZ |
1006 | return -EINVAL; |
1007 | ||
1008 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
1009 | ||
1010 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) | |
1011 | result = phm_get_max_high_clocks(hwmgr, clocks); | |
1012 | ||
1013 | return result; | |
1014 | } | |
1015 |