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1f7371b2 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/types.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/gfp.h> | |
ac885b3a | 26 | #include <linux/slab.h> |
1f7371b2 AD |
27 | #include "amd_shared.h" |
28 | #include "amd_powerplay.h" | |
ac885b3a | 29 | #include "pp_instance.h" |
577bbe01 RZ |
30 | #include "power_state.h" |
31 | #include "eventmanager.h" | |
e273b041 | 32 | #include "pp_debug.h" |
1f7371b2 | 33 | |
a969e163 RZ |
34 | #define PP_CHECK(handle) \ |
35 | do { \ | |
36 | if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \ | |
37 | return -EINVAL; \ | |
38 | } while (0) | |
39 | ||
7383bcb9 RZ |
40 | #define PP_CHECK_HW(hwmgr) \ |
41 | do { \ | |
42 | if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ | |
43 | return -EINVAL; \ | |
44 | } while (0) | |
45 | ||
1f7371b2 AD |
46 | static int pp_early_init(void *handle) |
47 | { | |
48 | return 0; | |
49 | } | |
50 | ||
51 | static int pp_sw_init(void *handle) | |
52 | { | |
3bace359 JZ |
53 | struct pp_instance *pp_handle; |
54 | struct pp_hwmgr *hwmgr; | |
55 | int ret = 0; | |
56 | ||
57 | if (handle == NULL) | |
58 | return -EINVAL; | |
59 | ||
60 | pp_handle = (struct pp_instance *)handle; | |
61 | hwmgr = pp_handle->hwmgr; | |
62 | ||
7383bcb9 RZ |
63 | PP_CHECK_HW(hwmgr); |
64 | ||
65 | if (hwmgr->pptable_func == NULL || | |
3bace359 JZ |
66 | hwmgr->pptable_func->pptable_init == NULL || |
67 | hwmgr->hwmgr_func->backend_init == NULL) | |
68 | return -EINVAL; | |
69 | ||
70 | ret = hwmgr->pptable_func->pptable_init(hwmgr); | |
b4eeed59 HR |
71 | if (ret) |
72 | goto err; | |
e92a0370 | 73 | |
b4eeed59 | 74 | ret = hwmgr->hwmgr_func->backend_init(hwmgr); |
9441f964 | 75 | if (ret) |
9d8f086c | 76 | goto err1; |
9441f964 | 77 | |
b4eeed59 HR |
78 | pr_info("amdgpu: powerplay initialized\n"); |
79 | ||
80 | return 0; | |
9d8f086c ML |
81 | err1: |
82 | if (hwmgr->pptable_func->pptable_fini) | |
83 | hwmgr->pptable_func->pptable_fini(hwmgr); | |
b4eeed59 HR |
84 | err: |
85 | pr_err("amdgpu: powerplay initialization failed\n"); | |
3bace359 | 86 | return ret; |
1f7371b2 AD |
87 | } |
88 | ||
89 | static int pp_sw_fini(void *handle) | |
90 | { | |
3bace359 JZ |
91 | struct pp_instance *pp_handle; |
92 | struct pp_hwmgr *hwmgr; | |
93 | int ret = 0; | |
94 | ||
95 | if (handle == NULL) | |
96 | return -EINVAL; | |
97 | ||
98 | pp_handle = (struct pp_instance *)handle; | |
99 | hwmgr = pp_handle->hwmgr; | |
100 | ||
7383bcb9 RZ |
101 | PP_CHECK_HW(hwmgr); |
102 | ||
103 | if (hwmgr->hwmgr_func->backend_fini != NULL) | |
3bace359 JZ |
104 | ret = hwmgr->hwmgr_func->backend_fini(hwmgr); |
105 | ||
9d8f086c ML |
106 | if (hwmgr->pptable_func->pptable_fini) |
107 | hwmgr->pptable_func->pptable_fini(hwmgr); | |
108 | ||
3bace359 | 109 | return ret; |
1f7371b2 AD |
110 | } |
111 | ||
112 | static int pp_hw_init(void *handle) | |
113 | { | |
ac885b3a JZ |
114 | struct pp_instance *pp_handle; |
115 | struct pp_smumgr *smumgr; | |
e92a0370 | 116 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
117 | int ret = 0; |
118 | ||
119 | if (handle == NULL) | |
120 | return -EINVAL; | |
121 | ||
122 | pp_handle = (struct pp_instance *)handle; | |
123 | smumgr = pp_handle->smu_mgr; | |
124 | ||
125 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
126 | smumgr->smumgr_funcs->smu_init == NULL || | |
127 | smumgr->smumgr_funcs->start_smu == NULL) | |
128 | return -EINVAL; | |
129 | ||
130 | ret = smumgr->smumgr_funcs->smu_init(smumgr); | |
131 | if (ret) { | |
132 | printk(KERN_ERR "[ powerplay ] smc initialization failed\n"); | |
133 | return ret; | |
134 | } | |
135 | ||
136 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
137 | if (ret) { | |
138 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
139 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
140 | return ret; | |
141 | } | |
e92a0370 | 142 | |
3bace359 | 143 | hw_init_power_state_table(pp_handle->hwmgr); |
e92a0370 | 144 | eventmgr = pp_handle->eventmgr; |
3bace359 | 145 | |
e92a0370 RZ |
146 | if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) |
147 | return -EINVAL; | |
148 | ||
149 | ret = eventmgr->pp_eventmgr_init(eventmgr); | |
1f7371b2 AD |
150 | return 0; |
151 | } | |
152 | ||
153 | static int pp_hw_fini(void *handle) | |
154 | { | |
ac885b3a JZ |
155 | struct pp_instance *pp_handle; |
156 | struct pp_smumgr *smumgr; | |
e92a0370 | 157 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
158 | |
159 | if (handle == NULL) | |
160 | return -EINVAL; | |
161 | ||
162 | pp_handle = (struct pp_instance *)handle; | |
e92a0370 RZ |
163 | eventmgr = pp_handle->eventmgr; |
164 | ||
165 | if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL) | |
166 | eventmgr->pp_eventmgr_fini(eventmgr); | |
167 | ||
ac885b3a JZ |
168 | smumgr = pp_handle->smu_mgr; |
169 | ||
170 | if (smumgr != NULL || smumgr->smumgr_funcs != NULL || | |
171 | smumgr->smumgr_funcs->smu_fini != NULL) | |
172 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
173 | ||
1f7371b2 AD |
174 | return 0; |
175 | } | |
176 | ||
177 | static bool pp_is_idle(void *handle) | |
178 | { | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static int pp_wait_for_idle(void *handle) | |
183 | { | |
184 | return 0; | |
185 | } | |
186 | ||
187 | static int pp_sw_reset(void *handle) | |
188 | { | |
189 | return 0; | |
190 | } | |
191 | ||
1f7371b2 AD |
192 | |
193 | static int pp_set_clockgating_state(void *handle, | |
194 | enum amd_clockgating_state state) | |
195 | { | |
03e3905f EH |
196 | struct pp_hwmgr *hwmgr; |
197 | uint32_t msg_id, pp_state; | |
198 | ||
199 | if (handle == NULL) | |
200 | return -EINVAL; | |
201 | ||
202 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
203 | ||
7383bcb9 | 204 | PP_CHECK_HW(hwmgr); |
03e3905f | 205 | |
7383bcb9 RZ |
206 | if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { |
207 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
538333f0 | 208 | return 0; |
7383bcb9 | 209 | } |
538333f0 | 210 | |
03e3905f EH |
211 | if (state == AMD_CG_STATE_UNGATE) |
212 | pp_state = 0; | |
213 | else | |
214 | pp_state = PP_STATE_CG | PP_STATE_LS; | |
215 | ||
216 | /* Enable/disable GFX blocks clock gating through SMU */ | |
217 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
218 | PP_BLOCK_GFX_CG, | |
219 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
220 | pp_state); | |
221 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
222 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
223 | PP_BLOCK_GFX_3D, | |
224 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
225 | pp_state); | |
226 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
227 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
228 | PP_BLOCK_GFX_RLC, | |
229 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
230 | pp_state); | |
231 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
232 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
233 | PP_BLOCK_GFX_CP, | |
234 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
235 | pp_state); | |
236 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
237 | msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, | |
238 | PP_BLOCK_GFX_MG, | |
239 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
240 | pp_state); | |
241 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
242 | ||
243 | /* Enable/disable System blocks clock gating through SMU */ | |
244 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
245 | PP_BLOCK_SYS_BIF, | |
246 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
247 | pp_state); | |
248 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
249 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
250 | PP_BLOCK_SYS_BIF, | |
251 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
252 | pp_state); | |
253 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
254 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
255 | PP_BLOCK_SYS_MC, | |
256 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
257 | pp_state); | |
258 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
259 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
260 | PP_BLOCK_SYS_ROM, | |
261 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
262 | pp_state); | |
263 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
264 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
265 | PP_BLOCK_SYS_DRM, | |
266 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
267 | pp_state); | |
268 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
269 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
270 | PP_BLOCK_SYS_HDP, | |
271 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
272 | pp_state); | |
273 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
274 | msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, | |
275 | PP_BLOCK_SYS_SDMA, | |
276 | PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, | |
277 | pp_state); | |
278 | hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); | |
279 | ||
1f7371b2 AD |
280 | return 0; |
281 | } | |
282 | ||
283 | static int pp_set_powergating_state(void *handle, | |
284 | enum amd_powergating_state state) | |
285 | { | |
65f85e7d EH |
286 | struct pp_hwmgr *hwmgr; |
287 | ||
288 | if (handle == NULL) | |
289 | return -EINVAL; | |
290 | ||
291 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
292 | ||
7383bcb9 RZ |
293 | PP_CHECK_HW(hwmgr); |
294 | ||
295 | if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) { | |
296 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
297 | return 0; | |
298 | } | |
65f85e7d EH |
299 | |
300 | /* Enable/disable GFX per cu powergating through SMU */ | |
301 | return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr, | |
302 | state == AMD_PG_STATE_GATE ? true : false); | |
1f7371b2 AD |
303 | } |
304 | ||
305 | static int pp_suspend(void *handle) | |
306 | { | |
577bbe01 RZ |
307 | struct pp_instance *pp_handle; |
308 | struct pp_eventmgr *eventmgr; | |
309 | struct pem_event_data event_data = { {0} }; | |
310 | ||
311 | if (handle == NULL) | |
312 | return -EINVAL; | |
313 | ||
314 | pp_handle = (struct pp_instance *)handle; | |
315 | eventmgr = pp_handle->eventmgr; | |
316 | pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); | |
1f7371b2 AD |
317 | return 0; |
318 | } | |
319 | ||
320 | static int pp_resume(void *handle) | |
321 | { | |
577bbe01 RZ |
322 | struct pp_instance *pp_handle; |
323 | struct pp_eventmgr *eventmgr; | |
324 | struct pem_event_data event_data = { {0} }; | |
e0b71a7e RZ |
325 | struct pp_smumgr *smumgr; |
326 | int ret; | |
577bbe01 RZ |
327 | |
328 | if (handle == NULL) | |
329 | return -EINVAL; | |
330 | ||
331 | pp_handle = (struct pp_instance *)handle; | |
e0b71a7e RZ |
332 | smumgr = pp_handle->smu_mgr; |
333 | ||
334 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
335 | smumgr->smumgr_funcs->start_smu == NULL) | |
336 | return -EINVAL; | |
337 | ||
338 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
339 | if (ret) { | |
340 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
341 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
342 | return ret; | |
343 | } | |
344 | ||
577bbe01 RZ |
345 | eventmgr = pp_handle->eventmgr; |
346 | pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); | |
e0b71a7e | 347 | |
1f7371b2 AD |
348 | return 0; |
349 | } | |
350 | ||
351 | const struct amd_ip_funcs pp_ip_funcs = { | |
88a907d6 | 352 | .name = "powerplay", |
1f7371b2 AD |
353 | .early_init = pp_early_init, |
354 | .late_init = NULL, | |
355 | .sw_init = pp_sw_init, | |
356 | .sw_fini = pp_sw_fini, | |
357 | .hw_init = pp_hw_init, | |
358 | .hw_fini = pp_hw_fini, | |
359 | .suspend = pp_suspend, | |
360 | .resume = pp_resume, | |
361 | .is_idle = pp_is_idle, | |
362 | .wait_for_idle = pp_wait_for_idle, | |
363 | .soft_reset = pp_sw_reset, | |
1f7371b2 AD |
364 | .set_clockgating_state = pp_set_clockgating_state, |
365 | .set_powergating_state = pp_set_powergating_state, | |
366 | }; | |
367 | ||
368 | static int pp_dpm_load_fw(void *handle) | |
369 | { | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static int pp_dpm_fw_loading_complete(void *handle) | |
374 | { | |
375 | return 0; | |
376 | } | |
377 | ||
378 | static int pp_dpm_force_performance_level(void *handle, | |
379 | enum amd_dpm_forced_level level) | |
380 | { | |
577bbe01 RZ |
381 | struct pp_instance *pp_handle; |
382 | struct pp_hwmgr *hwmgr; | |
383 | ||
384 | if (handle == NULL) | |
385 | return -EINVAL; | |
386 | ||
387 | pp_handle = (struct pp_instance *)handle; | |
388 | ||
389 | hwmgr = pp_handle->hwmgr; | |
390 | ||
7383bcb9 RZ |
391 | PP_CHECK_HW(hwmgr); |
392 | ||
393 | if (hwmgr->hwmgr_func->force_dpm_level == NULL) { | |
394 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
395 | return 0; | |
396 | } | |
577bbe01 RZ |
397 | |
398 | hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); | |
399 | ||
1f7371b2 AD |
400 | return 0; |
401 | } | |
577bbe01 | 402 | |
1f7371b2 AD |
403 | static enum amd_dpm_forced_level pp_dpm_get_performance_level( |
404 | void *handle) | |
405 | { | |
577bbe01 RZ |
406 | struct pp_hwmgr *hwmgr; |
407 | ||
408 | if (handle == NULL) | |
409 | return -EINVAL; | |
410 | ||
411 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
412 | ||
413 | if (hwmgr == NULL) | |
414 | return -EINVAL; | |
415 | ||
416 | return (((struct pp_instance *)handle)->hwmgr->dpm_level); | |
1f7371b2 | 417 | } |
577bbe01 | 418 | |
1f7371b2 AD |
419 | static int pp_dpm_get_sclk(void *handle, bool low) |
420 | { | |
577bbe01 RZ |
421 | struct pp_hwmgr *hwmgr; |
422 | ||
423 | if (handle == NULL) | |
424 | return -EINVAL; | |
425 | ||
426 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
427 | ||
7383bcb9 RZ |
428 | PP_CHECK_HW(hwmgr); |
429 | ||
430 | if (hwmgr->hwmgr_func->get_sclk == NULL) { | |
431 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
432 | return 0; | |
433 | } | |
577bbe01 RZ |
434 | |
435 | return hwmgr->hwmgr_func->get_sclk(hwmgr, low); | |
1f7371b2 | 436 | } |
577bbe01 | 437 | |
1f7371b2 AD |
438 | static int pp_dpm_get_mclk(void *handle, bool low) |
439 | { | |
577bbe01 RZ |
440 | struct pp_hwmgr *hwmgr; |
441 | ||
442 | if (handle == NULL) | |
443 | return -EINVAL; | |
444 | ||
445 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
446 | ||
7383bcb9 RZ |
447 | PP_CHECK_HW(hwmgr); |
448 | ||
449 | if (hwmgr->hwmgr_func->get_mclk == NULL) { | |
450 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
451 | return 0; | |
452 | } | |
577bbe01 RZ |
453 | |
454 | return hwmgr->hwmgr_func->get_mclk(hwmgr, low); | |
1f7371b2 | 455 | } |
577bbe01 | 456 | |
1f7371b2 AD |
457 | static int pp_dpm_powergate_vce(void *handle, bool gate) |
458 | { | |
577bbe01 RZ |
459 | struct pp_hwmgr *hwmgr; |
460 | ||
461 | if (handle == NULL) | |
462 | return -EINVAL; | |
463 | ||
464 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
465 | ||
7383bcb9 RZ |
466 | PP_CHECK_HW(hwmgr); |
467 | ||
468 | if (hwmgr->hwmgr_func->powergate_vce == NULL) { | |
469 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
470 | return 0; | |
471 | } | |
577bbe01 RZ |
472 | |
473 | return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); | |
1f7371b2 | 474 | } |
577bbe01 | 475 | |
1f7371b2 AD |
476 | static int pp_dpm_powergate_uvd(void *handle, bool gate) |
477 | { | |
577bbe01 RZ |
478 | struct pp_hwmgr *hwmgr; |
479 | ||
480 | if (handle == NULL) | |
481 | return -EINVAL; | |
482 | ||
483 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
484 | ||
7383bcb9 RZ |
485 | PP_CHECK_HW(hwmgr); |
486 | ||
487 | if (hwmgr->hwmgr_func->powergate_uvd == NULL) { | |
488 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
489 | return 0; | |
490 | } | |
577bbe01 RZ |
491 | |
492 | return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); | |
493 | } | |
494 | ||
495 | static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) | |
496 | { | |
497 | switch (state) { | |
498 | case POWER_STATE_TYPE_BATTERY: | |
499 | return PP_StateUILabel_Battery; | |
500 | case POWER_STATE_TYPE_BALANCED: | |
501 | return PP_StateUILabel_Balanced; | |
502 | case POWER_STATE_TYPE_PERFORMANCE: | |
503 | return PP_StateUILabel_Performance; | |
504 | default: | |
505 | return PP_StateUILabel_None; | |
506 | } | |
1f7371b2 AD |
507 | } |
508 | ||
509 | int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) | |
510 | { | |
577bbe01 RZ |
511 | int ret = 0; |
512 | struct pp_instance *pp_handle; | |
513 | struct pem_event_data data = { {0} }; | |
514 | ||
515 | pp_handle = (struct pp_instance *)handle; | |
516 | ||
517 | if (pp_handle == NULL) | |
518 | return -EINVAL; | |
519 | ||
520 | switch (event_id) { | |
521 | case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: | |
522 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
523 | break; | |
524 | case AMD_PP_EVENT_ENABLE_USER_STATE: | |
525 | { | |
526 | enum amd_pm_state_type ps; | |
527 | ||
528 | if (input == NULL) | |
529 | return -EINVAL; | |
530 | ps = *(unsigned long *)input; | |
531 | ||
532 | data.requested_ui_label = power_state_convert(ps); | |
533 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
dc26a2a2 | 534 | break; |
577bbe01 | 535 | } |
dc26a2a2 RZ |
536 | case AMD_PP_EVENT_COMPLETE_INIT: |
537 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
538 | break; | |
577bbe01 RZ |
539 | default: |
540 | break; | |
541 | } | |
542 | return ret; | |
1f7371b2 | 543 | } |
577bbe01 | 544 | |
1f7371b2 AD |
545 | enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) |
546 | { | |
577bbe01 RZ |
547 | struct pp_hwmgr *hwmgr; |
548 | struct pp_power_state *state; | |
549 | ||
550 | if (handle == NULL) | |
551 | return -EINVAL; | |
552 | ||
553 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
554 | ||
555 | if (hwmgr == NULL || hwmgr->current_ps == NULL) | |
556 | return -EINVAL; | |
557 | ||
558 | state = hwmgr->current_ps; | |
559 | ||
560 | switch (state->classification.ui_label) { | |
561 | case PP_StateUILabel_Battery: | |
562 | return POWER_STATE_TYPE_BATTERY; | |
563 | case PP_StateUILabel_Balanced: | |
564 | return POWER_STATE_TYPE_BALANCED; | |
565 | case PP_StateUILabel_Performance: | |
566 | return POWER_STATE_TYPE_PERFORMANCE; | |
567 | default: | |
f3898ea1 EH |
568 | if (state->classification.flags & PP_StateClassificationFlag_Boot) |
569 | return POWER_STATE_TYPE_INTERNAL_BOOT; | |
570 | else | |
571 | return POWER_STATE_TYPE_DEFAULT; | |
577bbe01 | 572 | } |
1f7371b2 | 573 | } |
577bbe01 | 574 | |
1f7371b2 AD |
575 | static void |
576 | pp_debugfs_print_current_performance_level(void *handle, | |
577 | struct seq_file *m) | |
578 | { | |
577bbe01 RZ |
579 | struct pp_hwmgr *hwmgr; |
580 | ||
581 | if (handle == NULL) | |
582 | return; | |
583 | ||
584 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
585 | ||
7383bcb9 RZ |
586 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL) |
587 | return; | |
588 | ||
589 | if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) { | |
590 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
577bbe01 | 591 | return; |
7383bcb9 | 592 | } |
577bbe01 RZ |
593 | |
594 | hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); | |
1f7371b2 | 595 | } |
3bace359 | 596 | |
cac9a199 RZ |
597 | static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) |
598 | { | |
599 | struct pp_hwmgr *hwmgr; | |
600 | ||
601 | if (handle == NULL) | |
602 | return -EINVAL; | |
603 | ||
604 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
605 | ||
7383bcb9 RZ |
606 | PP_CHECK_HW(hwmgr); |
607 | ||
608 | if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { | |
609 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
610 | return 0; | |
611 | } | |
cac9a199 RZ |
612 | |
613 | return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); | |
614 | } | |
615 | ||
616 | static int pp_dpm_get_fan_control_mode(void *handle) | |
617 | { | |
618 | struct pp_hwmgr *hwmgr; | |
619 | ||
620 | if (handle == NULL) | |
621 | return -EINVAL; | |
622 | ||
623 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
624 | ||
7383bcb9 RZ |
625 | PP_CHECK_HW(hwmgr); |
626 | ||
627 | if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) { | |
628 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
629 | return 0; | |
630 | } | |
cac9a199 RZ |
631 | |
632 | return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); | |
633 | } | |
634 | ||
635 | static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) | |
636 | { | |
637 | struct pp_hwmgr *hwmgr; | |
638 | ||
639 | if (handle == NULL) | |
640 | return -EINVAL; | |
641 | ||
642 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
643 | ||
7383bcb9 RZ |
644 | PP_CHECK_HW(hwmgr); |
645 | ||
646 | if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) { | |
647 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
648 | return 0; | |
649 | } | |
cac9a199 RZ |
650 | |
651 | return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); | |
652 | } | |
653 | ||
654 | static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) | |
655 | { | |
656 | struct pp_hwmgr *hwmgr; | |
657 | ||
658 | if (handle == NULL) | |
659 | return -EINVAL; | |
660 | ||
661 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
662 | ||
7383bcb9 RZ |
663 | PP_CHECK_HW(hwmgr); |
664 | ||
665 | if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) { | |
666 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
667 | return 0; | |
668 | } | |
cac9a199 RZ |
669 | |
670 | return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); | |
671 | } | |
672 | ||
673 | static int pp_dpm_get_temperature(void *handle) | |
674 | { | |
675 | struct pp_hwmgr *hwmgr; | |
676 | ||
677 | if (handle == NULL) | |
678 | return -EINVAL; | |
679 | ||
680 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
681 | ||
7383bcb9 RZ |
682 | PP_CHECK_HW(hwmgr); |
683 | ||
684 | if (hwmgr->hwmgr_func->get_temperature == NULL) { | |
685 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
686 | return 0; | |
687 | } | |
cac9a199 RZ |
688 | |
689 | return hwmgr->hwmgr_func->get_temperature(hwmgr); | |
690 | } | |
577bbe01 | 691 | |
f3898ea1 EH |
692 | static int pp_dpm_get_pp_num_states(void *handle, |
693 | struct pp_states_info *data) | |
694 | { | |
695 | struct pp_hwmgr *hwmgr; | |
696 | int i; | |
697 | ||
698 | if (!handle) | |
699 | return -EINVAL; | |
700 | ||
701 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
702 | ||
703 | if (hwmgr == NULL || hwmgr->ps == NULL) | |
704 | return -EINVAL; | |
705 | ||
706 | data->nums = hwmgr->num_ps; | |
707 | ||
708 | for (i = 0; i < hwmgr->num_ps; i++) { | |
709 | struct pp_power_state *state = (struct pp_power_state *) | |
710 | ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); | |
711 | switch (state->classification.ui_label) { | |
712 | case PP_StateUILabel_Battery: | |
713 | data->states[i] = POWER_STATE_TYPE_BATTERY; | |
714 | break; | |
715 | case PP_StateUILabel_Balanced: | |
716 | data->states[i] = POWER_STATE_TYPE_BALANCED; | |
717 | break; | |
718 | case PP_StateUILabel_Performance: | |
719 | data->states[i] = POWER_STATE_TYPE_PERFORMANCE; | |
720 | break; | |
721 | default: | |
722 | if (state->classification.flags & PP_StateClassificationFlag_Boot) | |
723 | data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; | |
724 | else | |
725 | data->states[i] = POWER_STATE_TYPE_DEFAULT; | |
726 | } | |
727 | } | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
732 | static int pp_dpm_get_pp_table(void *handle, char **table) | |
733 | { | |
734 | struct pp_hwmgr *hwmgr; | |
735 | ||
736 | if (!handle) | |
737 | return -EINVAL; | |
738 | ||
739 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
740 | ||
7383bcb9 RZ |
741 | PP_CHECK_HW(hwmgr); |
742 | ||
743 | if (hwmgr->hwmgr_func->get_pp_table == NULL) { | |
744 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
745 | return 0; | |
746 | } | |
f3898ea1 EH |
747 | |
748 | return hwmgr->hwmgr_func->get_pp_table(hwmgr, table); | |
749 | } | |
750 | ||
751 | static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) | |
752 | { | |
753 | struct pp_hwmgr *hwmgr; | |
754 | ||
755 | if (!handle) | |
756 | return -EINVAL; | |
757 | ||
758 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
759 | ||
7383bcb9 RZ |
760 | PP_CHECK_HW(hwmgr); |
761 | ||
762 | if (hwmgr->hwmgr_func->set_pp_table == NULL) { | |
763 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
764 | return 0; | |
765 | } | |
f3898ea1 EH |
766 | |
767 | return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size); | |
768 | } | |
769 | ||
770 | static int pp_dpm_force_clock_level(void *handle, | |
5632708f | 771 | enum pp_clock_type type, uint32_t mask) |
f3898ea1 EH |
772 | { |
773 | struct pp_hwmgr *hwmgr; | |
774 | ||
775 | if (!handle) | |
776 | return -EINVAL; | |
777 | ||
778 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
779 | ||
7383bcb9 RZ |
780 | PP_CHECK_HW(hwmgr); |
781 | ||
782 | if (hwmgr->hwmgr_func->force_clock_level == NULL) { | |
783 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
784 | return 0; | |
785 | } | |
f3898ea1 | 786 | |
5632708f | 787 | return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); |
f3898ea1 EH |
788 | } |
789 | ||
790 | static int pp_dpm_print_clock_levels(void *handle, | |
791 | enum pp_clock_type type, char *buf) | |
792 | { | |
793 | struct pp_hwmgr *hwmgr; | |
794 | ||
795 | if (!handle) | |
796 | return -EINVAL; | |
797 | ||
798 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
799 | ||
7383bcb9 | 800 | PP_CHECK_HW(hwmgr); |
f3898ea1 | 801 | |
7383bcb9 RZ |
802 | if (hwmgr->hwmgr_func->print_clock_levels == NULL) { |
803 | printk(KERN_INFO "%s was not implemented.\n", __func__); | |
804 | return 0; | |
805 | } | |
f3898ea1 EH |
806 | return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); |
807 | } | |
808 | ||
1f7371b2 | 809 | const struct amd_powerplay_funcs pp_dpm_funcs = { |
cac9a199 | 810 | .get_temperature = pp_dpm_get_temperature, |
1f7371b2 AD |
811 | .load_firmware = pp_dpm_load_fw, |
812 | .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, | |
813 | .force_performance_level = pp_dpm_force_performance_level, | |
814 | .get_performance_level = pp_dpm_get_performance_level, | |
815 | .get_current_power_state = pp_dpm_get_current_power_state, | |
816 | .get_sclk = pp_dpm_get_sclk, | |
817 | .get_mclk = pp_dpm_get_mclk, | |
818 | .powergate_vce = pp_dpm_powergate_vce, | |
819 | .powergate_uvd = pp_dpm_powergate_uvd, | |
820 | .dispatch_tasks = pp_dpm_dispatch_tasks, | |
821 | .print_current_performance_level = pp_debugfs_print_current_performance_level, | |
cac9a199 RZ |
822 | .set_fan_control_mode = pp_dpm_set_fan_control_mode, |
823 | .get_fan_control_mode = pp_dpm_get_fan_control_mode, | |
824 | .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, | |
825 | .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, | |
f3898ea1 EH |
826 | .get_pp_num_states = pp_dpm_get_pp_num_states, |
827 | .get_pp_table = pp_dpm_get_pp_table, | |
828 | .set_pp_table = pp_dpm_set_pp_table, | |
829 | .force_clock_level = pp_dpm_force_clock_level, | |
830 | .print_clock_levels = pp_dpm_print_clock_levels, | |
1f7371b2 AD |
831 | }; |
832 | ||
ac885b3a JZ |
833 | static int amd_pp_instance_init(struct amd_pp_init *pp_init, |
834 | struct amd_powerplay *amd_pp) | |
835 | { | |
836 | int ret; | |
837 | struct pp_instance *handle; | |
838 | ||
839 | handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); | |
840 | if (handle == NULL) | |
841 | return -ENOMEM; | |
842 | ||
a969e163 RZ |
843 | handle->pp_valid = PP_VALID; |
844 | ||
ac885b3a JZ |
845 | ret = smum_init(pp_init, handle); |
846 | if (ret) | |
3bace359 JZ |
847 | goto fail_smum; |
848 | ||
849 | ret = hwmgr_init(pp_init, handle); | |
850 | if (ret) | |
851 | goto fail_hwmgr; | |
ac885b3a | 852 | |
e92a0370 RZ |
853 | ret = eventmgr_init(handle); |
854 | if (ret) | |
855 | goto fail_eventmgr; | |
856 | ||
ac885b3a JZ |
857 | amd_pp->pp_handle = handle; |
858 | return 0; | |
3bace359 | 859 | |
e92a0370 RZ |
860 | fail_eventmgr: |
861 | hwmgr_fini(handle->hwmgr); | |
3bace359 JZ |
862 | fail_hwmgr: |
863 | smum_fini(handle->smu_mgr); | |
864 | fail_smum: | |
865 | kfree(handle); | |
866 | return ret; | |
ac885b3a JZ |
867 | } |
868 | ||
869 | static int amd_pp_instance_fini(void *handle) | |
870 | { | |
871 | struct pp_instance *instance = (struct pp_instance *)handle; | |
e92a0370 | 872 | |
ac885b3a JZ |
873 | if (instance == NULL) |
874 | return -EINVAL; | |
875 | ||
e92a0370 RZ |
876 | eventmgr_fini(instance->eventmgr); |
877 | ||
3bace359 JZ |
878 | hwmgr_fini(instance->hwmgr); |
879 | ||
ac885b3a JZ |
880 | smum_fini(instance->smu_mgr); |
881 | ||
882 | kfree(handle); | |
883 | return 0; | |
884 | } | |
885 | ||
1f7371b2 AD |
886 | int amd_powerplay_init(struct amd_pp_init *pp_init, |
887 | struct amd_powerplay *amd_pp) | |
888 | { | |
ac885b3a JZ |
889 | int ret; |
890 | ||
1f7371b2 AD |
891 | if (pp_init == NULL || amd_pp == NULL) |
892 | return -EINVAL; | |
893 | ||
ac885b3a JZ |
894 | ret = amd_pp_instance_init(pp_init, amd_pp); |
895 | ||
896 | if (ret) | |
897 | return ret; | |
898 | ||
1f7371b2 AD |
899 | amd_pp->ip_funcs = &pp_ip_funcs; |
900 | amd_pp->pp_funcs = &pp_dpm_funcs; | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | int amd_powerplay_fini(void *handle) | |
906 | { | |
ac885b3a JZ |
907 | amd_pp_instance_fini(handle); |
908 | ||
1f7371b2 AD |
909 | return 0; |
910 | } | |
7fb72a1f RZ |
911 | |
912 | /* export this function to DAL */ | |
913 | ||
155f1127 DR |
914 | int amd_powerplay_display_configuration_change(void *handle, |
915 | const struct amd_pp_display_configuration *display_config) | |
7fb72a1f RZ |
916 | { |
917 | struct pp_hwmgr *hwmgr; | |
7fb72a1f | 918 | |
a969e163 | 919 | PP_CHECK((struct pp_instance *)handle); |
7fb72a1f RZ |
920 | |
921 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
922 | ||
923 | phm_store_dal_configuration_data(hwmgr, display_config); | |
e0b71a7e | 924 | |
7fb72a1f RZ |
925 | return 0; |
926 | } | |
c4dd206b | 927 | |
1c9a9082 | 928 | int amd_powerplay_get_display_power_level(void *handle, |
47329134 | 929 | struct amd_pp_simple_clock_info *output) |
c4dd206b VP |
930 | { |
931 | struct pp_hwmgr *hwmgr; | |
932 | ||
a969e163 RZ |
933 | PP_CHECK((struct pp_instance *)handle); |
934 | ||
935 | if (output == NULL) | |
c4dd206b VP |
936 | return -EINVAL; |
937 | ||
938 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
939 | ||
1c9a9082 | 940 | return phm_get_dal_power_level(hwmgr, output); |
c4dd206b | 941 | } |
e273b041 RZ |
942 | |
943 | int amd_powerplay_get_current_clocks(void *handle, | |
155f1127 | 944 | struct amd_pp_clock_info *clocks) |
e273b041 RZ |
945 | { |
946 | struct pp_hwmgr *hwmgr; | |
947 | struct amd_pp_simple_clock_info simple_clocks; | |
948 | struct pp_clock_info hw_clocks; | |
e273b041 | 949 | |
fa9e6991 RZ |
950 | PP_CHECK((struct pp_instance *)handle); |
951 | ||
952 | if (clocks == NULL) | |
e273b041 RZ |
953 | return -EINVAL; |
954 | ||
955 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
956 | ||
957 | phm_get_dal_power_level(hwmgr, &simple_clocks); | |
958 | ||
959 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { | |
960 | if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment)) | |
961 | PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1); | |
962 | } else { | |
963 | if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity)) | |
964 | PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1); | |
965 | } | |
966 | ||
967 | clocks->min_engine_clock = hw_clocks.min_eng_clk; | |
968 | clocks->max_engine_clock = hw_clocks.max_eng_clk; | |
969 | clocks->min_memory_clock = hw_clocks.min_mem_clk; | |
970 | clocks->max_memory_clock = hw_clocks.max_mem_clk; | |
971 | clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; | |
972 | clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; | |
973 | ||
974 | clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; | |
975 | clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; | |
976 | ||
977 | clocks->max_clocks_state = simple_clocks.level; | |
978 | ||
979 | if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { | |
980 | clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; | |
981 | clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; | |
982 | } | |
983 | ||
984 | return 0; | |
985 | ||
986 | } | |
987 | ||
988 | int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) | |
989 | { | |
990 | int result = -1; | |
991 | ||
992 | struct pp_hwmgr *hwmgr; | |
993 | ||
fa9e6991 RZ |
994 | PP_CHECK((struct pp_instance *)handle); |
995 | ||
996 | if (clocks == NULL) | |
e273b041 RZ |
997 | return -EINVAL; |
998 | ||
999 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
1000 | ||
1001 | result = phm_get_clock_by_type(hwmgr, type, clocks); | |
1002 | ||
1003 | return result; | |
1004 | } | |
1005 | ||
155f1127 DR |
1006 | int amd_powerplay_get_display_mode_validation_clocks(void *handle, |
1007 | struct amd_pp_simple_clock_info *clocks) | |
e273b041 RZ |
1008 | { |
1009 | int result = -1; | |
e273b041 RZ |
1010 | struct pp_hwmgr *hwmgr; |
1011 | ||
fa9e6991 RZ |
1012 | PP_CHECK((struct pp_instance *)handle); |
1013 | ||
1014 | if (clocks == NULL) | |
e273b041 RZ |
1015 | return -EINVAL; |
1016 | ||
1017 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
1018 | ||
1019 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) | |
1020 | result = phm_get_max_high_clocks(hwmgr, clocks); | |
1021 | ||
1022 | return result; | |
1023 | } | |
1024 |