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1f7371b2 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/types.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/gfp.h> | |
ac885b3a | 26 | #include <linux/slab.h> |
1f7371b2 AD |
27 | #include "amd_shared.h" |
28 | #include "amd_powerplay.h" | |
ac885b3a | 29 | #include "pp_instance.h" |
577bbe01 RZ |
30 | #include "power_state.h" |
31 | #include "eventmanager.h" | |
1f7371b2 | 32 | |
a969e163 RZ |
33 | #define PP_CHECK(handle) \ |
34 | do { \ | |
35 | if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \ | |
36 | return -EINVAL; \ | |
37 | } while (0) | |
38 | ||
1f7371b2 AD |
39 | static int pp_early_init(void *handle) |
40 | { | |
41 | return 0; | |
42 | } | |
43 | ||
44 | static int pp_sw_init(void *handle) | |
45 | { | |
3bace359 JZ |
46 | struct pp_instance *pp_handle; |
47 | struct pp_hwmgr *hwmgr; | |
48 | int ret = 0; | |
49 | ||
50 | if (handle == NULL) | |
51 | return -EINVAL; | |
52 | ||
53 | pp_handle = (struct pp_instance *)handle; | |
54 | hwmgr = pp_handle->hwmgr; | |
55 | ||
56 | if (hwmgr == NULL || hwmgr->pptable_func == NULL || | |
57 | hwmgr->hwmgr_func == NULL || | |
58 | hwmgr->pptable_func->pptable_init == NULL || | |
59 | hwmgr->hwmgr_func->backend_init == NULL) | |
60 | return -EINVAL; | |
61 | ||
62 | ret = hwmgr->pptable_func->pptable_init(hwmgr); | |
e92a0370 | 63 | |
3bace359 JZ |
64 | if (ret == 0) |
65 | ret = hwmgr->hwmgr_func->backend_init(hwmgr); | |
66 | ||
9441f964 AD |
67 | if (ret) |
68 | printk("amdgpu: powerplay initialization failed\n"); | |
69 | else | |
70 | printk("amdgpu: powerplay initialized\n"); | |
71 | ||
3bace359 | 72 | return ret; |
1f7371b2 AD |
73 | } |
74 | ||
75 | static int pp_sw_fini(void *handle) | |
76 | { | |
3bace359 JZ |
77 | struct pp_instance *pp_handle; |
78 | struct pp_hwmgr *hwmgr; | |
79 | int ret = 0; | |
80 | ||
81 | if (handle == NULL) | |
82 | return -EINVAL; | |
83 | ||
84 | pp_handle = (struct pp_instance *)handle; | |
85 | hwmgr = pp_handle->hwmgr; | |
86 | ||
87 | if (hwmgr != NULL || hwmgr->hwmgr_func != NULL || | |
88 | hwmgr->hwmgr_func->backend_fini != NULL) | |
89 | ret = hwmgr->hwmgr_func->backend_fini(hwmgr); | |
90 | ||
91 | return ret; | |
1f7371b2 AD |
92 | } |
93 | ||
94 | static int pp_hw_init(void *handle) | |
95 | { | |
ac885b3a JZ |
96 | struct pp_instance *pp_handle; |
97 | struct pp_smumgr *smumgr; | |
e92a0370 | 98 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
99 | int ret = 0; |
100 | ||
101 | if (handle == NULL) | |
102 | return -EINVAL; | |
103 | ||
104 | pp_handle = (struct pp_instance *)handle; | |
105 | smumgr = pp_handle->smu_mgr; | |
106 | ||
107 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
108 | smumgr->smumgr_funcs->smu_init == NULL || | |
109 | smumgr->smumgr_funcs->start_smu == NULL) | |
110 | return -EINVAL; | |
111 | ||
112 | ret = smumgr->smumgr_funcs->smu_init(smumgr); | |
113 | if (ret) { | |
114 | printk(KERN_ERR "[ powerplay ] smc initialization failed\n"); | |
115 | return ret; | |
116 | } | |
117 | ||
118 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
119 | if (ret) { | |
120 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
121 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
122 | return ret; | |
123 | } | |
e92a0370 | 124 | |
3bace359 | 125 | hw_init_power_state_table(pp_handle->hwmgr); |
e92a0370 | 126 | eventmgr = pp_handle->eventmgr; |
3bace359 | 127 | |
e92a0370 RZ |
128 | if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) |
129 | return -EINVAL; | |
130 | ||
131 | ret = eventmgr->pp_eventmgr_init(eventmgr); | |
1f7371b2 AD |
132 | return 0; |
133 | } | |
134 | ||
135 | static int pp_hw_fini(void *handle) | |
136 | { | |
ac885b3a JZ |
137 | struct pp_instance *pp_handle; |
138 | struct pp_smumgr *smumgr; | |
e92a0370 | 139 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
140 | |
141 | if (handle == NULL) | |
142 | return -EINVAL; | |
143 | ||
144 | pp_handle = (struct pp_instance *)handle; | |
e92a0370 RZ |
145 | eventmgr = pp_handle->eventmgr; |
146 | ||
147 | if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL) | |
148 | eventmgr->pp_eventmgr_fini(eventmgr); | |
149 | ||
ac885b3a JZ |
150 | smumgr = pp_handle->smu_mgr; |
151 | ||
152 | if (smumgr != NULL || smumgr->smumgr_funcs != NULL || | |
153 | smumgr->smumgr_funcs->smu_fini != NULL) | |
154 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
155 | ||
1f7371b2 AD |
156 | return 0; |
157 | } | |
158 | ||
159 | static bool pp_is_idle(void *handle) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | ||
164 | static int pp_wait_for_idle(void *handle) | |
165 | { | |
166 | return 0; | |
167 | } | |
168 | ||
169 | static int pp_sw_reset(void *handle) | |
170 | { | |
171 | return 0; | |
172 | } | |
173 | ||
174 | static void pp_print_status(void *handle) | |
175 | { | |
176 | ||
177 | } | |
178 | ||
179 | static int pp_set_clockgating_state(void *handle, | |
180 | enum amd_clockgating_state state) | |
181 | { | |
182 | return 0; | |
183 | } | |
184 | ||
185 | static int pp_set_powergating_state(void *handle, | |
186 | enum amd_powergating_state state) | |
187 | { | |
188 | return 0; | |
189 | } | |
190 | ||
191 | static int pp_suspend(void *handle) | |
192 | { | |
577bbe01 RZ |
193 | struct pp_instance *pp_handle; |
194 | struct pp_eventmgr *eventmgr; | |
195 | struct pem_event_data event_data = { {0} }; | |
196 | ||
197 | if (handle == NULL) | |
198 | return -EINVAL; | |
199 | ||
200 | pp_handle = (struct pp_instance *)handle; | |
201 | eventmgr = pp_handle->eventmgr; | |
202 | pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); | |
1f7371b2 AD |
203 | return 0; |
204 | } | |
205 | ||
206 | static int pp_resume(void *handle) | |
207 | { | |
577bbe01 RZ |
208 | struct pp_instance *pp_handle; |
209 | struct pp_eventmgr *eventmgr; | |
210 | struct pem_event_data event_data = { {0} }; | |
e0b71a7e RZ |
211 | struct pp_smumgr *smumgr; |
212 | int ret; | |
577bbe01 RZ |
213 | |
214 | if (handle == NULL) | |
215 | return -EINVAL; | |
216 | ||
217 | pp_handle = (struct pp_instance *)handle; | |
e0b71a7e RZ |
218 | smumgr = pp_handle->smu_mgr; |
219 | ||
220 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
221 | smumgr->smumgr_funcs->start_smu == NULL) | |
222 | return -EINVAL; | |
223 | ||
224 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
225 | if (ret) { | |
226 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
227 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
228 | return ret; | |
229 | } | |
230 | ||
577bbe01 RZ |
231 | eventmgr = pp_handle->eventmgr; |
232 | pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); | |
e0b71a7e | 233 | |
1f7371b2 AD |
234 | return 0; |
235 | } | |
236 | ||
237 | const struct amd_ip_funcs pp_ip_funcs = { | |
238 | .early_init = pp_early_init, | |
239 | .late_init = NULL, | |
240 | .sw_init = pp_sw_init, | |
241 | .sw_fini = pp_sw_fini, | |
242 | .hw_init = pp_hw_init, | |
243 | .hw_fini = pp_hw_fini, | |
244 | .suspend = pp_suspend, | |
245 | .resume = pp_resume, | |
246 | .is_idle = pp_is_idle, | |
247 | .wait_for_idle = pp_wait_for_idle, | |
248 | .soft_reset = pp_sw_reset, | |
249 | .print_status = pp_print_status, | |
250 | .set_clockgating_state = pp_set_clockgating_state, | |
251 | .set_powergating_state = pp_set_powergating_state, | |
252 | }; | |
253 | ||
254 | static int pp_dpm_load_fw(void *handle) | |
255 | { | |
256 | return 0; | |
257 | } | |
258 | ||
259 | static int pp_dpm_fw_loading_complete(void *handle) | |
260 | { | |
261 | return 0; | |
262 | } | |
263 | ||
264 | static int pp_dpm_force_performance_level(void *handle, | |
265 | enum amd_dpm_forced_level level) | |
266 | { | |
577bbe01 RZ |
267 | struct pp_instance *pp_handle; |
268 | struct pp_hwmgr *hwmgr; | |
269 | ||
270 | if (handle == NULL) | |
271 | return -EINVAL; | |
272 | ||
273 | pp_handle = (struct pp_instance *)handle; | |
274 | ||
275 | hwmgr = pp_handle->hwmgr; | |
276 | ||
277 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
278 | hwmgr->hwmgr_func->force_dpm_level == NULL) | |
279 | return -EINVAL; | |
280 | ||
281 | hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); | |
282 | ||
1f7371b2 AD |
283 | return 0; |
284 | } | |
577bbe01 | 285 | |
1f7371b2 AD |
286 | static enum amd_dpm_forced_level pp_dpm_get_performance_level( |
287 | void *handle) | |
288 | { | |
577bbe01 RZ |
289 | struct pp_hwmgr *hwmgr; |
290 | ||
291 | if (handle == NULL) | |
292 | return -EINVAL; | |
293 | ||
294 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
295 | ||
296 | if (hwmgr == NULL) | |
297 | return -EINVAL; | |
298 | ||
299 | return (((struct pp_instance *)handle)->hwmgr->dpm_level); | |
1f7371b2 | 300 | } |
577bbe01 | 301 | |
1f7371b2 AD |
302 | static int pp_dpm_get_sclk(void *handle, bool low) |
303 | { | |
577bbe01 RZ |
304 | struct pp_hwmgr *hwmgr; |
305 | ||
306 | if (handle == NULL) | |
307 | return -EINVAL; | |
308 | ||
309 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
310 | ||
311 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
312 | hwmgr->hwmgr_func->get_sclk == NULL) | |
313 | return -EINVAL; | |
314 | ||
315 | return hwmgr->hwmgr_func->get_sclk(hwmgr, low); | |
1f7371b2 | 316 | } |
577bbe01 | 317 | |
1f7371b2 AD |
318 | static int pp_dpm_get_mclk(void *handle, bool low) |
319 | { | |
577bbe01 RZ |
320 | struct pp_hwmgr *hwmgr; |
321 | ||
322 | if (handle == NULL) | |
323 | return -EINVAL; | |
324 | ||
325 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
326 | ||
327 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
328 | hwmgr->hwmgr_func->get_mclk == NULL) | |
329 | return -EINVAL; | |
330 | ||
331 | return hwmgr->hwmgr_func->get_mclk(hwmgr, low); | |
1f7371b2 | 332 | } |
577bbe01 | 333 | |
1f7371b2 AD |
334 | static int pp_dpm_powergate_vce(void *handle, bool gate) |
335 | { | |
577bbe01 RZ |
336 | struct pp_hwmgr *hwmgr; |
337 | ||
338 | if (handle == NULL) | |
339 | return -EINVAL; | |
340 | ||
341 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
342 | ||
343 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
344 | hwmgr->hwmgr_func->powergate_vce == NULL) | |
345 | return -EINVAL; | |
346 | ||
347 | return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); | |
1f7371b2 | 348 | } |
577bbe01 | 349 | |
1f7371b2 AD |
350 | static int pp_dpm_powergate_uvd(void *handle, bool gate) |
351 | { | |
577bbe01 RZ |
352 | struct pp_hwmgr *hwmgr; |
353 | ||
354 | if (handle == NULL) | |
355 | return -EINVAL; | |
356 | ||
357 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
358 | ||
359 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
360 | hwmgr->hwmgr_func->powergate_uvd == NULL) | |
361 | return -EINVAL; | |
362 | ||
363 | return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); | |
364 | } | |
365 | ||
366 | static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) | |
367 | { | |
368 | switch (state) { | |
369 | case POWER_STATE_TYPE_BATTERY: | |
370 | return PP_StateUILabel_Battery; | |
371 | case POWER_STATE_TYPE_BALANCED: | |
372 | return PP_StateUILabel_Balanced; | |
373 | case POWER_STATE_TYPE_PERFORMANCE: | |
374 | return PP_StateUILabel_Performance; | |
375 | default: | |
376 | return PP_StateUILabel_None; | |
377 | } | |
1f7371b2 AD |
378 | } |
379 | ||
380 | int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) | |
381 | { | |
577bbe01 RZ |
382 | int ret = 0; |
383 | struct pp_instance *pp_handle; | |
384 | struct pem_event_data data = { {0} }; | |
385 | ||
386 | pp_handle = (struct pp_instance *)handle; | |
387 | ||
388 | if (pp_handle == NULL) | |
389 | return -EINVAL; | |
390 | ||
391 | switch (event_id) { | |
392 | case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: | |
393 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
394 | break; | |
395 | case AMD_PP_EVENT_ENABLE_USER_STATE: | |
396 | { | |
397 | enum amd_pm_state_type ps; | |
398 | ||
399 | if (input == NULL) | |
400 | return -EINVAL; | |
401 | ps = *(unsigned long *)input; | |
402 | ||
403 | data.requested_ui_label = power_state_convert(ps); | |
404 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
405 | } | |
406 | break; | |
407 | default: | |
408 | break; | |
409 | } | |
410 | return ret; | |
1f7371b2 | 411 | } |
577bbe01 | 412 | |
1f7371b2 AD |
413 | enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) |
414 | { | |
577bbe01 RZ |
415 | struct pp_hwmgr *hwmgr; |
416 | struct pp_power_state *state; | |
417 | ||
418 | if (handle == NULL) | |
419 | return -EINVAL; | |
420 | ||
421 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
422 | ||
423 | if (hwmgr == NULL || hwmgr->current_ps == NULL) | |
424 | return -EINVAL; | |
425 | ||
426 | state = hwmgr->current_ps; | |
427 | ||
428 | switch (state->classification.ui_label) { | |
429 | case PP_StateUILabel_Battery: | |
430 | return POWER_STATE_TYPE_BATTERY; | |
431 | case PP_StateUILabel_Balanced: | |
432 | return POWER_STATE_TYPE_BALANCED; | |
433 | case PP_StateUILabel_Performance: | |
434 | return POWER_STATE_TYPE_PERFORMANCE; | |
435 | default: | |
436 | return POWER_STATE_TYPE_DEFAULT; | |
437 | } | |
1f7371b2 | 438 | } |
577bbe01 | 439 | |
1f7371b2 AD |
440 | static void |
441 | pp_debugfs_print_current_performance_level(void *handle, | |
442 | struct seq_file *m) | |
443 | { | |
577bbe01 RZ |
444 | struct pp_hwmgr *hwmgr; |
445 | ||
446 | if (handle == NULL) | |
447 | return; | |
448 | ||
449 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
450 | ||
451 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
452 | hwmgr->hwmgr_func->print_current_perforce_level == NULL) | |
453 | return; | |
454 | ||
455 | hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); | |
1f7371b2 | 456 | } |
3bace359 | 457 | |
cac9a199 RZ |
458 | static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) |
459 | { | |
460 | struct pp_hwmgr *hwmgr; | |
461 | ||
462 | if (handle == NULL) | |
463 | return -EINVAL; | |
464 | ||
465 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
466 | ||
467 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
468 | hwmgr->hwmgr_func->set_fan_control_mode == NULL) | |
469 | return -EINVAL; | |
470 | ||
471 | return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); | |
472 | } | |
473 | ||
474 | static int pp_dpm_get_fan_control_mode(void *handle) | |
475 | { | |
476 | struct pp_hwmgr *hwmgr; | |
477 | ||
478 | if (handle == NULL) | |
479 | return -EINVAL; | |
480 | ||
481 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
482 | ||
483 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
484 | hwmgr->hwmgr_func->get_fan_control_mode == NULL) | |
485 | return -EINVAL; | |
486 | ||
487 | return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); | |
488 | } | |
489 | ||
490 | static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) | |
491 | { | |
492 | struct pp_hwmgr *hwmgr; | |
493 | ||
494 | if (handle == NULL) | |
495 | return -EINVAL; | |
496 | ||
497 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
498 | ||
499 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
500 | hwmgr->hwmgr_func->set_fan_speed_percent == NULL) | |
501 | return -EINVAL; | |
502 | ||
503 | return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); | |
504 | } | |
505 | ||
506 | static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) | |
507 | { | |
508 | struct pp_hwmgr *hwmgr; | |
509 | ||
510 | if (handle == NULL) | |
511 | return -EINVAL; | |
512 | ||
513 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
514 | ||
515 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
516 | hwmgr->hwmgr_func->get_fan_speed_percent == NULL) | |
517 | return -EINVAL; | |
518 | ||
519 | return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); | |
520 | } | |
521 | ||
522 | static int pp_dpm_get_temperature(void *handle) | |
523 | { | |
524 | struct pp_hwmgr *hwmgr; | |
525 | ||
526 | if (handle == NULL) | |
527 | return -EINVAL; | |
528 | ||
529 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
530 | ||
531 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
532 | hwmgr->hwmgr_func->get_temperature == NULL) | |
533 | return -EINVAL; | |
534 | ||
535 | return hwmgr->hwmgr_func->get_temperature(hwmgr); | |
536 | } | |
577bbe01 | 537 | |
1f7371b2 | 538 | const struct amd_powerplay_funcs pp_dpm_funcs = { |
cac9a199 | 539 | .get_temperature = pp_dpm_get_temperature, |
1f7371b2 AD |
540 | .load_firmware = pp_dpm_load_fw, |
541 | .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, | |
542 | .force_performance_level = pp_dpm_force_performance_level, | |
543 | .get_performance_level = pp_dpm_get_performance_level, | |
544 | .get_current_power_state = pp_dpm_get_current_power_state, | |
545 | .get_sclk = pp_dpm_get_sclk, | |
546 | .get_mclk = pp_dpm_get_mclk, | |
547 | .powergate_vce = pp_dpm_powergate_vce, | |
548 | .powergate_uvd = pp_dpm_powergate_uvd, | |
549 | .dispatch_tasks = pp_dpm_dispatch_tasks, | |
550 | .print_current_performance_level = pp_debugfs_print_current_performance_level, | |
cac9a199 RZ |
551 | .set_fan_control_mode = pp_dpm_set_fan_control_mode, |
552 | .get_fan_control_mode = pp_dpm_get_fan_control_mode, | |
553 | .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, | |
554 | .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, | |
1f7371b2 AD |
555 | }; |
556 | ||
ac885b3a JZ |
557 | static int amd_pp_instance_init(struct amd_pp_init *pp_init, |
558 | struct amd_powerplay *amd_pp) | |
559 | { | |
560 | int ret; | |
561 | struct pp_instance *handle; | |
562 | ||
563 | handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); | |
564 | if (handle == NULL) | |
565 | return -ENOMEM; | |
566 | ||
a969e163 RZ |
567 | handle->pp_valid = PP_VALID; |
568 | ||
ac885b3a JZ |
569 | ret = smum_init(pp_init, handle); |
570 | if (ret) | |
3bace359 JZ |
571 | goto fail_smum; |
572 | ||
573 | ret = hwmgr_init(pp_init, handle); | |
574 | if (ret) | |
575 | goto fail_hwmgr; | |
ac885b3a | 576 | |
e92a0370 RZ |
577 | ret = eventmgr_init(handle); |
578 | if (ret) | |
579 | goto fail_eventmgr; | |
580 | ||
ac885b3a JZ |
581 | amd_pp->pp_handle = handle; |
582 | return 0; | |
3bace359 | 583 | |
e92a0370 RZ |
584 | fail_eventmgr: |
585 | hwmgr_fini(handle->hwmgr); | |
3bace359 JZ |
586 | fail_hwmgr: |
587 | smum_fini(handle->smu_mgr); | |
588 | fail_smum: | |
589 | kfree(handle); | |
590 | return ret; | |
ac885b3a JZ |
591 | } |
592 | ||
593 | static int amd_pp_instance_fini(void *handle) | |
594 | { | |
595 | struct pp_instance *instance = (struct pp_instance *)handle; | |
e92a0370 | 596 | |
ac885b3a JZ |
597 | if (instance == NULL) |
598 | return -EINVAL; | |
599 | ||
e92a0370 RZ |
600 | eventmgr_fini(instance->eventmgr); |
601 | ||
3bace359 JZ |
602 | hwmgr_fini(instance->hwmgr); |
603 | ||
ac885b3a JZ |
604 | smum_fini(instance->smu_mgr); |
605 | ||
606 | kfree(handle); | |
607 | return 0; | |
608 | } | |
609 | ||
1f7371b2 AD |
610 | int amd_powerplay_init(struct amd_pp_init *pp_init, |
611 | struct amd_powerplay *amd_pp) | |
612 | { | |
ac885b3a JZ |
613 | int ret; |
614 | ||
1f7371b2 AD |
615 | if (pp_init == NULL || amd_pp == NULL) |
616 | return -EINVAL; | |
617 | ||
ac885b3a JZ |
618 | ret = amd_pp_instance_init(pp_init, amd_pp); |
619 | ||
620 | if (ret) | |
621 | return ret; | |
622 | ||
1f7371b2 AD |
623 | amd_pp->ip_funcs = &pp_ip_funcs; |
624 | amd_pp->pp_funcs = &pp_dpm_funcs; | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | int amd_powerplay_fini(void *handle) | |
630 | { | |
ac885b3a JZ |
631 | amd_pp_instance_fini(handle); |
632 | ||
1f7371b2 AD |
633 | return 0; |
634 | } | |
7fb72a1f RZ |
635 | |
636 | /* export this function to DAL */ | |
637 | ||
638 | int amd_powerplay_display_configuration_change(void *handle, const void *input) | |
639 | { | |
640 | struct pp_hwmgr *hwmgr; | |
641 | const struct amd_pp_display_configuration *display_config = input; | |
642 | ||
a969e163 | 643 | PP_CHECK((struct pp_instance *)handle); |
7fb72a1f RZ |
644 | |
645 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
646 | ||
647 | phm_store_dal_configuration_data(hwmgr, display_config); | |
e0b71a7e | 648 | |
7fb72a1f RZ |
649 | return 0; |
650 | } | |
c4dd206b | 651 | |
1c9a9082 VP |
652 | int amd_powerplay_get_display_power_level(void *handle, |
653 | struct amd_pp_dal_clock_info *output) | |
c4dd206b VP |
654 | { |
655 | struct pp_hwmgr *hwmgr; | |
656 | ||
a969e163 RZ |
657 | PP_CHECK((struct pp_instance *)handle); |
658 | ||
659 | if (output == NULL) | |
c4dd206b VP |
660 | return -EINVAL; |
661 | ||
662 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
663 | ||
1c9a9082 | 664 | return phm_get_dal_power_level(hwmgr, output); |
c4dd206b | 665 | } |