[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hardwaremanager.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/errno.h>
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "power_state.h"
#include "pp_debug.h"

#define PHM_FUNC_CHECK(hw) \
	do {							\
		if ((hw) == NULL || (hw)->hwmgr_func == NULL)	\
			return -EINVAL;				\
	} while (0)

bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
{
	return hwmgr->block_hw_access;
}

int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
{
	hwmgr->block_hw_access = block;
	return 0;
}

int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->asic_setup)
			return hwmgr->hwmgr_func->asic_setup(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_power_down_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_off_asic)
			return hwmgr->hwmgr_func->power_off_asic(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		    const struct pp_hw_power_state *pnew_power_state)
{
	struct phm_set_power_state_input states;

	PHM_FUNC_CHECK(hwmgr);

	states.pcurrent_state = pcurrent_state;
	states.pnew_state = pnew_power_state;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_state_set)
			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	}

	return 0;
}

int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	int ret = 1;
	bool enabled;
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
			ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	} else {
		ret = phm_dispatch_table(hwmgr,
				&(hwmgr->enable_dynamic_state_management),
				NULL, NULL);
	}

	enabled = ret == 0 ? true : false;

	cgs_notify_dpm_enabled(hwmgr->device, enabled);

	return ret;
}

int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	int ret = -1;
	bool enabled;

	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (hwmgr->hwmgr_func->dynamic_state_management_disable)
			ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
	} else {
		ret = phm_dispatch_table(hwmgr,
				&(hwmgr->disable_dynamic_state_management),
				NULL, NULL);
	}

	enabled = ret == 0 ? false : true;

	cgs_notify_dpm_enabled(hwmgr->device, enabled);

	return ret;
}

int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

	return 0;
}

int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
		return hwmgr->hwmgr_func->apply_state_adjust_rules(
									hwmgr,
								 adjusted_ps,
								 current_ps);
	return 0;
}

int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	return 0;
}

int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	return 0;
}

int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_vce != NULL)
		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	return 0;
}

int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	}
	return 0;
}

int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->display_config_changed)
			hwmgr->hwmgr_func->display_config_changed(hwmgr);
	} else
		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
	return 0;
}

int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface))
		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);

	return 0;
}

int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
}

int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
}

/**
* Initializes the thermal controller subsystem.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pTemperatureRange the address of the structure holding the temperature range.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
*/
int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
{
	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
}


bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
		return false;

	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
}


int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_states_equal == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
}

int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		    const struct amd_pp_display_configuration *display_config)
{
	PHM_FUNC_CHECK(hwmgr);

	if (display_config == NULL)
		return -EINVAL;

	hwmgr->display_config = *display_config;

	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
		return -EINVAL;

	/* TODO: pass other display configuration in the future */

	if (hwmgr->hwmgr_func->store_cc6_data)
		hwmgr->hwmgr_func->store_cc6_data(hwmgr,
				display_config->cpu_pstate_separation_time,
				display_config->cpu_cc6_disable,
				display_config->cpu_pstate_disable,
				display_config->nb_pstate_switch_disable);

	return 0;
}

int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_simple_clock_info *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
		return -EINVAL;
	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
}

int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);

	return 0;
}


int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
				PHM_PerformanceLevelDesignation designation, uint32_t index,
				PHM_PerformanceLevel *level)
{
	PHM_FUNC_CHECK(hwmgr);
	if (hwmgr->hwmgr_func->get_performance_level == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);


}


/**
* Gets Clock Info.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pPowerState the address of the Power State structure.
* @param    pClockInfo the address of PP_ClockInfo structure where the result will be returned.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
*/
int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
			PHM_PerformanceLevelDesignation designation)
{
	int result;
	PHM_PerformanceLevel performance_level;

	PHM_FUNC_CHECK(hwmgr);

	PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
	PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);

	result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);

	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);


	pclock_info->min_mem_clk = performance_level.memory_clock;
	pclock_info->min_eng_clk = performance_level.coreClock;
	pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;


	result = phm_get_performance_level(hwmgr, state, designation,
					(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);

	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);

	pclock_info->max_mem_clk = performance_level.memory_clock;
	pclock_info->max_eng_clk = performance_level.coreClock;
	pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;

	return 0;
}

int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);

}

int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);

}

int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
}
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/errno.h>
	24	#include "hwmgr.h"
	25	#include "hardwaremanager.h"
28a18bab	26	#include "power_state.h"
e273b041	27	#include "pp_debug.h"
3bace359	28
88b8dcbe RZ	29	#define PHM_FUNC_CHECK(hw) \
	30	do { \
	31	if ((hw) == NULL \|\| (hw)->hwmgr_func == NULL) \
	32	return -EINVAL; \
	33	} while (0)
	34
28a18bab RZ	35	bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
	36	{
	37	return hwmgr->block_hw_access;
	38	}
	39
	40	int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
	41	{
	42	hwmgr->block_hw_access = block;
	43	return 0;
	44	}
	45
3bace359 JZ	46	int phm_setup_asic(struct pp_hwmgr *hwmgr)
3bace359 JZ	47	{
88b8dcbe RZ	48	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	49
3bace359 JZ	50	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	51	PHM_PlatformCaps_TablelessHardwareInterface)) {
	52	if (NULL != hwmgr->hwmgr_func->asic_setup)
	53	return hwmgr->hwmgr_func->asic_setup(hwmgr);
	54	} else {
28a18bab	55	return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
3bace359 JZ	56	NULL, NULL);
	57	}
	58
	59	return 0;
	60	}
	61
e1d32e60 RZ	62	int phm_power_down_asic(struct pp_hwmgr *hwmgr)
	63	{
	64	PHM_FUNC_CHECK(hwmgr);
	65
	66	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	67	PHM_PlatformCaps_TablelessHardwareInterface)) {
	68	if (NULL != hwmgr->hwmgr_func->power_off_asic)
	69	return hwmgr->hwmgr_func->power_off_asic(hwmgr);
	70	} else {
	71	return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
	72	NULL, NULL);
	73	}
	74
	75	return 0;
	76	}
	77
28a18bab RZ	78	int phm_set_power_state(struct pp_hwmgr *hwmgr,
	79	const struct pp_hw_power_state *pcurrent_state,
	80	const struct pp_hw_power_state *pnew_power_state)
	81	{
	82	struct phm_set_power_state_input states;
	83
88b8dcbe RZ	84	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	85
28a18bab RZ	86	states.pcurrent_state = pcurrent_state;
	87	states.pnew_state = pnew_power_state;
	88
	89	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	90	PHM_PlatformCaps_TablelessHardwareInterface)) {
	91	if (NULL != hwmgr->hwmgr_func->power_state_set)
	92	return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	93	} else {
	94	return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	95	}
	96
	97	return 0;
	98	}
	99
3bace359 JZ	100	int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
3bace359 JZ	101	{
4cd05a74 RZ	102	int ret = 1;
4cd05a74 RZ	103	bool enabled;
88b8dcbe RZ	104	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	105
3bace359 JZ	106	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	107	PHM_PlatformCaps_TablelessHardwareInterface)) {
	108	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
4cd05a74	109	ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
3bace359	110	} else {
4cd05a74	111	ret = phm_dispatch_table(hwmgr,
3bace359 JZ	112	&(hwmgr->enable_dynamic_state_management),
	113	NULL, NULL);
	114	}
4cd05a74 RZ	115
	116	enabled = ret == 0 ? true : false;
	117
	118	cgs_notify_dpm_enabled(hwmgr->device, enabled);
	119
80597521 EH	120	return ret;
	121	}
	122
	123	int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
	124	{
	125	int ret = -1;
	126	bool enabled;
	127
	128	PHM_FUNC_CHECK(hwmgr);
	129
	130	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	131	PHM_PlatformCaps_TablelessHardwareInterface)) {
	132	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
	133	ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
	134	} else {
	135	ret = phm_dispatch_table(hwmgr,
	136	&(hwmgr->disable_dynamic_state_management),
	137	NULL, NULL);
	138	}
	139
	140	enabled = ret == 0 ? false : true;
	141
	142	cgs_notify_dpm_enabled(hwmgr->device, enabled);
	143
4cd05a74	144	return ret;
3bace359	145	}
28a18bab RZ	146
	147	int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
	148	{
88b8dcbe RZ	149	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	150
28a18bab RZ	151	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
	152	return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
	153
	154	return 0;
	155	}
	156
	157	int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
	158	struct pp_power_state *adjusted_ps,
	159	const struct pp_power_state *current_ps)
	160	{
88b8dcbe RZ	161	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	162
28a18bab RZ	163	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
	164	return hwmgr->hwmgr_func->apply_state_adjust_rules(
	165	hwmgr,
	166	adjusted_ps,
	167	current_ps);
	168	return 0;
	169	}
	170
	171	int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
	172	{
88b8dcbe RZ	173	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	174
28a18bab RZ	175	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
	176	return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	177	return 0;
	178	}
	179
	180	int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
	181	{
88b8dcbe RZ	182	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	183
28a18bab RZ	184	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
	185	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	186	return 0;
	187	}
	188
	189	int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
	190	{
88b8dcbe RZ	191	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	192
28a18bab RZ	193	if (hwmgr->hwmgr_func->powergate_vce != NULL)
	194	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	195	return 0;
	196	}
	197
	198	int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
	199	{
88b8dcbe RZ	200	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	201
28a18bab RZ	202	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	203	PHM_PlatformCaps_TablelessHardwareInterface)) {
	204	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
	205	return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	206	} else {
	207	return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	208	}
	209	return 0;
	210	}
6f3bf747 RZ	211
	212	int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
	213	{
88b8dcbe	214	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	215
	216	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	217	PHM_PlatformCaps_TablelessHardwareInterface)) {
	218	if (NULL != hwmgr->hwmgr_func->display_config_changed)
	219	hwmgr->hwmgr_func->display_config_changed(hwmgr);
	220	} else
	221	return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
73afe621	222	return 0;
6f3bf747 RZ	223	}
	224
	225	int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
	226	{
88b8dcbe	227	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	228
	229	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	230	PHM_PlatformCaps_TablelessHardwareInterface))
eafbbd98	231	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
6f3bf747 RZ	232	hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
6f3bf747 RZ	233
73afe621	234	return 0;
6f3bf747	235	}
fba4eef5 RZ	236
	237	int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
	238	{
88b8dcbe RZ	239	PHM_FUNC_CHECK(hwmgr);
	240
	241	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
fba4eef5 RZ	242	return -EINVAL;
	243
	244	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
	245	}
	246
	247	int phm_register_thermal_interrupt(struct pp_hwmgr hwmgr, const void info)
	248	{
88b8dcbe RZ	249	PHM_FUNC_CHECK(hwmgr);
	250
	251	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
fba4eef5 RZ	252	return -EINVAL;
	253
	254	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
	255	}
	256
	257	/**
	258	* Initializes the thermal controller subsystem.
	259	*
	260	* @param pHwMgr the address of the powerplay hardware manager.
	261	* @param pTemperatureRange the address of the structure holding the temperature range.
	262	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
	263	*/
	264	int phm_start_thermal_controller(struct pp_hwmgr hwmgr, struct PP_TemperatureRange temperature_range)
	265	{
fba4eef5 RZ	266	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
fba4eef5 RZ	267	}
09b4c872 RZ	268
	269
	270	bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
	271	{
88b8dcbe RZ	272	PHM_FUNC_CHECK(hwmgr);
	273
	274	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
f20024d8	275	return false;
09b4c872 RZ	276
	277	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
	278	}
	279
	280
	281	int phm_check_states_equal(struct pp_hwmgr *hwmgr,
	282	const struct pp_hw_power_state *pstate1,
	283	const struct pp_hw_power_state *pstate2,
	284	bool *equal)
	285	{
88b8dcbe RZ	286	PHM_FUNC_CHECK(hwmgr);
	287
	288	if (hwmgr->hwmgr_func->check_states_equal == NULL)
09b4c872 RZ	289	return -EINVAL;
	290
	291	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
	292	}
7fb72a1f RZ	293
	294	int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
	295	const struct amd_pp_display_configuration *display_config)
	296	{
88b8dcbe	297	PHM_FUNC_CHECK(hwmgr);
14f63411	298
1d7b84d1	299	if (display_config == NULL)
7fb72a1f RZ	300	return -EINVAL;
7fb72a1f RZ	301
14f63411	302	hwmgr->display_config = *display_config;
1d7b84d1 RZ	303
	304	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
	305	return -EINVAL;
	306
023efca2	307	/* TODO: pass other display configuration in the future */
7fb72a1f	308
14f63411 EY	309	if (hwmgr->hwmgr_func->store_cc6_data)
	310	hwmgr->hwmgr_func->store_cc6_data(hwmgr,
	311	display_config->cpu_pstate_separation_time,
	312	display_config->cpu_cc6_disable,
	313	display_config->cpu_pstate_disable,
	314	display_config->nb_pstate_switch_disable);
	315
	316	return 0;
7fb72a1f	317	}
73afe621	318
c4dd206b	319	int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
47329134	320	struct amd_pp_simple_clock_info *info)
c4dd206b	321	{
88b8dcbe RZ	322	PHM_FUNC_CHECK(hwmgr);
	323
	324	if (info == NULL \|\| hwmgr->hwmgr_func->get_dal_power_level == NULL)
c4dd206b	325	return -EINVAL;
1c9a9082	326	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
c4dd206b VP	327	}
c4dd206b VP	328
73afe621 RZ	329	int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
73afe621 RZ	330	{
88b8dcbe RZ	331	PHM_FUNC_CHECK(hwmgr);
	332
	333	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
73afe621 RZ	334	return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
	335
	336	return 0;
	337	}
e273b041 RZ	338
	339
	340	int phm_get_performance_level(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state,
	341	PHM_PerformanceLevelDesignation designation, uint32_t index,
	342	PHM_PerformanceLevel *level)
	343	{
	344	PHM_FUNC_CHECK(hwmgr);
	345	if (hwmgr->hwmgr_func->get_performance_level == NULL)
	346	return -EINVAL;
	347
	348	return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
	349
	350
	351	}
	352
	353
	354	/**
	355	* Gets Clock Info.
	356	*
	357	* @param pHwMgr the address of the powerplay hardware manager.
	358	* @param pPowerState the address of the Power State structure.
	359	* @param pClockInfo the address of PP_ClockInfo structure where the result will be returned.
	360	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
	361	*/
	362	int phm_get_clock_info(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state, struct pp_clock_info *pclock_info,
	363	PHM_PerformanceLevelDesignation designation)
	364	{
	365	int result;
	366	PHM_PerformanceLevel performance_level;
	367
	368	PHM_FUNC_CHECK(hwmgr);
	369
	370	PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
	371	PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
	372
	373	result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
	374
	375	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
	376
	377
	378	pclock_info->min_mem_clk = performance_level.memory_clock;
	379	pclock_info->min_eng_clk = performance_level.coreClock;
	380	pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
	381
	382
	383	result = phm_get_performance_level(hwmgr, state, designation,
	384	(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
	385
	386	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
	387
	388	pclock_info->max_mem_clk = performance_level.memory_clock;
	389	pclock_info->max_eng_clk = performance_level.coreClock;
	390	pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
	391
	392	return 0;
	393	}
	394
	395	int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state, struct pp_clock_info *clock_info)
	396	{
	397	PHM_FUNC_CHECK(hwmgr);
	398
	399	if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
	400	return -EINVAL;
	401
402	return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
403
404	}
405
406	int phm_get_clock_by_type(struct pp_hwmgr hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks clocks)
407	{
408	PHM_FUNC_CHECK(hwmgr);
409
410	if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
411	return -EINVAL;
412
413	return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
414
415	}
416
417	int phm_get_max_high_clocks(struct pp_hwmgr hwmgr, struct amd_pp_simple_clock_info clocks)
418	{
419	PHM_FUNC_CHECK(hwmgr);
420
421	if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
422	return -EINVAL;
423
424	return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
425	}